Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	159973	1		T1	580		T2	645		T4	1248
auto[FlashEraseBank]	198119	1		T1	326		T2	285		T14	8

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	173480	1		T1	906		T2	930		T4	624
auto[FlashOpProgram]	166357	1		T4	312		T14	1		T6	550
auto[FlashOpErase]	14255	1		T4	312		T6	49		T42	71
auto[FlashOpInvalid]	4000	1		T76	200		T222	200		T96	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	173480	1		T1	906		T2	930		T4	624
op[FlashOpProgram]	166357	1		T4	312		T14	1		T6	550
op[FlashOpErase]	14255	1		T4	312		T6	49		T42	71
read_erase_read	703	1		T6	3		T26	3		T27	3
read_prog_read	1047	1		T14	1		T6	4		T18	3

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	249880	1		T1	903		T2	921		T14	1
auto[FlashPartInfo]	105178	1		T4	1248		T14	10		T6	982
auto[FlashPartInfo1]	730	1		T2	1		T5	2		T18	7
auto[FlashPartInfo2]	2304	1		T1	3		T2	8		T5	7

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	132895	1		T1	903		T2	921		T14	1
auto[FlashPartData]	auto[FlashOpProgram]	109304	1		T6	37		T16	1		T17	1
auto[FlashPartData]	auto[FlashOpErase]	3777	1		T6	29		T27	35		T55	1
auto[FlashPartData]	auto[FlashOpInvalid]	3904	1		T76	198		T222	198		T96	196
auto[FlashPartInfo]	auto[FlashOpRead]	38861	1		T4	624		T14	9		T6	449
auto[FlashPartInfo]	auto[FlashOpProgram]	55841	1		T4	312		T14	1		T6	513
auto[FlashPartInfo]	auto[FlashOpErase]	10396	1		T4	312		T6	20		T42	71
auto[FlashPartInfo]	auto[FlashOpInvalid]	80	1		T222	2		T96	4		T178	6
auto[FlashPartInfo1]	auto[FlashOpRead]	554	1		T2	1		T5	2		T18	7
auto[FlashPartInfo1]	auto[FlashOpProgram]	166	1		T233	1		T81	32		T100	1
auto[FlashPartInfo1]	auto[FlashOpErase]	4	1		T100	1		T83	1		T402	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	6	1		T100	2		T83	2		T402	2
auto[FlashPartInfo2]	auto[FlashOpRead]	1170	1		T1	3		T2	8		T5	7
auto[FlashPartInfo2]	auto[FlashOpProgram]	1046	1		T18	11		T20	1		T78	5
auto[FlashPartInfo2]	auto[FlashOpErase]	78	1		T76	1		T178	1		T403	2
auto[FlashPartInfo2]	auto[FlashOpInvalid]	10	1		T76	2		T178	2		T403	4