Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.48	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	4	28	87.50

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	4	28	87.50	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	27552	1		T4	584		T18	1		T42	144
auto[1]	16	1		T34	2		T206	1		T216	1
auto[2]	169	1		T219	12		T286	32		T124	8
auto[3]	264	1		T14	2		T20	1		T22	2

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7045	1		T4	146		T42	36		T27	4
evic_idx[1]	6982	1		T4	146		T14	1		T18	1
evic_idx[2]	6992	1		T4	146		T14	1		T42	36
evic_idx[3]	6982	1		T4	146		T42	36		T27	4

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	26792	1		T4	584		T42	144		T106	256
evic_op[2]	457	1		T14	2		T18	1		T20	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	4	28	87.50	4

Automatically Generated Cross Bins for evic_all_cross

Element holes

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
*	[evic_op[1]]	[auto[1]]	--	--	4

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	6640	1		T4	146		T42	36		T106	64
evic_idx[0]	evic_op[1]	auto[2]	9	1		T350	9		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	88	1		T351	3		T352	3		T353	38
evic_idx[0]	evic_op[2]	auto[0]	71	1		T115	4		T219	1		T117	4
evic_idx[0]	evic_op[2]	auto[1]	4	1		T216	1		T354	1		T355	1
evic_idx[0]	evic_op[2]	auto[2]	31	1		T219	6		T286	8		T208	1
evic_idx[0]	evic_op[2]	auto[3]	14	1		T22	1		T48	1		T192	1
evic_idx[1]	evic_op[1]	auto[0]	6635	1		T4	146		T42	36		T106	64
evic_idx[1]	evic_op[1]	auto[2]	3	1		T350	3		-	-		-	-
evic_idx[1]	evic_op[1]	auto[3]	57	1		T351	3		T352	2		T353	25
evic_idx[1]	evic_op[2]	auto[0]	65	1		T18	1		T115	4		T117	4
evic_idx[1]	evic_op[2]	auto[1]	3	1		T206	1		T354	1		T285	1
evic_idx[1]	evic_op[2]	auto[2]	25	1		T219	6		T286	6		T208	1
evic_idx[1]	evic_op[2]	auto[3]	6	1		T14	1		T20	1		T289	1
evic_idx[2]	evic_op[1]	auto[0]	6641	1		T4	146		T42	36		T106	64
evic_idx[2]	evic_op[1]	auto[2]	6	1		T350	6		-	-		-	-
evic_idx[2]	evic_op[1]	auto[3]	43	1		T351	4		T352	2		T353	13
evic_idx[2]	evic_op[2]	auto[0]	69	1		T118	1		T115	4		T219	3
evic_idx[2]	evic_op[2]	auto[1]	5	1		T34	1		T209	1		T356	1
evic_idx[2]	evic_op[2]	auto[2]	33	1		T286	11		T208	2		T357	3
evic_idx[2]	evic_op[2]	auto[3]	7	1		T14	1		T35	1		T358	1
evic_idx[3]	evic_op[1]	auto[0]	6634	1		T4	146		T42	36		T106	64
evic_idx[3]	evic_op[1]	auto[2]	5	1		T350	5		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	31	1		T351	5		T352	1		T353	9
evic_idx[3]	evic_op[2]	auto[0]	73	1		T115	4		T117	4		T234	4
evic_idx[3]	evic_op[2]	auto[1]	4	1		T34	1		T218	1		T359	1
evic_idx[3]	evic_op[2]	auto[2]	29	1		T286	7		T208	2		T357	2
evic_idx[3]	evic_op[2]	auto[3]	18	1		T22	1		T48	1		T207	1