Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	1519	1		T212	1519		-	-		-	-
rd_lvl[2]	14019	1		T341	6398		T212	1527		T342	6094
rd_lvl[3]	9006	1		T341	477		T212	480		T343	2418
rd_lvl[4]	15679	1		T231	2668		T212	973		T343	1427
rd_lvl[5]	9919	1		T21	1510		T231	845		T344	1566
rd_lvl[6]	10893	1		T21	932		T231	1		T344	891
rd_lvl[7]	7591	1		T231	2		T212	180		T345	946
rd_lvl[8]	7145	1		T231	1		T346	1364		T212	479
rd_lvl[9]	3526	1		T335	519		T346	414		T212	572
rd_lvl[10]	3059	1		T31	554		T335	195		T212	78
rd_lvl[11]	3616	1		T31	295		T28	592		T212	1196
rd_lvl[12]	897	1		T28	304		T231	2		T347	589
rd_lvl[13]	843	1		T347	208		T212	1		T348	560
rd_lvl[14]	1701	1		T28	1		T212	11		T349	431
rd_lvl[15]	2587	1		T29	517		T349	434		T30	455