Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	146351	1		T1	2		T2	2		T3	1
all_pins[1]	146351	1		T1	2		T2	2		T3	1
all_pins[2]	146351	1		T1	2		T2	2		T3	1
all_pins[3]	146351	1		T1	2		T2	2		T3	1
all_pins[4]	146351	1		T1	2		T2	2		T3	1
all_pins[5]	146351	1		T1	2		T2	2		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	721926	1		T1	12		T2	12		T3	6
values[0x1]	156180	1		T21	3582		T23	1054		T24	1018
transitions[0x0=>0x1]	143233	1		T21	3256		T23	1054		T24	1018
transitions[0x1=>0x0]	143220	1		T21	3256		T23	1054		T24	1018

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	146177	1		T1	2		T2	2		T3	1
all_pins[0]	values[0x1]	174	1		T269	6		T270	1		T336	5
all_pins[0]	transitions[0x0=>0x1]	91	1		T269	5		T270	1		T336	3
all_pins[0]	transitions[0x1=>0x0]	58	1		T269	1		T336	3		T337	3
all_pins[1]	values[0x0]	146210	1		T1	2		T2	2		T3	1
all_pins[1]	values[0x1]	141	1		T269	2		T336	5		T337	5
all_pins[1]	transitions[0x0=>0x1]	116	1		T269	2		T336	3		T337	4
all_pins[1]	transitions[0x1=>0x0]	1064	1		T29	298		T30	395		T364	330
all_pins[2]	values[0x0]	145262	1		T1	2		T2	2		T3	1
all_pins[2]	values[0x1]	1089	1		T29	298		T30	395		T364	330
all_pins[2]	transitions[0x0=>0x1]	54	1		T269	1		T336	1		T337	2
all_pins[2]	transitions[0x1=>0x0]	92041	1		T21	2442		T31	849		T28	897
all_pins[3]	values[0x0]	53275	1		T1	2		T2	2		T3	1
all_pins[3]	values[0x1]	93076	1		T21	2442		T31	849		T28	897
all_pins[3]	transitions[0x0=>0x1]	81330	1		T21	2116		T31	849		T28	897
all_pins[3]	transitions[0x1=>0x0]	49890	1		T21	814		T23	1054		T24	1018
all_pins[4]	values[0x0]	84715	1		T1	2		T2	2		T3	1
all_pins[4]	values[0x1]	61636	1		T21	1140		T23	1054		T24	1018
all_pins[4]	transitions[0x0=>0x1]	61622	1		T21	1140		T23	1054		T24	1018
all_pins[4]	transitions[0x1=>0x0]	50	1		T336	1		T337	1		T338	3
all_pins[5]	values[0x0]	146287	1		T1	2		T2	2		T3	1
all_pins[5]	values[0x1]	64	1		T270	1		T336	1		T337	2
all_pins[5]	transitions[0x0=>0x1]	20	1		T338	3		T339	3		T340	1
all_pins[5]	transitions[0x1=>0x0]	117	1		T269	5		T270	1		T336	4