|  |  |  |  |  |  |  |     
    
| flash_ctrl_core_csr_assert | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
100.00 | 
    
    
| gen_alert_senders[0].u_alert_sender | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| gen_alert_senders[1].u_alert_sender | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| gen_alert_senders[2].u_alert_sender | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| gen_alert_senders[3].u_alert_sender | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| gen_alert_senders[4].u_alert_sender | 
 77.78 | 
 | 
 | 
 77.78 | 
 | 
 | 
 | 
    
    
| tlul_assert_device | 
 99.77 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 99.30 | 
    
    
| u_ctrl_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
100.00 | 
100.00 | 
100.00 | 
    
    
| u_state_regs | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_state_flop | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_disable_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
100.00 | 
    
    
| gen_buffs[0].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[1].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[1].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[1].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[1].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[2].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[2].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[2].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[2].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[3].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[3].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[3].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[3].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[4].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[4].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[4].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[4].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[5].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[5].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[5].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[5].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[6].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[6].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[6].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[6].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[7].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[7].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[7].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[7].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_eflash | 
 97.67 | 
 98.50 | 
 93.30 | 
 99.49 | 
 97.62 | 
 99.61 | 
 97.49 | 
    
    
| subtree... | 
 | 
 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_exec_en_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_flash_ctrl_erase | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_flash_ctrl_prog | 
 97.88 | 
100.00 | 
 97.06 | 
100.00 | 
 | 
 94.44 | 
 | 
    
    
| u_cnt | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_flash_ctrl_rd | 
 94.44 | 
 83.02 | 
 93.94 | 
100.00 | 
100.00 | 
 95.24 | 
 | 
    
    
| u_bus_intg | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_data_gen | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_cnt | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_flash_hw_if | 
 96.18 | 
 99.02 | 
 93.52 | 
 95.83 | 
 92.11 | 
 96.62 | 
100.00 | 
    
    
| u_addr_cnt | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_addr_sync_reqack | 
 96.46 | 
 95.83 | 
100.00 | 
 | 
 | 
 90.00 | 
100.00 | 
    
    
| gen_nrz_hs_protocol.ack_sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_nrz_hs_protocol.req_sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_bus_intg | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_data_gen | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_data_intg_chk | 
100.00 | 
100.00 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_data_chk | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_data_sync_reqack | 
 96.46 | 
 95.83 | 
100.00 | 
 | 
 | 
 90.00 | 
100.00 | 
    
    
| gen_nrz_hs_protocol.ack_sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_nrz_hs_protocol.req_sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_page_cnt | 
 78.79 | 
 | 
 | 
 78.79 | 
 | 
 | 
 | 
    
    
| u_prim_flop_err_sts | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_rma_state_regs | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_state_flop | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_seed_cnt | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_state_regs | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_state_flop | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_flash_init | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_rma_req | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_buffs[0].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[1].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[1].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[1].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[1].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[2].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[2].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[2].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[2].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_flops.u_prim_flop_2sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_wipe_idx_cnt | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_word_cnt | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_flash_mp | 
 99.54 | 
100.00 | 
 98.16 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_hw_sel | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sw_sel | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_intr_corr_err | 
 93.75 | 
100.00 | 
 75.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_intr_op_done | 
 93.75 | 
100.00 | 
 75.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_intr_prog_empty | 
 86.94 | 
 90.00 | 
 77.78 | 
 | 
 | 
 80.00 | 
100.00 | 
    
    
| u_intr_prog_lvl | 
 86.94 | 
 90.00 | 
 77.78 | 
 | 
 | 
 80.00 | 
100.00 | 
    
    
| u_intr_rd_full | 
 86.94 | 
 90.00 | 
 77.78 | 
 | 
 | 
 80.00 | 
100.00 | 
    
    
| u_intr_rd_lvl | 
 86.94 | 
 90.00 | 
 77.78 | 
 | 
 | 
 80.00 | 
100.00 | 
    
    
| u_lc_escalation_en_sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_buffs[0].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_flops.u_prim_flop_2sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_lc_seed_hw_rd_en_sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_buffs[0].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_flops.u_prim_flop_2sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_lfsr | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_prog_fifo | 
 97.06 | 
100.00 | 
 88.24 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_normal_fifo.u_fifo_cnt | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_prog_tl_gate | 
 86.86 | 
100.00 | 
 92.50 | 
 | 
 57.14 | 
 97.14 | 
 87.50 | 
    
    
| gen_lc_gating_muxes[0].u_prim_blanker_d2h | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_blank_and | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_lc_gating_muxes[0].u_prim_blanker_h2d | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_blank_and | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_lc_gating_muxes[1].u_prim_blanker_d2h | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_blank_and | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_lc_gating_muxes[1].u_prim_blanker_h2d | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_blank_and | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_err_en_sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
100.00 | 
    
    
| gen_buffs[0].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[1].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[1].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[1].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[1].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_state_regs | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_state_flop | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_tlul_err_resp | 
 98.86 | 
100.00 | 
 95.45 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_intg_gen | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
100.00 | 
    
    
| gen_data_intg.u_tlul_data_integ_enc | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_data_gen | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_rsp_intg.u_rsp_gen | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_reg_core | 
 99.25 | 
 98.96 | 
 98.41 | 
100.00 | 
 | 
 98.88 | 
100.00 | 
    
    
| subtree... | 
 | 
 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_reg_idle | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_region_cfg | 
 87.91 | 
 63.73 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_creator_mubi | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_sec_buf.u_prim_sec_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_owner_mubi | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_sec_buf.u_prim_sec_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg | 
 90.00 | 
 70.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_creator_mubi | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_sec_buf.u_prim_sec_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_owner_mubi | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_sec_buf.u_prim_sec_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg | 
 91.11 | 
 73.33 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_creator_mubi | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_sec_buf.u_prim_sec_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_owner_mubi | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_sec_buf.u_prim_sec_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_creator_mubi | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_sec_buf.u_prim_sec_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_owner_mubi | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_sec_buf.u_prim_sec_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg | 
 90.00 | 
 70.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_creator_mubi | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_sec_buf.u_prim_sec_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_owner_mubi | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_sec_buf.u_prim_sec_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg | 
 91.11 | 
 73.33 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_creator_mubi | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_sec_buf.u_prim_sec_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_owner_mubi | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_sec_buf.u_prim_sec_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_lc_creator_seed_sw_rw_en_sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_buffs[0].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_flops.u_prim_flop_2sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_lc_iso_part_sw_rd_en_sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_buffs[0].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_flops.u_prim_flop_2sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_lc_iso_part_sw_wr_en_sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_buffs[0].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_flops.u_prim_flop_2sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_lc_owner_seed_sw_rw_en_sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_buffs[0].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_flops.u_prim_flop_2sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sw_rd_fifo | 
 92.86 | 
 95.24 | 
 85.29 | 
 | 
 | 
 90.91 | 
100.00 | 
    
    
| gen_normal_fifo.u_fifo_cnt | 
 85.00 | 
 90.00 | 
 | 
 | 
 | 
 80.00 | 
 | 
    
    
| u_tl_adapter_eflash | 
 93.20 | 
 91.60 | 
 81.01 | 
100.00 | 
 | 
 93.41 | 
100.00 | 
    
    
| gen_cmd_intg_check.u_cmd_intg_chk | 
100.00 | 
100.00 | 
 | 
100.00 | 
 | 
 | 
100.00 | 
    
    
| u_chk | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_tlul_data_integ_dec | 
100.00 | 
100.00 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_data_chk | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_err | 
 73.63 | 
 88.46 | 
 68.57 | 
 | 
 | 
 37.50 | 
100.00 | 
    
    
| u_reqfifo | 
 95.19 | 
100.00 | 
 80.77 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_normal_fifo.u_fifo_cnt | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_rsp_gen | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
100.00 | 
    
    
| gen_rsp_intg.u_rsp_gen | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_rspfifo | 
 96.32 | 
100.00 | 
 85.29 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_normal_fifo.u_fifo_cnt | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sram_byte | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_sramreqfifo | 
 95.19 | 
100.00 | 
 80.77 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_normal_fifo.u_fifo_cnt | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_tlul_data_integ_enc_data | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_data_gen | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_tlul_data_integ_enc_instr | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_data_gen | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_tl_gate | 
 84.79 | 
100.00 | 
 85.00 | 
 | 
 57.14 | 
 94.29 | 
 87.50 | 
    
    
| gen_lc_gating_muxes[0].u_prim_blanker_d2h | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_blank_and | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_lc_gating_muxes[0].u_prim_blanker_h2d | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_blank_and | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_lc_gating_muxes[1].u_prim_blanker_d2h | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_blank_and | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_lc_gating_muxes[1].u_prim_blanker_h2d | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_blank_and | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_err_en_sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
100.00 | 
    
    
| gen_buffs[0].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[0].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[1].gen_bits[0].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[1].gen_bits[1].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[1].gen_bits[2].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_buffs[1].gen_bits[3].u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_secure_anchor_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_state_regs | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_state_flop | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_tlul_err_resp | 
 90.40 | 
100.00 | 
 72.73 | 
 | 
 | 
 88.89 | 
100.00 | 
    
    
| u_intg_gen | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
100.00 | 
    
    
| gen_data_intg.u_tlul_data_integ_enc | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_data_gen | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_rsp_intg.u_rsp_gen | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_to_prog_fifo | 
 79.40 | 
 89.33 | 
 64.86 | 
 | 
 | 
 82.14 | 
 81.25 | 
    
    
| u_err | 
 87.32 | 
100.00 | 
 74.29 | 
 | 
 | 
 75.00 | 
100.00 | 
    
    
| u_reqfifo | 
 91.88 | 
100.00 | 
 73.08 | 
 | 
 | 
 94.44 | 
100.00 | 
    
    
| gen_normal_fifo.u_fifo_cnt | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_rsp_gen | 
 91.67 | 
 83.33 | 
 | 
 | 
 | 
 | 
100.00 | 
    
    
| u_rspfifo | 
 68.01 | 
 91.43 | 
 51.85 | 
 | 
 | 
 68.75 | 
 60.00 | 
    
    
| gen_normal_fifo.u_fifo_cnt | 
 76.67 | 
 86.67 | 
 | 
 | 
 | 
 66.67 | 
 | 
    
    
| u_sram_byte | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_sramreqfifo | 
 70.88 | 
 94.44 | 
 47.83 | 
 | 
 | 
 81.25 | 
 60.00 | 
    
    
| gen_normal_fifo.u_fifo_cnt | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_tlul_data_integ_enc_data | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_data_gen | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_tlul_data_integ_enc_instr | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_data_gen | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_to_rd_fifo | 
 91.01 | 
 88.89 | 
 76.99 | 
100.00 | 
 | 
 89.16 | 
100.00 | 
    
    
| u_err | 
 66.91 | 
 76.92 | 
 65.71 | 
 | 
 | 
 25.00 | 
100.00 | 
    
    
| u_reqfifo | 
 91.88 | 
100.00 | 
 73.08 | 
 | 
 | 
 94.44 | 
100.00 | 
    
    
| gen_normal_fifo.u_fifo_cnt | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_rsp_gen | 
 91.67 | 
 83.33 | 
 | 
 | 
 | 
 | 
100.00 | 
    
    
| u_rspfifo | 
 97.84 | 
100.00 | 
 89.19 | 
100.00 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_normal_fifo.u_fifo_cnt | 
100.00 | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
    
    
| gen_secure_ptrs.u_rptr | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| gen_secure_ptrs.u_wptr | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_sram_byte | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_sramreqfifo | 
 90.92 | 
100.00 | 
 69.23 | 
 | 
 | 
 94.44 | 
100.00 | 
    
    
| gen_normal_fifo.u_fifo_cnt | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_tlul_data_integ_enc_data | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_data_gen | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_tlul_data_integ_enc_instr | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_data_gen | 
  0.00 | 
  0.00 | 
 | 
 | 
 | 
 | 
 |