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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.54 95.80 94.17 98.85 92.52 98.27 98.11 98.09


Total test records in report: 1195
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T1051 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.1816557679 Mar 21 01:47:37 PM PDT 24 Mar 21 01:47:50 PM PDT 24 40807000 ps
T1052 /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.1970532124 Mar 21 01:47:57 PM PDT 24 Mar 21 01:48:11 PM PDT 24 52200000 ps
T340 /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.701554414 Mar 21 01:48:34 PM PDT 24 Mar 21 01:48:48 PM PDT 24 43698100 ps
T1053 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.4154274155 Mar 21 01:47:46 PM PDT 24 Mar 21 01:48:02 PM PDT 24 71296700 ps
T171 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.2485193141 Mar 21 01:47:59 PM PDT 24 Mar 21 02:03:01 PM PDT 24 794818900 ps
T241 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.42875736 Mar 21 01:48:19 PM PDT 24 Mar 21 02:03:27 PM PDT 24 5951144500 ps
T254 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2845939770 Mar 21 01:47:55 PM PDT 24 Mar 21 01:48:12 PM PDT 24 151467500 ps
T1054 /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2412503142 Mar 21 01:48:49 PM PDT 24 Mar 21 01:49:03 PM PDT 24 44361900 ps
T1055 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.4024736714 Mar 21 01:47:35 PM PDT 24 Mar 21 01:47:51 PM PDT 24 21010100 ps
T1056 /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.1487861654 Mar 21 01:48:41 PM PDT 24 Mar 21 01:48:54 PM PDT 24 122788300 ps
T255 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1678091976 Mar 21 01:47:36 PM PDT 24 Mar 21 01:47:54 PM PDT 24 42847700 ps
T404 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2869808206 Mar 21 01:47:37 PM PDT 24 Mar 21 01:48:22 PM PDT 24 5356396500 ps
T237 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.3880011262 Mar 21 01:47:33 PM PDT 24 Mar 21 01:55:22 PM PDT 24 926907600 ps
T1057 /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.4231392027 Mar 21 01:48:47 PM PDT 24 Mar 21 01:49:02 PM PDT 24 64299100 ps
T248 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3662641913 Mar 21 01:47:48 PM PDT 24 Mar 21 01:48:02 PM PDT 24 46503000 ps
T1058 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.1024827067 Mar 21 01:47:51 PM PDT 24 Mar 21 01:48:07 PM PDT 24 12091800 ps
T1059 /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.2515723467 Mar 21 01:48:36 PM PDT 24 Mar 21 01:48:50 PM PDT 24 56131500 ps
T1060 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.2416959493 Mar 21 01:47:46 PM PDT 24 Mar 21 01:48:03 PM PDT 24 20030500 ps
T238 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.705730676 Mar 21 01:47:49 PM PDT 24 Mar 21 01:55:13 PM PDT 24 1206801000 ps
T1061 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.874058905 Mar 21 01:47:40 PM PDT 24 Mar 21 01:47:53 PM PDT 24 32869700 ps
T277 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1277368817 Mar 21 01:48:34 PM PDT 24 Mar 21 01:54:55 PM PDT 24 694408400 ps
T1062 /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.4157861868 Mar 21 01:48:39 PM PDT 24 Mar 21 01:48:53 PM PDT 24 32033800 ps
T303 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.723468942 Mar 21 01:47:47 PM PDT 24 Mar 21 01:48:26 PM PDT 24 823216100 ps
T1063 /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.3891984989 Mar 21 01:47:52 PM PDT 24 Mar 21 01:48:06 PM PDT 24 43538200 ps
T1064 /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.553251792 Mar 21 01:48:35 PM PDT 24 Mar 21 01:48:49 PM PDT 24 54696200 ps
T224 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.1332676082 Mar 21 01:48:22 PM PDT 24 Mar 21 01:48:41 PM PDT 24 576349400 ps
T239 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1982682315 Mar 21 01:47:57 PM PDT 24 Mar 21 01:48:14 PM PDT 24 246650000 ps
T1065 /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.1127189932 Mar 21 01:48:23 PM PDT 24 Mar 21 01:48:36 PM PDT 24 15498400 ps
T240 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.715027507 Mar 21 01:47:48 PM PDT 24 Mar 21 01:48:07 PM PDT 24 50086200 ps
T256 /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.122302532 Mar 21 01:47:35 PM PDT 24 Mar 21 01:48:05 PM PDT 24 2160107800 ps
T1066 /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.1638741195 Mar 21 01:48:11 PM PDT 24 Mar 21 01:48:26 PM PDT 24 29355300 ps
T242 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.4178827546 Mar 21 01:48:35 PM PDT 24 Mar 21 01:48:51 PM PDT 24 448565600 ps
T1067 /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.1716542525 Mar 21 01:47:49 PM PDT 24 Mar 21 01:48:03 PM PDT 24 58532200 ps
T1068 /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.3054884245 Mar 21 01:47:56 PM PDT 24 Mar 21 01:48:10 PM PDT 24 180696700 ps
T257 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.35502859 Mar 21 01:48:08 PM PDT 24 Mar 21 01:48:21 PM PDT 24 37077300 ps
T1069 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2418457787 Mar 21 01:47:46 PM PDT 24 Mar 21 01:48:02 PM PDT 24 11187300 ps
T243 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.1215646054 Mar 21 01:48:08 PM PDT 24 Mar 21 01:48:27 PM PDT 24 188768000 ps
T244 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.3850069584 Mar 21 01:47:53 PM PDT 24 Mar 21 01:48:11 PM PDT 24 449520800 ps
T1070 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.716743613 Mar 21 01:48:20 PM PDT 24 Mar 21 01:48:36 PM PDT 24 17873400 ps
T249 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.344451216 Mar 21 01:47:36 PM PDT 24 Mar 21 01:47:50 PM PDT 24 45932500 ps
T245 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1693934181 Mar 21 01:47:33 PM PDT 24 Mar 21 01:47:53 PM PDT 24 206388500 ps
T1071 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.105443851 Mar 21 01:48:12 PM PDT 24 Mar 21 01:48:28 PM PDT 24 37587800 ps
T1072 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.3555895876 Mar 21 01:47:52 PM PDT 24 Mar 21 01:48:08 PM PDT 24 34244100 ps
T258 /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.93514506 Mar 21 01:47:57 PM PDT 24 Mar 21 01:48:13 PM PDT 24 556810800 ps
T271 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.2384173376 Mar 21 01:47:42 PM PDT 24 Mar 21 01:47:58 PM PDT 24 58408600 ps
T1073 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.2693554975 Mar 21 01:47:47 PM PDT 24 Mar 21 01:48:03 PM PDT 24 16891200 ps
T1074 /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.2820394051 Mar 21 01:47:36 PM PDT 24 Mar 21 01:47:50 PM PDT 24 155546900 ps
T1075 /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.861145001 Mar 21 01:47:35 PM PDT 24 Mar 21 01:47:49 PM PDT 24 27690300 ps
T1076 /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.2850661735 Mar 21 01:48:34 PM PDT 24 Mar 21 01:48:48 PM PDT 24 26638200 ps
T259 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1734689545 Mar 21 01:48:02 PM PDT 24 Mar 21 01:48:19 PM PDT 24 40317400 ps
T1077 /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2540616514 Mar 21 01:48:21 PM PDT 24 Mar 21 01:48:38 PM PDT 24 88505700 ps
T304 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1876074750 Mar 21 01:47:48 PM PDT 24 Mar 21 01:48:03 PM PDT 24 57858600 ps
T1078 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.1997553757 Mar 21 01:47:57 PM PDT 24 Mar 21 01:48:14 PM PDT 24 14039500 ps
T1079 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.2316584229 Mar 21 01:47:46 PM PDT 24 Mar 21 01:48:01 PM PDT 24 42617300 ps
T1080 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.1471728094 Mar 21 01:47:46 PM PDT 24 Mar 21 01:48:03 PM PDT 24 194643600 ps
T1081 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.499125188 Mar 21 01:47:55 PM PDT 24 Mar 21 01:48:11 PM PDT 24 30431400 ps
T268 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.984621140 Mar 21 01:47:39 PM PDT 24 Mar 21 01:47:58 PM PDT 24 152016200 ps
T1082 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.424498211 Mar 21 01:47:56 PM PDT 24 Mar 21 01:48:35 PM PDT 24 1333804100 ps
T1083 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.2344168585 Mar 21 01:47:45 PM PDT 24 Mar 21 01:48:04 PM PDT 24 186840900 ps
T1084 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2669381723 Mar 21 01:47:58 PM PDT 24 Mar 21 01:48:18 PM PDT 24 148563800 ps
T1085 /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.1901421954 Mar 21 01:47:56 PM PDT 24 Mar 21 01:48:26 PM PDT 24 160850000 ps
T305 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.492138208 Mar 21 01:47:47 PM PDT 24 Mar 21 01:48:48 PM PDT 24 2915784400 ps
T1086 /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3032570435 Mar 21 01:48:37 PM PDT 24 Mar 21 01:48:51 PM PDT 24 18966100 ps
T274 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3991295527 Mar 21 01:47:48 PM PDT 24 Mar 21 01:55:24 PM PDT 24 379229100 ps
T1087 /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.1257834495 Mar 21 01:48:12 PM PDT 24 Mar 21 01:48:26 PM PDT 24 51827600 ps
T1088 /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.70380228 Mar 21 01:47:55 PM PDT 24 Mar 21 01:48:13 PM PDT 24 38762600 ps
T1089 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.1805062781 Mar 21 01:48:10 PM PDT 24 Mar 21 01:48:29 PM PDT 24 42621800 ps
T1090 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.708690022 Mar 21 01:47:58 PM PDT 24 Mar 21 01:48:11 PM PDT 24 13897600 ps
T1091 /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1673247896 Mar 21 01:47:55 PM PDT 24 Mar 21 01:48:32 PM PDT 24 1656800600 ps
T281 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.332173786 Mar 21 01:48:39 PM PDT 24 Mar 21 02:03:42 PM PDT 24 696829000 ps
T279 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.48404087 Mar 21 01:47:48 PM PDT 24 Mar 21 02:02:38 PM PDT 24 956579000 ps
T1092 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.4104333256 Mar 21 01:47:35 PM PDT 24 Mar 21 01:47:49 PM PDT 24 21219700 ps
T365 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2653912475 Mar 21 01:47:59 PM PDT 24 Mar 21 02:02:57 PM PDT 24 672193800 ps
T276 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2417360853 Mar 21 01:47:40 PM PDT 24 Mar 21 01:47:56 PM PDT 24 32007800 ps
T1093 /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.699624990 Mar 21 01:48:51 PM PDT 24 Mar 21 01:49:04 PM PDT 24 99906300 ps
T1094 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2826081045 Mar 21 01:48:09 PM PDT 24 Mar 21 01:48:25 PM PDT 24 30899700 ps
T1095 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.2949568922 Mar 21 01:47:57 PM PDT 24 Mar 21 01:48:14 PM PDT 24 141732600 ps
T275 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.2041282695 Mar 21 01:47:58 PM PDT 24 Mar 21 01:48:17 PM PDT 24 47750700 ps
T267 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.374385630 Mar 21 01:47:57 PM PDT 24 Mar 21 01:48:17 PM PDT 24 51142800 ps
T1096 /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.715704877 Mar 21 01:48:06 PM PDT 24 Mar 21 01:48:19 PM PDT 24 32281500 ps
T1097 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.2430866577 Mar 21 01:47:58 PM PDT 24 Mar 21 01:48:15 PM PDT 24 187117100 ps
T273 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.1743201725 Mar 21 01:48:33 PM PDT 24 Mar 21 01:48:52 PM PDT 24 44985100 ps
T1098 /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.1169851781 Mar 21 01:47:46 PM PDT 24 Mar 21 01:48:16 PM PDT 24 326854100 ps
T306 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.3716345064 Mar 21 01:48:34 PM PDT 24 Mar 21 01:48:49 PM PDT 24 68426300 ps
T1099 /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.2082074254 Mar 21 01:47:56 PM PDT 24 Mar 21 01:48:30 PM PDT 24 300475500 ps
T1100 /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.810503303 Mar 21 01:47:48 PM PDT 24 Mar 21 01:48:01 PM PDT 24 29008100 ps
T1101 /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2197401185 Mar 21 01:48:23 PM PDT 24 Mar 21 01:48:41 PM PDT 24 187849200 ps
T1102 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.523330486 Mar 21 01:47:36 PM PDT 24 Mar 21 01:47:51 PM PDT 24 75803200 ps
T1103 /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.2314109978 Mar 21 01:48:08 PM PDT 24 Mar 21 01:48:37 PM PDT 24 68199100 ps
T1104 /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.4139224185 Mar 21 01:48:39 PM PDT 24 Mar 21 01:48:53 PM PDT 24 27985700 ps
T1105 /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.3697648111 Mar 21 01:48:41 PM PDT 24 Mar 21 01:48:54 PM PDT 24 30384800 ps
T1106 /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.2722548794 Mar 21 01:48:48 PM PDT 24 Mar 21 01:49:02 PM PDT 24 16238000 ps
T1107 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.610628528 Mar 21 01:47:58 PM PDT 24 Mar 21 01:48:12 PM PDT 24 24914300 ps
T1108 /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.33764769 Mar 21 01:48:39 PM PDT 24 Mar 21 01:48:53 PM PDT 24 17916600 ps
T1109 /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.14754766 Mar 21 01:48:34 PM PDT 24 Mar 21 01:48:47 PM PDT 24 28635100 ps
T1110 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1945443203 Mar 21 01:48:37 PM PDT 24 Mar 21 01:48:54 PM PDT 24 189519300 ps
T1111 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2499107907 Mar 21 01:47:57 PM PDT 24 Mar 21 01:48:13 PM PDT 24 13982200 ps
T1112 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.980564087 Mar 21 01:47:56 PM PDT 24 Mar 21 01:55:34 PM PDT 24 325460500 ps
T1113 /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.3046207876 Mar 21 01:48:36 PM PDT 24 Mar 21 01:48:50 PM PDT 24 17761700 ps
T1114 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.8079810 Mar 21 01:48:08 PM PDT 24 Mar 21 01:48:24 PM PDT 24 215406500 ps
T1115 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.984009440 Mar 21 01:47:36 PM PDT 24 Mar 21 01:48:10 PM PDT 24 223822900 ps
T1116 /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2183888965 Mar 21 01:47:47 PM PDT 24 Mar 21 01:48:08 PM PDT 24 633991900 ps
T1117 /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.2072381547 Mar 21 01:47:36 PM PDT 24 Mar 21 01:47:57 PM PDT 24 149034700 ps
T307 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.866185708 Mar 21 01:47:45 PM PDT 24 Mar 21 01:48:31 PM PDT 24 48197400 ps
T1118 /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.1972205077 Mar 21 01:48:02 PM PDT 24 Mar 21 01:48:15 PM PDT 24 23953600 ps
T1119 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1006671386 Mar 21 01:48:35 PM PDT 24 Mar 21 01:48:53 PM PDT 24 87402700 ps
T1120 /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.270765187 Mar 21 01:48:35 PM PDT 24 Mar 21 01:48:49 PM PDT 24 37944400 ps
T272 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.858032687 Mar 21 01:47:47 PM PDT 24 Mar 21 01:48:07 PM PDT 24 54615800 ps
T308 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.4012207173 Mar 21 01:47:35 PM PDT 24 Mar 21 01:47:53 PM PDT 24 57354500 ps
T1121 /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.1285896592 Mar 21 01:48:34 PM PDT 24 Mar 21 01:48:48 PM PDT 24 163569400 ps
T1122 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.2081637267 Mar 21 01:47:46 PM PDT 24 Mar 21 01:48:03 PM PDT 24 44164800 ps
T1123 /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.746594830 Mar 21 01:47:56 PM PDT 24 Mar 21 01:48:09 PM PDT 24 16962900 ps
T247 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.670073730 Mar 21 01:47:35 PM PDT 24 Mar 21 01:47:49 PM PDT 24 16737400 ps
T1124 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.1670780570 Mar 21 01:48:33 PM PDT 24 Mar 21 01:48:47 PM PDT 24 28831600 ps
T1125 /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.937849062 Mar 21 01:47:46 PM PDT 24 Mar 21 01:48:01 PM PDT 24 64073000 ps
T1126 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3563553898 Mar 21 01:47:33 PM PDT 24 Mar 21 01:48:37 PM PDT 24 674059500 ps
T1127 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.3144907232 Mar 21 01:47:47 PM PDT 24 Mar 21 01:48:03 PM PDT 24 40436300 ps
T1128 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.682167918 Mar 21 01:48:03 PM PDT 24 Mar 21 01:48:20 PM PDT 24 91792000 ps
T1129 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.27327080 Mar 21 01:48:10 PM PDT 24 Mar 21 01:48:29 PM PDT 24 124216100 ps
T1130 /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2301501463 Mar 21 01:47:45 PM PDT 24 Mar 21 01:48:03 PM PDT 24 574914900 ps
T280 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.3495410341 Mar 21 01:48:12 PM PDT 24 Mar 21 01:48:29 PM PDT 24 77254300 ps
T1131 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2044350772 Mar 21 01:48:34 PM PDT 24 Mar 21 01:48:50 PM PDT 24 46070500 ps
T1132 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.4100046391 Mar 21 01:47:57 PM PDT 24 Mar 21 01:48:14 PM PDT 24 36632100 ps
T1133 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.935658852 Mar 21 01:47:47 PM PDT 24 Mar 21 01:48:50 PM PDT 24 1509970500 ps
T1134 /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.1302224135 Mar 21 01:48:36 PM PDT 24 Mar 21 01:48:54 PM PDT 24 165121400 ps
T1135 /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.3654414868 Mar 21 01:48:36 PM PDT 24 Mar 21 01:48:49 PM PDT 24 28046500 ps
T1136 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2662666881 Mar 21 01:47:35 PM PDT 24 Mar 21 01:47:51 PM PDT 24 16580200 ps
T1137 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3790837883 Mar 21 01:47:38 PM PDT 24 Mar 21 01:47:54 PM PDT 24 12431300 ps
T1138 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.2958309801 Mar 21 01:47:50 PM PDT 24 Mar 21 01:48:04 PM PDT 24 26820100 ps
T1139 /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.1521370421 Mar 21 01:47:48 PM PDT 24 Mar 21 01:48:01 PM PDT 24 24124400 ps
T1140 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.3566354870 Mar 21 01:47:57 PM PDT 24 Mar 21 01:48:16 PM PDT 24 30595500 ps
T1141 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1907868792 Mar 21 01:48:23 PM PDT 24 Mar 21 01:48:43 PM PDT 24 110716600 ps
T1142 /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.2398080044 Mar 21 01:48:38 PM PDT 24 Mar 21 01:48:55 PM PDT 24 167326800 ps
T1143 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.3387974626 Mar 21 01:47:58 PM PDT 24 Mar 21 01:48:14 PM PDT 24 27553600 ps
T1144 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2266934194 Mar 21 01:47:51 PM PDT 24 Mar 21 01:55:30 PM PDT 24 1360091700 ps
T1145 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.1146065842 Mar 21 01:47:55 PM PDT 24 Mar 21 01:48:10 PM PDT 24 44036100 ps
T1146 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.3469859320 Mar 21 01:48:11 PM PDT 24 Mar 21 01:48:27 PM PDT 24 20063000 ps
T1147 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.193895293 Mar 21 01:48:20 PM PDT 24 Mar 21 01:56:10 PM PDT 24 1027044000 ps
T309 /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.618445209 Mar 21 01:47:57 PM PDT 24 Mar 21 01:48:16 PM PDT 24 228615100 ps
T1148 /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.1882937441 Mar 21 01:48:47 PM PDT 24 Mar 21 01:49:01 PM PDT 24 54950100 ps
T1149 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1742344623 Mar 21 01:47:55 PM PDT 24 Mar 21 01:48:40 PM PDT 24 89145200 ps
T1150 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.3120527129 Mar 21 01:47:48 PM PDT 24 Mar 21 01:48:04 PM PDT 24 107309200 ps
T1151 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.1223869678 Mar 21 01:48:20 PM PDT 24 Mar 21 01:48:38 PM PDT 24 619491300 ps
T1152 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.4047078318 Mar 21 01:47:56 PM PDT 24 Mar 21 01:48:12 PM PDT 24 20194100 ps
T1153 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.3791051778 Mar 21 01:47:48 PM PDT 24 Mar 21 01:48:05 PM PDT 24 29996500 ps
T1154 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.500794896 Mar 21 01:47:56 PM PDT 24 Mar 21 01:48:12 PM PDT 24 16496800 ps
T1155 /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1229901525 Mar 21 01:48:12 PM PDT 24 Mar 21 01:48:46 PM PDT 24 202299500 ps
T1156 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2971592893 Mar 21 01:48:35 PM PDT 24 Mar 21 01:48:52 PM PDT 24 30021100 ps
T1157 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.1312821224 Mar 21 01:47:58 PM PDT 24 Mar 21 01:48:15 PM PDT 24 35084300 ps
T1158 /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.112806370 Mar 21 01:47:55 PM PDT 24 Mar 21 01:48:09 PM PDT 24 46945600 ps
T1159 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.108573891 Mar 21 01:47:36 PM PDT 24 Mar 21 01:48:42 PM PDT 24 660944900 ps
T1160 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2318668469 Mar 21 01:48:20 PM PDT 24 Mar 21 01:48:36 PM PDT 24 14012700 ps
T1161 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.2600492077 Mar 21 01:48:21 PM PDT 24 Mar 21 01:48:40 PM PDT 24 76243100 ps
T1162 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.1090295706 Mar 21 01:48:09 PM PDT 24 Mar 21 01:48:25 PM PDT 24 12278000 ps
T1163 /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.2134051159 Mar 21 01:48:34 PM PDT 24 Mar 21 01:48:48 PM PDT 24 28027000 ps
T1164 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.2719601906 Mar 21 01:48:11 PM PDT 24 Mar 21 01:48:27 PM PDT 24 18486800 ps
T1165 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.3247440449 Mar 21 01:48:33 PM PDT 24 Mar 21 01:48:50 PM PDT 24 137527900 ps
T278 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2918329639 Mar 21 01:47:45 PM PDT 24 Mar 21 01:48:04 PM PDT 24 707655000 ps
T1166 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.715812563 Mar 21 01:47:47 PM PDT 24 Mar 21 01:48:05 PM PDT 24 51588900 ps
T1167 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.1729261550 Mar 21 01:47:33 PM PDT 24 Mar 21 01:48:12 PM PDT 24 214968300 ps
T1168 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1711414775 Mar 21 01:47:46 PM PDT 24 Mar 21 01:48:06 PM PDT 24 419540200 ps
T366 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.2698823550 Mar 21 01:48:10 PM PDT 24 Mar 21 02:00:42 PM PDT 24 1713151100 ps
T1169 /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.553498903 Mar 21 01:48:33 PM PDT 24 Mar 21 01:48:47 PM PDT 24 43093600 ps
T1170 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.2628477458 Mar 21 01:47:48 PM PDT 24 Mar 21 01:48:06 PM PDT 24 39632500 ps
T1171 /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.1882464981 Mar 21 01:48:35 PM PDT 24 Mar 21 01:48:48 PM PDT 24 15430500 ps
T1172 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.1938050133 Mar 21 01:47:45 PM PDT 24 Mar 21 01:48:00 PM PDT 24 476427600 ps
T250 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.423621565 Mar 21 01:47:50 PM PDT 24 Mar 21 01:48:03 PM PDT 24 47128300 ps
T1173 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.421531440 Mar 21 01:47:51 PM PDT 24 Mar 21 01:48:07 PM PDT 24 50831300 ps
T1174 /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.1339329416 Mar 21 01:48:34 PM PDT 24 Mar 21 01:48:48 PM PDT 24 28795200 ps
T1175 /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.1928260939 Mar 21 01:48:35 PM PDT 24 Mar 21 01:48:49 PM PDT 24 87984600 ps
T370 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1781300705 Mar 21 01:48:12 PM PDT 24 Mar 21 02:00:49 PM PDT 24 679721000 ps
T1176 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3089189274 Mar 21 01:47:35 PM PDT 24 Mar 21 01:47:54 PM PDT 24 257564300 ps
T1177 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.258400189 Mar 21 01:47:35 PM PDT 24 Mar 21 01:48:37 PM PDT 24 5169307900 ps
T1178 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3186000596 Mar 21 01:48:33 PM PDT 24 Mar 21 01:48:49 PM PDT 24 19544900 ps
T1179 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1363654683 Mar 21 01:47:50 PM PDT 24 Mar 21 01:48:07 PM PDT 24 83700700 ps
T1180 /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.3014214975 Mar 21 01:48:37 PM PDT 24 Mar 21 01:48:51 PM PDT 24 31289900 ps
T369 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3032963079 Mar 21 01:47:35 PM PDT 24 Mar 21 02:00:02 PM PDT 24 332538700 ps
T367 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2533222448 Mar 21 01:47:57 PM PDT 24 Mar 21 01:55:38 PM PDT 24 789750400 ps
T1181 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1243802699 Mar 21 01:48:20 PM PDT 24 Mar 21 01:48:33 PM PDT 24 21449600 ps
T251 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.4017952481 Mar 21 01:47:42 PM PDT 24 Mar 21 01:47:55 PM PDT 24 57052100 ps
T368 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2596547897 Mar 21 01:47:41 PM PDT 24 Mar 21 02:02:33 PM PDT 24 2705965600 ps
T1182 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.2299001626 Mar 21 01:47:58 PM PDT 24 Mar 21 01:48:17 PM PDT 24 200709800 ps
T1183 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.3871321465 Mar 21 01:47:56 PM PDT 24 Mar 21 01:48:12 PM PDT 24 34313400 ps
T1184 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2613507904 Mar 21 01:47:35 PM PDT 24 Mar 21 01:47:48 PM PDT 24 51003800 ps
T1185 /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.2504520174 Mar 21 01:48:47 PM PDT 24 Mar 21 01:49:01 PM PDT 24 40010400 ps
T1186 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.3002948275 Mar 21 01:47:46 PM PDT 24 Mar 21 01:48:02 PM PDT 24 79278400 ps
T1187 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3019395204 Mar 21 01:47:57 PM PDT 24 Mar 21 01:48:13 PM PDT 24 40549900 ps
T1188 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2063603700 Mar 21 01:48:11 PM PDT 24 Mar 21 01:48:25 PM PDT 24 22696200 ps
T1189 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.578080979 Mar 21 01:48:35 PM PDT 24 Mar 21 01:48:55 PM PDT 24 190950900 ps
T1190 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.1265019559 Mar 21 01:48:08 PM PDT 24 Mar 21 01:55:43 PM PDT 24 427684700 ps
T1191 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2955579034 Mar 21 01:47:35 PM PDT 24 Mar 21 01:47:49 PM PDT 24 46997300 ps
T1192 /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3511886248 Mar 21 01:48:36 PM PDT 24 Mar 21 01:48:51 PM PDT 24 100220400 ps
T1193 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.1601640701 Mar 21 01:47:55 PM PDT 24 Mar 21 01:48:12 PM PDT 24 29420000 ps
T1194 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.437567605 Mar 21 01:47:57 PM PDT 24 Mar 21 01:48:14 PM PDT 24 28633300 ps
T1195 /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.2599850630 Mar 21 01:48:34 PM PDT 24 Mar 21 01:48:48 PM PDT 24 17630800 ps

Test location /workspace/coverage/default/19.flash_ctrl_mp_regions.4150926057
Short name T6
Test name
Test status
Simulation time 3900154600 ps
CPU time 146.39 seconds
Started Mar 21 03:17:27 PM PDT 24
Finished Mar 21 03:19:54 PM PDT 24
Peak memory 265176 kb
Host smart-7d9170cd-4fba-49e6-899f-20fd78d237be
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150926057 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 19.flash_ctrl_mp_regions.4150926057
Directory /workspace/19.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.2485193141
Short name T171
Test name
Test status
Simulation time 794818900 ps
CPU time 901.77 seconds
Started Mar 21 01:47:59 PM PDT 24
Finished Mar 21 02:03:01 PM PDT 24
Peak memory 263088 kb
Host smart-0b729be5-aebf-49f9-b4f7-68c122bd1d87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485193141 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl
_tl_intg_err.2485193141
Directory /workspace/9.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/47.flash_ctrl_otp_reset.4246124104
Short name T68
Test name
Test status
Simulation time 128026100 ps
CPU time 134.41 seconds
Started Mar 21 03:20:14 PM PDT 24
Finished Mar 21 03:22:28 PM PDT 24
Peak memory 264224 kb
Host smart-6250e51c-db3f-4e6b-ad49-af1463619111
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246124104 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_o
tp_reset.4246124104
Directory /workspace/47.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw.4192721236
Short name T18
Test name
Test status
Simulation time 17216254000 ps
CPU time 495.84 seconds
Started Mar 21 03:16:19 PM PDT 24
Finished Mar 21 03:24:35 PM PDT 24
Peak memory 309492 kb
Host smart-741fe706-832e-408f-af60-9664f55a1a20
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192721236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_c
trl_rw.4192721236
Directory /workspace/14.flash_ctrl_rw/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_rma_reset.644678824
Short name T63
Test name
Test status
Simulation time 80150008500 ps
CPU time 865.09 seconds
Started Mar 21 03:17:17 PM PDT 24
Finished Mar 21 03:31:42 PM PDT 24
Peak memory 263364 kb
Host smart-f87da3cf-844f-4295-b1c9-335d15d7a8ae
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644678824 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.flash_ctrl_hw_rma_reset.644678824
Directory /workspace/18.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_cm.1276651353
Short name T12
Test name
Test status
Simulation time 7132660500 ps
CPU time 4988.34 seconds
Started Mar 21 03:11:52 PM PDT 24
Finished Mar 21 04:35:03 PM PDT 24
Peak memory 282372 kb
Host smart-584e907f-5732-4fc8-95a6-fc6a5507df11
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276651353 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.1276651353
Directory /workspace/0.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict.1212435538
Short name T20
Test name
Test status
Simulation time 30451400 ps
CPU time 31.95 seconds
Started Mar 21 03:15:46 PM PDT 24
Finished Mar 21 03:16:18 PM PDT 24
Peak memory 273572 kb
Host smart-7281792f-f5e3-4b38-9f21-eb1dc5b6e344
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212435538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl
ash_ctrl_rw_evict.1212435538
Directory /workspace/12.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_erase_suspend.458793856
Short name T124
Test name
Test status
Simulation time 4098552400 ps
CPU time 353.09 seconds
Started Mar 21 03:11:51 PM PDT 24
Finished Mar 21 03:17:47 PM PDT 24
Peak memory 262468 kb
Host smart-51e91464-5387-41b8-b674-97b0e7445915
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=458793856 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.458793856
Directory /workspace/0.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd_slow_flash.3078479808
Short name T28
Test name
Test status
Simulation time 36515721600 ps
CPU time 250.1 seconds
Started Mar 21 03:18:07 PM PDT 24
Finished Mar 21 03:22:18 PM PDT 24
Peak memory 293960 kb
Host smart-520aa1f1-6688-4b15-8ffa-13e500b09261
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078479808 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd_slow_flash.3078479808
Directory /workspace/24.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.715027507
Short name T240
Test name
Test status
Simulation time 50086200 ps
CPU time 18.52 seconds
Started Mar 21 01:47:48 PM PDT 24
Finished Mar 21 01:48:07 PM PDT 24
Peak memory 264236 kb
Host smart-aa231012-f06d-4aa5-ac69-7de45304333f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715027507 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.715027507
Directory /workspace/8.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/38.flash_ctrl_otp_reset.564594972
Short name T3
Test name
Test status
Simulation time 75295700 ps
CPU time 111.26 seconds
Started Mar 21 03:19:40 PM PDT 24
Finished Mar 21 03:21:32 PM PDT 24
Peak memory 259824 kb
Host smart-56a96b2f-3c22-4b3b-9881-e94a6d33330c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564594972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_ot
p_reset.564594972
Directory /workspace/38.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_host_grant_err.2119410971
Short name T7
Test name
Test status
Simulation time 71773100 ps
CPU time 14.29 seconds
Started Mar 21 03:12:31 PM PDT 24
Finished Mar 21 03:12:45 PM PDT 24
Peak memory 265440 kb
Host smart-acfd6453-28cf-4296-8ff5-3254cd6071f0
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119410971 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.2119410971
Directory /workspace/2.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_mid_op_rst.3871756955
Short name T107
Test name
Test status
Simulation time 826930100 ps
CPU time 68.15 seconds
Started Mar 21 03:12:24 PM PDT 24
Finished Mar 21 03:13:33 PM PDT 24
Peak memory 260452 kb
Host smart-f4ee0bd2-3ccb-49da-8b27-09d565a93cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871756955 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.3871756955
Directory /workspace/2.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/16.flash_ctrl_mp_regions.3330119217
Short name T60
Test name
Test status
Simulation time 15803812300 ps
CPU time 406.37 seconds
Started Mar 21 03:16:47 PM PDT 24
Finished Mar 21 03:23:33 PM PDT 24
Peak memory 274684 kb
Host smart-fca13250-739f-48f1-8725-194da2ae8166
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330119217 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 16.flash_ctrl_mp_regions.3330119217
Directory /workspace/16.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.887569886
Short name T337
Test name
Test status
Simulation time 24799000 ps
CPU time 13.58 seconds
Started Mar 21 01:47:57 PM PDT 24
Finished Mar 21 01:48:11 PM PDT 24
Peak memory 261104 kb
Host smart-deae3ae9-a29b-42d6-b35b-6d71129694e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887569886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.887569886
Directory /workspace/9.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/46.flash_ctrl_hw_sec_otp.3983614259
Short name T312
Test name
Test status
Simulation time 3704970100 ps
CPU time 123.01 seconds
Started Mar 21 03:20:02 PM PDT 24
Finished Mar 21 03:22:05 PM PDT 24
Peak memory 262536 kb
Host smart-bba82a5a-eca3-414f-bf69-b1d1c3f09d6a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983614259 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_
hw_sec_otp.3983614259
Directory /workspace/46.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_serr.2282623144
Short name T166
Test name
Test status
Simulation time 4124688100 ps
CPU time 477.31 seconds
Started Mar 21 03:12:07 PM PDT 24
Finished Mar 21 03:20:05 PM PDT 24
Peak memory 312648 kb
Host smart-ea8ba333-983e-4968-a2cd-80ab6a42bdaf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282623144 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_s
err.2282623144
Directory /workspace/1.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/23.flash_ctrl_otp_reset.2618684704
Short name T137
Test name
Test status
Simulation time 71971700 ps
CPU time 133.05 seconds
Started Mar 21 03:18:05 PM PDT 24
Finished Mar 21 03:20:18 PM PDT 24
Peak memory 261052 kb
Host smart-10dbea4c-7b00-45bc-9f27-40ce5d629ff6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618684704 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_o
tp_reset.2618684704
Directory /workspace/23.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_alert_test.996797500
Short name T91
Test name
Test status
Simulation time 43958900 ps
CPU time 13.47 seconds
Started Mar 21 03:13:43 PM PDT 24
Finished Mar 21 03:13:56 PM PDT 24
Peak memory 264608 kb
Host smart-d1f90465-784c-4681-b4c5-16f4a2c91ba6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996797500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.996797500
Directory /workspace/5.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.889842756
Short name T90
Test name
Test status
Simulation time 10012730000 ps
CPU time 314.21 seconds
Started Mar 21 03:15:46 PM PDT 24
Finished Mar 21 03:21:01 PM PDT 24
Peak memory 332676 kb
Host smart-b03ff63d-dc57-4c94-b9b3-85adb53b08d8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889842756 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.889842756
Directory /workspace/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb_redun.160627101
Short name T65
Test name
Test status
Simulation time 661263100 ps
CPU time 17.81 seconds
Started Mar 21 03:12:28 PM PDT 24
Finished Mar 21 03:12:46 PM PDT 24
Peak memory 265004 kb
Host smart-44df6fc5-742d-4c66-896e-353ea71afb13
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160627101 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.160627101
Directory /workspace/2.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/44.flash_ctrl_disable.2792298355
Short name T54
Test name
Test status
Simulation time 30014300 ps
CPU time 21.77 seconds
Started Mar 21 03:19:59 PM PDT 24
Finished Mar 21 03:20:21 PM PDT 24
Peak memory 265476 kb
Host smart-1fc6c1e7-13c2-4f22-acfd-a91c7e8a6cef
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792298355 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.flash_ctrl_disable.2792298355
Directory /workspace/44.flash_ctrl_disable/latest

Test location /workspace/coverage/default/35.flash_ctrl_sec_info_access.324455634
Short name T26
Test name
Test status
Simulation time 1083110200 ps
CPU time 63.04 seconds
Started Mar 21 03:19:35 PM PDT 24
Finished Mar 21 03:20:38 PM PDT 24
Peak memory 263056 kb
Host smart-ff6ca0b7-79d6-4916-bec5-96abf0f99d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324455634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.324455634
Directory /workspace/35.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/78.flash_ctrl_otp_reset.2241004474
Short name T148
Test name
Test status
Simulation time 165244900 ps
CPU time 132.32 seconds
Started Mar 21 03:20:53 PM PDT 24
Finished Mar 21 03:23:05 PM PDT 24
Peak memory 259804 kb
Host smart-31aef141-eacc-4168-bc46-cba60558ae42
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241004474 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_o
tp_reset.2241004474
Directory /workspace/78.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_ctrl_arb.3247576173
Short name T149
Test name
Test status
Simulation time 294237741400 ps
CPU time 2904.09 seconds
Started Mar 21 03:13:10 PM PDT 24
Finished Mar 21 04:01:35 PM PDT 24
Peak memory 264844 kb
Host smart-1b639e86-2699-4024-84f8-2cf0ef74a4bc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247576173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 4.flash_ctrl_host_ctrl_arb.3247576173
Directory /workspace/4.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_mid_op_rst.2378967024
Short name T122
Test name
Test status
Simulation time 1687439800 ps
CPU time 71.24 seconds
Started Mar 21 03:13:19 PM PDT 24
Finished Mar 21 03:14:31 PM PDT 24
Peak memory 259724 kb
Host smart-8672b24b-fc16-458e-8de4-d2f644d73c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378967024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.2378967024
Directory /workspace/4.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/0.flash_ctrl_fetch_code.3707719456
Short name T45
Test name
Test status
Simulation time 150577300 ps
CPU time 27.6 seconds
Started Mar 21 03:11:50 PM PDT 24
Finished Mar 21 03:12:19 PM PDT 24
Peak memory 265212 kb
Host smart-98e6a487-5061-41e2-8adb-82ed83dda754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707719456 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetch_code.3707719456
Directory /workspace/0.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/1.flash_ctrl_mid_op_rst.854676339
Short name T123
Test name
Test status
Simulation time 9513726500 ps
CPU time 76.75 seconds
Started Mar 21 03:12:04 PM PDT 24
Finished Mar 21 03:13:21 PM PDT 24
Peak memory 260796 kb
Host smart-68a4f9e6-ab00-4f4e-9e0b-9f89ca77615e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854676339 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.854676339
Directory /workspace/1.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/0.flash_ctrl_rma_err.2185484521
Short name T150
Test name
Test status
Simulation time 165775478000 ps
CPU time 980.37 seconds
Started Mar 21 03:11:54 PM PDT 24
Finished Mar 21 03:28:16 PM PDT 24
Peak memory 259380 kb
Host smart-e13708a0-0c47-42b8-8fa3-2f75e511f114
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185484521 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rma_err.2185484521
Directory /workspace/0.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma_reset.538738159
Short name T120
Test name
Test status
Simulation time 70139148000 ps
CPU time 900.22 seconds
Started Mar 21 03:12:25 PM PDT 24
Finished Mar 21 03:27:26 PM PDT 24
Peak memory 263832 kb
Host smart-85943e86-9f27-46d9-9aa3-c28329b8f431
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538738159 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_hw_rma_reset.538738159
Directory /workspace/2.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd.121644968
Short name T212
Test name
Test status
Simulation time 1920245400 ps
CPU time 177.43 seconds
Started Mar 21 03:15:51 PM PDT 24
Finished Mar 21 03:18:48 PM PDT 24
Peak memory 293932 kb
Host smart-5a5743d4-e40b-4873-ad08-7329c9e660c5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121644968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flas
h_ctrl_intr_rd.121644968
Directory /workspace/12.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.1215646054
Short name T243
Test name
Test status
Simulation time 188768000 ps
CPU time 19.29 seconds
Started Mar 21 01:48:08 PM PDT 24
Finished Mar 21 01:48:27 PM PDT 24
Peak memory 261556 kb
Host smart-2e373a8f-dc12-42c3-8e2e-7999dc2bfa91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215646054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.
1215646054
Directory /workspace/13.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.670073730
Short name T247
Test name
Test status
Simulation time 16737400 ps
CPU time 13.52 seconds
Started Mar 21 01:47:35 PM PDT 24
Finished Mar 21 01:47:49 PM PDT 24
Peak memory 261180 kb
Host smart-fd86c2c8-ba99-4ed7-9129-9aabdaf72da5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670073730 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flas
h_ctrl_mem_partial_access.670073730
Directory /workspace/1.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/17.flash_ctrl_lcmgr_intg.1831624260
Short name T133
Test name
Test status
Simulation time 24651000 ps
CPU time 13.74 seconds
Started Mar 21 03:17:16 PM PDT 24
Finished Mar 21 03:17:30 PM PDT 24
Peak memory 265232 kb
Host smart-16167cec-4ef2-4ccd-910c-e797743a4f5e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831624260 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.flash_ctrl_lcmgr_intg.1831624260
Directory /workspace/17.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_cm.856538969
Short name T39
Test name
Test status
Simulation time 5369368100 ps
CPU time 4958.27 seconds
Started Mar 21 03:12:56 PM PDT 24
Finished Mar 21 04:35:36 PM PDT 24
Peak memory 287468 kb
Host smart-1a98c027-1aba-4c50-bb44-6b7bda3af8fe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856538969 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.856538969
Directory /workspace/3.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_derr.4280160408
Short name T167
Test name
Test status
Simulation time 3894965200 ps
CPU time 629.34 seconds
Started Mar 21 03:12:46 PM PDT 24
Finished Mar 21 03:23:15 PM PDT 24
Peak memory 336044 kb
Host smart-aec6878a-209b-4fcc-8d12-e7abc00c3f42
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280160408 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_rw_derr.4280160408
Directory /workspace/3.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.2964473519
Short name T300
Test name
Test status
Simulation time 10018459100 ps
CPU time 80.41 seconds
Started Mar 21 03:16:34 PM PDT 24
Finished Mar 21 03:17:54 PM PDT 24
Peak memory 314108 kb
Host smart-e172377a-2446-4004-9909-49b6869a67f8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964473519 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.2964473519
Directory /workspace/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_invalid_op.439444539
Short name T76
Test name
Test status
Simulation time 4388284100 ps
CPU time 87.13 seconds
Started Mar 21 03:13:21 PM PDT 24
Finished Mar 21 03:14:48 PM PDT 24
Peak memory 259840 kb
Host smart-c993f129-7c39-42b2-b658-08065241d79c
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439444539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.439444539
Directory /workspace/4.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_fs_sup.3031480513
Short name T34
Test name
Test status
Simulation time 3706884500 ps
CPU time 38.91 seconds
Started Mar 21 03:12:31 PM PDT 24
Finished Mar 21 03:13:10 PM PDT 24
Peak memory 273452 kb
Host smart-d55a899a-d680-4f2c-a86a-57167c58dc18
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031480513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.flash_ctrl_fs_sup.3031480513
Directory /workspace/2.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.749917335
Short name T57
Test name
Test status
Simulation time 2285252100 ps
CPU time 460.47 seconds
Started Mar 21 01:47:45 PM PDT 24
Finished Mar 21 01:55:26 PM PDT 24
Peak memory 264120 kb
Host smart-dacfef90-cb8d-4261-8e9e-71408012d425
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749917335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_
tl_intg_err.749917335
Directory /workspace/6.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict_all_en.1053178957
Short name T357
Test name
Test status
Simulation time 796514900 ps
CPU time 38.97 seconds
Started Mar 21 03:12:58 PM PDT 24
Finished Mar 21 03:13:37 PM PDT 24
Peak memory 273524 kb
Host smart-d28164fa-ff87-4d1b-b8b7-5d38fb0368b9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053178957 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict_all_en.1053178957
Directory /workspace/3.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma.709687519
Short name T72
Test name
Test status
Simulation time 167433141200 ps
CPU time 1908.24 seconds
Started Mar 21 03:12:25 PM PDT 24
Finished Mar 21 03:44:13 PM PDT 24
Peak memory 263808 kb
Host smart-1ee38e27-dfbb-4bf6-9bcc-acac04978d1b
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709687519 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.flash_ctrl_hw_rma.709687519
Directory /workspace/2.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/0.flash_ctrl_wr_intg.1851503766
Short name T8
Test name
Test status
Simulation time 339209200 ps
CPU time 14.91 seconds
Started Mar 21 03:11:52 PM PDT 24
Finished Mar 21 03:12:09 PM PDT 24
Peak memory 260472 kb
Host smart-8e6a6dd6-7220-4f29-abb3-8e2c4609ea47
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851503766 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wr_intg.1851503766
Directory /workspace/0.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.2698823550
Short name T366
Test name
Test status
Simulation time 1713151100 ps
CPU time 751.9 seconds
Started Mar 21 01:48:10 PM PDT 24
Finished Mar 21 02:00:42 PM PDT 24
Peak memory 264036 kb
Host smart-9b027c94-47bf-4dc6-9d6b-945dcbd1817c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698823550 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctr
l_tl_intg_err.2698823550
Directory /workspace/15.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_invalid_op.2354640575
Short name T100
Test name
Test status
Simulation time 1636844700 ps
CPU time 72.62 seconds
Started Mar 21 03:14:45 PM PDT 24
Finished Mar 21 03:15:57 PM PDT 24
Peak memory 259908 kb
Host smart-7aaa9098-f624-4f5c-bf0a-10ad5b405d0f
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354640575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.2354640575
Directory /workspace/9.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.701554414
Short name T340
Test name
Test status
Simulation time 43698100 ps
CPU time 13.42 seconds
Started Mar 21 01:48:34 PM PDT 24
Finished Mar 21 01:48:48 PM PDT 24
Peak memory 261132 kb
Host smart-992cd7ac-97c1-4709-a87d-395f368a687d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701554414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test.701554414
Directory /workspace/35.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/1.flash_ctrl_re_evict.1657928970
Short name T351
Test name
Test status
Simulation time 262169800 ps
CPU time 33.51 seconds
Started Mar 21 03:12:07 PM PDT 24
Finished Mar 21 03:12:41 PM PDT 24
Peak memory 273608 kb
Host smart-5524cc16-920c-4814-812d-bf1bff5814e6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657928970 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_re_evict.1657928970
Directory /workspace/1.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict_all_en.3870181449
Short name T354
Test name
Test status
Simulation time 43166800 ps
CPU time 28.95 seconds
Started Mar 21 03:18:47 PM PDT 24
Finished Mar 21 03:19:16 PM PDT 24
Peak memory 274616 kb
Host smart-33e7a486-d0a4-4555-abe8-ca1ba7b1e16c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870181449 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict_all_en.3870181449
Directory /workspace/29.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/19.flash_ctrl_re_evict.2469996325
Short name T350
Test name
Test status
Simulation time 182834500 ps
CPU time 36.3 seconds
Started Mar 21 03:17:39 PM PDT 24
Finished Mar 21 03:18:16 PM PDT 24
Peak memory 273544 kb
Host smart-90b5aabb-e9c8-46d7-ad0c-aef73c9a650d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469996325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl
ash_ctrl_re_evict.2469996325
Directory /workspace/19.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd_slow_flash.2496484814
Short name T31
Test name
Test status
Simulation time 8627756600 ps
CPU time 214.07 seconds
Started Mar 21 03:19:40 PM PDT 24
Finished Mar 21 03:23:15 PM PDT 24
Peak memory 289860 kb
Host smart-398d9e32-bb73-40c9-91fa-f7098e1945e4
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496484814 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd_slow_flash.2496484814
Directory /workspace/37.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_fetch_code.1118593012
Short name T50
Test name
Test status
Simulation time 1067853700 ps
CPU time 23.36 seconds
Started Mar 21 03:14:25 PM PDT 24
Finished Mar 21 03:14:50 PM PDT 24
Peak memory 265200 kb
Host smart-8258df43-f1ab-4919-bb2b-d9b6ba67027d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118593012 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetch_code.1118593012
Directory /workspace/8.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_ack_consistency.1836120762
Short name T64
Test name
Test status
Simulation time 15193900 ps
CPU time 14.38 seconds
Started Mar 21 03:12:20 PM PDT 24
Finished Mar 21 03:12:35 PM PDT 24
Peak memory 277032 kb
Host smart-31fab590-b3fa-44e3-a1b1-a87cb7683853
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1836120762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.1836120762
Directory /workspace/1.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.2041282695
Short name T275
Test name
Test status
Simulation time 47750700 ps
CPU time 18.82 seconds
Started Mar 21 01:47:58 PM PDT 24
Finished Mar 21 01:48:17 PM PDT 24
Peak memory 261428 kb
Host smart-bf7f5eaf-265c-4e4a-97ce-5506cd071599
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041282695 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.
2041282695
Directory /workspace/12.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/46.flash_ctrl_connect.536303298
Short name T105
Test name
Test status
Simulation time 48971500 ps
CPU time 16.17 seconds
Started Mar 21 03:20:00 PM PDT 24
Finished Mar 21 03:20:16 PM PDT 24
Peak memory 275824 kb
Host smart-f5d436af-f63d-4797-8e91-de0a7776ab1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536303298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.536303298
Directory /workspace/46.flash_ctrl_connect/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_info_access.1166444948
Short name T384
Test name
Test status
Simulation time 5475071100 ps
CPU time 70.8 seconds
Started Mar 21 03:12:07 PM PDT 24
Finished Mar 21 03:13:18 PM PDT 24
Peak memory 262644 kb
Host smart-899f8edc-94c2-4737-9f20-e077ff1b17b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166444948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.1166444948
Directory /workspace/1.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_type.4059196592
Short name T164
Test name
Test status
Simulation time 4529583200 ps
CPU time 2198.01 seconds
Started Mar 21 03:12:32 PM PDT 24
Finished Mar 21 03:49:11 PM PDT 24
Peak memory 261828 kb
Host smart-9e37b746-e9e6-4adc-b24e-66d5f9886b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059196592 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_type.4059196592
Directory /workspace/3.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.344451216
Short name T249
Test name
Test status
Simulation time 45932500 ps
CPU time 13.71 seconds
Started Mar 21 01:47:36 PM PDT 24
Finished Mar 21 01:47:50 PM PDT 24
Peak memory 261192 kb
Host smart-285fbf21-2eba-4baf-acea-b41ad9d1aaee
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344451216 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flas
h_ctrl_mem_partial_access.344451216
Directory /workspace/0.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_read_seed_err.2437427197
Short name T771
Test name
Test status
Simulation time 15450300 ps
CPU time 13.71 seconds
Started Mar 21 03:11:50 PM PDT 24
Finished Mar 21 03:12:05 PM PDT 24
Peak memory 265216 kb
Host smart-d6135433-c40f-40e5-bb1f-96b10abd40df
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437427197 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.2437427197
Directory /workspace/0.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_win.3168646783
Short name T577
Test name
Test status
Simulation time 717087400 ps
CPU time 870.28 seconds
Started Mar 21 03:11:56 PM PDT 24
Finished Mar 21 03:26:27 PM PDT 24
Peak memory 273404 kb
Host smart-7d3c0132-b5a3-4220-b307-9a501ad8add5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168646783 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.3168646783
Directory /workspace/0.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_serr.2407632850
Short name T111
Test name
Test status
Simulation time 2401992600 ps
CPU time 491.13 seconds
Started Mar 21 03:11:57 PM PDT 24
Finished Mar 21 03:20:08 PM PDT 24
Peak memory 314508 kb
Host smart-488abefb-9be8-47ac-8f7d-9661a3ab3b66
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407632850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_s
err.2407632850
Directory /workspace/0.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict_all_en.4182044509
Short name T48
Test name
Test status
Simulation time 33379600 ps
CPU time 31.28 seconds
Started Mar 21 03:15:46 PM PDT 24
Finished Mar 21 03:16:17 PM PDT 24
Peak memory 268316 kb
Host smart-d0bc122b-f5a8-45fe-bb1b-4383890e3ff0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182044509 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict_all_en.4182044509
Directory /workspace/12.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_host_grant_err.3224455980
Short name T112
Test name
Test status
Simulation time 42229500 ps
CPU time 13.98 seconds
Started Mar 21 03:12:22 PM PDT 24
Finished Mar 21 03:12:36 PM PDT 24
Peak memory 265448 kb
Host smart-2ee599f9-ff74-4899-851a-4e70bc736ebb
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224455980 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.3224455980
Directory /workspace/1.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_rd_buff_evict.2294645953
Short name T284
Test name
Test status
Simulation time 5765183100 ps
CPU time 130.7 seconds
Started Mar 21 03:13:12 PM PDT 24
Finished Mar 21 03:15:23 PM PDT 24
Peak memory 265212 kb
Host smart-8decaf2b-b6cb-4027-88cf-09ad0213fc98
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2294645953 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.2294645953
Directory /workspace/4.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_rma_reset.1510310235
Short name T141
Test name
Test status
Simulation time 40127413600 ps
CPU time 889.8 seconds
Started Mar 21 03:16:09 PM PDT 24
Finished Mar 21 03:30:59 PM PDT 24
Peak memory 263444 kb
Host smart-ed651a46-f1cb-48e1-a8fc-fdfb9cd4148c
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510310235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.flash_ctrl_hw_rma_reset.1510310235
Directory /workspace/14.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_lcmgr_intg.2511956046
Short name T299
Test name
Test status
Simulation time 79390600 ps
CPU time 13.4 seconds
Started Mar 21 03:14:20 PM PDT 24
Finished Mar 21 03:14:34 PM PDT 24
Peak memory 259740 kb
Host smart-a724f4b9-e423-4241-a051-26bf1cac2d2a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511956046 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.flash_ctrl_lcmgr_intg.2511956046
Directory /workspace/6.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/13.flash_ctrl_disable.2601407467
Short name T375
Test name
Test status
Simulation time 12933200 ps
CPU time 22.11 seconds
Started Mar 21 03:16:07 PM PDT 24
Finished Mar 21 03:16:29 PM PDT 24
Peak memory 265284 kb
Host smart-114c718e-5662-4705-bfb3-79334a411a31
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601407467 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_disable.2601407467
Directory /workspace/13.flash_ctrl_disable/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict_all_en.1694235974
Short name T14
Test name
Test status
Simulation time 78665200 ps
CPU time 31.63 seconds
Started Mar 21 03:19:26 PM PDT 24
Finished Mar 21 03:19:58 PM PDT 24
Peak memory 274572 kb
Host smart-b43c5efb-eafe-4d34-bb1e-40dc814c9f22
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694235974 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict_all_en.1694235974
Directory /workspace/34.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.41565358
Short name T295
Test name
Test status
Simulation time 10034587100 ps
CPU time 52.07 seconds
Started Mar 21 03:15:34 PM PDT 24
Finished Mar 21 03:16:27 PM PDT 24
Peak memory 271512 kb
Host smart-c5d46af6-a646-43a7-bdd9-ced3a7ec2c6f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41565358 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.41565358
Directory /workspace/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_read_seed_err.1018276265
Short name T872
Test name
Test status
Simulation time 15013600 ps
CPU time 13.66 seconds
Started Mar 21 03:15:24 PM PDT 24
Finished Mar 21 03:15:37 PM PDT 24
Peak memory 264776 kb
Host smart-ae529b3d-37bb-40aa-9eae-1a6713656d50
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018276265 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_seed_err.1018276265
Directory /workspace/10.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2596547897
Short name T368
Test name
Test status
Simulation time 2705965600 ps
CPU time 891.9 seconds
Started Mar 21 01:47:41 PM PDT 24
Finished Mar 21 02:02:33 PM PDT 24
Peak memory 264160 kb
Host smart-b5a4d85d-4040-4165-9331-b630c18c4cf7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596547897 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl
_tl_intg_err.2596547897
Directory /workspace/0.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2653912475
Short name T365
Test name
Test status
Simulation time 672193800 ps
CPU time 898.43 seconds
Started Mar 21 01:47:59 PM PDT 24
Finished Mar 21 02:02:57 PM PDT 24
Peak memory 264128 kb
Host smart-a8cdeb8f-0aa4-4763-952e-e6f93762d6bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653912475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctr
l_tl_intg_err.2653912475
Directory /workspace/11.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_mp_regions.306373151
Short name T85
Test name
Test status
Simulation time 69909143000 ps
CPU time 485.46 seconds
Started Mar 21 03:11:54 PM PDT 24
Finished Mar 21 03:20:01 PM PDT 24
Peak memory 274412 kb
Host smart-3d574f23-4329-403f-a14d-e6b8c6d7e490
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306373151 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_mp_regions.306373151
Directory /workspace/0.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/12.flash_ctrl_sec_info_access.3473693320
Short name T388
Test name
Test status
Simulation time 8824312800 ps
CPU time 75.58 seconds
Started Mar 21 03:15:49 PM PDT 24
Finished Mar 21 03:17:05 PM PDT 24
Peak memory 262432 kb
Host smart-ee108f2d-1401-41b9-b131-2306fc77ce13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473693320 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.3473693320
Directory /workspace/12.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/19.flash_ctrl_sec_info_access.3581945656
Short name T162
Test name
Test status
Simulation time 4087560100 ps
CPU time 69.77 seconds
Started Mar 21 03:17:38 PM PDT 24
Finished Mar 21 03:18:48 PM PDT 24
Peak memory 263112 kb
Host smart-e71bbe13-d012-4343-90c8-d6196a6555ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581945656 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.3581945656
Directory /workspace/19.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd_slow_flash.3166354507
Short name T29
Test name
Test status
Simulation time 16892530900 ps
CPU time 197.21 seconds
Started Mar 21 03:18:38 PM PDT 24
Finished Mar 21 03:21:55 PM PDT 24
Peak memory 284728 kb
Host smart-7fda39bf-fc4d-4fc0-aa31-87bc9b7e8fab
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166354507 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd_slow_flash.3166354507
Directory /workspace/28.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/44.flash_ctrl_sec_info_access.2784706282
Short name T392
Test name
Test status
Simulation time 2642490500 ps
CPU time 79.13 seconds
Started Mar 21 03:20:00 PM PDT 24
Finished Mar 21 03:21:19 PM PDT 24
Peak memory 263264 kb
Host smart-4e839ad7-9569-4cac-9baf-9ee41a4b483e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784706282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.2784706282
Directory /workspace/44.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/49.flash_ctrl_disable.3295831747
Short name T226
Test name
Test status
Simulation time 33533100 ps
CPU time 21.79 seconds
Started Mar 21 03:20:15 PM PDT 24
Finished Mar 21 03:20:37 PM PDT 24
Peak memory 265296 kb
Host smart-575b894d-f609-4f3b-8c09-263d8b0dfb33
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295831747 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.flash_ctrl_disable.3295831747
Directory /workspace/49.flash_ctrl_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_access_after_disable.3141485535
Short name T41
Test name
Test status
Simulation time 13913900 ps
CPU time 13.78 seconds
Started Mar 21 03:11:51 PM PDT 24
Finished Mar 21 03:12:07 PM PDT 24
Peak memory 265332 kb
Host smart-9ebacafb-c526-4985-8879-e0efa82d5ec1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141485535 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.3141485535
Directory /workspace/0.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_config_regwen.743122075
Short name T264
Test name
Test status
Simulation time 317701200 ps
CPU time 14.27 seconds
Started Mar 21 03:11:51 PM PDT 24
Finished Mar 21 03:12:08 PM PDT 24
Peak memory 261228 kb
Host smart-24b0fa54-fbbb-4850-8870-9c23fa57d50e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743122075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
flash_ctrl_config_regwen.743122075
Directory /workspace/0.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1711414775
Short name T1168
Test name
Test status
Simulation time 419540200 ps
CPU time 19.99 seconds
Started Mar 21 01:47:46 PM PDT 24
Finished Mar 21 01:48:06 PM PDT 24
Peak memory 261252 kb
Host smart-e8495095-ef41-481a-8cf4-f7a1fbe8f493
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711414775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.1
711414775
Directory /workspace/3.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_cm.1844119723
Short name T177
Test name
Test status
Simulation time 6238140200 ps
CPU time 4966.46 seconds
Started Mar 21 03:13:20 PM PDT 24
Finished Mar 21 04:36:07 PM PDT 24
Peak memory 294908 kb
Host smart-7ccaafe9-b604-404c-b4ca-64c6c1a9c15c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844119723 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.1844119723
Directory /workspace/4.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.3880011262
Short name T237
Test name
Test status
Simulation time 926907600 ps
CPU time 467.09 seconds
Started Mar 21 01:47:33 PM PDT 24
Finished Mar 21 01:55:22 PM PDT 24
Peak memory 264120 kb
Host smart-28a8b975-3155-403c-a9b2-bc7b6b95420d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880011262 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl
_tl_intg_err.3880011262
Directory /workspace/1.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_disable.1304548925
Short name T797
Test name
Test status
Simulation time 26583400 ps
CPU time 22.67 seconds
Started Mar 21 03:12:03 PM PDT 24
Finished Mar 21 03:12:26 PM PDT 24
Peak memory 280488 kb
Host smart-05c98782-91d6-48ba-a464-5f0e1569444e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304548925 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_disable.1304548925
Directory /workspace/1.flash_ctrl_disable/latest

Test location /workspace/coverage/default/12.flash_ctrl_disable.1616649594
Short name T1029
Test name
Test status
Simulation time 12894000 ps
CPU time 22.14 seconds
Started Mar 21 03:15:47 PM PDT 24
Finished Mar 21 03:16:09 PM PDT 24
Peak memory 280320 kb
Host smart-1df211f9-1b3f-4c81-888c-49f0a695c134
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616649594 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_disable.1616649594
Directory /workspace/12.flash_ctrl_disable/latest

Test location /workspace/coverage/default/16.flash_ctrl_disable.1452512138
Short name T564
Test name
Test status
Simulation time 121994700 ps
CPU time 21.68 seconds
Started Mar 21 03:16:45 PM PDT 24
Finished Mar 21 03:17:07 PM PDT 24
Peak memory 273728 kb
Host smart-a7cf50b4-e8fc-4c1a-b0f8-e30d9e162729
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452512138 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_disable.1452512138
Directory /workspace/16.flash_ctrl_disable/latest

Test location /workspace/coverage/default/17.flash_ctrl_disable.1471812400
Short name T567
Test name
Test status
Simulation time 31959300 ps
CPU time 21.89 seconds
Started Mar 21 03:17:03 PM PDT 24
Finished Mar 21 03:17:25 PM PDT 24
Peak memory 265284 kb
Host smart-dfca67f5-478e-49e2-a7b2-6709453e5bb7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471812400 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_disable.1471812400
Directory /workspace/17.flash_ctrl_disable/latest

Test location /workspace/coverage/default/25.flash_ctrl_disable.1476122281
Short name T827
Test name
Test status
Simulation time 35341600 ps
CPU time 21.81 seconds
Started Mar 21 03:18:16 PM PDT 24
Finished Mar 21 03:18:38 PM PDT 24
Peak memory 280568 kb
Host smart-3710b6db-6f1c-4f3c-91ed-574c1e87e07a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476122281 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.flash_ctrl_disable.1476122281
Directory /workspace/25.flash_ctrl_disable/latest

Test location /workspace/coverage/default/32.flash_ctrl_sec_info_access.2578324180
Short name T383
Test name
Test status
Simulation time 2865039600 ps
CPU time 64.27 seconds
Started Mar 21 03:19:25 PM PDT 24
Finished Mar 21 03:20:29 PM PDT 24
Peak memory 262484 kb
Host smart-cf612853-ee97-42fa-a682-61707141276f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578324180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.2578324180
Directory /workspace/32.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/36.flash_ctrl_sec_info_access.3424538893
Short name T397
Test name
Test status
Simulation time 534832800 ps
CPU time 63.18 seconds
Started Mar 21 03:19:36 PM PDT 24
Finished Mar 21 03:20:41 PM PDT 24
Peak memory 263280 kb
Host smart-4ca9d462-849f-4ea6-b4f1-05e87be03c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424538893 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.3424538893
Directory /workspace/36.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr.129163448
Short name T24
Test name
Test status
Simulation time 3948003300 ps
CPU time 96.68 seconds
Started Mar 21 03:12:04 PM PDT 24
Finished Mar 21 03:13:41 PM PDT 24
Peak memory 260552 kb
Host smart-d8714619-0f95-4968-8180-7416682b3fad
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129163448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.flash_ctrl_intr_wr.129163448
Directory /workspace/1.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_serr.983765452
Short name T205
Test name
Test status
Simulation time 3464981600 ps
CPU time 569.53 seconds
Started Mar 21 03:12:25 PM PDT 24
Finished Mar 21 03:21:55 PM PDT 24
Peak memory 312132 kb
Host smart-f0a19870-8c77-402c-ab21-814077b9e566
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983765452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_se
rr.983765452
Directory /workspace/2.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.62401391
Short name T113
Test name
Test status
Simulation time 47214800 ps
CPU time 15.04 seconds
Started Mar 21 03:12:58 PM PDT 24
Finished Mar 21 03:13:14 PM PDT 24
Peak memory 265444 kb
Host smart-0a6014f8-f84c-46d4-81ea-bf494f5cc269
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=62401391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.62401391
Directory /workspace/3.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma_reset.609187473
Short name T139
Test name
Test status
Simulation time 40127721800 ps
CPU time 884.75 seconds
Started Mar 21 03:11:51 PM PDT 24
Finished Mar 21 03:26:38 PM PDT 24
Peak memory 263152 kb
Host smart-ddb10328-86b3-4854-b3c8-9558108562b5
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609187473 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_hw_rma_reset.609187473
Directory /workspace/0.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2449635182
Short name T59
Test name
Test status
Simulation time 111033900 ps
CPU time 30.94 seconds
Started Mar 21 01:47:39 PM PDT 24
Finished Mar 21 01:48:10 PM PDT 24
Peak memory 260672 kb
Host smart-86770fab-fb1a-40db-a309-2bae4aa3af5a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449635182 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_hw_reset.2449635182
Directory /workspace/0.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.2299001626
Short name T1182
Test name
Test status
Simulation time 200709800 ps
CPU time 18.97 seconds
Started Mar 21 01:47:58 PM PDT 24
Finished Mar 21 01:48:17 PM PDT 24
Peak memory 264140 kb
Host smart-3a678d49-0cf9-43f9-8805-7de78a3d12da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299001626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.
2299001626
Directory /workspace/11.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_mp.3767412993
Short name T458
Test name
Test status
Simulation time 162919453600 ps
CPU time 2614.25 seconds
Started Mar 21 03:11:49 PM PDT 24
Finished Mar 21 03:55:25 PM PDT 24
Peak memory 265108 kb
Host smart-a181ba6e-e35b-4fb7-924d-4e39c8acb1b8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767412993 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_err
or_mp.3767412993
Directory /workspace/0.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/0.flash_ctrl_full_mem_access.3551284094
Short name T81
Test name
Test status
Simulation time 106194103600 ps
CPU time 2723.58 seconds
Started Mar 21 03:11:51 PM PDT 24
Finished Mar 21 03:57:17 PM PDT 24
Peak memory 265108 kb
Host smart-c0ad5ceb-b5f5-4b0a-af51-a703e8537b90
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551284094 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_c
trl_full_mem_access.3551284094
Directory /workspace/0.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_ctrl_arb.1757260248
Short name T173
Test name
Test status
Simulation time 282835418600 ps
CPU time 3107.5 seconds
Started Mar 21 03:11:52 PM PDT 24
Finished Mar 21 04:03:42 PM PDT 24
Peak memory 265204 kb
Host smart-ca4eae51-62e2-4c26-8ad8-583406d6acd7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757260248 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.flash_ctrl_host_ctrl_arb.1757260248
Directory /workspace/0.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_ctrl_arb.1527268610
Short name T199
Test name
Test status
Simulation time 231928733800 ps
CPU time 2579.83 seconds
Started Mar 21 03:12:03 PM PDT 24
Finished Mar 21 03:55:03 PM PDT 24
Peak memory 262288 kb
Host smart-68a7b1b7-b79b-49fd-8c10-efcce5625cb3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527268610 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.flash_ctrl_host_ctrl_arb.1527268610
Directory /workspace/1.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro.3756265601
Short name T104
Test name
Test status
Simulation time 455094200 ps
CPU time 107.48 seconds
Started Mar 21 03:12:06 PM PDT 24
Finished Mar 21 03:13:54 PM PDT 24
Peak memory 281124 kb
Host smart-d7c79cce-cf61-41f0-ae73-5856bd6e88a3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756265601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.flash_ctrl_ro.3756265601
Directory /workspace/1.flash_ctrl_ro/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_ctrl_arb.3766111246
Short name T200
Test name
Test status
Simulation time 2009567874500 ps
CPU time 2042.81 seconds
Started Mar 21 03:12:29 PM PDT 24
Finished Mar 21 03:46:32 PM PDT 24
Peak memory 265152 kb
Host smart-a725e08c-d22e-4893-8dc6-edefc7827c63
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766111246 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.flash_ctrl_host_ctrl_arb.3766111246
Directory /workspace/3.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.1479811513
Short name T198
Test name
Test status
Simulation time 52504000 ps
CPU time 13.98 seconds
Started Mar 21 03:12:57 PM PDT 24
Finished Mar 21 03:13:12 PM PDT 24
Peak memory 265424 kb
Host smart-26ad1901-704b-45e4-9a8b-13ff7e541220
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479811513 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.1479811513
Directory /workspace/3.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.984009440
Short name T1115
Test name
Test status
Simulation time 223822900 ps
CPU time 33.99 seconds
Started Mar 21 01:47:36 PM PDT 24
Finished Mar 21 01:48:10 PM PDT 24
Peak memory 260612 kb
Host smart-40147f01-8a91-4d4c-ada4-4d8eaee3959b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984009440 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.flash_ctrl_csr_aliasing.984009440
Directory /workspace/0.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.368821650
Short name T58
Test name
Test status
Simulation time 13814001800 ps
CPU time 54.96 seconds
Started Mar 21 01:47:34 PM PDT 24
Finished Mar 21 01:48:29 PM PDT 24
Peak memory 260616 kb
Host smart-664ecedf-ce3c-4941-9657-9b6d633a690f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368821650 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.flash_ctrl_csr_bit_bash.368821650
Directory /workspace/0.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.984621140
Short name T268
Test name
Test status
Simulation time 152016200 ps
CPU time 18.84 seconds
Started Mar 21 01:47:39 PM PDT 24
Finished Mar 21 01:47:58 PM PDT 24
Peak memory 272288 kb
Host smart-dc0f5cbe-f0ad-4026-9d84-f5ef04d6d5ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984621140 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.984621140
Directory /workspace/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.523330486
Short name T1102
Test name
Test status
Simulation time 75803200 ps
CPU time 14.09 seconds
Started Mar 21 01:47:36 PM PDT 24
Finished Mar 21 01:47:51 PM PDT 24
Peak memory 260580 kb
Host smart-522280f4-b7dc-4296-8f45-a923cf3aedf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523330486 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 0.flash_ctrl_csr_rw.523330486
Directory /workspace/0.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.861145001
Short name T1075
Test name
Test status
Simulation time 27690300 ps
CPU time 13.45 seconds
Started Mar 21 01:47:35 PM PDT 24
Finished Mar 21 01:47:49 PM PDT 24
Peak memory 261196 kb
Host smart-1e3d787f-a1fc-484c-8bb1-17c2c91b16ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861145001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.861145001
Directory /workspace/0.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.4104333256
Short name T1092
Test name
Test status
Simulation time 21219700 ps
CPU time 13.67 seconds
Started Mar 21 01:47:35 PM PDT 24
Finished Mar 21 01:47:49 PM PDT 24
Peak memory 261068 kb
Host smart-9bdbfe62-309c-45b6-abb1-1f5b198ee45c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104333256 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_me
m_walk.4104333256
Directory /workspace/0.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.1111146322
Short name T252
Test name
Test status
Simulation time 168138400 ps
CPU time 18.56 seconds
Started Mar 21 01:47:33 PM PDT 24
Finished Mar 21 01:47:52 PM PDT 24
Peak memory 262004 kb
Host smart-3b72636e-8221-4c76-9434-1c74810042c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111146322 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.flash_ctrl_same_csr_outstanding.1111146322
Directory /workspace/0.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.3752718643
Short name T1048
Test name
Test status
Simulation time 68962200 ps
CPU time 15.55 seconds
Started Mar 21 01:47:41 PM PDT 24
Finished Mar 21 01:47:57 PM PDT 24
Peak memory 260656 kb
Host smart-b28f4c42-548c-4143-9b6a-f0c9ade64a81
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752718643 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors.3752718643
Directory /workspace/0.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.874058905
Short name T1061
Test name
Test status
Simulation time 32869700 ps
CPU time 13.27 seconds
Started Mar 21 01:47:40 PM PDT 24
Finished Mar 21 01:47:53 PM PDT 24
Peak memory 260548 kb
Host smart-6dbb9d3a-f497-4554-97f9-9b78d1f3ec44
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874058905 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors_with_csr_rw.874058905
Directory /workspace/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.2384173376
Short name T271
Test name
Test status
Simulation time 58408600 ps
CPU time 15.96 seconds
Started Mar 21 01:47:42 PM PDT 24
Finished Mar 21 01:47:58 PM PDT 24
Peak memory 264160 kb
Host smart-f7fe4b81-34d9-4740-b2cf-cd7b602e7d46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384173376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.2
384173376
Directory /workspace/0.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2869808206
Short name T404
Test name
Test status
Simulation time 5356396500 ps
CPU time 43.9 seconds
Started Mar 21 01:47:37 PM PDT 24
Finished Mar 21 01:48:22 PM PDT 24
Peak memory 260680 kb
Host smart-cdf69a3e-a2d4-47e7-9bc6-27f761a19c32
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869808206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_aliasing.2869808206
Directory /workspace/1.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3563553898
Short name T1126
Test name
Test status
Simulation time 674059500 ps
CPU time 62.91 seconds
Started Mar 21 01:47:33 PM PDT 24
Finished Mar 21 01:48:37 PM PDT 24
Peak memory 260644 kb
Host smart-f789499f-7f2b-4971-bfd4-6df4b7149405
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563553898 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_bit_bash.3563553898
Directory /workspace/1.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.1729261550
Short name T1167
Test name
Test status
Simulation time 214968300 ps
CPU time 38.16 seconds
Started Mar 21 01:47:33 PM PDT 24
Finished Mar 21 01:48:12 PM PDT 24
Peak memory 260700 kb
Host smart-58e9f21c-3952-4d69-aee6-5c990b1e6af3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729261550 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_hw_reset.1729261550
Directory /workspace/1.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.2344168585
Short name T1083
Test name
Test status
Simulation time 186840900 ps
CPU time 18.69 seconds
Started Mar 21 01:47:45 PM PDT 24
Finished Mar 21 01:48:04 PM PDT 24
Peak memory 277612 kb
Host smart-1fe11a6a-e4a0-44d9-a3c3-819d4932715e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344168585 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.2344168585
Directory /workspace/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1678091976
Short name T255
Test name
Test status
Simulation time 42847700 ps
CPU time 16.63 seconds
Started Mar 21 01:47:36 PM PDT 24
Finished Mar 21 01:47:54 PM PDT 24
Peak memory 264068 kb
Host smart-aeca1ddc-92bb-429e-b8a5-7ccb8e09673b
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678091976 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.flash_ctrl_csr_rw.1678091976
Directory /workspace/1.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.3564326212
Short name T269
Test name
Test status
Simulation time 54806400 ps
CPU time 13.25 seconds
Started Mar 21 01:47:34 PM PDT 24
Finished Mar 21 01:47:48 PM PDT 24
Peak memory 261484 kb
Host smart-b0819b38-7a10-4e61-9e3a-176098d09c38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564326212 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.3
564326212
Directory /workspace/1.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2613507904
Short name T1184
Test name
Test status
Simulation time 51003800 ps
CPU time 13.63 seconds
Started Mar 21 01:47:35 PM PDT 24
Finished Mar 21 01:47:48 PM PDT 24
Peak memory 261048 kb
Host smart-bf3de825-9116-48fc-ae7e-e1a06ca9ff45
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613507904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_me
m_walk.2613507904
Directory /workspace/1.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.122302532
Short name T256
Test name
Test status
Simulation time 2160107800 ps
CPU time 30.2 seconds
Started Mar 21 01:47:35 PM PDT 24
Finished Mar 21 01:48:05 PM PDT 24
Peak memory 262128 kb
Host smart-24d077b7-c10b-48ef-966b-055f6af66432
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122302532 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.flash_ctrl_same_csr_outstanding.122302532
Directory /workspace/1.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2662666881
Short name T1136
Test name
Test status
Simulation time 16580200 ps
CPU time 15.65 seconds
Started Mar 21 01:47:35 PM PDT 24
Finished Mar 21 01:47:51 PM PDT 24
Peak memory 260556 kb
Host smart-2820d712-9fa8-491b-8fe6-b13ba0a57aef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662666881 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors.2662666881
Directory /workspace/1.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3790837883
Short name T1137
Test name
Test status
Simulation time 12431300 ps
CPU time 16.02 seconds
Started Mar 21 01:47:38 PM PDT 24
Finished Mar 21 01:47:54 PM PDT 24
Peak memory 260492 kb
Host smart-a19b7bf1-1283-4a91-851e-e7b5c683a906
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790837883 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors_with_csr_rw.3790837883
Directory /workspace/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1693934181
Short name T245
Test name
Test status
Simulation time 206388500 ps
CPU time 19.43 seconds
Started Mar 21 01:47:33 PM PDT 24
Finished Mar 21 01:47:53 PM PDT 24
Peak memory 264168 kb
Host smart-824a896d-2232-4fbe-91be-43308507f6a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693934181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.1
693934181
Directory /workspace/1.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.682167918
Short name T1128
Test name
Test status
Simulation time 91792000 ps
CPU time 17.23 seconds
Started Mar 21 01:48:03 PM PDT 24
Finished Mar 21 01:48:20 PM PDT 24
Peak memory 272336 kb
Host smart-4b7bce39-1abc-41fd-930e-ca039a65d0c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682167918 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.682167918
Directory /workspace/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.4100046391
Short name T1132
Test name
Test status
Simulation time 36632100 ps
CPU time 17.07 seconds
Started Mar 21 01:47:57 PM PDT 24
Finished Mar 21 01:48:14 PM PDT 24
Peak memory 260604 kb
Host smart-39bdcdf4-073e-4b63-876b-43386734668d
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100046391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.flash_ctrl_csr_rw.4100046391
Directory /workspace/10.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.1972205077
Short name T1118
Test name
Test status
Simulation time 23953600 ps
CPU time 13.44 seconds
Started Mar 21 01:48:02 PM PDT 24
Finished Mar 21 01:48:15 PM PDT 24
Peak memory 261128 kb
Host smart-bf1190cb-f401-44f6-a95d-a2fae1e6c20a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972205077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.
1972205077
Directory /workspace/10.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.2082074254
Short name T1099
Test name
Test status
Simulation time 300475500 ps
CPU time 34.59 seconds
Started Mar 21 01:47:56 PM PDT 24
Finished Mar 21 01:48:30 PM PDT 24
Peak memory 260724 kb
Host smart-8e4c582a-5c21-4776-9157-e403acb329b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082074254 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.flash_ctrl_same_csr_outstanding.2082074254
Directory /workspace/10.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.3387974626
Short name T1143
Test name
Test status
Simulation time 27553600 ps
CPU time 15.91 seconds
Started Mar 21 01:47:58 PM PDT 24
Finished Mar 21 01:48:14 PM PDT 24
Peak memory 260624 kb
Host smart-14855644-a5fb-4919-b6f8-2d741724096f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387974626 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors.3387974626
Directory /workspace/10.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.4047078318
Short name T1152
Test name
Test status
Simulation time 20194100 ps
CPU time 15.81 seconds
Started Mar 21 01:47:56 PM PDT 24
Finished Mar 21 01:48:12 PM PDT 24
Peak memory 260652 kb
Host smart-f0589660-eca6-4a2d-bd7a-eccc08b95747
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047078318 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors_with_csr_rw.4047078318
Directory /workspace/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1982682315
Short name T239
Test name
Test status
Simulation time 246650000 ps
CPU time 16.21 seconds
Started Mar 21 01:47:57 PM PDT 24
Finished Mar 21 01:48:14 PM PDT 24
Peak memory 261248 kb
Host smart-e7db7eff-f2cf-4264-b0af-b560758d4697
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982682315 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.
1982682315
Directory /workspace/10.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.980564087
Short name T1112
Test name
Test status
Simulation time 325460500 ps
CPU time 457.74 seconds
Started Mar 21 01:47:56 PM PDT 24
Finished Mar 21 01:55:34 PM PDT 24
Peak memory 264164 kb
Host smart-f002df44-20e6-4487-8c7a-6dc1ad537d14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980564087 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl
_tl_intg_err.980564087
Directory /workspace/10.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.2430866577
Short name T1097
Test name
Test status
Simulation time 187117100 ps
CPU time 17.6 seconds
Started Mar 21 01:47:58 PM PDT 24
Finished Mar 21 01:48:15 PM PDT 24
Peak memory 264148 kb
Host smart-01bb6b51-086f-4345-93e9-12bd5777d5ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430866577 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.2430866577
Directory /workspace/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1734689545
Short name T259
Test name
Test status
Simulation time 40317400 ps
CPU time 16.49 seconds
Started Mar 21 01:48:02 PM PDT 24
Finished Mar 21 01:48:19 PM PDT 24
Peak memory 260724 kb
Host smart-17167aec-c407-4276-9965-b5eb44dc1638
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734689545 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.flash_ctrl_csr_rw.1734689545
Directory /workspace/11.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.112806370
Short name T1158
Test name
Test status
Simulation time 46945600 ps
CPU time 13.47 seconds
Started Mar 21 01:47:55 PM PDT 24
Finished Mar 21 01:48:09 PM PDT 24
Peak memory 261144 kb
Host smart-686e5ea6-57df-4c9e-8ee9-4b0e797c9bd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112806370 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.112806370
Directory /workspace/11.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.618445209
Short name T309
Test name
Test status
Simulation time 228615100 ps
CPU time 18.82 seconds
Started Mar 21 01:47:57 PM PDT 24
Finished Mar 21 01:48:16 PM PDT 24
Peak memory 260720 kb
Host smart-7aad71fb-923b-4833-8d40-758f83659222
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618445209 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.flash_ctrl_same_csr_outstanding.618445209
Directory /workspace/11.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3019395204
Short name T1187
Test name
Test status
Simulation time 40549900 ps
CPU time 15.71 seconds
Started Mar 21 01:47:57 PM PDT 24
Finished Mar 21 01:48:13 PM PDT 24
Peak memory 260540 kb
Host smart-daa28c4e-43ac-474f-bc0b-648a5ace483b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019395204 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors.3019395204
Directory /workspace/11.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.708690022
Short name T1090
Test name
Test status
Simulation time 13897600 ps
CPU time 13.26 seconds
Started Mar 21 01:47:58 PM PDT 24
Finished Mar 21 01:48:11 PM PDT 24
Peak memory 260544 kb
Host smart-ffb1ed07-2f4d-4216-86b8-99c9ccafc6cc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708690022 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors_with_csr_rw.708690022
Directory /workspace/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2669381723
Short name T1084
Test name
Test status
Simulation time 148563800 ps
CPU time 19.91 seconds
Started Mar 21 01:47:58 PM PDT 24
Finished Mar 21 01:48:18 PM PDT 24
Peak memory 279184 kb
Host smart-c3815c98-e771-421e-9664-41bfad3cb232
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669381723 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.2669381723
Directory /workspace/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.1312821224
Short name T1157
Test name
Test status
Simulation time 35084300 ps
CPU time 16.67 seconds
Started Mar 21 01:47:58 PM PDT 24
Finished Mar 21 01:48:15 PM PDT 24
Peak memory 260608 kb
Host smart-1fc38f6b-cbd4-4aef-b272-2c0016e19815
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312821224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.flash_ctrl_csr_rw.1312821224
Directory /workspace/12.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.1970532124
Short name T1052
Test name
Test status
Simulation time 52200000 ps
CPU time 13.41 seconds
Started Mar 21 01:47:57 PM PDT 24
Finished Mar 21 01:48:11 PM PDT 24
Peak memory 261068 kb
Host smart-676b1281-513e-4161-8dcb-2497d378978a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970532124 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.
1970532124
Directory /workspace/12.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1673247896
Short name T1091
Test name
Test status
Simulation time 1656800600 ps
CPU time 36.4 seconds
Started Mar 21 01:47:55 PM PDT 24
Finished Mar 21 01:48:32 PM PDT 24
Peak memory 260628 kb
Host smart-73b479a5-3280-4292-bf9b-8950f63653ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673247896 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.flash_ctrl_same_csr_outstanding.1673247896
Directory /workspace/12.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.1146065842
Short name T1145
Test name
Test status
Simulation time 44036100 ps
CPU time 15.77 seconds
Started Mar 21 01:47:55 PM PDT 24
Finished Mar 21 01:48:10 PM PDT 24
Peak memory 260528 kb
Host smart-dd34d06f-07ec-4d37-b27d-8c0816ace166
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146065842 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors.1146065842
Directory /workspace/12.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.610628528
Short name T1107
Test name
Test status
Simulation time 24914300 ps
CPU time 13.27 seconds
Started Mar 21 01:47:58 PM PDT 24
Finished Mar 21 01:48:12 PM PDT 24
Peak memory 260536 kb
Host smart-1cf891dd-c387-4020-bb3c-1e1c171c7508
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610628528 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors_with_csr_rw.610628528
Directory /workspace/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2533222448
Short name T367
Test name
Test status
Simulation time 789750400 ps
CPU time 460.66 seconds
Started Mar 21 01:47:57 PM PDT 24
Finished Mar 21 01:55:38 PM PDT 24
Peak memory 264156 kb
Host smart-32fd973b-8003-465a-8448-cb01b0df0101
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533222448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctr
l_tl_intg_err.2533222448
Directory /workspace/12.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.1805062781
Short name T1089
Test name
Test status
Simulation time 42621800 ps
CPU time 18.97 seconds
Started Mar 21 01:48:10 PM PDT 24
Finished Mar 21 01:48:29 PM PDT 24
Peak memory 272244 kb
Host smart-23292b66-3f47-4fed-a670-3808e1e9752b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805062781 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.1805062781
Directory /workspace/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.3469859320
Short name T1146
Test name
Test status
Simulation time 20063000 ps
CPU time 16.14 seconds
Started Mar 21 01:48:11 PM PDT 24
Finished Mar 21 01:48:27 PM PDT 24
Peak memory 260692 kb
Host smart-e28238b3-569f-4d66-b8a8-6a43f0c8dc09
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469859320 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.flash_ctrl_csr_rw.3469859320
Directory /workspace/13.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.715704877
Short name T1096
Test name
Test status
Simulation time 32281500 ps
CPU time 13.4 seconds
Started Mar 21 01:48:06 PM PDT 24
Finished Mar 21 01:48:19 PM PDT 24
Peak memory 261180 kb
Host smart-d2d731ba-1e9a-478e-ba0a-83556d6cf9d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715704877 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.715704877
Directory /workspace/13.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.2314109978
Short name T1103
Test name
Test status
Simulation time 68199100 ps
CPU time 28.76 seconds
Started Mar 21 01:48:08 PM PDT 24
Finished Mar 21 01:48:37 PM PDT 24
Peak memory 260720 kb
Host smart-40669b0e-5711-4cf4-8a03-9cca7beb4369
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314109978 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.flash_ctrl_same_csr_outstanding.2314109978
Directory /workspace/13.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.1090295706
Short name T1162
Test name
Test status
Simulation time 12278000 ps
CPU time 15.93 seconds
Started Mar 21 01:48:09 PM PDT 24
Finished Mar 21 01:48:25 PM PDT 24
Peak memory 260596 kb
Host smart-4a6e0049-dc63-4040-bf1f-7f0bba95fa86
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090295706 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors.1090295706
Directory /workspace/13.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.105443851
Short name T1071
Test name
Test status
Simulation time 37587800 ps
CPU time 16.1 seconds
Started Mar 21 01:48:12 PM PDT 24
Finished Mar 21 01:48:28 PM PDT 24
Peak memory 260652 kb
Host smart-af1bccf9-3c77-4ecf-a1cd-145823a44874
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105443851 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors_with_csr_rw.105443851
Directory /workspace/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1781300705
Short name T370
Test name
Test status
Simulation time 679721000 ps
CPU time 756.36 seconds
Started Mar 21 01:48:12 PM PDT 24
Finished Mar 21 02:00:49 PM PDT 24
Peak memory 260632 kb
Host smart-984cf7e9-1f84-4c44-ac77-1e677ad287cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781300705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctr
l_tl_intg_err.1781300705
Directory /workspace/13.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.8079810
Short name T1114
Test name
Test status
Simulation time 215406500 ps
CPU time 15.27 seconds
Started Mar 21 01:48:08 PM PDT 24
Finished Mar 21 01:48:24 PM PDT 24
Peak memory 272376 kb
Host smart-2b5b5330-de41-4725-8728-34a2574dade6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8079810 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.8079810
Directory /workspace/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.27327080
Short name T1129
Test name
Test status
Simulation time 124216100 ps
CPU time 18.17 seconds
Started Mar 21 01:48:10 PM PDT 24
Finished Mar 21 01:48:29 PM PDT 24
Peak memory 260712 kb
Host smart-79454d28-f6b5-4c1c-91b1-69163a410a10
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27327080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 14.flash_ctrl_csr_rw.27327080
Directory /workspace/14.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.1257834495
Short name T1087
Test name
Test status
Simulation time 51827600 ps
CPU time 13.68 seconds
Started Mar 21 01:48:12 PM PDT 24
Finished Mar 21 01:48:26 PM PDT 24
Peak memory 261092 kb
Host smart-4a115fea-b448-49d0-aa22-268dfd845c76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257834495 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.
1257834495
Directory /workspace/14.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1229901525
Short name T1155
Test name
Test status
Simulation time 202299500 ps
CPU time 33.77 seconds
Started Mar 21 01:48:12 PM PDT 24
Finished Mar 21 01:48:46 PM PDT 24
Peak memory 260596 kb
Host smart-62064afa-7ab5-4bd3-ac6e-aa0e3c36caec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229901525 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.flash_ctrl_same_csr_outstanding.1229901525
Directory /workspace/14.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2063603700
Short name T1188
Test name
Test status
Simulation time 22696200 ps
CPU time 13.49 seconds
Started Mar 21 01:48:11 PM PDT 24
Finished Mar 21 01:48:25 PM PDT 24
Peak memory 260568 kb
Host smart-6a647f0d-0b27-4fc9-a979-6f4149eef5a5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063603700 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors.2063603700
Directory /workspace/14.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.644640575
Short name T1047
Test name
Test status
Simulation time 29366500 ps
CPU time 15.97 seconds
Started Mar 21 01:48:08 PM PDT 24
Finished Mar 21 01:48:24 PM PDT 24
Peak memory 260608 kb
Host smart-12f70b0d-d3b8-478f-9cd5-b6e76ddd5e7f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644640575 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors_with_csr_rw.644640575
Directory /workspace/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.3546114973
Short name T172
Test name
Test status
Simulation time 298179100 ps
CPU time 16.06 seconds
Started Mar 21 01:48:09 PM PDT 24
Finished Mar 21 01:48:25 PM PDT 24
Peak memory 261344 kb
Host smart-ffb2544d-e518-4a7d-8487-a32ede093dd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546114973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.
3546114973
Directory /workspace/14.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.1265019559
Short name T1190
Test name
Test status
Simulation time 427684700 ps
CPU time 454.32 seconds
Started Mar 21 01:48:08 PM PDT 24
Finished Mar 21 01:55:43 PM PDT 24
Peak memory 264060 kb
Host smart-25005e50-9a02-46b2-b635-e84f820dbc0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265019559 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctr
l_tl_intg_err.1265019559
Directory /workspace/14.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.1223869678
Short name T1151
Test name
Test status
Simulation time 619491300 ps
CPU time 18.28 seconds
Started Mar 21 01:48:20 PM PDT 24
Finished Mar 21 01:48:38 PM PDT 24
Peak memory 272336 kb
Host smart-b1fa4b0b-c5e3-4eb2-81f8-70c4ed450a55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223869678 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.1223869678
Directory /workspace/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.35502859
Short name T257
Test name
Test status
Simulation time 37077300 ps
CPU time 13.76 seconds
Started Mar 21 01:48:08 PM PDT 24
Finished Mar 21 01:48:21 PM PDT 24
Peak memory 260584 kb
Host smart-e5bd50d5-8836-492a-8734-bf9a1ca9967e
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35502859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 15.flash_ctrl_csr_rw.35502859
Directory /workspace/15.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.1638741195
Short name T1066
Test name
Test status
Simulation time 29355300 ps
CPU time 14.01 seconds
Started Mar 21 01:48:11 PM PDT 24
Finished Mar 21 01:48:26 PM PDT 24
Peak memory 261084 kb
Host smart-386e3e9f-0c22-4c76-b497-3148fd057aed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638741195 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.
1638741195
Directory /workspace/15.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2540616514
Short name T1077
Test name
Test status
Simulation time 88505700 ps
CPU time 17.37 seconds
Started Mar 21 01:48:21 PM PDT 24
Finished Mar 21 01:48:38 PM PDT 24
Peak memory 262160 kb
Host smart-80ec4050-68bf-4737-ab94-b08e5569e4c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540616514 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.flash_ctrl_same_csr_outstanding.2540616514
Directory /workspace/15.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2826081045
Short name T1094
Test name
Test status
Simulation time 30899700 ps
CPU time 15.87 seconds
Started Mar 21 01:48:09 PM PDT 24
Finished Mar 21 01:48:25 PM PDT 24
Peak memory 260568 kb
Host smart-57306f49-0895-4d37-9787-ae89aedef4e9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826081045 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors.2826081045
Directory /workspace/15.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.2719601906
Short name T1164
Test name
Test status
Simulation time 18486800 ps
CPU time 15.66 seconds
Started Mar 21 01:48:11 PM PDT 24
Finished Mar 21 01:48:27 PM PDT 24
Peak memory 260548 kb
Host smart-821e9f7e-afdb-4670-a31a-ce693ca5a700
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719601906 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors_with_csr_rw.2719601906
Directory /workspace/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.3495410341
Short name T280
Test name
Test status
Simulation time 77254300 ps
CPU time 17.01 seconds
Started Mar 21 01:48:12 PM PDT 24
Finished Mar 21 01:48:29 PM PDT 24
Peak memory 261420 kb
Host smart-43202312-8878-4ad0-bdb2-f328bd1fe163
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495410341 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.
3495410341
Directory /workspace/15.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.1332676082
Short name T224
Test name
Test status
Simulation time 576349400 ps
CPU time 18.65 seconds
Started Mar 21 01:48:22 PM PDT 24
Finished Mar 21 01:48:41 PM PDT 24
Peak memory 270664 kb
Host smart-fc275fc2-a9c6-4c33-87bf-93520bd5379c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332676082 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.1332676082
Directory /workspace/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.2600492077
Short name T1161
Test name
Test status
Simulation time 76243100 ps
CPU time 18.71 seconds
Started Mar 21 01:48:21 PM PDT 24
Finished Mar 21 01:48:40 PM PDT 24
Peak memory 264188 kb
Host smart-b327393d-ee84-49ba-9f4f-3e14d92b6b50
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600492077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.flash_ctrl_csr_rw.2600492077
Directory /workspace/16.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.1127189932
Short name T1065
Test name
Test status
Simulation time 15498400 ps
CPU time 13.29 seconds
Started Mar 21 01:48:23 PM PDT 24
Finished Mar 21 01:48:36 PM PDT 24
Peak memory 261076 kb
Host smart-bb381d24-d154-455a-8f56-9ba7656f18b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127189932 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test.
1127189932
Directory /workspace/16.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2197401185
Short name T1101
Test name
Test status
Simulation time 187849200 ps
CPU time 18.57 seconds
Started Mar 21 01:48:23 PM PDT 24
Finished Mar 21 01:48:41 PM PDT 24
Peak memory 260728 kb
Host smart-485d8a3a-d463-4c55-84c6-df14003ebd7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197401185 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.flash_ctrl_same_csr_outstanding.2197401185
Directory /workspace/16.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.2698187072
Short name T1050
Test name
Test status
Simulation time 14068000 ps
CPU time 15.78 seconds
Started Mar 21 01:48:22 PM PDT 24
Finished Mar 21 01:48:38 PM PDT 24
Peak memory 260568 kb
Host smart-d3adf0cd-e6f6-4913-b7e0-aff6172fbbb4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698187072 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors.2698187072
Directory /workspace/16.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2318668469
Short name T1160
Test name
Test status
Simulation time 14012700 ps
CPU time 15.76 seconds
Started Mar 21 01:48:20 PM PDT 24
Finished Mar 21 01:48:36 PM PDT 24
Peak memory 260564 kb
Host smart-c7b253df-2055-42f5-83fe-47a952cb13f7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318668469 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors_with_csr_rw.2318668469
Directory /workspace/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.3350756693
Short name T169
Test name
Test status
Simulation time 61408500 ps
CPU time 16.57 seconds
Started Mar 21 01:48:20 PM PDT 24
Finished Mar 21 01:48:36 PM PDT 24
Peak memory 261364 kb
Host smart-15d78f8c-8914-4a7f-a7c1-6875e41911db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350756693 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.
3350756693
Directory /workspace/16.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.42875736
Short name T241
Test name
Test status
Simulation time 5951144500 ps
CPU time 907.22 seconds
Started Mar 21 01:48:19 PM PDT 24
Finished Mar 21 02:03:27 PM PDT 24
Peak memory 264168 kb
Host smart-2c9a08bb-e41a-466a-a387-4a750ef0bf89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42875736 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_
tl_intg_err.42875736
Directory /workspace/16.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1006671386
Short name T1119
Test name
Test status
Simulation time 87402700 ps
CPU time 18.25 seconds
Started Mar 21 01:48:35 PM PDT 24
Finished Mar 21 01:48:53 PM PDT 24
Peak memory 272368 kb
Host smart-c1dc5725-f4f1-4072-8234-6f124328895b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006671386 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.1006671386
Directory /workspace/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.3247440449
Short name T1165
Test name
Test status
Simulation time 137527900 ps
CPU time 17.24 seconds
Started Mar 21 01:48:33 PM PDT 24
Finished Mar 21 01:48:50 PM PDT 24
Peak memory 261992 kb
Host smart-e6f2f778-3b87-432b-97b3-a1c8bbc98e7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247440449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.flash_ctrl_csr_rw.3247440449
Directory /workspace/17.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.2515723467
Short name T1059
Test name
Test status
Simulation time 56131500 ps
CPU time 14.03 seconds
Started Mar 21 01:48:36 PM PDT 24
Finished Mar 21 01:48:50 PM PDT 24
Peak memory 261116 kb
Host smart-a03fcc0e-506f-44f8-ad0b-f9e133b7638d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515723467 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.
2515723467
Directory /workspace/17.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.2398080044
Short name T1142
Test name
Test status
Simulation time 167326800 ps
CPU time 15.73 seconds
Started Mar 21 01:48:38 PM PDT 24
Finished Mar 21 01:48:55 PM PDT 24
Peak memory 260632 kb
Host smart-b58be3a1-8f74-4a96-b70f-aa2df618bc2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398080044 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.flash_ctrl_same_csr_outstanding.2398080044
Directory /workspace/17.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.716743613
Short name T1070
Test name
Test status
Simulation time 17873400 ps
CPU time 15.88 seconds
Started Mar 21 01:48:20 PM PDT 24
Finished Mar 21 01:48:36 PM PDT 24
Peak memory 260544 kb
Host smart-827d8efe-2e77-4e0a-816a-62ff395439c1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716743613 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.flash_ctrl_shadow_reg_errors.716743613
Directory /workspace/17.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1243802699
Short name T1181
Test name
Test status
Simulation time 21449600 ps
CPU time 13.32 seconds
Started Mar 21 01:48:20 PM PDT 24
Finished Mar 21 01:48:33 PM PDT 24
Peak memory 260644 kb
Host smart-984ae9d6-d757-4b9d-bd20-c23f01f09713
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243802699 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors_with_csr_rw.1243802699
Directory /workspace/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1907868792
Short name T1141
Test name
Test status
Simulation time 110716600 ps
CPU time 19.55 seconds
Started Mar 21 01:48:23 PM PDT 24
Finished Mar 21 01:48:43 PM PDT 24
Peak memory 264164 kb
Host smart-03770566-a641-44a7-b69f-12109844bfb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907868792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.
1907868792
Directory /workspace/17.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.193895293
Short name T1147
Test name
Test status
Simulation time 1027044000 ps
CPU time 469.99 seconds
Started Mar 21 01:48:20 PM PDT 24
Finished Mar 21 01:56:10 PM PDT 24
Peak memory 260604 kb
Host smart-9262a29e-9f26-44f1-a264-d1412c207c1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193895293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl
_tl_intg_err.193895293
Directory /workspace/17.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.4178827546
Short name T242
Test name
Test status
Simulation time 448565600 ps
CPU time 15.41 seconds
Started Mar 21 01:48:35 PM PDT 24
Finished Mar 21 01:48:51 PM PDT 24
Peak memory 263340 kb
Host smart-a51face3-d78f-4a0a-b9bb-173148c85598
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178827546 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.4178827546
Directory /workspace/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.3716345064
Short name T306
Test name
Test status
Simulation time 68426300 ps
CPU time 15.03 seconds
Started Mar 21 01:48:34 PM PDT 24
Finished Mar 21 01:48:49 PM PDT 24
Peak memory 260616 kb
Host smart-25e8df22-df82-4ce6-86e0-81596a15eb7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716345064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.flash_ctrl_csr_rw.3716345064
Directory /workspace/18.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.553498903
Short name T1169
Test name
Test status
Simulation time 43093600 ps
CPU time 13.99 seconds
Started Mar 21 01:48:33 PM PDT 24
Finished Mar 21 01:48:47 PM PDT 24
Peak memory 261140 kb
Host smart-3d5af80e-fd80-4d91-b6de-bdc25455eaab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553498903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.553498903
Directory /workspace/18.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.1302224135
Short name T1134
Test name
Test status
Simulation time 165121400 ps
CPU time 17.95 seconds
Started Mar 21 01:48:36 PM PDT 24
Finished Mar 21 01:48:54 PM PDT 24
Peak memory 264116 kb
Host smart-9dd4928e-21d9-4740-8dac-bed7673f0da7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302224135 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.flash_ctrl_same_csr_outstanding.1302224135
Directory /workspace/18.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.3120511704
Short name T1049
Test name
Test status
Simulation time 27069500 ps
CPU time 15.71 seconds
Started Mar 21 01:48:39 PM PDT 24
Finished Mar 21 01:48:55 PM PDT 24
Peak memory 260664 kb
Host smart-c6a5ad96-2274-4022-82aa-57748fb172b9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120511704 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors.3120511704
Directory /workspace/18.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3186000596
Short name T1178
Test name
Test status
Simulation time 19544900 ps
CPU time 15.81 seconds
Started Mar 21 01:48:33 PM PDT 24
Finished Mar 21 01:48:49 PM PDT 24
Peak memory 260548 kb
Host smart-6bec0d10-40ff-4577-a377-5ee08f7f8dae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186000596 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors_with_csr_rw.3186000596
Directory /workspace/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.1743201725
Short name T273
Test name
Test status
Simulation time 44985100 ps
CPU time 18.65 seconds
Started Mar 21 01:48:33 PM PDT 24
Finished Mar 21 01:48:52 PM PDT 24
Peak memory 261576 kb
Host smart-4d2fe215-6bdc-43da-b1ac-8605e7682945
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743201725 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.
1743201725
Directory /workspace/18.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.332173786
Short name T281
Test name
Test status
Simulation time 696829000 ps
CPU time 902.14 seconds
Started Mar 21 01:48:39 PM PDT 24
Finished Mar 21 02:03:42 PM PDT 24
Peak memory 264168 kb
Host smart-fa8526b6-21b5-489e-9dd0-f30fb1c648ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332173786 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl
_tl_intg_err.332173786
Directory /workspace/18.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1945443203
Short name T1110
Test name
Test status
Simulation time 189519300 ps
CPU time 17.71 seconds
Started Mar 21 01:48:37 PM PDT 24
Finished Mar 21 01:48:54 PM PDT 24
Peak memory 270592 kb
Host smart-35ef387b-8108-44b6-bdd4-9a57353182e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945443203 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.1945443203
Directory /workspace/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2971592893
Short name T1156
Test name
Test status
Simulation time 30021100 ps
CPU time 16.81 seconds
Started Mar 21 01:48:35 PM PDT 24
Finished Mar 21 01:48:52 PM PDT 24
Peak memory 260624 kb
Host smart-a6318d27-fca5-48e2-ad66-653b95098cb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971592893 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.flash_ctrl_csr_rw.2971592893
Directory /workspace/19.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.3654414868
Short name T1135
Test name
Test status
Simulation time 28046500 ps
CPU time 13.51 seconds
Started Mar 21 01:48:36 PM PDT 24
Finished Mar 21 01:48:49 PM PDT 24
Peak memory 261144 kb
Host smart-e8ecb31d-b7ec-465b-8607-bd29906e5537
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654414868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.
3654414868
Directory /workspace/19.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.3086390411
Short name T253
Test name
Test status
Simulation time 169713300 ps
CPU time 18.25 seconds
Started Mar 21 01:48:39 PM PDT 24
Finished Mar 21 01:48:58 PM PDT 24
Peak memory 260616 kb
Host smart-a1f8152e-1407-47a8-b36a-c0290824dcbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086390411 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.flash_ctrl_same_csr_outstanding.3086390411
Directory /workspace/19.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.1670780570
Short name T1124
Test name
Test status
Simulation time 28831600 ps
CPU time 14.13 seconds
Started Mar 21 01:48:33 PM PDT 24
Finished Mar 21 01:48:47 PM PDT 24
Peak memory 260620 kb
Host smart-7f0ca68b-18c4-4ed5-af74-d2ae1723fab3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670780570 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors.1670780570
Directory /workspace/19.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2044350772
Short name T1131
Test name
Test status
Simulation time 46070500 ps
CPU time 16.27 seconds
Started Mar 21 01:48:34 PM PDT 24
Finished Mar 21 01:48:50 PM PDT 24
Peak memory 260680 kb
Host smart-1ce32518-7cc8-41d6-b782-f4b465794afe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044350772 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors_with_csr_rw.2044350772
Directory /workspace/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.578080979
Short name T1189
Test name
Test status
Simulation time 190950900 ps
CPU time 20.13 seconds
Started Mar 21 01:48:35 PM PDT 24
Finished Mar 21 01:48:55 PM PDT 24
Peak memory 261396 kb
Host smart-0eb0b744-4e0e-44b4-b98f-b72dfd4d3231
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578080979 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.578080979
Directory /workspace/19.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1277368817
Short name T277
Test name
Test status
Simulation time 694408400 ps
CPU time 380.73 seconds
Started Mar 21 01:48:34 PM PDT 24
Finished Mar 21 01:54:55 PM PDT 24
Peak memory 264152 kb
Host smart-72a6f2fc-0c45-44da-9fba-7b0ad9ab39d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277368817 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctr
l_tl_intg_err.1277368817
Directory /workspace/19.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.258400189
Short name T1177
Test name
Test status
Simulation time 5169307900 ps
CPU time 62.2 seconds
Started Mar 21 01:47:35 PM PDT 24
Finished Mar 21 01:48:37 PM PDT 24
Peak memory 260608 kb
Host smart-8ae998cc-f00d-4966-a816-35267d422980
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258400189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.flash_ctrl_csr_aliasing.258400189
Directory /workspace/2.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.108573891
Short name T1159
Test name
Test status
Simulation time 660944900 ps
CPU time 64.98 seconds
Started Mar 21 01:47:36 PM PDT 24
Finished Mar 21 01:48:42 PM PDT 24
Peak memory 260692 kb
Host smart-1bb96ecc-4800-4524-bdb5-533a70b6ae32
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108573891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.flash_ctrl_csr_bit_bash.108573891
Directory /workspace/2.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.276731690
Short name T266
Test name
Test status
Simulation time 61800300 ps
CPU time 30.82 seconds
Started Mar 21 01:47:36 PM PDT 24
Finished Mar 21 01:48:07 PM PDT 24
Peak memory 260612 kb
Host smart-33c8430a-e3d5-443b-b2c2-d97b84b68462
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276731690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.flash_ctrl_csr_hw_reset.276731690
Directory /workspace/2.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.4012207173
Short name T308
Test name
Test status
Simulation time 57354500 ps
CPU time 17.53 seconds
Started Mar 21 01:47:35 PM PDT 24
Finished Mar 21 01:47:53 PM PDT 24
Peak memory 263268 kb
Host smart-e255b70b-2289-48b6-a5ad-5fd50acbf168
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012207173 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.4012207173
Directory /workspace/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3089189274
Short name T1176
Test name
Test status
Simulation time 257564300 ps
CPU time 17.94 seconds
Started Mar 21 01:47:35 PM PDT 24
Finished Mar 21 01:47:54 PM PDT 24
Peak memory 260608 kb
Host smart-98ea1a87-e15c-41a2-b6dd-cf0f5cc096ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089189274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.flash_ctrl_csr_rw.3089189274
Directory /workspace/2.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.2820394051
Short name T1074
Test name
Test status
Simulation time 155546900 ps
CPU time 13.42 seconds
Started Mar 21 01:47:36 PM PDT 24
Finished Mar 21 01:47:50 PM PDT 24
Peak memory 261076 kb
Host smart-b585e2aa-157c-4b2c-a0a3-97ae126cb6f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820394051 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.2
820394051
Directory /workspace/2.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.4017952481
Short name T251
Test name
Test status
Simulation time 57052100 ps
CPU time 13.27 seconds
Started Mar 21 01:47:42 PM PDT 24
Finished Mar 21 01:47:55 PM PDT 24
Peak memory 261244 kb
Host smart-9cdb8f99-1c74-4082-948d-019f2ed8a134
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017952481 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_mem_partial_access.4017952481
Directory /workspace/2.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.1816557679
Short name T1051
Test name
Test status
Simulation time 40807000 ps
CPU time 13.35 seconds
Started Mar 21 01:47:37 PM PDT 24
Finished Mar 21 01:47:50 PM PDT 24
Peak memory 261028 kb
Host smart-9aa9f8f8-11f7-42ef-a540-c4eca0d6eb23
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816557679 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_me
m_walk.1816557679
Directory /workspace/2.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.2072381547
Short name T1117
Test name
Test status
Simulation time 149034700 ps
CPU time 20.55 seconds
Started Mar 21 01:47:36 PM PDT 24
Finished Mar 21 01:47:57 PM PDT 24
Peak memory 260712 kb
Host smart-6471bcb5-8dde-4895-bb67-43a0061dd1ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072381547 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.flash_ctrl_same_csr_outstanding.2072381547
Directory /workspace/2.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2955579034
Short name T1191
Test name
Test status
Simulation time 46997300 ps
CPU time 13.45 seconds
Started Mar 21 01:47:35 PM PDT 24
Finished Mar 21 01:47:49 PM PDT 24
Peak memory 260640 kb
Host smart-0e452d57-0931-4a88-80fe-dd7c2fb02c60
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955579034 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors.2955579034
Directory /workspace/2.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.4024736714
Short name T1055
Test name
Test status
Simulation time 21010100 ps
CPU time 15.78 seconds
Started Mar 21 01:47:35 PM PDT 24
Finished Mar 21 01:47:51 PM PDT 24
Peak memory 260492 kb
Host smart-4fa99f26-f69e-4da5-b2a4-8e430edbd1ea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024736714 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors_with_csr_rw.4024736714
Directory /workspace/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2417360853
Short name T276
Test name
Test status
Simulation time 32007800 ps
CPU time 15.74 seconds
Started Mar 21 01:47:40 PM PDT 24
Finished Mar 21 01:47:56 PM PDT 24
Peak memory 264144 kb
Host smart-bd0c86c3-cca5-46cb-9a95-92daf6c09317
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417360853 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.2
417360853
Directory /workspace/2.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3032963079
Short name T369
Test name
Test status
Simulation time 332538700 ps
CPU time 746.73 seconds
Started Mar 21 01:47:35 PM PDT 24
Finished Mar 21 02:00:02 PM PDT 24
Peak memory 264156 kb
Host smart-284e22a4-1bb6-42f1-96e8-3f6a6debefa2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032963079 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl
_tl_intg_err.3032963079
Directory /workspace/2.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.1339329416
Short name T1174
Test name
Test status
Simulation time 28795200 ps
CPU time 13.64 seconds
Started Mar 21 01:48:34 PM PDT 24
Finished Mar 21 01:48:48 PM PDT 24
Peak memory 261080 kb
Host smart-aa049b38-b7f5-4536-a11a-7bcaf17dc75d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339329416 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.
1339329416
Directory /workspace/20.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.4139224185
Short name T1104
Test name
Test status
Simulation time 27985700 ps
CPU time 13.58 seconds
Started Mar 21 01:48:39 PM PDT 24
Finished Mar 21 01:48:53 PM PDT 24
Peak memory 261100 kb
Host smart-b126c0cc-da5d-4afa-b3a2-f6b363750f6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139224185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.
4139224185
Directory /workspace/21.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.4157861868
Short name T1062
Test name
Test status
Simulation time 32033800 ps
CPU time 13.48 seconds
Started Mar 21 01:48:39 PM PDT 24
Finished Mar 21 01:48:53 PM PDT 24
Peak memory 261076 kb
Host smart-c94cd0d8-0e9f-48f6-83e8-efcdbd564982
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157861868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.
4157861868
Directory /workspace/22.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.3014214975
Short name T1180
Test name
Test status
Simulation time 31289900 ps
CPU time 14.07 seconds
Started Mar 21 01:48:37 PM PDT 24
Finished Mar 21 01:48:51 PM PDT 24
Peak memory 261196 kb
Host smart-1f87f18c-0e63-48ba-abe4-415f896e3836
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014214975 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.
3014214975
Directory /workspace/23.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.1285896592
Short name T1121
Test name
Test status
Simulation time 163569400 ps
CPU time 13.31 seconds
Started Mar 21 01:48:34 PM PDT 24
Finished Mar 21 01:48:48 PM PDT 24
Peak memory 261064 kb
Host smart-d8e7fbd8-f8b0-4219-991e-9284eb4fa138
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285896592 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.
1285896592
Directory /workspace/24.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.270765187
Short name T1120
Test name
Test status
Simulation time 37944400 ps
CPU time 13.49 seconds
Started Mar 21 01:48:35 PM PDT 24
Finished Mar 21 01:48:49 PM PDT 24
Peak memory 261056 kb
Host smart-f77fbcdb-35c8-4a6a-b84f-304c0b0e751a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270765187 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.270765187
Directory /workspace/25.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.14754766
Short name T1109
Test name
Test status
Simulation time 28635100 ps
CPU time 13.43 seconds
Started Mar 21 01:48:34 PM PDT 24
Finished Mar 21 01:48:47 PM PDT 24
Peak memory 261084 kb
Host smart-3300f243-184d-4ac6-8b11-8d5afd1db11e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14754766 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.14754766
Directory /workspace/26.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.1882464981
Short name T1171
Test name
Test status
Simulation time 15430500 ps
CPU time 13.62 seconds
Started Mar 21 01:48:35 PM PDT 24
Finished Mar 21 01:48:48 PM PDT 24
Peak memory 261172 kb
Host smart-1c3828ff-7314-4e83-ad52-db682cb03c21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882464981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.
1882464981
Directory /workspace/27.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.2599850630
Short name T1195
Test name
Test status
Simulation time 17630800 ps
CPU time 13.55 seconds
Started Mar 21 01:48:34 PM PDT 24
Finished Mar 21 01:48:48 PM PDT 24
Peak memory 261080 kb
Host smart-d055af66-937e-4270-8c5a-534a90e4074b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599850630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.
2599850630
Directory /workspace/28.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.553251792
Short name T1064
Test name
Test status
Simulation time 54696200 ps
CPU time 13.58 seconds
Started Mar 21 01:48:35 PM PDT 24
Finished Mar 21 01:48:49 PM PDT 24
Peak memory 261172 kb
Host smart-60666a51-7190-4fa1-9de0-b812889b5983
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553251792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.553251792
Directory /workspace/29.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.723468942
Short name T303
Test name
Test status
Simulation time 823216100 ps
CPU time 38.75 seconds
Started Mar 21 01:47:47 PM PDT 24
Finished Mar 21 01:48:26 PM PDT 24
Peak memory 260720 kb
Host smart-cd8d9d45-2378-4842-9e38-999aacc69edd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723468942 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.flash_ctrl_csr_aliasing.723468942
Directory /workspace/3.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.424498211
Short name T1082
Test name
Test status
Simulation time 1333804100 ps
CPU time 38.74 seconds
Started Mar 21 01:47:56 PM PDT 24
Finished Mar 21 01:48:35 PM PDT 24
Peak memory 260636 kb
Host smart-15ba8975-ff8e-48a4-b2f7-aa17aebf1b35
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424498211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.flash_ctrl_csr_bit_bash.424498211
Directory /workspace/3.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.866185708
Short name T307
Test name
Test status
Simulation time 48197400 ps
CPU time 45.6 seconds
Started Mar 21 01:47:45 PM PDT 24
Finished Mar 21 01:48:31 PM PDT 24
Peak memory 260688 kb
Host smart-647035e4-f39b-41b2-a448-c4fa1e937ab3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866185708 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.flash_ctrl_csr_hw_reset.866185708
Directory /workspace/3.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.2628477458
Short name T1170
Test name
Test status
Simulation time 39632500 ps
CPU time 17.72 seconds
Started Mar 21 01:47:48 PM PDT 24
Finished Mar 21 01:48:06 PM PDT 24
Peak memory 278388 kb
Host smart-ffee8a5b-0453-4748-87b0-6cb282542ca6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628477458 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.2628477458
Directory /workspace/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1363654683
Short name T1179
Test name
Test status
Simulation time 83700700 ps
CPU time 16.45 seconds
Started Mar 21 01:47:50 PM PDT 24
Finished Mar 21 01:48:07 PM PDT 24
Peak memory 260616 kb
Host smart-b10c011c-0493-43c5-8407-9361ac740a9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363654683 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.flash_ctrl_csr_rw.1363654683
Directory /workspace/3.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.1716542525
Short name T1067
Test name
Test status
Simulation time 58532200 ps
CPU time 13.29 seconds
Started Mar 21 01:47:49 PM PDT 24
Finished Mar 21 01:48:03 PM PDT 24
Peak memory 261096 kb
Host smart-89cdfa8c-6be8-4300-a975-492ce4150977
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716542525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.1
716542525
Directory /workspace/3.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3662641913
Short name T248
Test name
Test status
Simulation time 46503000 ps
CPU time 13.87 seconds
Started Mar 21 01:47:48 PM PDT 24
Finished Mar 21 01:48:02 PM PDT 24
Peak memory 261140 kb
Host smart-41f2af17-afc3-4157-97be-a92f37fea865
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662641913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_mem_partial_access.3662641913
Directory /workspace/3.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.2316584229
Short name T1079
Test name
Test status
Simulation time 42617300 ps
CPU time 13.89 seconds
Started Mar 21 01:47:46 PM PDT 24
Finished Mar 21 01:48:01 PM PDT 24
Peak memory 260964 kb
Host smart-a3450950-2537-4e51-be20-6e88c4ea8add
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316584229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_me
m_walk.2316584229
Directory /workspace/3.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.937849062
Short name T1125
Test name
Test status
Simulation time 64073000 ps
CPU time 14.84 seconds
Started Mar 21 01:47:46 PM PDT 24
Finished Mar 21 01:48:01 PM PDT 24
Peak memory 260624 kb
Host smart-c7d6e220-ffbe-4f1c-9d8d-0a406b5b421d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937849062 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.flash_ctrl_same_csr_outstanding.937849062
Directory /workspace/3.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2418457787
Short name T1069
Test name
Test status
Simulation time 11187300 ps
CPU time 15.87 seconds
Started Mar 21 01:47:46 PM PDT 24
Finished Mar 21 01:48:02 PM PDT 24
Peak memory 260596 kb
Host smart-e12adb17-1788-4b8b-b9e4-b2fdbcac023a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418457787 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors.2418457787
Directory /workspace/3.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.964184270
Short name T1046
Test name
Test status
Simulation time 39954900 ps
CPU time 13.3 seconds
Started Mar 21 01:47:55 PM PDT 24
Finished Mar 21 01:48:08 PM PDT 24
Peak memory 260628 kb
Host smart-192c85ae-4666-4da8-bc45-7d734e4c8198
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964184270 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors_with_csr_rw.964184270
Directory /workspace/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3991295527
Short name T274
Test name
Test status
Simulation time 379229100 ps
CPU time 455.67 seconds
Started Mar 21 01:47:48 PM PDT 24
Finished Mar 21 01:55:24 PM PDT 24
Peak memory 260604 kb
Host smart-b9cecf93-0655-4980-8a11-018f5d805713
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991295527 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl
_tl_intg_err.3991295527
Directory /workspace/3.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.573276785
Short name T336
Test name
Test status
Simulation time 50017200 ps
CPU time 13.41 seconds
Started Mar 21 01:48:35 PM PDT 24
Finished Mar 21 01:48:48 PM PDT 24
Peak memory 260960 kb
Host smart-1333a7d2-0dbb-4b05-a6be-b2ccd1df83b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573276785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.573276785
Directory /workspace/30.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.3697648111
Short name T1105
Test name
Test status
Simulation time 30384800 ps
CPU time 13.42 seconds
Started Mar 21 01:48:41 PM PDT 24
Finished Mar 21 01:48:54 PM PDT 24
Peak memory 261112 kb
Host smart-7c1b15ac-908c-4b1f-aada-d5865803ad98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697648111 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.
3697648111
Directory /workspace/31.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.505765769
Short name T270
Test name
Test status
Simulation time 52019400 ps
CPU time 13.45 seconds
Started Mar 21 01:48:41 PM PDT 24
Finished Mar 21 01:48:54 PM PDT 24
Peak memory 261000 kb
Host smart-3add6dcb-4e2f-41a4-be16-a3a9a5c74859
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505765769 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.505765769
Directory /workspace/32.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.2850661735
Short name T1076
Test name
Test status
Simulation time 26638200 ps
CPU time 13.55 seconds
Started Mar 21 01:48:34 PM PDT 24
Finished Mar 21 01:48:48 PM PDT 24
Peak memory 261100 kb
Host smart-77c37eee-9d35-4b37-a934-3f1f26e25e0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850661735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.
2850661735
Directory /workspace/33.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.2134051159
Short name T1163
Test name
Test status
Simulation time 28027000 ps
CPU time 13.78 seconds
Started Mar 21 01:48:34 PM PDT 24
Finished Mar 21 01:48:48 PM PDT 24
Peak memory 261020 kb
Host smart-6feea44b-0e2f-45cc-afea-36c2a41e11a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134051159 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.
2134051159
Directory /workspace/34.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3511886248
Short name T1192
Test name
Test status
Simulation time 100220400 ps
CPU time 14.17 seconds
Started Mar 21 01:48:36 PM PDT 24
Finished Mar 21 01:48:51 PM PDT 24
Peak memory 261120 kb
Host smart-16d40fda-a486-47b7-bb5e-5a2a3161e5dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511886248 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.
3511886248
Directory /workspace/36.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.2750186447
Short name T339
Test name
Test status
Simulation time 253157000 ps
CPU time 13.89 seconds
Started Mar 21 01:48:39 PM PDT 24
Finished Mar 21 01:48:53 PM PDT 24
Peak memory 261104 kb
Host smart-131ad347-ecf8-404e-b680-d779f99d44be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750186447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test.
2750186447
Directory /workspace/37.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.3046207876
Short name T1113
Test name
Test status
Simulation time 17761700 ps
CPU time 14.02 seconds
Started Mar 21 01:48:36 PM PDT 24
Finished Mar 21 01:48:50 PM PDT 24
Peak memory 261180 kb
Host smart-713a69f2-9165-41ed-8ab0-d5f155cea8bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046207876 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.
3046207876
Directory /workspace/38.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.33764769
Short name T1108
Test name
Test status
Simulation time 17916600 ps
CPU time 13.58 seconds
Started Mar 21 01:48:39 PM PDT 24
Finished Mar 21 01:48:53 PM PDT 24
Peak memory 261116 kb
Host smart-e5244eb8-bfb9-4844-83de-b53815b8889f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33764769 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.33764769
Directory /workspace/39.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.492138208
Short name T305
Test name
Test status
Simulation time 2915784400 ps
CPU time 60.95 seconds
Started Mar 21 01:47:47 PM PDT 24
Finished Mar 21 01:48:48 PM PDT 24
Peak memory 260596 kb
Host smart-fb51abc7-ded0-4954-b813-9d1da7a7f392
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492138208 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.flash_ctrl_csr_aliasing.492138208
Directory /workspace/4.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.935658852
Short name T1133
Test name
Test status
Simulation time 1509970500 ps
CPU time 62.87 seconds
Started Mar 21 01:47:47 PM PDT 24
Finished Mar 21 01:48:50 PM PDT 24
Peak memory 262208 kb
Host smart-0c94bda4-0651-4f46-8a35-adacc662d8c6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935658852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.flash_ctrl_csr_bit_bash.935658852
Directory /workspace/4.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1742344623
Short name T1149
Test name
Test status
Simulation time 89145200 ps
CPU time 45.2 seconds
Started Mar 21 01:47:55 PM PDT 24
Finished Mar 21 01:48:40 PM PDT 24
Peak memory 260728 kb
Host smart-2bcc29a3-9af4-405f-b1c7-9dcc4faff49b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742344623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_hw_reset.1742344623
Directory /workspace/4.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1876074750
Short name T304
Test name
Test status
Simulation time 57858600 ps
CPU time 14.97 seconds
Started Mar 21 01:47:48 PM PDT 24
Finished Mar 21 01:48:03 PM PDT 24
Peak memory 264172 kb
Host smart-7e8951aa-2998-4090-a1e8-9ab6234c2096
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876074750 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.1876074750
Directory /workspace/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.1471728094
Short name T1080
Test name
Test status
Simulation time 194643600 ps
CPU time 17.34 seconds
Started Mar 21 01:47:46 PM PDT 24
Finished Mar 21 01:48:03 PM PDT 24
Peak memory 260612 kb
Host smart-1f56d580-a1aa-4287-80cb-0dda0eafc844
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471728094 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.flash_ctrl_csr_rw.1471728094
Directory /workspace/4.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.1521370421
Short name T1139
Test name
Test status
Simulation time 24124400 ps
CPU time 13.68 seconds
Started Mar 21 01:47:48 PM PDT 24
Finished Mar 21 01:48:01 PM PDT 24
Peak memory 261136 kb
Host smart-3f2a8387-1902-4c5f-88b2-d51ad4f23c59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521370421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.1
521370421
Directory /workspace/4.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.423621565
Short name T250
Test name
Test status
Simulation time 47128300 ps
CPU time 13.19 seconds
Started Mar 21 01:47:50 PM PDT 24
Finished Mar 21 01:48:03 PM PDT 24
Peak memory 261200 kb
Host smart-63abfef7-d08b-4d2c-934e-534575a7bf94
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423621565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_mem_partial_access.423621565
Directory /workspace/4.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.2958309801
Short name T1138
Test name
Test status
Simulation time 26820100 ps
CPU time 13.53 seconds
Started Mar 21 01:47:50 PM PDT 24
Finished Mar 21 01:48:04 PM PDT 24
Peak memory 261108 kb
Host smart-5daff97a-4b64-4ad2-805f-e0113271d73a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958309801 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_me
m_walk.2958309801
Directory /workspace/4.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.1169851781
Short name T1098
Test name
Test status
Simulation time 326854100 ps
CPU time 30.23 seconds
Started Mar 21 01:47:46 PM PDT 24
Finished Mar 21 01:48:16 PM PDT 24
Peak memory 263380 kb
Host smart-1d861697-1bbc-42d3-bb70-d4881bc233ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169851781 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.flash_ctrl_same_csr_outstanding.1169851781
Directory /workspace/4.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.3555895876
Short name T1072
Test name
Test status
Simulation time 34244100 ps
CPU time 15.95 seconds
Started Mar 21 01:47:52 PM PDT 24
Finished Mar 21 01:48:08 PM PDT 24
Peak memory 260580 kb
Host smart-6a014bea-000e-47c1-bb38-b9a2107ffcd5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555895876 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors.3555895876
Directory /workspace/4.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.2693554975
Short name T1073
Test name
Test status
Simulation time 16891200 ps
CPU time 15.62 seconds
Started Mar 21 01:47:47 PM PDT 24
Finished Mar 21 01:48:03 PM PDT 24
Peak memory 260656 kb
Host smart-847f3a67-18c4-4807-b219-11da8d6e33c8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693554975 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors_with_csr_rw.2693554975
Directory /workspace/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2918329639
Short name T278
Test name
Test status
Simulation time 707655000 ps
CPU time 19.09 seconds
Started Mar 21 01:47:45 PM PDT 24
Finished Mar 21 01:48:04 PM PDT 24
Peak memory 264036 kb
Host smart-ceb43a78-bcdc-4ef6-9844-d7094ea1f801
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918329639 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.2
918329639
Directory /workspace/4.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.48404087
Short name T279
Test name
Test status
Simulation time 956579000 ps
CPU time 889.96 seconds
Started Mar 21 01:47:48 PM PDT 24
Finished Mar 21 02:02:38 PM PDT 24
Peak memory 262812 kb
Host smart-563e1cda-c5ef-4315-a7d8-47ad37cb73d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48404087 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_t
l_intg_err.48404087
Directory /workspace/4.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.1928260939
Short name T1175
Test name
Test status
Simulation time 87984600 ps
CPU time 13.81 seconds
Started Mar 21 01:48:35 PM PDT 24
Finished Mar 21 01:48:49 PM PDT 24
Peak memory 261096 kb
Host smart-5ac27505-1305-46b0-b88b-5b02f885b928
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928260939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.
1928260939
Directory /workspace/40.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3032570435
Short name T1086
Test name
Test status
Simulation time 18966100 ps
CPU time 13.88 seconds
Started Mar 21 01:48:37 PM PDT 24
Finished Mar 21 01:48:51 PM PDT 24
Peak memory 261116 kb
Host smart-94b2a8a7-bb29-4460-9b80-ed745eedd96e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032570435 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.
3032570435
Directory /workspace/41.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.1487861654
Short name T1056
Test name
Test status
Simulation time 122788300 ps
CPU time 13.58 seconds
Started Mar 21 01:48:41 PM PDT 24
Finished Mar 21 01:48:54 PM PDT 24
Peak memory 261016 kb
Host smart-9fc80ac4-576d-40f7-b061-687c3f413417
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487861654 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.
1487861654
Directory /workspace/42.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.1882937441
Short name T1148
Test name
Test status
Simulation time 54950100 ps
CPU time 13.52 seconds
Started Mar 21 01:48:47 PM PDT 24
Finished Mar 21 01:49:01 PM PDT 24
Peak memory 261076 kb
Host smart-fd22d6f0-ba00-4874-9b1f-253a8c9232e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882937441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.
1882937441
Directory /workspace/43.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.4231392027
Short name T1057
Test name
Test status
Simulation time 64299100 ps
CPU time 14.26 seconds
Started Mar 21 01:48:47 PM PDT 24
Finished Mar 21 01:49:02 PM PDT 24
Peak memory 261104 kb
Host smart-f9bbc1da-a0ab-4da7-8d89-5b4454b9a71c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231392027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.
4231392027
Directory /workspace/44.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.2504520174
Short name T1185
Test name
Test status
Simulation time 40010400 ps
CPU time 13.36 seconds
Started Mar 21 01:48:47 PM PDT 24
Finished Mar 21 01:49:01 PM PDT 24
Peak memory 261100 kb
Host smart-c133f1c4-341a-4843-9467-3588e81cfb0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504520174 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.
2504520174
Directory /workspace/45.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.2722548794
Short name T1106
Test name
Test status
Simulation time 16238000 ps
CPU time 13.66 seconds
Started Mar 21 01:48:48 PM PDT 24
Finished Mar 21 01:49:02 PM PDT 24
Peak memory 261000 kb
Host smart-9a302c95-2192-419c-9643-c5022985d037
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722548794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.
2722548794
Directory /workspace/46.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.699624990
Short name T1093
Test name
Test status
Simulation time 99906300 ps
CPU time 13.65 seconds
Started Mar 21 01:48:51 PM PDT 24
Finished Mar 21 01:49:04 PM PDT 24
Peak memory 261116 kb
Host smart-23a4c374-1bdd-4c40-a95e-57edf51ae883
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699624990 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.699624990
Directory /workspace/47.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2412503142
Short name T1054
Test name
Test status
Simulation time 44361900 ps
CPU time 13.49 seconds
Started Mar 21 01:48:49 PM PDT 24
Finished Mar 21 01:49:03 PM PDT 24
Peak memory 261016 kb
Host smart-32648ed4-4089-4fc9-8a8b-b6d194ce8fdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412503142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.
2412503142
Directory /workspace/48.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.95789324
Short name T338
Test name
Test status
Simulation time 16513000 ps
CPU time 13.4 seconds
Started Mar 21 01:48:49 PM PDT 24
Finished Mar 21 01:49:03 PM PDT 24
Peak memory 261220 kb
Host smart-7c91ef7c-f887-44dc-a4c0-c957320f8f08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95789324 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.95789324
Directory /workspace/49.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.3002948275
Short name T1186
Test name
Test status
Simulation time 79278400 ps
CPU time 15.73 seconds
Started Mar 21 01:47:46 PM PDT 24
Finished Mar 21 01:48:02 PM PDT 24
Peak memory 272328 kb
Host smart-5e92534b-939d-4af7-8bf7-8cd8be92c993
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002948275 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.3002948275
Directory /workspace/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.1601640701
Short name T1193
Test name
Test status
Simulation time 29420000 ps
CPU time 17.35 seconds
Started Mar 21 01:47:55 PM PDT 24
Finished Mar 21 01:48:12 PM PDT 24
Peak memory 260860 kb
Host smart-909cdc89-1020-4d25-a00f-47b6ac22e20d
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601640701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.flash_ctrl_csr_rw.1601640701
Directory /workspace/5.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.746594830
Short name T1123
Test name
Test status
Simulation time 16962900 ps
CPU time 13.42 seconds
Started Mar 21 01:47:56 PM PDT 24
Finished Mar 21 01:48:09 PM PDT 24
Peak memory 261192 kb
Host smart-30245fd7-3358-44f7-9fd8-8a73f708f9f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746594830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.746594830
Directory /workspace/5.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.70380228
Short name T1088
Test name
Test status
Simulation time 38762600 ps
CPU time 17.67 seconds
Started Mar 21 01:47:55 PM PDT 24
Finished Mar 21 01:48:13 PM PDT 24
Peak memory 262136 kb
Host smart-900cc46b-64c7-4d26-9abc-b71c19358f4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70380228 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.flash_ctrl_same_csr_outstanding.70380228
Directory /workspace/5.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.2416959493
Short name T1060
Test name
Test status
Simulation time 20030500 ps
CPU time 15.98 seconds
Started Mar 21 01:47:46 PM PDT 24
Finished Mar 21 01:48:03 PM PDT 24
Peak memory 260532 kb
Host smart-5dc5fb74-ddbc-4450-ab15-922b6ba7e520
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416959493 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors.2416959493
Directory /workspace/5.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.2081637267
Short name T1122
Test name
Test status
Simulation time 44164800 ps
CPU time 15.83 seconds
Started Mar 21 01:47:46 PM PDT 24
Finished Mar 21 01:48:03 PM PDT 24
Peak memory 260532 kb
Host smart-1fabfc39-5904-4f9e-8849-d8667abc4e1d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081637267 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors_with_csr_rw.2081637267
Directory /workspace/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.3120527129
Short name T1150
Test name
Test status
Simulation time 107309200 ps
CPU time 15.5 seconds
Started Mar 21 01:47:48 PM PDT 24
Finished Mar 21 01:48:04 PM PDT 24
Peak memory 264152 kb
Host smart-ae437c5e-785b-4b0b-8f83-b87ba62a8ce0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120527129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.3
120527129
Directory /workspace/5.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2266934194
Short name T1144
Test name
Test status
Simulation time 1360091700 ps
CPU time 458.39 seconds
Started Mar 21 01:47:51 PM PDT 24
Finished Mar 21 01:55:30 PM PDT 24
Peak memory 264164 kb
Host smart-eb273838-bef8-451d-8096-6dc1a50e72bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266934194 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl
_tl_intg_err.2266934194
Directory /workspace/5.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.715812563
Short name T1166
Test name
Test status
Simulation time 51588900 ps
CPU time 17.84 seconds
Started Mar 21 01:47:47 PM PDT 24
Finished Mar 21 01:48:05 PM PDT 24
Peak memory 277792 kb
Host smart-57a40cb6-9139-46a0-8522-d27a02901e3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715812563 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.715812563
Directory /workspace/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.3791051778
Short name T1153
Test name
Test status
Simulation time 29996500 ps
CPU time 16.77 seconds
Started Mar 21 01:47:48 PM PDT 24
Finished Mar 21 01:48:05 PM PDT 24
Peak memory 260716 kb
Host smart-1089526d-4886-4037-a751-a20f9a898768
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791051778 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.flash_ctrl_csr_rw.3791051778
Directory /workspace/6.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.3891984989
Short name T1063
Test name
Test status
Simulation time 43538200 ps
CPU time 13.68 seconds
Started Mar 21 01:47:52 PM PDT 24
Finished Mar 21 01:48:06 PM PDT 24
Peak memory 261132 kb
Host smart-f39eccd4-1a95-4229-bf70-350dcebdf1fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891984989 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.3
891984989
Directory /workspace/6.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2301501463
Short name T1130
Test name
Test status
Simulation time 574914900 ps
CPU time 18.13 seconds
Started Mar 21 01:47:45 PM PDT 24
Finished Mar 21 01:48:03 PM PDT 24
Peak memory 260704 kb
Host smart-75a569f6-82d7-43e8-95a9-89da285a3a20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301501463 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.flash_ctrl_same_csr_outstanding.2301501463
Directory /workspace/6.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.3871321465
Short name T1183
Test name
Test status
Simulation time 34313400 ps
CPU time 15.59 seconds
Started Mar 21 01:47:56 PM PDT 24
Finished Mar 21 01:48:12 PM PDT 24
Peak memory 260568 kb
Host smart-950c2db9-dada-4749-987b-82c73fd02707
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871321465 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors.3871321465
Directory /workspace/6.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.4154274155
Short name T1053
Test name
Test status
Simulation time 71296700 ps
CPU time 15.64 seconds
Started Mar 21 01:47:46 PM PDT 24
Finished Mar 21 01:48:02 PM PDT 24
Peak memory 260628 kb
Host smart-6183ae6c-b0f2-4119-9643-ec36ac082ce4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154274155 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors_with_csr_rw.4154274155
Directory /workspace/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.858032687
Short name T272
Test name
Test status
Simulation time 54615800 ps
CPU time 19.79 seconds
Started Mar 21 01:47:47 PM PDT 24
Finished Mar 21 01:48:07 PM PDT 24
Peak memory 264092 kb
Host smart-6b0ee26d-de1a-4283-8197-4b58d94128d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858032687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.858032687
Directory /workspace/6.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.3850069584
Short name T244
Test name
Test status
Simulation time 449520800 ps
CPU time 18.13 seconds
Started Mar 21 01:47:53 PM PDT 24
Finished Mar 21 01:48:11 PM PDT 24
Peak memory 264140 kb
Host smart-0bb4a73f-e9b5-44fd-8cae-e573ee74d5cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850069584 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.3850069584
Directory /workspace/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.1938050133
Short name T1172
Test name
Test status
Simulation time 476427600 ps
CPU time 14.63 seconds
Started Mar 21 01:47:45 PM PDT 24
Finished Mar 21 01:48:00 PM PDT 24
Peak memory 260760 kb
Host smart-de1b8294-1532-4c8c-8f06-1dcdc38bdb65
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938050133 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.flash_ctrl_csr_rw.1938050133
Directory /workspace/7.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.810503303
Short name T1100
Test name
Test status
Simulation time 29008100 ps
CPU time 13.39 seconds
Started Mar 21 01:47:48 PM PDT 24
Finished Mar 21 01:48:01 PM PDT 24
Peak memory 261132 kb
Host smart-ef0e0c08-1ce0-4f17-9d40-c3f407b044f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810503303 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.810503303
Directory /workspace/7.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2183888965
Short name T1116
Test name
Test status
Simulation time 633991900 ps
CPU time 20.72 seconds
Started Mar 21 01:47:47 PM PDT 24
Finished Mar 21 01:48:08 PM PDT 24
Peak memory 260724 kb
Host smart-1e1e7b81-12cd-455b-b911-c5c360d8821b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183888965 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.flash_ctrl_same_csr_outstanding.2183888965
Directory /workspace/7.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.1024827067
Short name T1058
Test name
Test status
Simulation time 12091800 ps
CPU time 15.88 seconds
Started Mar 21 01:47:51 PM PDT 24
Finished Mar 21 01:48:07 PM PDT 24
Peak memory 260664 kb
Host smart-097b041b-12ae-4378-b56e-951e026a647a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024827067 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors.1024827067
Directory /workspace/7.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.3144907232
Short name T1127
Test name
Test status
Simulation time 40436300 ps
CPU time 15.91 seconds
Started Mar 21 01:47:47 PM PDT 24
Finished Mar 21 01:48:03 PM PDT 24
Peak memory 260572 kb
Host smart-c259c4b3-3838-47f3-9690-8bcdba77a8f8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144907232 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors_with_csr_rw.3144907232
Directory /workspace/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.421531440
Short name T1173
Test name
Test status
Simulation time 50831300 ps
CPU time 16.06 seconds
Started Mar 21 01:47:51 PM PDT 24
Finished Mar 21 01:48:07 PM PDT 24
Peak memory 264164 kb
Host smart-a846fff6-b2f1-4352-a682-f0eb8cc7f95a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421531440 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.421531440
Directory /workspace/7.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.705730676
Short name T238
Test name
Test status
Simulation time 1206801000 ps
CPU time 443.61 seconds
Started Mar 21 01:47:49 PM PDT 24
Finished Mar 21 01:55:13 PM PDT 24
Peak memory 264140 kb
Host smart-06d1d1f0-93b4-40af-b273-03ce7f80a975
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705730676 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_
tl_intg_err.705730676
Directory /workspace/7.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.3566354870
Short name T1140
Test name
Test status
Simulation time 30595500 ps
CPU time 18.42 seconds
Started Mar 21 01:47:57 PM PDT 24
Finished Mar 21 01:48:16 PM PDT 24
Peak memory 271712 kb
Host smart-b1c85df2-fcad-4700-829a-0884aca3bbd4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566354870 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.3566354870
Directory /workspace/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2845939770
Short name T254
Test name
Test status
Simulation time 151467500 ps
CPU time 16.69 seconds
Started Mar 21 01:47:55 PM PDT 24
Finished Mar 21 01:48:12 PM PDT 24
Peak memory 260708 kb
Host smart-24bd3153-caa6-49e8-9af2-430e24367e54
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845939770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.flash_ctrl_csr_rw.2845939770
Directory /workspace/8.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.3054884245
Short name T1068
Test name
Test status
Simulation time 180696700 ps
CPU time 13.54 seconds
Started Mar 21 01:47:56 PM PDT 24
Finished Mar 21 01:48:10 PM PDT 24
Peak memory 261180 kb
Host smart-9ba2cd80-4ed8-4d41-9de7-9d80ff3c9761
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054884245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.3
054884245
Directory /workspace/8.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.1901421954
Short name T1085
Test name
Test status
Simulation time 160850000 ps
CPU time 29.76 seconds
Started Mar 21 01:47:56 PM PDT 24
Finished Mar 21 01:48:26 PM PDT 24
Peak memory 260740 kb
Host smart-ae51e4ca-04eb-4530-b540-63aa736bb544
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901421954 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.flash_ctrl_same_csr_outstanding.1901421954
Directory /workspace/8.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.500794896
Short name T1154
Test name
Test status
Simulation time 16496800 ps
CPU time 15.79 seconds
Started Mar 21 01:47:56 PM PDT 24
Finished Mar 21 01:48:12 PM PDT 24
Peak memory 260656 kb
Host smart-84ae60f3-6ed4-489d-924e-a2e66ccab569
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500794896 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.flash_ctrl_shadow_reg_errors.500794896
Directory /workspace/8.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.499125188
Short name T1081
Test name
Test status
Simulation time 30431400 ps
CPU time 15.65 seconds
Started Mar 21 01:47:55 PM PDT 24
Finished Mar 21 01:48:11 PM PDT 24
Peak memory 260548 kb
Host smart-e3fd4237-7c6a-4443-9062-e8a311c08ecc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499125188 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors_with_csr_rw.499125188
Directory /workspace/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.1036205667
Short name T170
Test name
Test status
Simulation time 414800600 ps
CPU time 747.63 seconds
Started Mar 21 01:48:03 PM PDT 24
Finished Mar 21 02:00:31 PM PDT 24
Peak memory 264152 kb
Host smart-18f3b5d7-d6ae-4037-a5f8-2751325fd080
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036205667 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl
_tl_intg_err.1036205667
Directory /workspace/8.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.2949568922
Short name T1095
Test name
Test status
Simulation time 141732600 ps
CPU time 17.49 seconds
Started Mar 21 01:47:57 PM PDT 24
Finished Mar 21 01:48:14 PM PDT 24
Peak memory 271428 kb
Host smart-90712f28-48fb-4332-9437-bf8382198e61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949568922 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.2949568922
Directory /workspace/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.437567605
Short name T1194
Test name
Test status
Simulation time 28633300 ps
CPU time 17.19 seconds
Started Mar 21 01:47:57 PM PDT 24
Finished Mar 21 01:48:14 PM PDT 24
Peak memory 260608 kb
Host smart-9f0fd007-b7a1-4f40-a571-8387904da418
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437567605 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 9.flash_ctrl_csr_rw.437567605
Directory /workspace/9.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.93514506
Short name T258
Test name
Test status
Simulation time 556810800 ps
CPU time 15.3 seconds
Started Mar 21 01:47:57 PM PDT 24
Finished Mar 21 01:48:13 PM PDT 24
Peak memory 262504 kb
Host smart-07164ddc-5824-444b-8432-bbf85e7c67ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93514506 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.flash_ctrl_same_csr_outstanding.93514506
Directory /workspace/9.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2499107907
Short name T1111
Test name
Test status
Simulation time 13982200 ps
CPU time 15.66 seconds
Started Mar 21 01:47:57 PM PDT 24
Finished Mar 21 01:48:13 PM PDT 24
Peak memory 260588 kb
Host smart-a51bd0e1-5cd8-45ce-a5de-b1dc20cfd457
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499107907 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors.2499107907
Directory /workspace/9.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.1997553757
Short name T1078
Test name
Test status
Simulation time 14039500 ps
CPU time 16.26 seconds
Started Mar 21 01:47:57 PM PDT 24
Finished Mar 21 01:48:14 PM PDT 24
Peak memory 260548 kb
Host smart-b5f681d0-8059-4d10-a4ee-d67847586ec1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997553757 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors_with_csr_rw.1997553757
Directory /workspace/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.374385630
Short name T267
Test name
Test status
Simulation time 51142800 ps
CPU time 19.47 seconds
Started Mar 21 01:47:57 PM PDT 24
Finished Mar 21 01:48:17 PM PDT 24
Peak memory 261448 kb
Host smart-6107969d-2aa9-4085-87b6-67caaa12e718
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374385630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.374385630
Directory /workspace/9.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.flash_ctrl_alert_test.1877784785
Short name T743
Test name
Test status
Simulation time 152443400 ps
CPU time 13.7 seconds
Started Mar 21 03:12:04 PM PDT 24
Finished Mar 21 03:12:17 PM PDT 24
Peak memory 258160 kb
Host smart-ce0de48b-1652-4ec9-8d32-11aa19ff3938
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877784785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.1
877784785
Directory /workspace/0.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.flash_ctrl_connect.2337047692
Short name T870
Test name
Test status
Simulation time 15015100 ps
CPU time 16.16 seconds
Started Mar 21 03:11:52 PM PDT 24
Finished Mar 21 03:12:10 PM PDT 24
Peak memory 275072 kb
Host smart-adf19242-4188-42c0-9e8e-7c5c885923c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337047692 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.2337047692
Directory /workspace/0.flash_ctrl_connect/latest

Test location /workspace/coverage/default/0.flash_ctrl_derr_detect.2820730298
Short name T263
Test name
Test status
Simulation time 459250700 ps
CPU time 105.53 seconds
Started Mar 21 03:11:54 PM PDT 24
Finished Mar 21 03:13:41 PM PDT 24
Peak memory 274648 kb
Host smart-34467f87-9ce1-4527-a0ee-a7def46c576f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820730298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_derr_detect.2820730298
Directory /workspace/0.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/0.flash_ctrl_disable.2030783207
Short name T374
Test name
Test status
Simulation time 26558700 ps
CPU time 22.05 seconds
Started Mar 21 03:11:51 PM PDT 24
Finished Mar 21 03:12:15 PM PDT 24
Peak memory 273700 kb
Host smart-0e9ef930-36fa-4154-bfa2-725f3c1125c3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030783207 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_disable.2030783207
Directory /workspace/0.flash_ctrl_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_type.1527026949
Short name T960
Test name
Test status
Simulation time 1101988100 ps
CPU time 2980.43 seconds
Started Mar 21 03:11:51 PM PDT 24
Finished Mar 21 04:01:34 PM PDT 24
Peak memory 265232 kb
Host smart-12a5bdaf-1c90-47d6-80ef-ee1393c32720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527026949 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_type.1527026949
Directory /workspace/0.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/0.flash_ctrl_fs_sup.575646853
Short name T163
Test name
Test status
Simulation time 1268650000 ps
CPU time 38.32 seconds
Started Mar 21 03:11:51 PM PDT 24
Finished Mar 21 03:12:32 PM PDT 24
Peak memory 277476 kb
Host smart-90a52d32-3fd3-44fd-b329-954be042455b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575646853 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_fs_sup.575646853
Directory /workspace/0.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_dir_rd.1125150671
Short name T882
Test name
Test status
Simulation time 34673400 ps
CPU time 48.92 seconds
Started Mar 21 03:11:52 PM PDT 24
Finished Mar 21 03:12:43 PM PDT 24
Peak memory 264756 kb
Host smart-40798873-9f06-435b-a852-5cf7cd8e12ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1125150671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.1125150671
Directory /workspace/0.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.606027865
Short name T606
Test name
Test status
Simulation time 10016218600 ps
CPU time 216.74 seconds
Started Mar 21 03:12:03 PM PDT 24
Finished Mar 21 03:15:40 PM PDT 24
Peak memory 296824 kb
Host smart-362ad4c9-22fd-4a26-990b-222be8ee829b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606027865 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.606027865
Directory /workspace/0.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma.3750466326
Short name T604
Test name
Test status
Simulation time 1019874203400 ps
CPU time 2953.97 seconds
Started Mar 21 03:11:54 PM PDT 24
Finished Mar 21 04:01:10 PM PDT 24
Peak memory 263616 kb
Host smart-46029194-3e2b-4c3a-a126-7da422dfdad3
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750466326 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.flash_ctrl_hw_rma.3750466326
Directory /workspace/0.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_sec_otp.1744178101
Short name T766
Test name
Test status
Simulation time 3261290500 ps
CPU time 162.51 seconds
Started Mar 21 03:11:51 PM PDT 24
Finished Mar 21 03:14:35 PM PDT 24
Peak memory 262436 kb
Host smart-ee6f7ec7-e437-4e14-b540-82da0b9aa8bd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744178101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_h
w_sec_otp.1744178101
Directory /workspace/0.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd_slow_flash.2240590794
Short name T443
Test name
Test status
Simulation time 17678260800 ps
CPU time 237.32 seconds
Started Mar 21 03:11:50 PM PDT 24
Finished Mar 21 03:15:48 PM PDT 24
Peak memory 284724 kb
Host smart-3dbc4ff9-fb71-4594-aa71-66b9f3820fde
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240590794 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd_slow_flash.2240590794
Directory /workspace/0.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr.839151471
Short name T874
Test name
Test status
Simulation time 16442102900 ps
CPU time 103.13 seconds
Started Mar 21 03:11:51 PM PDT 24
Finished Mar 21 03:13:37 PM PDT 24
Peak memory 262048 kb
Host smart-42af9650-e914-4d00-91f8-328695d0511d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839151471 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.flash_ctrl_intr_wr.839151471
Directory /workspace/0.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr_slow_flash.120889438
Short name T786
Test name
Test status
Simulation time 341551037900 ps
CPU time 437.22 seconds
Started Mar 21 03:11:49 PM PDT 24
Finished Mar 21 03:19:08 PM PDT 24
Peak memory 261436 kb
Host smart-26b58490-ee16-4cee-896a-6a0013de367e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120
889438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.120889438
Directory /workspace/0.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_invalid_op.2406150148
Short name T419
Test name
Test status
Simulation time 16111539200 ps
CPU time 99.26 seconds
Started Mar 21 03:11:55 PM PDT 24
Finished Mar 21 03:13:36 PM PDT 24
Peak memory 259836 kb
Host smart-e65466a3-5c67-466b-90f5-10420d802d2b
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406150148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.2406150148
Directory /workspace/0.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_lcmgr_intg.3468264859
Short name T298
Test name
Test status
Simulation time 15456100 ps
CPU time 13.65 seconds
Started Mar 21 03:11:56 PM PDT 24
Finished Mar 21 03:12:10 PM PDT 24
Peak memory 265236 kb
Host smart-9919ed00-c2c8-4697-9c0f-420c0c2cce39
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468264859 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_lcmgr_intg.3468264859
Directory /workspace/0.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_mid_op_rst.2565125047
Short name T129
Test name
Test status
Simulation time 667933600 ps
CPU time 76.47 seconds
Started Mar 21 03:11:52 PM PDT 24
Finished Mar 21 03:13:10 PM PDT 24
Peak memory 259820 kb
Host smart-1b830c01-c7f7-42bf-abd2-25339c30855d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565125047 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.2565125047
Directory /workspace/0.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/0.flash_ctrl_otp_reset.1705786705
Short name T260
Test name
Test status
Simulation time 69978400 ps
CPU time 111.06 seconds
Started Mar 21 03:11:50 PM PDT 24
Finished Mar 21 03:13:43 PM PDT 24
Peak memory 259760 kb
Host smart-67bf9145-ecaa-4cee-b084-3c0981403f84
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705786705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ot
p_reset.1705786705
Directory /workspace/0.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_oversize_error.3335084742
Short name T905
Test name
Test status
Simulation time 2103361600 ps
CPU time 170.64 seconds
Started Mar 21 03:11:55 PM PDT 24
Finished Mar 21 03:14:47 PM PDT 24
Peak memory 290036 kb
Host smart-6ecd3ac9-a0e2-4867-9550-dcb783bf614e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335084742 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_oversize_error.3335084742
Directory /workspace/0.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_ack_consistency.81466548
Short name T184
Test name
Test status
Simulation time 45429300 ps
CPU time 14.47 seconds
Started Mar 21 03:11:53 PM PDT 24
Finished Mar 21 03:12:09 PM PDT 24
Peak memory 261184 kb
Host smart-62cca4e7-92f1-4a5a-a44a-2ec783c0ca24
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=81466548 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.81466548
Directory /workspace/0.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb.180303586
Short name T959
Test name
Test status
Simulation time 2740888500 ps
CPU time 454.03 seconds
Started Mar 21 03:11:52 PM PDT 24
Finished Mar 21 03:19:28 PM PDT 24
Peak memory 261804 kb
Host smart-ac29fbd2-0098-45d8-9887-d76fe2d36d82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=180303586 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.180303586
Directory /workspace/0.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb_redun.887772993
Short name T67
Test name
Test status
Simulation time 784657400 ps
CPU time 75.61 seconds
Started Mar 21 03:11:51 PM PDT 24
Finished Mar 21 03:13:09 PM PDT 24
Peak memory 265364 kb
Host smart-b0a62f51-829b-4dd5-8be8-3f2f34c7960f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887772993 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.887772993
Directory /workspace/0.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_host_grant_err.3609480898
Short name T202
Test name
Test status
Simulation time 24453600 ps
CPU time 14.18 seconds
Started Mar 21 03:11:52 PM PDT 24
Finished Mar 21 03:12:08 PM PDT 24
Peak memory 265376 kb
Host smart-ab742cb1-ed55-438f-b906-239f54f12231
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609480898 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.3609480898
Directory /workspace/0.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_prog_reset.4090636793
Short name T16
Test name
Test status
Simulation time 65666500 ps
CPU time 13.48 seconds
Started Mar 21 03:11:52 PM PDT 24
Finished Mar 21 03:12:07 PM PDT 24
Peak memory 260140 kb
Host smart-1273aaae-25ac-421f-b4a0-8391cd76d109
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090636793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_prog_res
et.4090636793
Directory /workspace/0.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_rand_ops.1560097384
Short name T843
Test name
Test status
Simulation time 1541959400 ps
CPU time 894.78 seconds
Started Mar 21 03:11:51 PM PDT 24
Finished Mar 21 03:26:48 PM PDT 24
Peak memory 282968 kb
Host smart-57ea0477-282b-485e-96fb-d644db0fb11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560097384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.1560097384
Directory /workspace/0.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_buff_evict.1019973838
Short name T117
Test name
Test status
Simulation time 157631000 ps
CPU time 103.06 seconds
Started Mar 21 03:11:56 PM PDT 24
Finished Mar 21 03:13:40 PM PDT 24
Peak memory 265200 kb
Host smart-8a7475a2-645b-4c00-81ab-885007ceb845
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1019973838 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.1019973838
Directory /workspace/0.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_intg.2812203983
Short name T196
Test name
Test status
Simulation time 636039500 ps
CPU time 29.54 seconds
Started Mar 21 03:11:51 PM PDT 24
Finished Mar 21 03:12:23 PM PDT 24
Peak memory 273532 kb
Host smart-5186f5b2-c123-4a08-9b46-af66b3b7139b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812203983 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_rd_intg.2812203983
Directory /workspace/0.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_ooo.3503747245
Short name T620
Test name
Test status
Simulation time 73809300 ps
CPU time 48.25 seconds
Started Mar 21 03:12:05 PM PDT 24
Finished Mar 21 03:12:53 PM PDT 24
Peak memory 274616 kb
Host smart-63127f83-be80-4bae-b7ea-417346c42e8d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503747245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_rd_ooo.3503747245
Directory /workspace/0.flash_ctrl_rd_ooo/latest

Test location /workspace/coverage/default/0.flash_ctrl_re_evict.2863104815
Short name T548
Test name
Test status
Simulation time 301301800 ps
CPU time 35.73 seconds
Started Mar 21 03:11:54 PM PDT 24
Finished Mar 21 03:12:31 PM PDT 24
Peak memory 273580 kb
Host smart-cc052055-7186-464f-8809-b864a2033de8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863104815 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_re_evict.2863104815
Directory /workspace/0.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep.3165472982
Short name T899
Test name
Test status
Simulation time 234040400 ps
CPU time 13.38 seconds
Started Mar 21 03:11:56 PM PDT 24
Finished Mar 21 03:12:10 PM PDT 24
Peak memory 258180 kb
Host smart-02263bf4-1702-4ed4-a85b-300a816848ff
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3165472982 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep
.3165472982
Directory /workspace/0.flash_ctrl_read_word_sweep/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_derr.1680007857
Short name T223
Test name
Test status
Simulation time 58928700 ps
CPU time 21.51 seconds
Started Mar 21 03:11:53 PM PDT 24
Finished Mar 21 03:12:15 PM PDT 24
Peak memory 265296 kb
Host smart-391c8984-7c7d-4617-91ee-1b82e944cb07
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680007857 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_derr.1680007857
Directory /workspace/0.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_serr.2383263601
Short name T981
Test name
Test status
Simulation time 24160800 ps
CPU time 23.02 seconds
Started Mar 21 03:11:54 PM PDT 24
Finished Mar 21 03:12:19 PM PDT 24
Peak memory 264472 kb
Host smart-82d64819-8704-4114-8799-3e930d3eb2d7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383263601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fl
ash_ctrl_read_word_sweep_serr.2383263601
Directory /workspace/0.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro.536892938
Short name T832
Test name
Test status
Simulation time 881388300 ps
CPU time 107.71 seconds
Started Mar 21 03:11:55 PM PDT 24
Finished Mar 21 03:13:43 PM PDT 24
Peak memory 281136 kb
Host smart-d82630c8-6ca5-403c-a899-508cdd131111
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536892938 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.flash_ctrl_ro.536892938
Directory /workspace/0.flash_ctrl_ro/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw.3152288370
Short name T918
Test name
Test status
Simulation time 10743276600 ps
CPU time 494.74 seconds
Started Mar 21 03:11:56 PM PDT 24
Finished Mar 21 03:20:12 PM PDT 24
Peak memory 313784 kb
Host smart-f2486215-a255-4e44-a1c0-af2504047e6b
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152288370 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ct
rl_rw.3152288370
Directory /workspace/0.flash_ctrl_rw/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict.4036574051
Short name T194
Test name
Test status
Simulation time 49058200 ps
CPU time 31.8 seconds
Started Mar 21 03:11:55 PM PDT 24
Finished Mar 21 03:12:28 PM PDT 24
Peak memory 274560 kb
Host smart-1d27aecf-69f5-456e-b83c-a56cf226b618
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036574051 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_rw_evict.4036574051
Directory /workspace/0.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict_all_en.1725994217
Short name T22
Test name
Test status
Simulation time 36351600 ps
CPU time 31.95 seconds
Started Mar 21 03:11:50 PM PDT 24
Finished Mar 21 03:12:23 PM PDT 24
Peak memory 272612 kb
Host smart-7ecde577-6f8a-4d10-b7a7-ee1a57226deb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725994217 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict_all_en.1725994217
Directory /workspace/0.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_info_access.2580197403
Short name T703
Test name
Test status
Simulation time 831985900 ps
CPU time 61.64 seconds
Started Mar 21 03:11:52 PM PDT 24
Finished Mar 21 03:12:56 PM PDT 24
Peak memory 262560 kb
Host smart-a6b43b53-c72c-4135-86e0-ad9760b8d483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580197403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.2580197403
Directory /workspace/0.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_address.2487496818
Short name T33
Test name
Test status
Simulation time 3700988800 ps
CPU time 87.98 seconds
Started Mar 21 03:11:55 PM PDT 24
Finished Mar 21 03:13:23 PM PDT 24
Peak memory 265376 kb
Host smart-e4e646ac-1564-4b09-85ad-32b2ad3d5237
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487496818 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_serr_address.2487496818
Directory /workspace/0.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_counter.3225095469
Short name T957
Test name
Test status
Simulation time 1181527700 ps
CPU time 58.36 seconds
Started Mar 21 03:11:57 PM PDT 24
Finished Mar 21 03:12:55 PM PDT 24
Peak memory 273632 kb
Host smart-c75de03f-38cd-4532-936a-ecf36f616f9a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225095469 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_serr_counter.3225095469
Directory /workspace/0.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke.3322190690
Short name T525
Test name
Test status
Simulation time 111833900 ps
CPU time 124.74 seconds
Started Mar 21 03:11:51 PM PDT 24
Finished Mar 21 03:13:58 PM PDT 24
Peak memory 275940 kb
Host smart-af8c0e18-cf64-483c-9da5-5b7d6d405aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322190690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.3322190690
Directory /workspace/0.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke_hw.285012275
Short name T819
Test name
Test status
Simulation time 97103100 ps
CPU time 27.15 seconds
Started Mar 21 03:11:53 PM PDT 24
Finished Mar 21 03:12:21 PM PDT 24
Peak memory 259096 kb
Host smart-c774176c-f45d-4426-955e-a93930ed6a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285012275 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.285012275
Directory /workspace/0.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/0.flash_ctrl_stress_all.1796909338
Short name T667
Test name
Test status
Simulation time 397712500 ps
CPU time 690.33 seconds
Started Mar 21 03:11:53 PM PDT 24
Finished Mar 21 03:23:25 PM PDT 24
Peak memory 281124 kb
Host smart-1ec850e6-db9b-4669-99b8-94201842f344
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796909338 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stres
s_all.1796909338
Directory /workspace/0.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.flash_ctrl_sw_op.1119927040
Short name T474
Test name
Test status
Simulation time 81661400 ps
CPU time 24.29 seconds
Started Mar 21 03:11:50 PM PDT 24
Finished Mar 21 03:12:15 PM PDT 24
Peak memory 258960 kb
Host smart-2a8204d5-7de5-4e7d-a733-4fa5312cefcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119927040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.1119927040
Directory /workspace/0.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_wo.2891290840
Short name T772
Test name
Test status
Simulation time 2482049300 ps
CPU time 116.63 seconds
Started Mar 21 03:11:54 PM PDT 24
Finished Mar 21 03:13:52 PM PDT 24
Peak memory 259044 kb
Host smart-5250ca9a-a15b-4415-9282-21174b1137c7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891290840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.flash_ctrl_wo.2891290840
Directory /workspace/0.flash_ctrl_wo/latest

Test location /workspace/coverage/default/0.flash_ctrl_write_word_sweep.4259419423
Short name T833
Test name
Test status
Simulation time 204194700 ps
CPU time 17.4 seconds
Started Mar 21 03:11:55 PM PDT 24
Finished Mar 21 03:12:13 PM PDT 24
Peak memory 260424 kb
Host smart-18b0cd2b-1489-41d4-a720-9d0832ac2607
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4259419423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_swe
ep.4259419423
Directory /workspace/0.flash_ctrl_write_word_sweep/latest

Test location /workspace/coverage/default/1.flash_ctrl_access_after_disable.519515580
Short name T43
Test name
Test status
Simulation time 19677700 ps
CPU time 13.58 seconds
Started Mar 21 03:12:19 PM PDT 24
Finished Mar 21 03:12:33 PM PDT 24
Peak memory 265284 kb
Host smart-0e731439-73d3-4220-8a8e-3d5c8f309880
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519515580 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.519515580
Directory /workspace/1.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_alert_test.3897306309
Short name T411
Test name
Test status
Simulation time 132632800 ps
CPU time 13.95 seconds
Started Mar 21 03:12:24 PM PDT 24
Finished Mar 21 03:12:38 PM PDT 24
Peak memory 265244 kb
Host smart-f00f8d81-c157-460a-9c11-b24f527014c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897306309 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.3
897306309
Directory /workspace/1.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.flash_ctrl_config_regwen.4105055534
Short name T775
Test name
Test status
Simulation time 19917800 ps
CPU time 13.9 seconds
Started Mar 21 03:12:22 PM PDT 24
Finished Mar 21 03:12:36 PM PDT 24
Peak memory 265204 kb
Host smart-060958e9-2a0b-47f3-8d55-582e6f4eb516
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105055534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.flash_ctrl_config_regwen.4105055534
Directory /workspace/1.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/1.flash_ctrl_connect.3213629899
Short name T506
Test name
Test status
Simulation time 41888900 ps
CPU time 16.47 seconds
Started Mar 21 03:12:04 PM PDT 24
Finished Mar 21 03:12:20 PM PDT 24
Peak memory 275076 kb
Host smart-dfe824c3-dbe9-42c9-8d95-cf4eabc6a8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213629899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.3213629899
Directory /workspace/1.flash_ctrl_connect/latest

Test location /workspace/coverage/default/1.flash_ctrl_erase_suspend.2834002508
Short name T803
Test name
Test status
Simulation time 8419297300 ps
CPU time 496.09 seconds
Started Mar 21 03:12:03 PM PDT 24
Finished Mar 21 03:20:19 PM PDT 24
Peak memory 261176 kb
Host smart-f0353f61-bced-425c-a938-781a8e190869
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2834002508 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.2834002508
Directory /workspace/1.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_mp.1933014332
Short name T569
Test name
Test status
Simulation time 4995237500 ps
CPU time 2388.07 seconds
Started Mar 21 03:12:07 PM PDT 24
Finished Mar 21 03:51:55 PM PDT 24
Peak memory 262692 kb
Host smart-c962490d-9be9-43ff-924c-6484c729158d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933014332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_err
or_mp.1933014332
Directory /workspace/1.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_type.1649946597
Short name T165
Test name
Test status
Simulation time 953686300 ps
CPU time 2607.8 seconds
Started Mar 21 03:12:04 PM PDT 24
Finished Mar 21 03:55:33 PM PDT 24
Peak memory 265144 kb
Host smart-79c27502-935e-4cd1-9516-938088fe38dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649946597 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_type.1649946597
Directory /workspace/1.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_win.767339129
Short name T672
Test name
Test status
Simulation time 659998500 ps
CPU time 869.85 seconds
Started Mar 21 03:12:03 PM PDT 24
Finished Mar 21 03:26:34 PM PDT 24
Peak memory 273972 kb
Host smart-1b3e928a-5c0e-41d0-a033-1bc820789f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767339129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.767339129
Directory /workspace/1.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/1.flash_ctrl_fetch_code.333977430
Short name T600
Test name
Test status
Simulation time 173780600 ps
CPU time 27.69 seconds
Started Mar 21 03:12:04 PM PDT 24
Finished Mar 21 03:12:32 PM PDT 24
Peak memory 265312 kb
Host smart-ac4f14bc-2fbc-4f1a-a938-5c5e74689f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333977430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetch_code.333977430
Directory /workspace/1.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/1.flash_ctrl_fs_sup.1470185895
Short name T826
Test name
Test status
Simulation time 1102796800 ps
CPU time 33.92 seconds
Started Mar 21 03:12:17 PM PDT 24
Finished Mar 21 03:12:51 PM PDT 24
Peak memory 273464 kb
Host smart-a8a2b16f-03de-4605-a601-758ebde4697c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470185895 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.flash_ctrl_fs_sup.1470185895
Directory /workspace/1.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/1.flash_ctrl_full_mem_access.542734671
Short name T596
Test name
Test status
Simulation time 81404632700 ps
CPU time 2804.64 seconds
Started Mar 21 03:12:02 PM PDT 24
Finished Mar 21 03:58:47 PM PDT 24
Peak memory 265100 kb
Host smart-e9fe0526-7e21-453b-923b-52e5a4a7f289
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542734671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ct
rl_full_mem_access.542734671
Directory /workspace/1.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_dir_rd.4153311030
Short name T282
Test name
Test status
Simulation time 260194300 ps
CPU time 127.47 seconds
Started Mar 21 03:12:03 PM PDT 24
Finished Mar 21 03:14:11 PM PDT 24
Peak memory 262584 kb
Host smart-c931f8b7-0aab-46fa-b48c-e0e15f6598df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4153311030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.4153311030
Directory /workspace/1.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.2043276211
Short name T632
Test name
Test status
Simulation time 10065706500 ps
CPU time 61.12 seconds
Started Mar 21 03:12:22 PM PDT 24
Finished Mar 21 03:13:23 PM PDT 24
Peak memory 265296 kb
Host smart-426397c8-4122-4a1d-97e0-05ae93e39f8d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043276211 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.2043276211
Directory /workspace/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_read_seed_err.3136705830
Short name T904
Test name
Test status
Simulation time 46534400 ps
CPU time 13.22 seconds
Started Mar 21 03:12:26 PM PDT 24
Finished Mar 21 03:12:39 PM PDT 24
Peak memory 265200 kb
Host smart-d66b0ff7-de31-4f30-b42a-46c4ac418fec
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136705830 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_read_seed_err.3136705830
Directory /workspace/1.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma.1459679478
Short name T770
Test name
Test status
Simulation time 1019909337800 ps
CPU time 2195.23 seconds
Started Mar 21 03:12:04 PM PDT 24
Finished Mar 21 03:48:40 PM PDT 24
Peak memory 263688 kb
Host smart-6d127089-617b-4261-ba34-5c32cf721e8a
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459679478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.flash_ctrl_hw_rma.1459679478
Directory /workspace/1.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma_reset.3520039585
Short name T462
Test name
Test status
Simulation time 70137004700 ps
CPU time 938.69 seconds
Started Mar 21 03:12:06 PM PDT 24
Finished Mar 21 03:27:45 PM PDT 24
Peak memory 265108 kb
Host smart-21d82cd8-c715-4145-841a-3de73e479df8
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520039585 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.flash_ctrl_hw_rma_reset.3520039585
Directory /workspace/1.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_sec_otp.1350419090
Short name T816
Test name
Test status
Simulation time 3224305800 ps
CPU time 290.72 seconds
Started Mar 21 03:12:03 PM PDT 24
Finished Mar 21 03:16:54 PM PDT 24
Peak memory 262436 kb
Host smart-7477945c-35c3-44e8-90f0-2cc8ccb1c42e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350419090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_h
w_sec_otp.1350419090
Directory /workspace/1.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.2216904461
Short name T750
Test name
Test status
Simulation time 16439738600 ps
CPU time 226.64 seconds
Started Mar 21 03:12:05 PM PDT 24
Finished Mar 21 03:15:52 PM PDT 24
Peak memory 284684 kb
Host smart-896823eb-254e-414b-ab18-98ecc821d755
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216904461 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd_slow_flash.2216904461
Directory /workspace/1.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr_slow_flash.3320144982
Short name T994
Test name
Test status
Simulation time 224139361300 ps
CPU time 416.49 seconds
Started Mar 21 03:12:05 PM PDT 24
Finished Mar 21 03:19:02 PM PDT 24
Peak memory 261008 kb
Host smart-11d31935-d5df-47cb-8022-1953cdae38c8
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332
0144982 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.3320144982
Directory /workspace/1.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_invalid_op.3318482689
Short name T403
Test name
Test status
Simulation time 1056623800 ps
CPU time 82.31 seconds
Started Mar 21 03:12:08 PM PDT 24
Finished Mar 21 03:13:30 PM PDT 24
Peak memory 263572 kb
Host smart-c9c0d095-339e-4db5-bb88-53d2189c713b
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318482689 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.3318482689
Directory /workspace/1.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_lcmgr_intg.928116537
Short name T642
Test name
Test status
Simulation time 19427300 ps
CPU time 13.47 seconds
Started Mar 21 03:12:24 PM PDT 24
Finished Mar 21 03:12:38 PM PDT 24
Peak memory 265244 kb
Host smart-375342fc-01eb-478c-b80c-b977d02b650d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928116537 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_lcmgr_intg.928116537
Directory /workspace/1.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_mp_regions.697328725
Short name T449
Test name
Test status
Simulation time 35628773000 ps
CPU time 157.1 seconds
Started Mar 21 03:12:04 PM PDT 24
Finished Mar 21 03:14:42 PM PDT 24
Peak memory 265224 kb
Host smart-26740283-04a0-4bdb-a180-81adefc07315
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697328725 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_mp_regions.697328725
Directory /workspace/1.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/1.flash_ctrl_otp_reset.4175508993
Short name T379
Test name
Test status
Simulation time 623747700 ps
CPU time 132.4 seconds
Started Mar 21 03:12:06 PM PDT 24
Finished Mar 21 03:14:19 PM PDT 24
Peak memory 261100 kb
Host smart-1360a5ab-f4c8-43c0-8a60-b8b42c733a36
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175508993 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ot
p_reset.4175508993
Directory /workspace/1.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb.2910950900
Short name T785
Test name
Test status
Simulation time 48664600 ps
CPU time 197.21 seconds
Started Mar 21 03:12:02 PM PDT 24
Finished Mar 21 03:15:19 PM PDT 24
Peak memory 261780 kb
Host smart-56af78b0-2d4b-48b6-838f-fe94d5ed0fbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2910950900 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.2910950900
Directory /workspace/1.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb_redun.97475052
Short name T903
Test name
Test status
Simulation time 673795800 ps
CPU time 41.21 seconds
Started Mar 21 03:12:22 PM PDT 24
Finished Mar 21 03:13:03 PM PDT 24
Peak memory 265416 kb
Host smart-77c6b8b6-c075-4221-8762-13378d76d945
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97475052 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.97475052
Directory /workspace/1.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/1.flash_ctrl_prog_reset.494650599
Short name T732
Test name
Test status
Simulation time 59637600 ps
CPU time 17.5 seconds
Started Mar 21 03:12:06 PM PDT 24
Finished Mar 21 03:12:24 PM PDT 24
Peak memory 261228 kb
Host smart-637321c3-ed77-4f81-87ac-2ad00f2ca4a0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494650599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_prog_rese
t.494650599
Directory /workspace/1.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_rand_ops.3584471772
Short name T539
Test name
Test status
Simulation time 583244600 ps
CPU time 522.67 seconds
Started Mar 21 03:12:03 PM PDT 24
Finished Mar 21 03:20:46 PM PDT 24
Peak memory 280436 kb
Host smart-c559f2c5-8573-4f7e-988a-f9fb05cb05db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584471772 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.3584471772
Directory /workspace/1.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_buff_evict.346094024
Short name T234
Test name
Test status
Simulation time 1415077400 ps
CPU time 178.04 seconds
Started Mar 21 03:12:02 PM PDT 24
Finished Mar 21 03:15:00 PM PDT 24
Peak memory 265212 kb
Host smart-6f21f55d-004b-48f7-b4ac-d49614614117
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=346094024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.346094024
Directory /workspace/1.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_intg.1981568072
Short name T838
Test name
Test status
Simulation time 208864500 ps
CPU time 30.21 seconds
Started Mar 21 03:12:24 PM PDT 24
Finished Mar 21 03:12:54 PM PDT 24
Peak memory 274560 kb
Host smart-d37a2863-19e6-4ad6-9589-5f87c0590725
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981568072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_rd_intg.1981568072
Directory /workspace/1.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_derr.685780139
Short name T211
Test name
Test status
Simulation time 19121000 ps
CPU time 23.06 seconds
Started Mar 21 03:12:04 PM PDT 24
Finished Mar 21 03:12:28 PM PDT 24
Peak memory 265348 kb
Host smart-6723eb01-7990-4812-bd05-e4dceb0d0c34
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685780139 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_derr.685780139
Directory /workspace/1.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_serr.1620248350
Short name T467
Test name
Test status
Simulation time 112351100 ps
CPU time 22.71 seconds
Started Mar 21 03:12:07 PM PDT 24
Finished Mar 21 03:12:30 PM PDT 24
Peak memory 264288 kb
Host smart-e8a60c9a-fd40-4e7c-9a3a-8566ddfc08ae
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620248350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fl
ash_ctrl_read_word_sweep_serr.1620248350
Directory /workspace/1.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rma_err.1872492308
Short name T151
Test name
Test status
Simulation time 101540169300 ps
CPU time 1450.39 seconds
Started Mar 21 03:12:18 PM PDT 24
Finished Mar 21 03:36:29 PM PDT 24
Peak memory 497296 kb
Host smart-c3c72fab-dcf3-4af6-8b2c-dd8c2d522dc9
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872492308 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rma_err.1872492308
Directory /workspace/1.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw.4023098506
Short name T864
Test name
Test status
Simulation time 6377292600 ps
CPU time 564.45 seconds
Started Mar 21 03:12:04 PM PDT 24
Finished Mar 21 03:21:29 PM PDT 24
Peak memory 314452 kb
Host smart-9d42a980-110e-4bf9-8236-6073a5f0d7d6
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023098506 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ct
rl_rw.4023098506
Directory /workspace/1.flash_ctrl_rw/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict.1363226597
Short name T763
Test name
Test status
Simulation time 34532300 ps
CPU time 32.57 seconds
Started Mar 21 03:12:04 PM PDT 24
Finished Mar 21 03:12:37 PM PDT 24
Peak memory 274620 kb
Host smart-903add6b-bcbc-452e-b4cd-9eac06345aa2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363226597 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_rw_evict.1363226597
Directory /workspace/1.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict_all_en.1510523058
Short name T733
Test name
Test status
Simulation time 44067000 ps
CPU time 27.86 seconds
Started Mar 21 03:12:03 PM PDT 24
Finished Mar 21 03:12:30 PM PDT 24
Peak memory 273532 kb
Host smart-d39ca08b-6095-4642-986c-f6c063ecf43b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510523058 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict_all_en.1510523058
Directory /workspace/1.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_cm.2212358007
Short name T114
Test name
Test status
Simulation time 2118223200 ps
CPU time 5006.37 seconds
Started Mar 21 03:12:03 PM PDT 24
Finished Mar 21 04:35:30 PM PDT 24
Peak memory 282660 kb
Host smart-ef186853-810b-444c-9fae-6c0da2a70f0d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212358007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.2212358007
Directory /workspace/1.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_address.3051894859
Short name T584
Test name
Test status
Simulation time 642124100 ps
CPU time 48.77 seconds
Started Mar 21 03:12:04 PM PDT 24
Finished Mar 21 03:12:53 PM PDT 24
Peak memory 265296 kb
Host smart-90873fff-f05c-4661-9417-ea31c4ab509a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051894859 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_serr_address.3051894859
Directory /workspace/1.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_counter.3576499423
Short name T191
Test name
Test status
Simulation time 995719300 ps
CPU time 74.13 seconds
Started Mar 21 03:12:07 PM PDT 24
Finished Mar 21 03:13:22 PM PDT 24
Peak memory 265424 kb
Host smart-c38095d1-5426-43ad-9dd8-7fae159b7965
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576499423 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_serr_counter.3576499423
Directory /workspace/1.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke.2764617678
Short name T926
Test name
Test status
Simulation time 26290900 ps
CPU time 197.22 seconds
Started Mar 21 03:12:04 PM PDT 24
Finished Mar 21 03:15:22 PM PDT 24
Peak memory 279104 kb
Host smart-2aef254b-ee70-4717-be6b-7fc36309f78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764617678 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.2764617678
Directory /workspace/1.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke_hw.621381878
Short name T334
Test name
Test status
Simulation time 50682500 ps
CPU time 24.1 seconds
Started Mar 21 03:12:04 PM PDT 24
Finished Mar 21 03:12:29 PM PDT 24
Peak memory 259068 kb
Host smart-bf0ec55e-c85b-4fbf-9841-6017caa424ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621381878 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.621381878
Directory /workspace/1.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/1.flash_ctrl_stress_all.1010641697
Short name T319
Test name
Test status
Simulation time 300964700 ps
CPU time 121.21 seconds
Started Mar 21 03:12:05 PM PDT 24
Finished Mar 21 03:14:06 PM PDT 24
Peak memory 281596 kb
Host smart-620672dd-e85b-453c-9379-9224e8eddd97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010641697 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stres
s_all.1010641697
Directory /workspace/1.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.flash_ctrl_sw_op.2673247032
Short name T842
Test name
Test status
Simulation time 21971100 ps
CPU time 24.63 seconds
Started Mar 21 03:12:04 PM PDT 24
Finished Mar 21 03:12:29 PM PDT 24
Peak memory 258860 kb
Host smart-76988152-107d-4bc3-bc96-ef25838d4043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673247032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.2673247032
Directory /workspace/1.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_wo.1233229182
Short name T684
Test name
Test status
Simulation time 5567309500 ps
CPU time 204.33 seconds
Started Mar 21 03:12:05 PM PDT 24
Finished Mar 21 03:15:29 PM PDT 24
Peak memory 259152 kb
Host smart-a709aaac-44f6-448e-b139-86fb5bc13f29
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233229182 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.flash_ctrl_wo.1233229182
Directory /workspace/1.flash_ctrl_wo/latest

Test location /workspace/coverage/default/1.flash_ctrl_wr_intg.2965021289
Short name T9
Test name
Test status
Simulation time 50676700 ps
CPU time 14.74 seconds
Started Mar 21 03:12:17 PM PDT 24
Finished Mar 21 03:12:32 PM PDT 24
Peak memory 260360 kb
Host smart-4f36a821-6f14-457e-8252-af99ca3eb428
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965021289 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wr_intg.2965021289
Directory /workspace/1.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/10.flash_ctrl_alert_test.214954998
Short name T515
Test name
Test status
Simulation time 117564000 ps
CPU time 14.12 seconds
Started Mar 21 03:15:35 PM PDT 24
Finished Mar 21 03:15:50 PM PDT 24
Peak memory 258292 kb
Host smart-35bdad2d-c679-4dc2-9f17-2333dc40e4cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214954998 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.214954998
Directory /workspace/10.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.flash_ctrl_connect.2611054074
Short name T426
Test name
Test status
Simulation time 51771400 ps
CPU time 13.94 seconds
Started Mar 21 03:15:24 PM PDT 24
Finished Mar 21 03:15:38 PM PDT 24
Peak memory 275184 kb
Host smart-5ee18e82-3ff1-4044-94f6-d1a2b6c15b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611054074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.2611054074
Directory /workspace/10.flash_ctrl_connect/latest

Test location /workspace/coverage/default/10.flash_ctrl_disable.3630178925
Short name T433
Test name
Test status
Simulation time 22435400 ps
CPU time 22.1 seconds
Started Mar 21 03:15:22 PM PDT 24
Finished Mar 21 03:15:44 PM PDT 24
Peak memory 273684 kb
Host smart-91f05def-c3ef-45d8-9e9f-5a8c3e1197ca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630178925 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_disable.3630178925
Directory /workspace/10.flash_ctrl_disable/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_rma_reset.2911090521
Short name T158
Test name
Test status
Simulation time 80149029200 ps
CPU time 887.95 seconds
Started Mar 21 03:15:23 PM PDT 24
Finished Mar 21 03:30:11 PM PDT 24
Peak memory 263208 kb
Host smart-f2cfa490-a048-4637-b9ed-23d9558f5aff
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911090521 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.flash_ctrl_hw_rma_reset.2911090521
Directory /workspace/10.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_sec_otp.4182604225
Short name T412
Test name
Test status
Simulation time 7714685100 ps
CPU time 38.22 seconds
Started Mar 21 03:15:21 PM PDT 24
Finished Mar 21 03:15:59 PM PDT 24
Peak memory 262456 kb
Host smart-6e2a336b-b252-4d2d-87b2-a0f34b616c73
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182604225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_
hw_sec_otp.4182604225
Directory /workspace/10.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd.2338217018
Short name T287
Test name
Test status
Simulation time 2256577400 ps
CPU time 167.77 seconds
Started Mar 21 03:15:21 PM PDT 24
Finished Mar 21 03:18:09 PM PDT 24
Peak memory 294112 kb
Host smart-8b9fc15f-06eb-4952-bb21-f931f15ea6e9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338217018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla
sh_ctrl_intr_rd.2338217018
Directory /workspace/10.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd_slow_flash.1001006469
Short name T700
Test name
Test status
Simulation time 38344718600 ps
CPU time 267.45 seconds
Started Mar 21 03:15:23 PM PDT 24
Finished Mar 21 03:19:50 PM PDT 24
Peak memory 289892 kb
Host smart-fc7c5421-2e01-4239-8d60-e035cc5ac3cc
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001006469 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd_slow_flash.1001006469
Directory /workspace/10.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/10.flash_ctrl_invalid_op.2861816643
Short name T807
Test name
Test status
Simulation time 2015165400 ps
CPU time 84.45 seconds
Started Mar 21 03:15:20 PM PDT 24
Finished Mar 21 03:16:45 PM PDT 24
Peak memory 259856 kb
Host smart-9aa35463-dc9b-4432-ae2e-5a0146cb10d6
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861816643 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.2
861816643
Directory /workspace/10.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/10.flash_ctrl_lcmgr_intg.625765866
Short name T1035
Test name
Test status
Simulation time 71492600 ps
CPU time 14.03 seconds
Started Mar 21 03:15:21 PM PDT 24
Finished Mar 21 03:15:36 PM PDT 24
Peak memory 265212 kb
Host smart-6d094741-8de1-4a32-b352-3436f57f8d89
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625765866 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.flash_ctrl_lcmgr_intg.625765866
Directory /workspace/10.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/10.flash_ctrl_mp_regions.2986379325
Short name T939
Test name
Test status
Simulation time 70189463300 ps
CPU time 182.77 seconds
Started Mar 21 03:15:23 PM PDT 24
Finished Mar 21 03:18:26 PM PDT 24
Peak memory 262964 kb
Host smart-e4c76950-ebb7-4779-bb18-2c8f9fd7a4c5
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986379325 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.flash_ctrl_mp_regions.2986379325
Directory /workspace/10.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/10.flash_ctrl_otp_reset.3085013587
Short name T324
Test name
Test status
Simulation time 101808700 ps
CPU time 111.56 seconds
Started Mar 21 03:15:21 PM PDT 24
Finished Mar 21 03:17:12 PM PDT 24
Peak memory 259756 kb
Host smart-bfa9e82b-85dd-4b0a-bbf4-67d654f714d0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085013587 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_o
tp_reset.3085013587
Directory /workspace/10.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_phy_arb.2695018911
Short name T62
Test name
Test status
Simulation time 1388761200 ps
CPU time 525.27 seconds
Started Mar 21 03:15:23 PM PDT 24
Finished Mar 21 03:24:08 PM PDT 24
Peak memory 265216 kb
Host smart-a8856ef9-db17-477a-a0f4-b1030aecda05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2695018911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.2695018911
Directory /workspace/10.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/10.flash_ctrl_prog_reset.566543314
Short name T598
Test name
Test status
Simulation time 70467700 ps
CPU time 13.91 seconds
Started Mar 21 03:15:22 PM PDT 24
Finished Mar 21 03:15:36 PM PDT 24
Peak memory 260148 kb
Host smart-0f2c842c-d7e4-4134-8956-378f49750781
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566543314 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_prog_res
et.566543314
Directory /workspace/10.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_rand_ops.717304286
Short name T108
Test name
Test status
Simulation time 127347900 ps
CPU time 355.68 seconds
Started Mar 21 03:15:23 PM PDT 24
Finished Mar 21 03:21:19 PM PDT 24
Peak memory 278208 kb
Host smart-090b8d19-de7e-4816-9f61-d9b1dd50d6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717304286 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.717304286
Directory /workspace/10.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/10.flash_ctrl_re_evict.2435908088
Short name T696
Test name
Test status
Simulation time 129759100 ps
CPU time 37.39 seconds
Started Mar 21 03:15:22 PM PDT 24
Finished Mar 21 03:15:59 PM PDT 24
Peak memory 273560 kb
Host smart-7e9b23f0-5e9e-4dff-b427-ca831773d3d2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435908088 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl
ash_ctrl_re_evict.2435908088
Directory /workspace/10.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_ro.291151543
Short name T201
Test name
Test status
Simulation time 718957100 ps
CPU time 97.85 seconds
Started Mar 21 03:15:20 PM PDT 24
Finished Mar 21 03:16:58 PM PDT 24
Peak memory 289304 kb
Host smart-bb47101a-a7d2-420e-9f22-b9daec6a99bc
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291151543 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.flash_ctrl_ro.291151543
Directory /workspace/10.flash_ctrl_ro/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw.2248867568
Short name T1033
Test name
Test status
Simulation time 12870318200 ps
CPU time 438.26 seconds
Started Mar 21 03:15:20 PM PDT 24
Finished Mar 21 03:22:39 PM PDT 24
Peak memory 314436 kb
Host smart-bc72d0d8-fd5e-4f62-b692-3356e71a1309
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248867568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_c
trl_rw.2248867568
Directory /workspace/10.flash_ctrl_rw/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict.275910215
Short name T210
Test name
Test status
Simulation time 71839700 ps
CPU time 31.93 seconds
Started Mar 21 03:15:22 PM PDT 24
Finished Mar 21 03:15:54 PM PDT 24
Peak memory 273544 kb
Host smart-6fc349f4-7ec2-4691-b86b-421f5279f854
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275910215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla
sh_ctrl_rw_evict.275910215
Directory /workspace/10.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict_all_en.2542057997
Short name T825
Test name
Test status
Simulation time 151334500 ps
CPU time 31.1 seconds
Started Mar 21 03:15:24 PM PDT 24
Finished Mar 21 03:15:55 PM PDT 24
Peak memory 274640 kb
Host smart-a651b1ef-32d1-442f-b039-958ce8b494c1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542057997 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict_all_en.2542057997
Directory /workspace/10.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/10.flash_ctrl_sec_info_access.1296738497
Short name T398
Test name
Test status
Simulation time 329152100 ps
CPU time 51.23 seconds
Started Mar 21 03:15:22 PM PDT 24
Finished Mar 21 03:16:14 PM PDT 24
Peak memory 264688 kb
Host smart-92db413f-0161-4726-85ef-b8acabff902f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296738497 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.1296738497
Directory /workspace/10.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/10.flash_ctrl_smoke.258324273
Short name T619
Test name
Test status
Simulation time 36454700 ps
CPU time 146.88 seconds
Started Mar 21 03:15:22 PM PDT 24
Finished Mar 21 03:17:49 PM PDT 24
Peak memory 276280 kb
Host smart-32b4fdc4-6908-4b60-9f95-a11bdea371ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258324273 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.258324273
Directory /workspace/10.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/10.flash_ctrl_wo.2501546755
Short name T828
Test name
Test status
Simulation time 2033906500 ps
CPU time 172.95 seconds
Started Mar 21 03:15:23 PM PDT 24
Finished Mar 21 03:18:16 PM PDT 24
Peak memory 259664 kb
Host smart-5e53ecce-1bf2-4ddc-931a-00c821d104ef
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501546755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.flash_ctrl_wo.2501546755
Directory /workspace/10.flash_ctrl_wo/latest

Test location /workspace/coverage/default/11.flash_ctrl_alert_test.2498452983
Short name T779
Test name
Test status
Simulation time 75306300 ps
CPU time 13.88 seconds
Started Mar 21 03:15:47 PM PDT 24
Finished Mar 21 03:16:01 PM PDT 24
Peak memory 265252 kb
Host smart-2f539181-b2d2-44fe-9dec-d23fbc0e9b49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498452983 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test.
2498452983
Directory /workspace/11.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.flash_ctrl_connect.4153081822
Short name T873
Test name
Test status
Simulation time 26094300 ps
CPU time 15.77 seconds
Started Mar 21 03:15:33 PM PDT 24
Finished Mar 21 03:15:49 PM PDT 24
Peak memory 275836 kb
Host smart-ad5d00ca-d9d7-4327-892a-26c005b9dd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153081822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.4153081822
Directory /workspace/11.flash_ctrl_connect/latest

Test location /workspace/coverage/default/11.flash_ctrl_disable.2749572481
Short name T10
Test name
Test status
Simulation time 20353300 ps
CPU time 22 seconds
Started Mar 21 03:15:33 PM PDT 24
Finished Mar 21 03:15:55 PM PDT 24
Peak memory 280572 kb
Host smart-fbd6d705-5120-40a1-8972-f9b0b66b20ae
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749572481 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_disable.2749572481
Directory /workspace/11.flash_ctrl_disable/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.1833688068
Short name T294
Test name
Test status
Simulation time 10019538800 ps
CPU time 98.45 seconds
Started Mar 21 03:15:34 PM PDT 24
Finished Mar 21 03:17:13 PM PDT 24
Peak memory 330856 kb
Host smart-9bbd13f2-c9a9-43e2-816a-a47b47883232
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833688068 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.1833688068
Directory /workspace/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.2278972833
Short name T293
Test name
Test status
Simulation time 75406200 ps
CPU time 13.46 seconds
Started Mar 21 03:15:34 PM PDT 24
Finished Mar 21 03:15:47 PM PDT 24
Peak memory 265268 kb
Host smart-584a7ae1-f59f-4094-bc9c-245be0830ca1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278972833 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.2278972833
Directory /workspace/11.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_rma_reset.933654199
Short name T717
Test name
Test status
Simulation time 80143771100 ps
CPU time 902.2 seconds
Started Mar 21 03:15:32 PM PDT 24
Finished Mar 21 03:30:34 PM PDT 24
Peak memory 263232 kb
Host smart-cba16a93-05dc-4172-be11-c2fdb22e842e
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933654199 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.flash_ctrl_hw_rma_reset.933654199
Directory /workspace/11.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_sec_otp.3781199757
Short name T579
Test name
Test status
Simulation time 1834400000 ps
CPU time 92.8 seconds
Started Mar 21 03:15:32 PM PDT 24
Finished Mar 21 03:17:05 PM PDT 24
Peak memory 262624 kb
Host smart-64a85b5f-0bc5-4183-953f-7712f2f73f4d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781199757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_
hw_sec_otp.3781199757
Directory /workspace/11.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd_slow_flash.3913260292
Short name T21
Test name
Test status
Simulation time 34715414600 ps
CPU time 235.61 seconds
Started Mar 21 03:15:35 PM PDT 24
Finished Mar 21 03:19:30 PM PDT 24
Peak memory 284656 kb
Host smart-3ecba495-aee3-47b2-bba9-cd160665b21d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913260292 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd_slow_flash.3913260292
Directory /workspace/11.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/11.flash_ctrl_invalid_op.2982523379
Short name T536
Test name
Test status
Simulation time 1931249600 ps
CPU time 93.54 seconds
Started Mar 21 03:15:33 PM PDT 24
Finished Mar 21 03:17:06 PM PDT 24
Peak memory 262780 kb
Host smart-caa2dd2c-6856-4e18-982c-44529e4dbe7e
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982523379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.2
982523379
Directory /workspace/11.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/11.flash_ctrl_lcmgr_intg.202737438
Short name T608
Test name
Test status
Simulation time 49947300 ps
CPU time 14.18 seconds
Started Mar 21 03:15:33 PM PDT 24
Finished Mar 21 03:15:48 PM PDT 24
Peak memory 265272 kb
Host smart-1ba21086-c192-4662-a21f-8631b805a4a9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202737438 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.flash_ctrl_lcmgr_intg.202737438
Directory /workspace/11.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/11.flash_ctrl_mp_regions.2782261959
Short name T798
Test name
Test status
Simulation time 1715085100 ps
CPU time 150.71 seconds
Started Mar 21 03:15:35 PM PDT 24
Finished Mar 21 03:18:06 PM PDT 24
Peak memory 262868 kb
Host smart-1042eb0f-2641-449f-939e-949ecb308c34
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782261959 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.flash_ctrl_mp_regions.2782261959
Directory /workspace/11.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/11.flash_ctrl_otp_reset.2166818101
Short name T901
Test name
Test status
Simulation time 41514400 ps
CPU time 112.64 seconds
Started Mar 21 03:15:33 PM PDT 24
Finished Mar 21 03:17:25 PM PDT 24
Peak memory 259848 kb
Host smart-8376794a-8778-4357-9c81-9cf2fb9f0f1b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166818101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_o
tp_reset.2166818101
Directory /workspace/11.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_phy_arb.821898352
Short name T989
Test name
Test status
Simulation time 735047800 ps
CPU time 305.72 seconds
Started Mar 21 03:15:33 PM PDT 24
Finished Mar 21 03:20:39 PM PDT 24
Peak memory 265188 kb
Host smart-7ec4b9b7-f8d9-4dcc-aaa8-ac30becc0cee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=821898352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.821898352
Directory /workspace/11.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/11.flash_ctrl_prog_reset.2421283701
Short name T685
Test name
Test status
Simulation time 166787600 ps
CPU time 17.95 seconds
Started Mar 21 03:15:36 PM PDT 24
Finished Mar 21 03:15:54 PM PDT 24
Peak memory 260628 kb
Host smart-7e4ed1dd-3220-45ad-a983-8b89f32ba3e8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421283701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_prog_re
set.2421283701
Directory /workspace/11.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_rand_ops.654104524
Short name T561
Test name
Test status
Simulation time 932935800 ps
CPU time 1032.78 seconds
Started Mar 21 03:15:33 PM PDT 24
Finished Mar 21 03:32:46 PM PDT 24
Peak memory 286564 kb
Host smart-8e974540-ea9b-4469-986e-31f252d637b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654104524 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.654104524
Directory /workspace/11.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/11.flash_ctrl_re_evict.3225115909
Short name T566
Test name
Test status
Simulation time 134607300 ps
CPU time 32.31 seconds
Started Mar 21 03:15:31 PM PDT 24
Finished Mar 21 03:16:04 PM PDT 24
Peak memory 273548 kb
Host smart-635a584c-a88c-412d-9ab2-a812d780c65e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225115909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl
ash_ctrl_re_evict.3225115909
Directory /workspace/11.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/11.flash_ctrl_ro.1047835106
Short name T982
Test name
Test status
Simulation time 484485400 ps
CPU time 120.5 seconds
Started Mar 21 03:15:32 PM PDT 24
Finished Mar 21 03:17:32 PM PDT 24
Peak memory 281052 kb
Host smart-7c208b73-cf1a-4299-8b08-2a627d6a9dd9
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047835106 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.flash_ctrl_ro.1047835106
Directory /workspace/11.flash_ctrl_ro/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw.3825188582
Short name T999
Test name
Test status
Simulation time 30086254200 ps
CPU time 501.63 seconds
Started Mar 21 03:15:33 PM PDT 24
Finished Mar 21 03:23:55 PM PDT 24
Peak memory 314424 kb
Host smart-6f526094-9ce5-4d1d-80b7-d44ba56b4eb2
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825188582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_c
trl_rw.3825188582
Directory /workspace/11.flash_ctrl_rw/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict.1632446153
Short name T851
Test name
Test status
Simulation time 146590600 ps
CPU time 34.53 seconds
Started Mar 21 03:15:32 PM PDT 24
Finished Mar 21 03:16:07 PM PDT 24
Peak memory 273536 kb
Host smart-2936f869-0051-4cd6-ac86-38f74c32aaf5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632446153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl
ash_ctrl_rw_evict.1632446153
Directory /workspace/11.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.447793632
Short name T208
Test name
Test status
Simulation time 95584400 ps
CPU time 28.88 seconds
Started Mar 21 03:15:34 PM PDT 24
Finished Mar 21 03:16:03 PM PDT 24
Peak memory 276944 kb
Host smart-3e703738-3673-4a0f-815a-e8add32e2626
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447793632 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict_all_en.447793632
Directory /workspace/11.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/11.flash_ctrl_sec_info_access.1510381504
Short name T87
Test name
Test status
Simulation time 351261100 ps
CPU time 54.13 seconds
Started Mar 21 03:15:33 PM PDT 24
Finished Mar 21 03:16:27 PM PDT 24
Peak memory 262908 kb
Host smart-4dc4c137-53cd-4368-a66e-b4a8e1886441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510381504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.1510381504
Directory /workspace/11.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/11.flash_ctrl_smoke.4081495414
Short name T602
Test name
Test status
Simulation time 79776700 ps
CPU time 101.12 seconds
Started Mar 21 03:15:34 PM PDT 24
Finished Mar 21 03:17:15 PM PDT 24
Peak memory 275384 kb
Host smart-e62f107f-7e1b-4485-9640-9f2d9a24982e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081495414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.4081495414
Directory /workspace/11.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/11.flash_ctrl_wo.2734417104
Short name T552
Test name
Test status
Simulation time 2065215900 ps
CPU time 140.77 seconds
Started Mar 21 03:15:33 PM PDT 24
Finished Mar 21 03:17:54 PM PDT 24
Peak memory 259288 kb
Host smart-be465208-4f53-4582-87ac-45e0f0b2338a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734417104 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.flash_ctrl_wo.2734417104
Directory /workspace/11.flash_ctrl_wo/latest

Test location /workspace/coverage/default/12.flash_ctrl_alert_test.4039951912
Short name T496
Test name
Test status
Simulation time 35525000 ps
CPU time 13.93 seconds
Started Mar 21 03:15:46 PM PDT 24
Finished Mar 21 03:16:00 PM PDT 24
Peak memory 258248 kb
Host smart-d44b3328-e589-4928-87ee-51d551e4173a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039951912 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.
4039951912
Directory /workspace/12.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.flash_ctrl_connect.3964012839
Short name T682
Test name
Test status
Simulation time 26841000 ps
CPU time 16.02 seconds
Started Mar 21 03:15:46 PM PDT 24
Finished Mar 21 03:16:03 PM PDT 24
Peak memory 276060 kb
Host smart-42798e6b-a315-456a-83c9-6a0ba0263760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964012839 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.3964012839
Directory /workspace/12.flash_ctrl_connect/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_read_seed_err.530923048
Short name T361
Test name
Test status
Simulation time 151155900 ps
CPU time 13.42 seconds
Started Mar 21 03:15:51 PM PDT 24
Finished Mar 21 03:16:04 PM PDT 24
Peak memory 265244 kb
Host smart-4c6fb9e7-917b-419f-ba2b-8e7a066caac2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530923048 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_seed_err.530923048
Directory /workspace/12.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_rma_reset.2440323972
Short name T119
Test name
Test status
Simulation time 80144673700 ps
CPU time 970.16 seconds
Started Mar 21 03:15:45 PM PDT 24
Finished Mar 21 03:31:56 PM PDT 24
Peak memory 263304 kb
Host smart-0d57c0fd-36b1-4c4e-bf57-3840633bd598
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440323972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.flash_ctrl_hw_rma_reset.2440323972
Directory /workspace/12.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_sec_otp.3701550244
Short name T601
Test name
Test status
Simulation time 18895212000 ps
CPU time 87.36 seconds
Started Mar 21 03:15:50 PM PDT 24
Finished Mar 21 03:17:17 PM PDT 24
Peak memory 262588 kb
Host smart-e2d320b5-4f95-4acf-b5ae-d459327a8609
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701550244 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_
hw_sec_otp.3701550244
Directory /workspace/12.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd_slow_flash.120052904
Short name T335
Test name
Test status
Simulation time 8035749200 ps
CPU time 234.98 seconds
Started Mar 21 03:15:47 PM PDT 24
Finished Mar 21 03:19:42 PM PDT 24
Peak memory 289776 kb
Host smart-74e1f57a-23ad-4a5d-a5fa-c199860fd1e6
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120052904 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd_slow_flash.120052904
Directory /workspace/12.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/12.flash_ctrl_invalid_op.2037321048
Short name T180
Test name
Test status
Simulation time 20885599400 ps
CPU time 72.75 seconds
Started Mar 21 03:15:50 PM PDT 24
Finished Mar 21 03:17:03 PM PDT 24
Peak memory 260564 kb
Host smart-c7372577-cdbf-4313-aca7-ec9f885e8044
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037321048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.2
037321048
Directory /workspace/12.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/12.flash_ctrl_mp_regions.2181508342
Short name T102
Test name
Test status
Simulation time 24396261600 ps
CPU time 302.84 seconds
Started Mar 21 03:15:46 PM PDT 24
Finished Mar 21 03:20:49 PM PDT 24
Peak memory 274668 kb
Host smart-af5fcc35-ef6e-4672-9685-5d12853122ec
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181508342 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 12.flash_ctrl_mp_regions.2181508342
Directory /workspace/12.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/12.flash_ctrl_otp_reset.736168664
Short name T863
Test name
Test status
Simulation time 83139800 ps
CPU time 132.15 seconds
Started Mar 21 03:15:45 PM PDT 24
Finished Mar 21 03:17:58 PM PDT 24
Peak memory 260936 kb
Host smart-23ade67e-4be7-418e-b874-6e316e9f82f1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736168664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_ot
p_reset.736168664
Directory /workspace/12.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_phy_arb.2267744632
Short name T189
Test name
Test status
Simulation time 768081700 ps
CPU time 503.67 seconds
Started Mar 21 03:15:47 PM PDT 24
Finished Mar 21 03:24:11 PM PDT 24
Peak memory 265208 kb
Host smart-bae52f85-6c58-4525-9200-adb5bdba584e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2267744632 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.2267744632
Directory /workspace/12.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/12.flash_ctrl_prog_reset.3804614816
Short name T639
Test name
Test status
Simulation time 37561500 ps
CPU time 13.64 seconds
Started Mar 21 03:15:45 PM PDT 24
Finished Mar 21 03:15:59 PM PDT 24
Peak memory 260192 kb
Host smart-07f28d9e-1ac7-4e11-be94-cd35026f1125
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804614816 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_prog_re
set.3804614816
Directory /workspace/12.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_rand_ops.1353893954
Short name T97
Test name
Test status
Simulation time 327605000 ps
CPU time 550.55 seconds
Started Mar 21 03:15:47 PM PDT 24
Finished Mar 21 03:24:58 PM PDT 24
Peak memory 281524 kb
Host smart-2c1c29c4-d0bc-44ad-8dac-4dae88749368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353893954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.1353893954
Directory /workspace/12.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/12.flash_ctrl_re_evict.1357144214
Short name T556
Test name
Test status
Simulation time 264499900 ps
CPU time 40.36 seconds
Started Mar 21 03:15:48 PM PDT 24
Finished Mar 21 03:16:29 PM PDT 24
Peak memory 266312 kb
Host smart-3ff6fcc0-c82a-4279-9d8b-213be8daf989
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357144214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl
ash_ctrl_re_evict.1357144214
Directory /workspace/12.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_ro.3559787904
Short name T465
Test name
Test status
Simulation time 705285900 ps
CPU time 115.05 seconds
Started Mar 21 03:15:45 PM PDT 24
Finished Mar 21 03:17:40 PM PDT 24
Peak memory 281100 kb
Host smart-2c84dc1e-f1e0-4b4f-87f2-55e885fb0a67
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559787904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.flash_ctrl_ro.3559787904
Directory /workspace/12.flash_ctrl_ro/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw.921220957
Short name T1040
Test name
Test status
Simulation time 14377123700 ps
CPU time 531.81 seconds
Started Mar 21 03:15:49 PM PDT 24
Finished Mar 21 03:24:41 PM PDT 24
Peak memory 312752 kb
Host smart-a00c492a-e5c6-4bf2-9dca-6c930589c96b
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921220957 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ct
rl_rw.921220957
Directory /workspace/12.flash_ctrl_rw/latest

Test location /workspace/coverage/default/12.flash_ctrl_smoke.1437447464
Short name T984
Test name
Test status
Simulation time 61563700 ps
CPU time 124.57 seconds
Started Mar 21 03:15:50 PM PDT 24
Finished Mar 21 03:17:55 PM PDT 24
Peak memory 276100 kb
Host smart-ce026ee9-eecb-4df6-a0fe-1464fe835de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437447464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.1437447464
Directory /workspace/12.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/12.flash_ctrl_wo.3303599799
Short name T933
Test name
Test status
Simulation time 1873336700 ps
CPU time 153.75 seconds
Started Mar 21 03:15:47 PM PDT 24
Finished Mar 21 03:18:21 PM PDT 24
Peak memory 259084 kb
Host smart-1d917baf-7a30-4f0a-826a-6b25e37c4250
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303599799 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.flash_ctrl_wo.3303599799
Directory /workspace/12.flash_ctrl_wo/latest

Test location /workspace/coverage/default/13.flash_ctrl_alert_test.3000030039
Short name T869
Test name
Test status
Simulation time 30013700 ps
CPU time 13.76 seconds
Started Mar 21 03:16:07 PM PDT 24
Finished Mar 21 03:16:21 PM PDT 24
Peak memory 265160 kb
Host smart-f88aec5d-6bd4-4843-ad64-0aef9c364eb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000030039 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test.
3000030039
Directory /workspace/13.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.flash_ctrl_connect.2753315225
Short name T974
Test name
Test status
Simulation time 15825000 ps
CPU time 16.03 seconds
Started Mar 21 03:16:07 PM PDT 24
Finished Mar 21 03:16:24 PM PDT 24
Peak memory 275184 kb
Host smart-706806be-8e35-4420-8de0-2c45029a36d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753315225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.2753315225
Directory /workspace/13.flash_ctrl_connect/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.663805100
Short name T140
Test name
Test status
Simulation time 10020320500 ps
CPU time 184.72 seconds
Started Mar 21 03:16:08 PM PDT 24
Finished Mar 21 03:19:14 PM PDT 24
Peak memory 292448 kb
Host smart-357c68ed-e331-4131-82fc-b64ae5811843
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663805100 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.663805100
Directory /workspace/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_read_seed_err.3348871236
Short name T852
Test name
Test status
Simulation time 24401700 ps
CPU time 13.68 seconds
Started Mar 21 03:16:08 PM PDT 24
Finished Mar 21 03:16:23 PM PDT 24
Peak memory 265212 kb
Host smart-05585f47-d913-4789-ae10-bebc4b5ad7ed
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348871236 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.3348871236
Directory /workspace/13.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_rma_reset.721044606
Short name T937
Test name
Test status
Simulation time 160167676200 ps
CPU time 1042.82 seconds
Started Mar 21 03:15:59 PM PDT 24
Finished Mar 21 03:33:22 PM PDT 24
Peak memory 263604 kb
Host smart-4594a423-62db-46e0-ace4-0a5b12d80d02
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721044606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.flash_ctrl_hw_rma_reset.721044606
Directory /workspace/13.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_sec_otp.3361593649
Short name T532
Test name
Test status
Simulation time 1727636800 ps
CPU time 158.42 seconds
Started Mar 21 03:15:58 PM PDT 24
Finished Mar 21 03:18:37 PM PDT 24
Peak memory 262496 kb
Host smart-11e12efa-c45c-4f2b-9d48-cee8fed3bd6b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361593649 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_
hw_sec_otp.3361593649
Directory /workspace/13.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd_slow_flash.2660837825
Short name T341
Test name
Test status
Simulation time 17385591700 ps
CPU time 288.64 seconds
Started Mar 21 03:15:57 PM PDT 24
Finished Mar 21 03:20:45 PM PDT 24
Peak memory 284740 kb
Host smart-d71ed07c-c538-46be-937d-fcb5acb0540f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660837825 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd_slow_flash.2660837825
Directory /workspace/13.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/13.flash_ctrl_invalid_op.1859349355
Short name T83
Test name
Test status
Simulation time 1983991200 ps
CPU time 74.69 seconds
Started Mar 21 03:15:56 PM PDT 24
Finished Mar 21 03:17:11 PM PDT 24
Peak memory 263280 kb
Host smart-6c3e34e2-ff65-48e6-94be-148c1f8722d9
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859349355 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.1
859349355
Directory /workspace/13.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/13.flash_ctrl_lcmgr_intg.2916611167
Short name T550
Test name
Test status
Simulation time 26315600 ps
CPU time 13.75 seconds
Started Mar 21 03:16:11 PM PDT 24
Finished Mar 21 03:16:25 PM PDT 24
Peak memory 265260 kb
Host smart-0e1b4e32-c998-4972-a489-49b8c847dd01
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916611167 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.flash_ctrl_lcmgr_intg.2916611167
Directory /workspace/13.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/13.flash_ctrl_mp_regions.2739871105
Short name T693
Test name
Test status
Simulation time 67715893200 ps
CPU time 884.85 seconds
Started Mar 21 03:15:59 PM PDT 24
Finished Mar 21 03:30:44 PM PDT 24
Peak memory 274484 kb
Host smart-7aaff5df-27f1-4975-b17e-583d9204e822
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739871105 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 13.flash_ctrl_mp_regions.2739871105
Directory /workspace/13.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/13.flash_ctrl_otp_reset.2718417481
Short name T1019
Test name
Test status
Simulation time 41931500 ps
CPU time 112.96 seconds
Started Mar 21 03:15:59 PM PDT 24
Finished Mar 21 03:17:53 PM PDT 24
Peak memory 259912 kb
Host smart-81a50458-b153-43f9-ab24-dfa71e0bcc45
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718417481 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_o
tp_reset.2718417481
Directory /workspace/13.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_phy_arb.527743682
Short name T741
Test name
Test status
Simulation time 2318201900 ps
CPU time 417.87 seconds
Started Mar 21 03:15:58 PM PDT 24
Finished Mar 21 03:22:56 PM PDT 24
Peak memory 261504 kb
Host smart-b3f51c9d-1537-4e4b-a63d-3b9defcb0a83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=527743682 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.527743682
Directory /workspace/13.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/13.flash_ctrl_prog_reset.3318088093
Short name T448
Test name
Test status
Simulation time 1860380100 ps
CPU time 21.52 seconds
Started Mar 21 03:15:59 PM PDT 24
Finished Mar 21 03:16:21 PM PDT 24
Peak memory 265260 kb
Host smart-4a3da7f8-859e-4a14-b949-61168998a0ba
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318088093 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_prog_re
set.3318088093
Directory /workspace/13.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_rand_ops.1757682804
Short name T935
Test name
Test status
Simulation time 81890600 ps
CPU time 433.23 seconds
Started Mar 21 03:15:50 PM PDT 24
Finished Mar 21 03:23:04 PM PDT 24
Peak memory 283540 kb
Host smart-d2a980d0-94f7-45aa-b0ec-4c445c7c436e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757682804 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.1757682804
Directory /workspace/13.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/13.flash_ctrl_re_evict.3776451201
Short name T182
Test name
Test status
Simulation time 600589800 ps
CPU time 34.5 seconds
Started Mar 21 03:16:08 PM PDT 24
Finished Mar 21 03:16:43 PM PDT 24
Peak memory 273544 kb
Host smart-51d18f42-fc1f-48fb-987c-d74ba1102ccb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776451201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl
ash_ctrl_re_evict.3776451201
Directory /workspace/13.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_ro.2343218690
Short name T1023
Test name
Test status
Simulation time 337171400 ps
CPU time 106.58 seconds
Started Mar 21 03:15:56 PM PDT 24
Finished Mar 21 03:17:43 PM PDT 24
Peak memory 281376 kb
Host smart-d736ea1e-eb75-43e0-bf0d-216af86e415a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343218690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.flash_ctrl_ro.2343218690
Directory /workspace/13.flash_ctrl_ro/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw.2642635136
Short name T782
Test name
Test status
Simulation time 30480627000 ps
CPU time 581.21 seconds
Started Mar 21 03:15:58 PM PDT 24
Finished Mar 21 03:25:39 PM PDT 24
Peak memory 314156 kb
Host smart-6c4c5cdc-efd8-40ba-920f-2e79cd002e24
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642635136 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_c
trl_rw.2642635136
Directory /workspace/13.flash_ctrl_rw/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict.1380144892
Short name T1032
Test name
Test status
Simulation time 80009300 ps
CPU time 28.28 seconds
Started Mar 21 03:16:02 PM PDT 24
Finished Mar 21 03:16:30 PM PDT 24
Peak memory 273540 kb
Host smart-a34a81f0-7d5e-465a-a5f0-b8c5e90e1a8e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380144892 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl
ash_ctrl_rw_evict.1380144892
Directory /workspace/13.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict_all_en.2777076949
Short name T592
Test name
Test status
Simulation time 64955300 ps
CPU time 32.22 seconds
Started Mar 21 03:16:07 PM PDT 24
Finished Mar 21 03:16:40 PM PDT 24
Peak memory 274916 kb
Host smart-9374d4d9-12a9-4561-9893-2521633e9334
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777076949 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict_all_en.2777076949
Directory /workspace/13.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/13.flash_ctrl_sec_info_access.1693424100
Short name T400
Test name
Test status
Simulation time 1058666800 ps
CPU time 64.28 seconds
Started Mar 21 03:16:07 PM PDT 24
Finished Mar 21 03:17:11 PM PDT 24
Peak memory 262756 kb
Host smart-e6898f5f-67da-4068-8538-e05fb4883e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693424100 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.1693424100
Directory /workspace/13.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/13.flash_ctrl_smoke.1666979440
Short name T760
Test name
Test status
Simulation time 118735900 ps
CPU time 170.44 seconds
Started Mar 21 03:15:51 PM PDT 24
Finished Mar 21 03:18:41 PM PDT 24
Peak memory 276840 kb
Host smart-ce3e461f-0700-42af-a709-86d8439611be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666979440 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.1666979440
Directory /workspace/13.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/13.flash_ctrl_wo.3071396313
Short name T694
Test name
Test status
Simulation time 4973745800 ps
CPU time 173.27 seconds
Started Mar 21 03:15:57 PM PDT 24
Finished Mar 21 03:18:50 PM PDT 24
Peak memory 259620 kb
Host smart-5953d1e6-4a3e-46d3-bb92-d9e3d64f4b9f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071396313 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.flash_ctrl_wo.3071396313
Directory /workspace/13.flash_ctrl_wo/latest

Test location /workspace/coverage/default/14.flash_ctrl_alert_test.1269345844
Short name T583
Test name
Test status
Simulation time 30131000 ps
CPU time 13.58 seconds
Started Mar 21 03:16:19 PM PDT 24
Finished Mar 21 03:16:33 PM PDT 24
Peak memory 258132 kb
Host smart-06a08a4b-e477-45e6-90dc-a3735972755e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269345844 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test.
1269345844
Directory /workspace/14.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.flash_ctrl_connect.700433262
Short name T423
Test name
Test status
Simulation time 14221800 ps
CPU time 16.36 seconds
Started Mar 21 03:16:21 PM PDT 24
Finished Mar 21 03:16:37 PM PDT 24
Peak memory 276084 kb
Host smart-d8831cc2-9b2b-4bd6-b095-92802082aff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700433262 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.700433262
Directory /workspace/14.flash_ctrl_connect/latest

Test location /workspace/coverage/default/14.flash_ctrl_disable.1103046848
Short name T75
Test name
Test status
Simulation time 14947700 ps
CPU time 22.48 seconds
Started Mar 21 03:16:20 PM PDT 24
Finished Mar 21 03:16:43 PM PDT 24
Peak memory 265264 kb
Host smart-f0e976c4-5e12-4707-aee0-0f8177ddc2cc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103046848 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.flash_ctrl_disable.1103046848
Directory /workspace/14.flash_ctrl_disable/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.3210361080
Short name T228
Test name
Test status
Simulation time 10018992800 ps
CPU time 66.47 seconds
Started Mar 21 03:16:20 PM PDT 24
Finished Mar 21 03:17:27 PM PDT 24
Peak memory 280372 kb
Host smart-88423e90-1f02-4b89-83fd-edabcb670a9e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210361080 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.3210361080
Directory /workspace/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_read_seed_err.2350482519
Short name T919
Test name
Test status
Simulation time 45845000 ps
CPU time 13.63 seconds
Started Mar 21 03:16:20 PM PDT 24
Finished Mar 21 03:16:34 PM PDT 24
Peak memory 259300 kb
Host smart-7e6e3c5d-e4ca-4db1-af89-dbaa8dc904eb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350482519 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_read_seed_err.2350482519
Directory /workspace/14.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_sec_otp.928766415
Short name T313
Test name
Test status
Simulation time 3864570100 ps
CPU time 68.2 seconds
Started Mar 21 03:16:11 PM PDT 24
Finished Mar 21 03:17:20 PM PDT 24
Peak memory 262688 kb
Host smart-414dc681-47b7-43a3-86c3-5703ea8b129c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928766415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_h
w_sec_otp.928766415
Directory /workspace/14.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.2044371909
Short name T793
Test name
Test status
Simulation time 34463145000 ps
CPU time 249.95 seconds
Started Mar 21 03:16:19 PM PDT 24
Finished Mar 21 03:20:29 PM PDT 24
Peak memory 289824 kb
Host smart-102ee388-ab3d-4680-a9f1-0fa15f74b4e1
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044371909 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd_slow_flash.2044371909
Directory /workspace/14.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/14.flash_ctrl_invalid_op.1030422294
Short name T541
Test name
Test status
Simulation time 8380743100 ps
CPU time 74.36 seconds
Started Mar 21 03:16:19 PM PDT 24
Finished Mar 21 03:17:34 PM PDT 24
Peak memory 260720 kb
Host smart-b9354523-431c-4369-bffb-9bec4e6e6b41
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030422294 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.1
030422294
Directory /workspace/14.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/14.flash_ctrl_lcmgr_intg.3572839340
Short name T537
Test name
Test status
Simulation time 31314300 ps
CPU time 13.94 seconds
Started Mar 21 03:16:18 PM PDT 24
Finished Mar 21 03:16:32 PM PDT 24
Peak memory 259712 kb
Host smart-a3289455-8f6a-4743-9526-cacc248d4e6c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572839340 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.flash_ctrl_lcmgr_intg.3572839340
Directory /workspace/14.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/14.flash_ctrl_mp_regions.1369559428
Short name T673
Test name
Test status
Simulation time 70946304700 ps
CPU time 1131.84 seconds
Started Mar 21 03:16:19 PM PDT 24
Finished Mar 21 03:35:11 PM PDT 24
Peak memory 273628 kb
Host smart-d5f64523-6ac8-42d8-8aaa-d8eaabe15582
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369559428 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.flash_ctrl_mp_regions.1369559428
Directory /workspace/14.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/14.flash_ctrl_otp_reset.2380013930
Short name T633
Test name
Test status
Simulation time 74470800 ps
CPU time 136.38 seconds
Started Mar 21 03:16:08 PM PDT 24
Finished Mar 21 03:18:25 PM PDT 24
Peak memory 259748 kb
Host smart-fff275e1-77fb-44b0-a2e6-68c58fd88f7d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380013930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_o
tp_reset.2380013930
Directory /workspace/14.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_phy_arb.2072938910
Short name T571
Test name
Test status
Simulation time 2924254500 ps
CPU time 459.43 seconds
Started Mar 21 03:16:08 PM PDT 24
Finished Mar 21 03:23:47 PM PDT 24
Peak memory 262464 kb
Host smart-680316c3-a5f0-4388-a7f4-b61921db7548
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2072938910 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.2072938910
Directory /workspace/14.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/14.flash_ctrl_prog_reset.3146924754
Short name T322
Test name
Test status
Simulation time 178024800 ps
CPU time 19.2 seconds
Started Mar 21 03:16:19 PM PDT 24
Finished Mar 21 03:16:38 PM PDT 24
Peak memory 261196 kb
Host smart-c28a28ff-3a7c-488b-aea0-cd843e410e4b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146924754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_prog_re
set.3146924754
Directory /workspace/14.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_rand_ops.773702598
Short name T570
Test name
Test status
Simulation time 928994600 ps
CPU time 908.64 seconds
Started Mar 21 03:16:07 PM PDT 24
Finished Mar 21 03:31:17 PM PDT 24
Peak memory 286056 kb
Host smart-4e7faf48-0ac7-4be3-a127-d9e3b6b77d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773702598 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.773702598
Directory /workspace/14.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/14.flash_ctrl_re_evict.3731534263
Short name T353
Test name
Test status
Simulation time 148717300 ps
CPU time 36.9 seconds
Started Mar 21 03:16:20 PM PDT 24
Finished Mar 21 03:16:57 PM PDT 24
Peak memory 273544 kb
Host smart-2c9a886f-a866-4692-a5d2-c6e4e77833a8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731534263 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_re_evict.3731534263
Directory /workspace/14.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_ro.1001496064
Short name T221
Test name
Test status
Simulation time 911835000 ps
CPU time 115.02 seconds
Started Mar 21 03:16:20 PM PDT 24
Finished Mar 21 03:18:15 PM PDT 24
Peak memory 281328 kb
Host smart-17b59179-4bca-4678-b40b-5d7c4b0b7d97
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001496064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.flash_ctrl_ro.1001496064
Directory /workspace/14.flash_ctrl_ro/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict.653420924
Short name T866
Test name
Test status
Simulation time 63246100 ps
CPU time 32.39 seconds
Started Mar 21 03:16:19 PM PDT 24
Finished Mar 21 03:16:51 PM PDT 24
Peak memory 278148 kb
Host smart-33ac5af1-4bd6-4a16-b07c-2756a4e5dd60
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653420924 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fla
sh_ctrl_rw_evict.653420924
Directory /workspace/14.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict_all_en.202046966
Short name T286
Test name
Test status
Simulation time 122651600 ps
CPU time 39.02 seconds
Started Mar 21 03:16:24 PM PDT 24
Finished Mar 21 03:17:03 PM PDT 24
Peak memory 266348 kb
Host smart-23cef4d0-0b86-435c-a5b9-0e8a4e06ec63
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202046966 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict_all_en.202046966
Directory /workspace/14.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/14.flash_ctrl_sec_info_access.567094297
Short name T658
Test name
Test status
Simulation time 9463394300 ps
CPU time 64.91 seconds
Started Mar 21 03:16:20 PM PDT 24
Finished Mar 21 03:17:26 PM PDT 24
Peak memory 264664 kb
Host smart-04391de4-e315-479b-aa1d-146c30766b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567094297 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.567094297
Directory /workspace/14.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/14.flash_ctrl_smoke.3000401558
Short name T576
Test name
Test status
Simulation time 23012000 ps
CPU time 52.93 seconds
Started Mar 21 03:16:08 PM PDT 24
Finished Mar 21 03:17:02 PM PDT 24
Peak memory 270672 kb
Host smart-0c6cf0cd-c5fb-4f97-a5d5-97a7bbaf595e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000401558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.3000401558
Directory /workspace/14.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/14.flash_ctrl_wo.1952589234
Short name T92
Test name
Test status
Simulation time 7595333500 ps
CPU time 155.01 seconds
Started Mar 21 03:16:19 PM PDT 24
Finished Mar 21 03:18:55 PM PDT 24
Peak memory 265228 kb
Host smart-452ba179-2518-460a-8c88-7bc29030a753
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952589234 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 14.flash_ctrl_wo.1952589234
Directory /workspace/14.flash_ctrl_wo/latest

Test location /workspace/coverage/default/15.flash_ctrl_alert_test.3676557757
Short name T549
Test name
Test status
Simulation time 128037500 ps
CPU time 14.05 seconds
Started Mar 21 03:16:33 PM PDT 24
Finished Mar 21 03:16:47 PM PDT 24
Peak memory 265212 kb
Host smart-8c2b6aa5-9eb4-464a-a6c7-cd1270fd962b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676557757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test.
3676557757
Directory /workspace/15.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.flash_ctrl_connect.3512194414
Short name T409
Test name
Test status
Simulation time 16148500 ps
CPU time 16.39 seconds
Started Mar 21 03:16:32 PM PDT 24
Finished Mar 21 03:16:49 PM PDT 24
Peak memory 275064 kb
Host smart-c21a6860-9c52-4688-ae44-36af4db4ba78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512194414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.3512194414
Directory /workspace/15.flash_ctrl_connect/latest

Test location /workspace/coverage/default/15.flash_ctrl_disable.464239891
Short name T373
Test name
Test status
Simulation time 25277600 ps
CPU time 22.34 seconds
Started Mar 21 03:16:33 PM PDT 24
Finished Mar 21 03:16:56 PM PDT 24
Peak memory 280828 kb
Host smart-2a7282d4-ddf7-47cd-b25f-5d32f3ed5548
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464239891 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.flash_ctrl_disable.464239891
Directory /workspace/15.flash_ctrl_disable/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.3771347766
Short name T360
Test name
Test status
Simulation time 24455800 ps
CPU time 13.49 seconds
Started Mar 21 03:16:34 PM PDT 24
Finished Mar 21 03:16:48 PM PDT 24
Peak memory 258200 kb
Host smart-1d469257-b1c1-425b-a8e8-a11ec2ad260e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771347766 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_read_seed_err.3771347766
Directory /workspace/15.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_rma_reset.1052763959
Short name T121
Test name
Test status
Simulation time 160162368200 ps
CPU time 1012.13 seconds
Started Mar 21 03:16:33 PM PDT 24
Finished Mar 21 03:33:26 PM PDT 24
Peak memory 263416 kb
Host smart-8362ab02-19a3-4621-9320-119007eb5042
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052763959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.flash_ctrl_hw_rma_reset.1052763959
Directory /workspace/15.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_sec_otp.1133497307
Short name T846
Test name
Test status
Simulation time 16497558800 ps
CPU time 92.86 seconds
Started Mar 21 03:16:33 PM PDT 24
Finished Mar 21 03:18:06 PM PDT 24
Peak memory 262532 kb
Host smart-17432b45-1841-47db-aba2-4c6b946f7e11
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133497307 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_
hw_sec_otp.1133497307
Directory /workspace/15.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd_slow_flash.702043015
Short name T346
Test name
Test status
Simulation time 34436045800 ps
CPU time 251.17 seconds
Started Mar 21 03:16:33 PM PDT 24
Finished Mar 21 03:20:44 PM PDT 24
Peak memory 289820 kb
Host smart-f3753217-85df-42d3-8ea5-1477a5cb531b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702043015 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd_slow_flash.702043015
Directory /workspace/15.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/15.flash_ctrl_invalid_op.2243710285
Short name T178
Test name
Test status
Simulation time 3871225300 ps
CPU time 78.38 seconds
Started Mar 21 03:16:33 PM PDT 24
Finished Mar 21 03:17:52 PM PDT 24
Peak memory 263232 kb
Host smart-fce19fae-929d-46cd-9fd1-95b918cd4b9c
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243710285 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.2
243710285
Directory /workspace/15.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/15.flash_ctrl_lcmgr_intg.3337212871
Short name T794
Test name
Test status
Simulation time 25984200 ps
CPU time 13.64 seconds
Started Mar 21 03:16:33 PM PDT 24
Finished Mar 21 03:16:47 PM PDT 24
Peak memory 265240 kb
Host smart-75fd4551-8a1e-48dc-aed5-293d4cc2a78b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337212871 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.flash_ctrl_lcmgr_intg.3337212871
Directory /workspace/15.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/15.flash_ctrl_mp_regions.2675920715
Short name T724
Test name
Test status
Simulation time 81287694500 ps
CPU time 762.96 seconds
Started Mar 21 03:16:33 PM PDT 24
Finished Mar 21 03:29:16 PM PDT 24
Peak memory 274440 kb
Host smart-38cf9312-d41b-42af-96f1-551a3d660494
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675920715 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.flash_ctrl_mp_regions.2675920715
Directory /workspace/15.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/15.flash_ctrl_otp_reset.280349273
Short name T11
Test name
Test status
Simulation time 75025600 ps
CPU time 132.92 seconds
Started Mar 21 03:16:33 PM PDT 24
Finished Mar 21 03:18:46 PM PDT 24
Peak memory 264180 kb
Host smart-94946970-58e0-4661-a06c-5e90f97e649e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280349273 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_ot
p_reset.280349273
Directory /workspace/15.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_phy_arb.3033542065
Short name T731
Test name
Test status
Simulation time 1659884400 ps
CPU time 436.99 seconds
Started Mar 21 03:16:33 PM PDT 24
Finished Mar 21 03:23:50 PM PDT 24
Peak memory 261588 kb
Host smart-e1cf02ef-f070-4145-9259-ac2df479ff09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3033542065 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.3033542065
Directory /workspace/15.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/15.flash_ctrl_prog_reset.2097408289
Short name T691
Test name
Test status
Simulation time 36298600 ps
CPU time 13.74 seconds
Started Mar 21 03:16:34 PM PDT 24
Finished Mar 21 03:16:48 PM PDT 24
Peak memory 260148 kb
Host smart-e5a31cf8-0544-423c-a135-c9daaeaaa3fb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097408289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_prog_re
set.2097408289
Directory /workspace/15.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_rand_ops.4070720530
Short name T599
Test name
Test status
Simulation time 693279900 ps
CPU time 1132.31 seconds
Started Mar 21 03:16:32 PM PDT 24
Finished Mar 21 03:35:24 PM PDT 24
Peak memory 285876 kb
Host smart-0ba5de62-af03-48b1-ac0d-b6a8d3ec579c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070720530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.4070720530
Directory /workspace/15.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/15.flash_ctrl_re_evict.1925264063
Short name T661
Test name
Test status
Simulation time 420322700 ps
CPU time 37.78 seconds
Started Mar 21 03:16:33 PM PDT 24
Finished Mar 21 03:17:11 PM PDT 24
Peak memory 273632 kb
Host smart-f2d54a21-f405-41ca-ae79-e8f31e204488
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925264063 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl
ash_ctrl_re_evict.1925264063
Directory /workspace/15.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_ro.1220980788
Short name T985
Test name
Test status
Simulation time 440785500 ps
CPU time 111.96 seconds
Started Mar 21 03:16:33 PM PDT 24
Finished Mar 21 03:18:25 PM PDT 24
Peak memory 280980 kb
Host smart-722beb8e-d41d-4537-8177-bf5baed7ea19
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220980788 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.flash_ctrl_ro.1220980788
Directory /workspace/15.flash_ctrl_ro/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw.4253499024
Short name T19
Test name
Test status
Simulation time 3006241400 ps
CPU time 537.89 seconds
Started Mar 21 03:16:34 PM PDT 24
Finished Mar 21 03:25:32 PM PDT 24
Peak memory 314456 kb
Host smart-47006744-1840-46a1-aac1-5fbcd514a644
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253499024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_c
trl_rw.4253499024
Directory /workspace/15.flash_ctrl_rw/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict.195984644
Short name T651
Test name
Test status
Simulation time 73634600 ps
CPU time 31.49 seconds
Started Mar 21 03:16:35 PM PDT 24
Finished Mar 21 03:17:06 PM PDT 24
Peak memory 273596 kb
Host smart-c0012daf-1ef0-49e7-9cf5-e66fd184a777
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195984644 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla
sh_ctrl_rw_evict.195984644
Directory /workspace/15.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.2259822399
Short name T906
Test name
Test status
Simulation time 30181200 ps
CPU time 31.22 seconds
Started Mar 21 03:16:34 PM PDT 24
Finished Mar 21 03:17:05 PM PDT 24
Peak memory 274624 kb
Host smart-01de8eb7-ad14-404c-acff-97a6f8dcbdaa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259822399 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict_all_en.2259822399
Directory /workspace/15.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/15.flash_ctrl_sec_info_access.3346974167
Short name T387
Test name
Test status
Simulation time 2104774000 ps
CPU time 80.13 seconds
Started Mar 21 03:16:32 PM PDT 24
Finished Mar 21 03:17:53 PM PDT 24
Peak memory 262764 kb
Host smart-83ac3019-47b5-4553-bab1-cbe137705810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346974167 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.3346974167
Directory /workspace/15.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/15.flash_ctrl_smoke.3824924260
Short name T810
Test name
Test status
Simulation time 25207400 ps
CPU time 124.36 seconds
Started Mar 21 03:16:20 PM PDT 24
Finished Mar 21 03:18:25 PM PDT 24
Peak memory 275680 kb
Host smart-68ff6fc8-3c97-4022-99e6-86034d2bc2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824924260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.3824924260
Directory /workspace/15.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/15.flash_ctrl_wo.2367737650
Short name T683
Test name
Test status
Simulation time 3767852800 ps
CPU time 173.32 seconds
Started Mar 21 03:16:34 PM PDT 24
Finished Mar 21 03:19:27 PM PDT 24
Peak memory 265196 kb
Host smart-6964ccab-163f-4f1f-be54-5e9f00e0e772
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367737650 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.flash_ctrl_wo.2367737650
Directory /workspace/15.flash_ctrl_wo/latest

Test location /workspace/coverage/default/16.flash_ctrl_alert_test.3623019238
Short name T624
Test name
Test status
Simulation time 26540400 ps
CPU time 14.01 seconds
Started Mar 21 03:16:46 PM PDT 24
Finished Mar 21 03:17:00 PM PDT 24
Peak memory 264316 kb
Host smart-2cde2cf5-be92-4ffd-ac58-58d04e46927e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623019238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.
3623019238
Directory /workspace/16.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.flash_ctrl_connect.1733646738
Short name T418
Test name
Test status
Simulation time 48965500 ps
CPU time 16.36 seconds
Started Mar 21 03:16:45 PM PDT 24
Finished Mar 21 03:17:01 PM PDT 24
Peak memory 275076 kb
Host smart-9525f086-bebc-4571-817a-0d469db076f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733646738 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.1733646738
Directory /workspace/16.flash_ctrl_connect/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.2137294649
Short name T723
Test name
Test status
Simulation time 10024067200 ps
CPU time 145.63 seconds
Started Mar 21 03:16:46 PM PDT 24
Finished Mar 21 03:19:11 PM PDT 24
Peak memory 278916 kb
Host smart-fbc5ab05-7156-4c15-a603-64549c17cbbb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137294649 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.2137294649
Directory /workspace/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.1241650485
Short name T292
Test name
Test status
Simulation time 37932500 ps
CPU time 13.58 seconds
Started Mar 21 03:16:46 PM PDT 24
Finished Mar 21 03:17:00 PM PDT 24
Peak memory 265372 kb
Host smart-bc128eb8-8a6a-4c99-8f1b-5add37d40f56
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241650485 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.1241650485
Directory /workspace/16.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_rma_reset.2838447338
Short name T155
Test name
Test status
Simulation time 160183110800 ps
CPU time 1034.26 seconds
Started Mar 21 03:16:46 PM PDT 24
Finished Mar 21 03:34:01 PM PDT 24
Peak memory 264140 kb
Host smart-fe5edc9b-fc89-49b8-9c07-85055f622dab
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838447338 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.flash_ctrl_hw_rma_reset.2838447338
Directory /workspace/16.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_sec_otp.3816915582
Short name T323
Test name
Test status
Simulation time 6986880700 ps
CPU time 160.83 seconds
Started Mar 21 03:16:48 PM PDT 24
Finished Mar 21 03:19:29 PM PDT 24
Peak memory 259476 kb
Host smart-bdac4640-a4a3-47b4-9a4a-c8bc1e41adaf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816915582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_
hw_sec_otp.3816915582
Directory /workspace/16.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.2047353281
Short name T475
Test name
Test status
Simulation time 8521295200 ps
CPU time 214.23 seconds
Started Mar 21 03:16:46 PM PDT 24
Finished Mar 21 03:20:21 PM PDT 24
Peak memory 289828 kb
Host smart-a36f7399-492e-4eff-87d6-04bc488dedfc
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047353281 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd_slow_flash.2047353281
Directory /workspace/16.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/16.flash_ctrl_invalid_op.1645050927
Short name T222
Test name
Test status
Simulation time 1970748800 ps
CPU time 77.81 seconds
Started Mar 21 03:16:46 PM PDT 24
Finished Mar 21 03:18:04 PM PDT 24
Peak memory 262912 kb
Host smart-b61ef8ab-1d41-41f3-862a-b9b6c95057be
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645050927 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.1
645050927
Directory /workspace/16.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/16.flash_ctrl_lcmgr_intg.510325391
Short name T716
Test name
Test status
Simulation time 45594800 ps
CPU time 13.67 seconds
Started Mar 21 03:16:46 PM PDT 24
Finished Mar 21 03:17:00 PM PDT 24
Peak memory 265248 kb
Host smart-8bdddc87-4794-4336-8cad-7c7a3dc1bfd8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510325391 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.flash_ctrl_lcmgr_intg.510325391
Directory /workspace/16.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/16.flash_ctrl_otp_reset.1129842396
Short name T568
Test name
Test status
Simulation time 38302700 ps
CPU time 133.75 seconds
Started Mar 21 03:16:46 PM PDT 24
Finished Mar 21 03:19:00 PM PDT 24
Peak memory 264344 kb
Host smart-c48e2a0b-97ac-49f4-a791-d9ff7cb2a7c3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129842396 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_o
tp_reset.1129842396
Directory /workspace/16.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_phy_arb.3655494986
Short name T1028
Test name
Test status
Simulation time 90671900 ps
CPU time 155.66 seconds
Started Mar 21 03:16:47 PM PDT 24
Finished Mar 21 03:19:23 PM PDT 24
Peak memory 261720 kb
Host smart-14558f0a-1cf4-4ee3-ae24-086216e46e82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3655494986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.3655494986
Directory /workspace/16.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/16.flash_ctrl_prog_reset.3859704533
Short name T949
Test name
Test status
Simulation time 93010600 ps
CPU time 18.46 seconds
Started Mar 21 03:16:47 PM PDT 24
Finished Mar 21 03:17:05 PM PDT 24
Peak memory 260732 kb
Host smart-b8110576-6718-4690-9069-02a053edb46c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859704533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_prog_re
set.3859704533
Directory /workspace/16.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_rand_ops.2926152204
Short name T453
Test name
Test status
Simulation time 171093300 ps
CPU time 202.6 seconds
Started Mar 21 03:16:47 PM PDT 24
Finished Mar 21 03:20:10 PM PDT 24
Peak memory 272652 kb
Host smart-44dd9ddc-afba-4b6c-9986-a315c6334b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926152204 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.2926152204
Directory /workspace/16.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/16.flash_ctrl_re_evict.3359034946
Short name T352
Test name
Test status
Simulation time 88139700 ps
CPU time 36.5 seconds
Started Mar 21 03:16:48 PM PDT 24
Finished Mar 21 03:17:25 PM PDT 24
Peak memory 273628 kb
Host smart-56381f75-eb6f-458a-86fa-2068d06255dc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359034946 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl
ash_ctrl_re_evict.3359034946
Directory /workspace/16.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_ro.1933426171
Short name T757
Test name
Test status
Simulation time 1194647700 ps
CPU time 152.55 seconds
Started Mar 21 03:16:46 PM PDT 24
Finished Mar 21 03:19:18 PM PDT 24
Peak memory 281084 kb
Host smart-6df356f1-32e6-4449-93bb-c891255958d3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933426171 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.flash_ctrl_ro.1933426171
Directory /workspace/16.flash_ctrl_ro/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw.2064798525
Short name T188
Test name
Test status
Simulation time 10145581700 ps
CPU time 581.08 seconds
Started Mar 21 03:16:47 PM PDT 24
Finished Mar 21 03:26:28 PM PDT 24
Peak memory 314372 kb
Host smart-a780e7eb-492f-4bc1-9398-a09c5a749763
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064798525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_c
trl_rw.2064798525
Directory /workspace/16.flash_ctrl_rw/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict.3748830001
Short name T356
Test name
Test status
Simulation time 70194100 ps
CPU time 31.21 seconds
Started Mar 21 03:16:46 PM PDT 24
Finished Mar 21 03:17:17 PM PDT 24
Peak memory 273560 kb
Host smart-2811ab9c-a791-4eac-9987-0fc629dda4f2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748830001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl
ash_ctrl_rw_evict.3748830001
Directory /workspace/16.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict_all_en.2249286929
Short name T858
Test name
Test status
Simulation time 164140400 ps
CPU time 33.14 seconds
Started Mar 21 03:16:46 PM PDT 24
Finished Mar 21 03:17:19 PM PDT 24
Peak memory 273556 kb
Host smart-8c5a8736-f033-4f7c-9c38-5c889f74055c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249286929 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict_all_en.2249286929
Directory /workspace/16.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/16.flash_ctrl_sec_info_access.3899512780
Short name T752
Test name
Test status
Simulation time 7577893100 ps
CPU time 85.45 seconds
Started Mar 21 03:16:46 PM PDT 24
Finished Mar 21 03:18:12 PM PDT 24
Peak memory 262640 kb
Host smart-5c05b127-7b0b-4a26-a98e-a4d13de359c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899512780 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.3899512780
Directory /workspace/16.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/16.flash_ctrl_smoke.3048000968
Short name T896
Test name
Test status
Simulation time 114331800 ps
CPU time 123.98 seconds
Started Mar 21 03:16:46 PM PDT 24
Finished Mar 21 03:18:51 PM PDT 24
Peak memory 275868 kb
Host smart-4945ff16-33ec-4fa6-88ec-baea28cb62d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048000968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.3048000968
Directory /workspace/16.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/16.flash_ctrl_wo.979000834
Short name T814
Test name
Test status
Simulation time 1733995200 ps
CPU time 157.34 seconds
Started Mar 21 03:16:48 PM PDT 24
Finished Mar 21 03:19:25 PM PDT 24
Peak memory 265276 kb
Host smart-bf12a7b4-36e7-4e34-8542-dc449eb9efdb
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979000834 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.flash_ctrl_wo.979000834
Directory /workspace/16.flash_ctrl_wo/latest

Test location /workspace/coverage/default/17.flash_ctrl_alert_test.711004272
Short name T333
Test name
Test status
Simulation time 69808300 ps
CPU time 13.66 seconds
Started Mar 21 03:17:16 PM PDT 24
Finished Mar 21 03:17:30 PM PDT 24
Peak memory 258192 kb
Host smart-83957234-439c-4a9a-8cac-5ec19db48ac5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711004272 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test.711004272
Directory /workspace/17.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.flash_ctrl_connect.52744447
Short name T595
Test name
Test status
Simulation time 15217100 ps
CPU time 15.99 seconds
Started Mar 21 03:17:16 PM PDT 24
Finished Mar 21 03:17:32 PM PDT 24
Peak memory 275672 kb
Host smart-1464ac35-dc58-4657-adc6-f79ca82597ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52744447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.52744447
Directory /workspace/17.flash_ctrl_connect/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.824671942
Short name T296
Test name
Test status
Simulation time 10019708100 ps
CPU time 177.2 seconds
Started Mar 21 03:17:14 PM PDT 24
Finished Mar 21 03:20:12 PM PDT 24
Peak memory 292296 kb
Host smart-76147b48-1092-4646-9ab4-7164506dc7f6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824671942 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.824671942
Directory /workspace/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.490790285
Short name T940
Test name
Test status
Simulation time 16302600 ps
CPU time 13.63 seconds
Started Mar 21 03:17:14 PM PDT 24
Finished Mar 21 03:17:28 PM PDT 24
Peak memory 265236 kb
Host smart-974fd4e1-438b-4a65-bba5-ce0582e3deeb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490790285 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_read_seed_err.490790285
Directory /workspace/17.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_rma_reset.2997537566
Short name T942
Test name
Test status
Simulation time 80149148000 ps
CPU time 921.72 seconds
Started Mar 21 03:17:02 PM PDT 24
Finished Mar 21 03:32:24 PM PDT 24
Peak memory 263260 kb
Host smart-b64a06f1-562c-4d62-88c5-b1c0906619fc
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997537566 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.flash_ctrl_hw_rma_reset.2997537566
Directory /workspace/17.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_sec_otp.1900094519
Short name T106
Test name
Test status
Simulation time 4811605700 ps
CPU time 107.23 seconds
Started Mar 21 03:16:46 PM PDT 24
Finished Mar 21 03:18:33 PM PDT 24
Peak memory 262580 kb
Host smart-e0808d8f-4763-4688-8b26-d691e49bb473
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900094519 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_
hw_sec_otp.1900094519
Directory /workspace/17.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.2226376810
Short name T348
Test name
Test status
Simulation time 8189597400 ps
CPU time 217.83 seconds
Started Mar 21 03:17:02 PM PDT 24
Finished Mar 21 03:20:40 PM PDT 24
Peak memory 289820 kb
Host smart-1ad6715e-c5aa-44d9-940b-b31790b0a9aa
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226376810 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd_slow_flash.2226376810
Directory /workspace/17.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/17.flash_ctrl_invalid_op.3519860640
Short name T586
Test name
Test status
Simulation time 2028393900 ps
CPU time 87.23 seconds
Started Mar 21 03:17:01 PM PDT 24
Finished Mar 21 03:18:29 PM PDT 24
Peak memory 259908 kb
Host smart-775de706-0c44-4a51-8855-2d268dc58967
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519860640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.3
519860640
Directory /workspace/17.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/17.flash_ctrl_mp_regions.1668371353
Short name T80
Test name
Test status
Simulation time 14231906000 ps
CPU time 359.16 seconds
Started Mar 21 03:17:02 PM PDT 24
Finished Mar 21 03:23:01 PM PDT 24
Peak memory 274432 kb
Host smart-c3c9ed3c-cb1e-4f1a-b4fe-975aa2ae9d4d
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668371353 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 17.flash_ctrl_mp_regions.1668371353
Directory /workspace/17.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/17.flash_ctrl_otp_reset.699425174
Short name T847
Test name
Test status
Simulation time 38313000 ps
CPU time 133.04 seconds
Started Mar 21 03:17:01 PM PDT 24
Finished Mar 21 03:19:14 PM PDT 24
Peak memory 264164 kb
Host smart-a34befcd-f2f7-413d-af37-f237c030e62a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699425174 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_ot
p_reset.699425174
Directory /workspace/17.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_phy_arb.4139211162
Short name T767
Test name
Test status
Simulation time 1729126200 ps
CPU time 492.92 seconds
Started Mar 21 03:16:46 PM PDT 24
Finished Mar 21 03:24:59 PM PDT 24
Peak memory 262468 kb
Host smart-ee26db6f-4178-416f-b982-7525394a3a41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4139211162 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.4139211162
Directory /workspace/17.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/17.flash_ctrl_prog_reset.1493315091
Short name T973
Test name
Test status
Simulation time 902970800 ps
CPU time 30.99 seconds
Started Mar 21 03:17:01 PM PDT 24
Finished Mar 21 03:17:32 PM PDT 24
Peak memory 260736 kb
Host smart-1d8c8799-8c63-4aa7-a002-296895371c3d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493315091 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_prog_re
set.1493315091
Directory /workspace/17.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_rand_ops.1167262454
Short name T804
Test name
Test status
Simulation time 4519615900 ps
CPU time 885.76 seconds
Started Mar 21 03:16:49 PM PDT 24
Finished Mar 21 03:31:35 PM PDT 24
Peak memory 287264 kb
Host smart-0a53418c-9463-4ac9-b6f8-6d7fa6e710dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167262454 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.1167262454
Directory /workspace/17.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/17.flash_ctrl_re_evict.2198469857
Short name T454
Test name
Test status
Simulation time 263375600 ps
CPU time 36.71 seconds
Started Mar 21 03:17:04 PM PDT 24
Finished Mar 21 03:17:40 PM PDT 24
Peak memory 266264 kb
Host smart-92fec688-4637-4be8-8b73-009e96a1d70c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198469857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl
ash_ctrl_re_evict.2198469857
Directory /workspace/17.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_ro.3661866403
Short name T469
Test name
Test status
Simulation time 893641800 ps
CPU time 106.71 seconds
Started Mar 21 03:17:01 PM PDT 24
Finished Mar 21 03:18:48 PM PDT 24
Peak memory 281152 kb
Host smart-cda291ba-d645-4e93-ad8c-6dd41f8e7e14
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661866403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.flash_ctrl_ro.3661866403
Directory /workspace/17.flash_ctrl_ro/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw.512768243
Short name T805
Test name
Test status
Simulation time 13492888100 ps
CPU time 561.98 seconds
Started Mar 21 03:17:03 PM PDT 24
Finished Mar 21 03:26:25 PM PDT 24
Peak memory 309604 kb
Host smart-9e31a6d7-3932-4ccd-b02f-958816355769
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512768243 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ct
rl_rw.512768243
Directory /workspace/17.flash_ctrl_rw/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict.192783298
Short name T650
Test name
Test status
Simulation time 53456800 ps
CPU time 33.63 seconds
Started Mar 21 03:17:01 PM PDT 24
Finished Mar 21 03:17:35 PM PDT 24
Peak memory 273580 kb
Host smart-b32ba0fe-f685-4efa-99c5-180346b539f3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192783298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla
sh_ctrl_rw_evict.192783298
Directory /workspace/17.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict_all_en.387915050
Short name T801
Test name
Test status
Simulation time 53489100 ps
CPU time 32.07 seconds
Started Mar 21 03:17:02 PM PDT 24
Finished Mar 21 03:17:35 PM PDT 24
Peak memory 274644 kb
Host smart-5f0563db-bbf5-4875-abef-381e3b7926a3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387915050 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict_all_en.387915050
Directory /workspace/17.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/17.flash_ctrl_sec_info_access.2765918247
Short name T670
Test name
Test status
Simulation time 472094000 ps
CPU time 51.66 seconds
Started Mar 21 03:17:02 PM PDT 24
Finished Mar 21 03:17:54 PM PDT 24
Peak memory 263220 kb
Host smart-3fe1c6c4-dabc-4050-94dd-ed113faf7873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765918247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.2765918247
Directory /workspace/17.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/17.flash_ctrl_smoke.4028249410
Short name T544
Test name
Test status
Simulation time 93142600 ps
CPU time 169.2 seconds
Started Mar 21 03:16:49 PM PDT 24
Finished Mar 21 03:19:39 PM PDT 24
Peak memory 276948 kb
Host smart-544654ee-5ee5-4ce6-83f5-7a802c6876a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028249410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.4028249410
Directory /workspace/17.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/17.flash_ctrl_wo.2618371780
Short name T897
Test name
Test status
Simulation time 9731713500 ps
CPU time 183.62 seconds
Started Mar 21 03:17:02 PM PDT 24
Finished Mar 21 03:20:05 PM PDT 24
Peak memory 259244 kb
Host smart-8a74a570-d02b-4097-82f2-6aed275441c4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618371780 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.flash_ctrl_wo.2618371780
Directory /workspace/17.flash_ctrl_wo/latest

Test location /workspace/coverage/default/18.flash_ctrl_alert_test.1193434553
Short name T880
Test name
Test status
Simulation time 38006200 ps
CPU time 14.1 seconds
Started Mar 21 03:17:25 PM PDT 24
Finished Mar 21 03:17:40 PM PDT 24
Peak memory 258324 kb
Host smart-ea6d973a-0e81-4389-8b3b-bf81caaa43d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193434553 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test.
1193434553
Directory /workspace/18.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.flash_ctrl_connect.2125423396
Short name T517
Test name
Test status
Simulation time 23552800 ps
CPU time 15.99 seconds
Started Mar 21 03:17:28 PM PDT 24
Finished Mar 21 03:17:44 PM PDT 24
Peak memory 275108 kb
Host smart-89032e07-dac0-48bb-b9bb-5cbd0b2cf48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125423396 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.2125423396
Directory /workspace/18.flash_ctrl_connect/latest

Test location /workspace/coverage/default/18.flash_ctrl_disable.3049924999
Short name T689
Test name
Test status
Simulation time 12062100 ps
CPU time 22.07 seconds
Started Mar 21 03:17:14 PM PDT 24
Finished Mar 21 03:17:36 PM PDT 24
Peak memory 265332 kb
Host smart-0560be6e-dc3e-4a0a-b513-57ca3c00097e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049924999 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_disable.3049924999
Directory /workspace/18.flash_ctrl_disable/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.296096035
Short name T970
Test name
Test status
Simulation time 10012325500 ps
CPU time 107.02 seconds
Started Mar 21 03:17:25 PM PDT 24
Finished Mar 21 03:19:12 PM PDT 24
Peak memory 305156 kb
Host smart-075940f2-6938-444c-ae53-e78ab3f6b013
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296096035 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.296096035
Directory /workspace/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.316653496
Short name T922
Test name
Test status
Simulation time 15815100 ps
CPU time 13.63 seconds
Started Mar 21 03:17:27 PM PDT 24
Finished Mar 21 03:17:41 PM PDT 24
Peak memory 265264 kb
Host smart-76c4f71d-f0aa-4c2f-82a0-d6dd2d951911
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316653496 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_read_seed_err.316653496
Directory /workspace/18.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_sec_otp.2650353541
Short name T966
Test name
Test status
Simulation time 8330262300 ps
CPU time 150.46 seconds
Started Mar 21 03:17:15 PM PDT 24
Finished Mar 21 03:19:45 PM PDT 24
Peak memory 262628 kb
Host smart-e54b8d34-bb1a-4dc8-8867-26184c2738bf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650353541 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_
hw_sec_otp.2650353541
Directory /workspace/18.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd_slow_flash.1826125330
Short name T187
Test name
Test status
Simulation time 17445397700 ps
CPU time 245.44 seconds
Started Mar 21 03:17:17 PM PDT 24
Finished Mar 21 03:21:23 PM PDT 24
Peak memory 284648 kb
Host smart-5a9aaa22-014e-4f5c-8e2f-3b142080ae37
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826125330 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd_slow_flash.1826125330
Directory /workspace/18.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/18.flash_ctrl_invalid_op.842309410
Short name T878
Test name
Test status
Simulation time 1931053500 ps
CPU time 80.64 seconds
Started Mar 21 03:17:15 PM PDT 24
Finished Mar 21 03:18:36 PM PDT 24
Peak memory 262916 kb
Host smart-94c5e943-0a7a-40c3-9342-ff4e13e2f847
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842309410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.842309410
Directory /workspace/18.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/18.flash_ctrl_lcmgr_intg.2958154828
Short name T135
Test name
Test status
Simulation time 48302400 ps
CPU time 13.38 seconds
Started Mar 21 03:17:25 PM PDT 24
Finished Mar 21 03:17:38 PM PDT 24
Peak memory 259784 kb
Host smart-b93dc9e7-33a0-4068-b67d-63125c5597ac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958154828 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.flash_ctrl_lcmgr_intg.2958154828
Directory /workspace/18.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/18.flash_ctrl_mp_regions.1022415359
Short name T82
Test name
Test status
Simulation time 23412994700 ps
CPU time 307.15 seconds
Started Mar 21 03:17:14 PM PDT 24
Finished Mar 21 03:22:21 PM PDT 24
Peak memory 274416 kb
Host smart-0cea46fd-6b14-490b-a91f-60343617125f
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022415359 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 18.flash_ctrl_mp_regions.1022415359
Directory /workspace/18.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/18.flash_ctrl_otp_reset.4029601449
Short name T1017
Test name
Test status
Simulation time 41470100 ps
CPU time 135.26 seconds
Started Mar 21 03:17:14 PM PDT 24
Finished Mar 21 03:19:30 PM PDT 24
Peak memory 259732 kb
Host smart-475a2718-1095-42f5-880f-b176a03784f6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029601449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_o
tp_reset.4029601449
Directory /workspace/18.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_phy_arb.3268509869
Short name T865
Test name
Test status
Simulation time 94194600 ps
CPU time 187.19 seconds
Started Mar 21 03:17:27 PM PDT 24
Finished Mar 21 03:20:35 PM PDT 24
Peak memory 262516 kb
Host smart-02a0ac73-ebc3-4b05-a6c2-3a4246fff80d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3268509869 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.3268509869
Directory /workspace/18.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/18.flash_ctrl_prog_reset.3183582868
Short name T749
Test name
Test status
Simulation time 23618700 ps
CPU time 14.15 seconds
Started Mar 21 03:17:15 PM PDT 24
Finished Mar 21 03:17:29 PM PDT 24
Peak memory 260568 kb
Host smart-68ae0b32-6dbf-4217-a5ae-fdb5f07fca0e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183582868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_prog_re
set.3183582868
Directory /workspace/18.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_rand_ops.1804767281
Short name T78
Test name
Test status
Simulation time 3151743100 ps
CPU time 1060.29 seconds
Started Mar 21 03:17:17 PM PDT 24
Finished Mar 21 03:34:57 PM PDT 24
Peak memory 286648 kb
Host smart-690aa13a-39aa-43b2-b741-b28311b0864c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804767281 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.1804767281
Directory /workspace/18.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/18.flash_ctrl_re_evict.937452299
Short name T848
Test name
Test status
Simulation time 83170900 ps
CPU time 33.64 seconds
Started Mar 21 03:17:14 PM PDT 24
Finished Mar 21 03:17:47 PM PDT 24
Peak memory 273544 kb
Host smart-75961bdd-5707-49e1-9288-eb4fdc5e08f9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937452299 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla
sh_ctrl_re_evict.937452299
Directory /workspace/18.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_ro.1097201828
Short name T911
Test name
Test status
Simulation time 6855211300 ps
CPU time 97.26 seconds
Started Mar 21 03:17:15 PM PDT 24
Finished Mar 21 03:18:52 PM PDT 24
Peak memory 281136 kb
Host smart-d2dc909d-073a-4dc8-b2d8-cbd7dee044a2
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097201828 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.flash_ctrl_ro.1097201828
Directory /workspace/18.flash_ctrl_ro/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw.2356327964
Short name T618
Test name
Test status
Simulation time 13424202500 ps
CPU time 459.46 seconds
Started Mar 21 03:17:17 PM PDT 24
Finished Mar 21 03:24:56 PM PDT 24
Peak memory 314412 kb
Host smart-4ae15463-d5ed-445a-96cf-6d7a78dddcd8
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356327964 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_c
trl_rw.2356327964
Directory /workspace/18.flash_ctrl_rw/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict.3934866845
Short name T930
Test name
Test status
Simulation time 175979300 ps
CPU time 37.47 seconds
Started Mar 21 03:17:15 PM PDT 24
Finished Mar 21 03:17:53 PM PDT 24
Peak memory 266376 kb
Host smart-147f7bb6-4654-4fbb-b4b9-f1281c659522
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934866845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl
ash_ctrl_rw_evict.3934866845
Directory /workspace/18.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict_all_en.2290570523
Short name T1018
Test name
Test status
Simulation time 92743300 ps
CPU time 30.32 seconds
Started Mar 21 03:17:13 PM PDT 24
Finished Mar 21 03:17:44 PM PDT 24
Peak memory 273576 kb
Host smart-17c46782-080f-4a48-8945-f63c71c86cf0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290570523 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict_all_en.2290570523
Directory /workspace/18.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/18.flash_ctrl_sec_info_access.3287679116
Short name T399
Test name
Test status
Simulation time 2933227000 ps
CPU time 71.28 seconds
Started Mar 21 03:17:26 PM PDT 24
Finished Mar 21 03:18:37 PM PDT 24
Peak memory 263216 kb
Host smart-44da2911-b736-4d59-acb0-ddea1b2b7757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287679116 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.3287679116
Directory /workspace/18.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/18.flash_ctrl_smoke.1455338254
Short name T464
Test name
Test status
Simulation time 39015300 ps
CPU time 173.44 seconds
Started Mar 21 03:17:14 PM PDT 24
Finished Mar 21 03:20:07 PM PDT 24
Peak memory 277712 kb
Host smart-af42dd7c-4966-4095-9337-02a5ae7b4774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455338254 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.1455338254
Directory /workspace/18.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/18.flash_ctrl_wo.2108518185
Short name T93
Test name
Test status
Simulation time 2601043300 ps
CPU time 209.47 seconds
Started Mar 21 03:17:15 PM PDT 24
Finished Mar 21 03:20:44 PM PDT 24
Peak memory 259052 kb
Host smart-7bd86343-c00e-4de7-a41c-2fe845dcd950
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108518185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.flash_ctrl_wo.2108518185
Directory /workspace/18.flash_ctrl_wo/latest

Test location /workspace/coverage/default/19.flash_ctrl_alert_test.2218912322
Short name T808
Test name
Test status
Simulation time 53836300 ps
CPU time 13.75 seconds
Started Mar 21 03:17:37 PM PDT 24
Finished Mar 21 03:17:51 PM PDT 24
Peak memory 258376 kb
Host smart-e75b0532-4b71-4059-ac33-18a7b813a2b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218912322 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test.
2218912322
Directory /workspace/19.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.flash_ctrl_connect.3762729154
Short name T928
Test name
Test status
Simulation time 21247100 ps
CPU time 13.39 seconds
Started Mar 21 03:17:40 PM PDT 24
Finished Mar 21 03:17:55 PM PDT 24
Peak memory 275672 kb
Host smart-81a9f6f8-debf-4e62-9cea-347d35f97260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762729154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.3762729154
Directory /workspace/19.flash_ctrl_connect/latest

Test location /workspace/coverage/default/19.flash_ctrl_disable.562938402
Short name T74
Test name
Test status
Simulation time 20489900 ps
CPU time 22.39 seconds
Started Mar 21 03:17:36 PM PDT 24
Finished Mar 21 03:17:59 PM PDT 24
Peak memory 273596 kb
Host smart-97d8da39-ea2f-41fb-85ae-4d5351f142e1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562938402 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.flash_ctrl_disable.562938402
Directory /workspace/19.flash_ctrl_disable/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.1494236112
Short name T1030
Test name
Test status
Simulation time 10034780700 ps
CPU time 51.53 seconds
Started Mar 21 03:17:37 PM PDT 24
Finished Mar 21 03:18:29 PM PDT 24
Peak memory 265972 kb
Host smart-77ab91cf-cb5d-4386-9602-1af0e11dda76
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494236112 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.1494236112
Directory /workspace/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_read_seed_err.1707762188
Short name T363
Test name
Test status
Simulation time 16186100 ps
CPU time 13.57 seconds
Started Mar 21 03:17:41 PM PDT 24
Finished Mar 21 03:17:55 PM PDT 24
Peak memory 259328 kb
Host smart-09e8b141-d0a0-4e4c-b7f2-b2110be9f1c3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707762188 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.1707762188
Directory /workspace/19.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_rma_reset.2097171882
Short name T483
Test name
Test status
Simulation time 40121315700 ps
CPU time 818.25 seconds
Started Mar 21 03:17:27 PM PDT 24
Finished Mar 21 03:31:06 PM PDT 24
Peak memory 263604 kb
Host smart-6df64ee2-4a10-47e6-9d3a-0c410cadf2e0
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097171882 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.flash_ctrl_hw_rma_reset.2097171882
Directory /workspace/19.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_sec_otp.2642656664
Short name T726
Test name
Test status
Simulation time 9724923200 ps
CPU time 206.37 seconds
Started Mar 21 03:17:27 PM PDT 24
Finished Mar 21 03:20:54 PM PDT 24
Peak memory 262584 kb
Host smart-0a84ac6b-8a44-425c-8ea0-ced75f345280
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642656664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_
hw_sec_otp.2642656664
Directory /workspace/19.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd_slow_flash.3200278301
Short name T884
Test name
Test status
Simulation time 16881247900 ps
CPU time 201.24 seconds
Started Mar 21 03:17:25 PM PDT 24
Finished Mar 21 03:20:46 PM PDT 24
Peak memory 289788 kb
Host smart-10fe297c-5ca4-4372-bfcd-4ec41d290f60
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200278301 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd_slow_flash.3200278301
Directory /workspace/19.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/19.flash_ctrl_invalid_op.2289004080
Short name T466
Test name
Test status
Simulation time 987437900 ps
CPU time 90.77 seconds
Started Mar 21 03:17:26 PM PDT 24
Finished Mar 21 03:18:57 PM PDT 24
Peak memory 262664 kb
Host smart-46d5a7a8-57c5-49d7-90a6-66ff06e1caa8
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289004080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.2
289004080
Directory /workspace/19.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/19.flash_ctrl_lcmgr_intg.3946754363
Short name T855
Test name
Test status
Simulation time 18983300 ps
CPU time 13.78 seconds
Started Mar 21 03:17:37 PM PDT 24
Finished Mar 21 03:17:51 PM PDT 24
Peak memory 265244 kb
Host smart-2cdfbb62-a96f-4e1b-8e33-0bf5efb3cf91
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946754363 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.flash_ctrl_lcmgr_intg.3946754363
Directory /workspace/19.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/19.flash_ctrl_otp_reset.2459263808
Short name T886
Test name
Test status
Simulation time 135131300 ps
CPU time 136.03 seconds
Started Mar 21 03:17:27 PM PDT 24
Finished Mar 21 03:19:43 PM PDT 24
Peak memory 264668 kb
Host smart-ca6763fe-f1fa-4c2a-98d6-1e094b79dc7a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459263808 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_o
tp_reset.2459263808
Directory /workspace/19.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_phy_arb.1929779587
Short name T1021
Test name
Test status
Simulation time 1513436500 ps
CPU time 483.6 seconds
Started Mar 21 03:17:26 PM PDT 24
Finished Mar 21 03:25:30 PM PDT 24
Peak memory 265180 kb
Host smart-542f6e2a-6f20-4146-ba05-78ea041d2eb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1929779587 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.1929779587
Directory /workspace/19.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/19.flash_ctrl_prog_reset.4047940486
Short name T495
Test name
Test status
Simulation time 18230800 ps
CPU time 13.52 seconds
Started Mar 21 03:17:26 PM PDT 24
Finished Mar 21 03:17:39 PM PDT 24
Peak memory 265168 kb
Host smart-dbf7a51a-0cf9-4de8-b7f5-a081ec2497e9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047940486 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_prog_re
set.4047940486
Directory /workspace/19.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_rand_ops.1725245889
Short name T440
Test name
Test status
Simulation time 658153700 ps
CPU time 527.99 seconds
Started Mar 21 03:17:27 PM PDT 24
Finished Mar 21 03:26:15 PM PDT 24
Peak memory 284236 kb
Host smart-9d43931b-79d1-4ba7-8fa1-71d7543bfc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725245889 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.1725245889
Directory /workspace/19.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/19.flash_ctrl_ro.2566905266
Short name T545
Test name
Test status
Simulation time 1004157500 ps
CPU time 95.27 seconds
Started Mar 21 03:17:25 PM PDT 24
Finished Mar 21 03:19:00 PM PDT 24
Peak memory 281200 kb
Host smart-250a5c6d-e494-47a7-83ac-1974a71d5ca4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566905266 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.flash_ctrl_ro.2566905266
Directory /workspace/19.flash_ctrl_ro/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw.2313905222
Short name T908
Test name
Test status
Simulation time 6638543100 ps
CPU time 550.88 seconds
Started Mar 21 03:17:28 PM PDT 24
Finished Mar 21 03:26:39 PM PDT 24
Peak memory 318776 kb
Host smart-46c85c5e-994b-425e-9019-308a0bb1791b
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313905222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_c
trl_rw.2313905222
Directory /workspace/19.flash_ctrl_rw/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict.803257312
Short name T507
Test name
Test status
Simulation time 98613000 ps
CPU time 33.56 seconds
Started Mar 21 03:17:38 PM PDT 24
Finished Mar 21 03:18:12 PM PDT 24
Peak memory 273572 kb
Host smart-d5617708-8734-4cd0-b8d2-bd49a772876a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803257312 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla
sh_ctrl_rw_evict.803257312
Directory /workspace/19.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict_all_en.1925230444
Short name T929
Test name
Test status
Simulation time 28529600 ps
CPU time 31.21 seconds
Started Mar 21 03:17:37 PM PDT 24
Finished Mar 21 03:18:09 PM PDT 24
Peak memory 273556 kb
Host smart-8968052b-d306-4610-b885-09d3bfb30d2e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925230444 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict_all_en.1925230444
Directory /workspace/19.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/19.flash_ctrl_smoke.1991301697
Short name T841
Test name
Test status
Simulation time 25101400 ps
CPU time 76.62 seconds
Started Mar 21 03:17:28 PM PDT 24
Finished Mar 21 03:18:44 PM PDT 24
Peak memory 274888 kb
Host smart-fc36137f-a312-4a40-8f6b-32b4199a9935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991301697 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.1991301697
Directory /workspace/19.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/19.flash_ctrl_wo.713386049
Short name T503
Test name
Test status
Simulation time 7599598500 ps
CPU time 182.24 seconds
Started Mar 21 03:17:27 PM PDT 24
Finished Mar 21 03:20:29 PM PDT 24
Peak memory 265220 kb
Host smart-66bb6873-9fcd-4a07-8077-a2bd8f15da26
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713386049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.flash_ctrl_wo.713386049
Directory /workspace/19.flash_ctrl_wo/latest

Test location /workspace/coverage/default/2.flash_ctrl_access_after_disable.1675715177
Short name T44
Test name
Test status
Simulation time 13695000 ps
CPU time 13.97 seconds
Started Mar 21 03:12:31 PM PDT 24
Finished Mar 21 03:12:45 PM PDT 24
Peak memory 265348 kb
Host smart-1ce336ea-73b7-4648-88c2-d6afba1d87fb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675715177 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.1675715177
Directory /workspace/2.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_alert_test.654592674
Short name T15
Test name
Test status
Simulation time 157522100 ps
CPU time 14 seconds
Started Mar 21 03:12:30 PM PDT 24
Finished Mar 21 03:12:44 PM PDT 24
Peak memory 265212 kb
Host smart-7b235215-9dd4-4066-8723-b9c1ddb5aa76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654592674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.654592674
Directory /workspace/2.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.flash_ctrl_config_regwen.1460696732
Short name T214
Test name
Test status
Simulation time 163297800 ps
CPU time 14.14 seconds
Started Mar 21 03:12:32 PM PDT 24
Finished Mar 21 03:12:46 PM PDT 24
Peak memory 261884 kb
Host smart-97e0548a-b2e3-411d-a567-533f04c3d3ff
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460696732 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.flash_ctrl_config_regwen.1460696732
Directory /workspace/2.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/2.flash_ctrl_connect.3281356315
Short name T505
Test name
Test status
Simulation time 37389200 ps
CPU time 15.52 seconds
Started Mar 21 03:12:30 PM PDT 24
Finished Mar 21 03:12:46 PM PDT 24
Peak memory 275700 kb
Host smart-b8251c8e-15e5-4055-bfde-d06b4c4300b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281356315 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.3281356315
Directory /workspace/2.flash_ctrl_connect/latest

Test location /workspace/coverage/default/2.flash_ctrl_disable.1130593317
Short name T849
Test name
Test status
Simulation time 17986500 ps
CPU time 21.28 seconds
Started Mar 21 03:12:30 PM PDT 24
Finished Mar 21 03:12:51 PM PDT 24
Peak memory 280668 kb
Host smart-1210eca8-6aae-419e-a9fc-fb95613f5465
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130593317 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_disable.1130593317
Directory /workspace/2.flash_ctrl_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_erase_suspend.2731631727
Short name T127
Test name
Test status
Simulation time 1481031400 ps
CPU time 298.08 seconds
Started Mar 21 03:12:20 PM PDT 24
Finished Mar 21 03:17:18 PM PDT 24
Peak memory 263076 kb
Host smart-9e5948fb-d110-4576-b4a3-4d0ce520cdbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2731631727 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.2731631727
Directory /workspace/2.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_mp.3514135534
Short name T792
Test name
Test status
Simulation time 19671792800 ps
CPU time 2302.24 seconds
Started Mar 21 03:12:22 PM PDT 24
Finished Mar 21 03:50:45 PM PDT 24
Peak memory 264820 kb
Host smart-56ca372d-9707-4994-8415-dc6cd8d8138c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514135534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_err
or_mp.3514135534
Directory /workspace/2.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_type.922559934
Short name T159
Test name
Test status
Simulation time 5875540200 ps
CPU time 2018.19 seconds
Started Mar 21 03:12:16 PM PDT 24
Finished Mar 21 03:45:55 PM PDT 24
Peak memory 265216 kb
Host smart-cb6facc5-7e79-436d-a5ab-e1c560061cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922559934 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_type.922559934
Directory /workspace/2.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_win.637830033
Short name T924
Test name
Test status
Simulation time 1493400800 ps
CPU time 769.94 seconds
Started Mar 21 03:12:23 PM PDT 24
Finished Mar 21 03:25:13 PM PDT 24
Peak memory 273420 kb
Host smart-40d3c7d9-8b48-47b6-bfc1-eb869a840a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637830033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.637830033
Directory /workspace/2.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/2.flash_ctrl_fetch_code.70880238
Short name T1015
Test name
Test status
Simulation time 1472165200 ps
CPU time 24.61 seconds
Started Mar 21 03:12:24 PM PDT 24
Finished Mar 21 03:12:49 PM PDT 24
Peak memory 265204 kb
Host smart-c27fd68b-edc0-4f40-937a-d148795004b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70880238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetch_code.70880238
Directory /workspace/2.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/2.flash_ctrl_full_mem_access.1557702381
Short name T664
Test name
Test status
Simulation time 96874808500 ps
CPU time 2485.22 seconds
Started Mar 21 03:12:23 PM PDT 24
Finished Mar 21 03:53:49 PM PDT 24
Peak memory 265140 kb
Host smart-6e1e7607-1486-4347-b091-ceb1bc3a6d9d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557702381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_c
trl_full_mem_access.1557702381
Directory /workspace/2.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_ctrl_arb.2064515591
Short name T174
Test name
Test status
Simulation time 523278195700 ps
CPU time 2021.97 seconds
Started Mar 21 03:12:21 PM PDT 24
Finished Mar 21 03:46:04 PM PDT 24
Peak memory 265204 kb
Host smart-764bb45d-21f1-4d11-b2e5-c341fd369e1e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064515591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.flash_ctrl_host_ctrl_arb.2064515591
Directory /workspace/2.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_dir_rd.3732143274
Short name T431
Test name
Test status
Simulation time 30146200 ps
CPU time 48.33 seconds
Started Mar 21 03:12:20 PM PDT 24
Finished Mar 21 03:13:08 PM PDT 24
Peak memory 262560 kb
Host smart-4e46e3a0-2a08-495d-931b-822685b0ed7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3732143274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.3732143274
Directory /workspace/2.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.3240837976
Short name T145
Test name
Test status
Simulation time 10012936200 ps
CPU time 106.53 seconds
Started Mar 21 03:12:36 PM PDT 24
Finished Mar 21 03:14:23 PM PDT 24
Peak memory 286068 kb
Host smart-c84bc5ca-cbc6-4f48-9b67-6a7f84e6b8af
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240837976 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.3240837976
Directory /workspace/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_read_seed_err.2786633107
Short name T883
Test name
Test status
Simulation time 15464000 ps
CPU time 13.48 seconds
Started Mar 21 03:12:34 PM PDT 24
Finished Mar 21 03:12:48 PM PDT 24
Peak memory 258400 kb
Host smart-932f7575-6a18-4679-b085-3ca0bce5659c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786633107 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_read_seed_err.2786633107
Directory /workspace/2.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_sec_otp.2796410918
Short name T823
Test name
Test status
Simulation time 2395184100 ps
CPU time 50.35 seconds
Started Mar 21 03:12:22 PM PDT 24
Finished Mar 21 03:13:13 PM PDT 24
Peak memory 262504 kb
Host smart-5b5b8c5c-9430-40df-86de-4e2aea549870
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796410918 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_h
w_sec_otp.2796410918
Directory /workspace/2.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd_slow_flash.488577411
Short name T728
Test name
Test status
Simulation time 17027945400 ps
CPU time 176.3 seconds
Started Mar 21 03:12:32 PM PDT 24
Finished Mar 21 03:15:28 PM PDT 24
Peak memory 289816 kb
Host smart-e308504c-7e29-4c60-9c99-0f3a0e468509
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488577411 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd_slow_flash.488577411
Directory /workspace/2.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr.2285848729
Short name T23
Test name
Test status
Simulation time 21973327800 ps
CPU time 118.11 seconds
Started Mar 21 03:12:36 PM PDT 24
Finished Mar 21 03:14:35 PM PDT 24
Peak memory 261004 kb
Host smart-c9a3821b-e550-4851-b47c-bf4daa8dd8a3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285848729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.flash_ctrl_intr_wr.2285848729
Directory /workspace/2.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr_slow_flash.1505215732
Short name T521
Test name
Test status
Simulation time 186882066900 ps
CPU time 396.98 seconds
Started Mar 21 03:12:28 PM PDT 24
Finished Mar 21 03:19:06 PM PDT 24
Peak memory 261012 kb
Host smart-90ade762-2a90-4ca0-8f43-692ce1884369
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150
5215732 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.1505215732
Directory /workspace/2.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_invalid_op.3093321985
Short name T778
Test name
Test status
Simulation time 1691659900 ps
CPU time 74.47 seconds
Started Mar 21 03:12:18 PM PDT 24
Finished Mar 21 03:13:32 PM PDT 24
Peak memory 259960 kb
Host smart-1477a890-db7b-4480-8b30-178df7807b5b
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093321985 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.3093321985
Directory /workspace/2.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_lcmgr_intg.1557986950
Short name T708
Test name
Test status
Simulation time 22220000 ps
CPU time 13.47 seconds
Started Mar 21 03:12:29 PM PDT 24
Finished Mar 21 03:12:43 PM PDT 24
Peak memory 265224 kb
Host smart-3494f95e-a86d-4b4c-8824-cc75a6f44a8a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557986950 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.flash_ctrl_lcmgr_intg.1557986950
Directory /workspace/2.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_mp_regions.2444322727
Short name T709
Test name
Test status
Simulation time 7494234500 ps
CPU time 454.77 seconds
Started Mar 21 03:12:24 PM PDT 24
Finished Mar 21 03:19:58 PM PDT 24
Peak memory 274220 kb
Host smart-6d324b94-6d30-47cf-9f21-6a16df62ae1b
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444322727 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_mp_regions.2444322727
Directory /workspace/2.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/2.flash_ctrl_otp_reset.3660575276
Short name T417
Test name
Test status
Simulation time 158578600 ps
CPU time 133.52 seconds
Started Mar 21 03:12:22 PM PDT 24
Finished Mar 21 03:14:35 PM PDT 24
Peak memory 261192 kb
Host smart-1fe7d33a-8c5b-4693-8989-fee9e83a9a13
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660575276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ot
p_reset.3660575276
Directory /workspace/2.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_ack_consistency.3583589460
Short name T227
Test name
Test status
Simulation time 15888500 ps
CPU time 14.1 seconds
Started Mar 21 03:12:29 PM PDT 24
Finished Mar 21 03:12:44 PM PDT 24
Peak memory 265476 kb
Host smart-b0ebbe00-7197-436e-88b1-7d2ac24e6f4d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3583589460 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.3583589460
Directory /workspace/2.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb.2181193417
Short name T840
Test name
Test status
Simulation time 115515500 ps
CPU time 69.7 seconds
Started Mar 21 03:12:22 PM PDT 24
Finished Mar 21 03:13:32 PM PDT 24
Peak memory 265168 kb
Host smart-c6bcb548-2a03-4aa7-8b41-e36887cfdec6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2181193417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.2181193417
Directory /workspace/2.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_prog_reset.3829634094
Short name T317
Test name
Test status
Simulation time 3380266000 ps
CPU time 64.37 seconds
Started Mar 21 03:12:27 PM PDT 24
Finished Mar 21 03:13:32 PM PDT 24
Peak memory 261308 kb
Host smart-3853883b-7046-4cac-bcae-a05ffbc2d996
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829634094 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_prog_res
et.3829634094
Directory /workspace/2.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_rand_ops.2763502948
Short name T996
Test name
Test status
Simulation time 846870600 ps
CPU time 938.5 seconds
Started Mar 21 03:12:26 PM PDT 24
Finished Mar 21 03:28:05 PM PDT 24
Peak memory 284904 kb
Host smart-005d59d6-5c4e-4eac-8f2b-054a7b42e601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763502948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.2763502948
Directory /workspace/2.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_buff_evict.1596866769
Short name T1031
Test name
Test status
Simulation time 5741785300 ps
CPU time 141.86 seconds
Started Mar 21 03:12:14 PM PDT 24
Finished Mar 21 03:14:36 PM PDT 24
Peak memory 265220 kb
Host smart-dcc0bdb9-d165-4a96-9061-b70c93aa59b2
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1596866769 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.1596866769
Directory /workspace/2.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_intg.917332840
Short name T907
Test name
Test status
Simulation time 77254700 ps
CPU time 31.94 seconds
Started Mar 21 03:12:30 PM PDT 24
Finished Mar 21 03:13:02 PM PDT 24
Peak memory 274540 kb
Host smart-17ba24ed-0fc1-41cf-bbe8-7efe19d28ef4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917332840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t
est +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.flash_ctrl_rd_intg.917332840
Directory /workspace/2.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_re_evict.3804473710
Short name T179
Test name
Test status
Simulation time 173571400 ps
CPU time 34.21 seconds
Started Mar 21 03:12:29 PM PDT 24
Finished Mar 21 03:13:04 PM PDT 24
Peak memory 273584 kb
Host smart-71ff1c03-1251-4df5-ab4c-83fae2f328fa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804473710 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_re_evict.3804473710
Directory /workspace/2.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_derr.3332048756
Short name T220
Test name
Test status
Simulation time 33682000 ps
CPU time 22.64 seconds
Started Mar 21 03:12:18 PM PDT 24
Finished Mar 21 03:12:41 PM PDT 24
Peak memory 265160 kb
Host smart-42ce1d8e-194d-47ba-98d3-8252296df51e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332048756 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_derr.3332048756
Directory /workspace/2.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_serr.2820713927
Short name T887
Test name
Test status
Simulation time 88477600 ps
CPU time 22.46 seconds
Started Mar 21 03:12:26 PM PDT 24
Finished Mar 21 03:12:49 PM PDT 24
Peak memory 265076 kb
Host smart-3c067e77-ccf3-4d40-b984-fe6a313b5fc3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820713927 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fl
ash_ctrl_read_word_sweep_serr.2820713927
Directory /workspace/2.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rma_err.423362222
Short name T142
Test name
Test status
Simulation time 79930636800 ps
CPU time 956.8 seconds
Started Mar 21 03:12:29 PM PDT 24
Finished Mar 21 03:28:26 PM PDT 24
Peak memory 259384 kb
Host smart-4702b6a8-cdc3-40f6-94c2-ea2959eb75a6
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423362222 -assert nopostproc +UVM_TEST
NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rma_err.423362222
Directory /workspace/2.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro.1810167526
Short name T813
Test name
Test status
Simulation time 2002092800 ps
CPU time 94.24 seconds
Started Mar 21 03:12:26 PM PDT 24
Finished Mar 21 03:14:00 PM PDT 24
Peak memory 281080 kb
Host smart-04d57fe7-f8c7-4c2a-9dbc-c14a999866c2
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810167526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.flash_ctrl_ro.1810167526
Directory /workspace/2.flash_ctrl_ro/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw.1568256610
Short name T190
Test name
Test status
Simulation time 7562028700 ps
CPU time 596.79 seconds
Started Mar 21 03:12:25 PM PDT 24
Finished Mar 21 03:22:21 PM PDT 24
Peak memory 313964 kb
Host smart-b4c6b2bd-e6bf-4746-8c34-cf74e4120139
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568256610 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ct
rl_rw.1568256610
Directory /workspace/2.flash_ctrl_rw/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict.3529291783
Short name T734
Test name
Test status
Simulation time 71236300 ps
CPU time 31.75 seconds
Started Mar 21 03:12:31 PM PDT 24
Finished Mar 21 03:13:03 PM PDT 24
Peak memory 266368 kb
Host smart-325e4d55-61c5-440b-8553-276499591a70
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529291783 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_rw_evict.3529291783
Directory /workspace/2.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict_all_en.1553178569
Short name T447
Test name
Test status
Simulation time 135604100 ps
CPU time 33.36 seconds
Started Mar 21 03:12:31 PM PDT 24
Finished Mar 21 03:13:04 PM PDT 24
Peak memory 274576 kb
Host smart-5432488f-0700-41af-9f1d-f1efe255438f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553178569 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict_all_en.1553178569
Directory /workspace/2.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_cm.238676458
Short name T13
Test name
Test status
Simulation time 1487793500 ps
CPU time 5015.08 seconds
Started Mar 21 03:12:32 PM PDT 24
Finished Mar 21 04:36:08 PM PDT 24
Peak memory 284112 kb
Host smart-4be5b315-6dd2-451a-9421-41bbe4493e76
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238676458 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.238676458
Directory /workspace/2.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_info_access.211021074
Short name T563
Test name
Test status
Simulation time 5217802700 ps
CPU time 63.46 seconds
Started Mar 21 03:12:28 PM PDT 24
Finished Mar 21 03:13:32 PM PDT 24
Peak memory 263752 kb
Host smart-66bb1277-31ed-458e-a24f-dd00f673eb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211021074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.211021074
Directory /workspace/2.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_address.1726070193
Short name T488
Test name
Test status
Simulation time 3427522400 ps
CPU time 88.05 seconds
Started Mar 21 03:12:16 PM PDT 24
Finished Mar 21 03:13:44 PM PDT 24
Peak memory 265292 kb
Host smart-aa59a9c7-5bc6-4145-9654-d83e126dde8a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726070193 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_serr_address.1726070193
Directory /workspace/2.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_counter.2910194058
Short name T902
Test name
Test status
Simulation time 1161063900 ps
CPU time 66.87 seconds
Started Mar 21 03:12:24 PM PDT 24
Finished Mar 21 03:13:31 PM PDT 24
Peak memory 274708 kb
Host smart-06361423-018d-42bf-8bda-36ae2ba0676a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910194058 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_serr_counter.2910194058
Directory /workspace/2.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke.364087065
Short name T480
Test name
Test status
Simulation time 29715600 ps
CPU time 127.16 seconds
Started Mar 21 03:12:26 PM PDT 24
Finished Mar 21 03:14:33 PM PDT 24
Peak memory 275632 kb
Host smart-9c49b89e-481b-49a9-9628-8d75c85bd10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364087065 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.364087065
Directory /workspace/2.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke_hw.3300785087
Short name T413
Test name
Test status
Simulation time 48943500 ps
CPU time 23.56 seconds
Started Mar 21 03:12:25 PM PDT 24
Finished Mar 21 03:12:49 PM PDT 24
Peak memory 259016 kb
Host smart-e0c15a00-236a-4de4-a04c-d42a9e175ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300785087 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.3300785087
Directory /workspace/2.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/2.flash_ctrl_stress_all.3291771194
Short name T645
Test name
Test status
Simulation time 1184016300 ps
CPU time 1740.39 seconds
Started Mar 21 03:12:30 PM PDT 24
Finished Mar 21 03:41:31 PM PDT 24
Peak memory 289700 kb
Host smart-719ae3d4-2a6a-4d4a-8952-6ab5745e293f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291771194 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stres
s_all.3291771194
Directory /workspace/2.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.flash_ctrl_sw_op.4088318403
Short name T427
Test name
Test status
Simulation time 77946500 ps
CPU time 24.17 seconds
Started Mar 21 03:12:24 PM PDT 24
Finished Mar 21 03:12:48 PM PDT 24
Peak memory 261764 kb
Host smart-476acdd4-f601-4204-9364-b9a6da2b761a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088318403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.4088318403
Directory /workspace/2.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_wo.2098668066
Short name T910
Test name
Test status
Simulation time 6950304800 ps
CPU time 129.99 seconds
Started Mar 21 03:12:23 PM PDT 24
Finished Mar 21 03:14:33 PM PDT 24
Peak memory 259588 kb
Host smart-3a9354ad-eae3-46b9-92f5-33f53cee6c5c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098668066 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.flash_ctrl_wo.2098668066
Directory /workspace/2.flash_ctrl_wo/latest

Test location /workspace/coverage/default/2.flash_ctrl_wr_intg.4002668524
Short name T230
Test name
Test status
Simulation time 170540600 ps
CPU time 14.69 seconds
Started Mar 21 03:12:36 PM PDT 24
Finished Mar 21 03:12:51 PM PDT 24
Peak memory 260076 kb
Host smart-f13eaf3c-1b68-473a-ba42-54b748735d6b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002668524 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wr_intg.4002668524
Directory /workspace/2.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/20.flash_ctrl_alert_test.1233177097
Short name T459
Test name
Test status
Simulation time 68232000 ps
CPU time 13.69 seconds
Started Mar 21 03:17:48 PM PDT 24
Finished Mar 21 03:18:02 PM PDT 24
Peak memory 258444 kb
Host smart-6d367050-1e76-496e-bff2-763a30484799
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233177097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.
1233177097
Directory /workspace/20.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.flash_ctrl_connect.4183637636
Short name T644
Test name
Test status
Simulation time 17003400 ps
CPU time 15.99 seconds
Started Mar 21 03:17:47 PM PDT 24
Finished Mar 21 03:18:03 PM PDT 24
Peak memory 275164 kb
Host smart-04992584-78c6-4f52-8959-d2c6f125fbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183637636 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.4183637636
Directory /workspace/20.flash_ctrl_connect/latest

Test location /workspace/coverage/default/20.flash_ctrl_disable.4289139495
Short name T371
Test name
Test status
Simulation time 16645300 ps
CPU time 20.54 seconds
Started Mar 21 03:17:47 PM PDT 24
Finished Mar 21 03:18:07 PM PDT 24
Peak memory 265288 kb
Host smart-30d29940-0062-4e68-9ba9-9b62d88b9c22
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289139495 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_disable.4289139495
Directory /workspace/20.flash_ctrl_disable/latest

Test location /workspace/coverage/default/20.flash_ctrl_hw_sec_otp.76936098
Short name T430
Test name
Test status
Simulation time 10844637100 ps
CPU time 85.18 seconds
Started Mar 21 03:17:36 PM PDT 24
Finished Mar 21 03:19:02 PM PDT 24
Peak memory 262548 kb
Host smart-c1692e78-159e-4087-833f-c53685ba3a5c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76936098 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_hw
_sec_otp.76936098
Directory /workspace/20.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd_slow_flash.1398746464
Short name T753
Test name
Test status
Simulation time 28894998500 ps
CPU time 227.38 seconds
Started Mar 21 03:17:41 PM PDT 24
Finished Mar 21 03:21:29 PM PDT 24
Peak memory 284792 kb
Host smart-eb1e1a97-5143-4537-912f-4147310e6e9c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398746464 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd_slow_flash.1398746464
Directory /workspace/20.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/20.flash_ctrl_otp_reset.1425869469
Short name T713
Test name
Test status
Simulation time 38284500 ps
CPU time 112.87 seconds
Started Mar 21 03:17:41 PM PDT 24
Finished Mar 21 03:19:35 PM PDT 24
Peak memory 260024 kb
Host smart-e29f7b44-326c-42c4-88ee-099b4556e586
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425869469 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_o
tp_reset.1425869469
Directory /workspace/20.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_prog_reset.4055980672
Short name T900
Test name
Test status
Simulation time 37726400 ps
CPU time 13.92 seconds
Started Mar 21 03:17:49 PM PDT 24
Finished Mar 21 03:18:03 PM PDT 24
Peak memory 265216 kb
Host smart-5115330c-8675-49a0-958a-9c829c7db837
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055980672 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_prog_re
set.4055980672
Directory /workspace/20.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict.4252590498
Short name T784
Test name
Test status
Simulation time 67457500 ps
CPU time 32 seconds
Started Mar 21 03:17:47 PM PDT 24
Finished Mar 21 03:18:20 PM PDT 24
Peak memory 274620 kb
Host smart-6e763ef0-43bf-401c-a740-b89fd785fc3f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252590498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fl
ash_ctrl_rw_evict.4252590498
Directory /workspace/20.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict_all_en.4218084945
Short name T207
Test name
Test status
Simulation time 31549300 ps
CPU time 31.99 seconds
Started Mar 21 03:17:49 PM PDT 24
Finished Mar 21 03:18:21 PM PDT 24
Peak memory 274620 kb
Host smart-a36ad4c6-f8ac-41cc-9e46-f6eadd44042a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218084945 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict_all_en.4218084945
Directory /workspace/20.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/20.flash_ctrl_sec_info_access.49739670
Short name T37
Test name
Test status
Simulation time 3804756400 ps
CPU time 74.06 seconds
Started Mar 21 03:17:49 PM PDT 24
Finished Mar 21 03:19:03 PM PDT 24
Peak memory 265072 kb
Host smart-8dca70e5-ec0f-4ab7-b7ce-26706c69b3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49739670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.49739670
Directory /workspace/20.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/20.flash_ctrl_smoke.3270025726
Short name T36
Test name
Test status
Simulation time 175385300 ps
CPU time 120.12 seconds
Started Mar 21 03:17:38 PM PDT 24
Finished Mar 21 03:19:38 PM PDT 24
Peak memory 275856 kb
Host smart-dbc6af09-82f2-4423-8270-2f5ed6a321c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270025726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.3270025726
Directory /workspace/20.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/21.flash_ctrl_alert_test.264413041
Short name T718
Test name
Test status
Simulation time 46179700 ps
CPU time 13.29 seconds
Started Mar 21 03:17:54 PM PDT 24
Finished Mar 21 03:18:07 PM PDT 24
Peak memory 258364 kb
Host smart-3ea8e745-2219-4712-89e1-6ee59bddc178
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264413041 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test.264413041
Directory /workspace/21.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.flash_ctrl_connect.489156023
Short name T765
Test name
Test status
Simulation time 42617500 ps
CPU time 16.66 seconds
Started Mar 21 03:17:47 PM PDT 24
Finished Mar 21 03:18:03 PM PDT 24
Peak memory 276116 kb
Host smart-d5309fc7-1695-4367-b056-cc7c54f4b704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489156023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.489156023
Directory /workspace/21.flash_ctrl_connect/latest

Test location /workspace/coverage/default/21.flash_ctrl_disable.217364051
Short name T888
Test name
Test status
Simulation time 15575900 ps
CPU time 21.87 seconds
Started Mar 21 03:17:54 PM PDT 24
Finished Mar 21 03:18:15 PM PDT 24
Peak memory 265268 kb
Host smart-d1f5eb7a-9566-4ffc-b6a5-5a905c9d42b6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217364051 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.flash_ctrl_disable.217364051
Directory /workspace/21.flash_ctrl_disable/latest

Test location /workspace/coverage/default/21.flash_ctrl_hw_sec_otp.2145283856
Short name T612
Test name
Test status
Simulation time 7388524700 ps
CPU time 57.83 seconds
Started Mar 21 03:17:48 PM PDT 24
Finished Mar 21 03:18:46 PM PDT 24
Peak memory 262624 kb
Host smart-460e712b-cb18-47a8-bfb4-8e5ee8146468
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145283856 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_
hw_sec_otp.2145283856
Directory /workspace/21.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd_slow_flash.131549216
Short name T349
Test name
Test status
Simulation time 85009113800 ps
CPU time 259.95 seconds
Started Mar 21 03:17:47 PM PDT 24
Finished Mar 21 03:22:07 PM PDT 24
Peak memory 289784 kb
Host smart-7266e415-263c-4103-9964-53d6a44aef43
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131549216 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd_slow_flash.131549216
Directory /workspace/21.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/21.flash_ctrl_otp_reset.2611833797
Short name T941
Test name
Test status
Simulation time 161505600 ps
CPU time 132.68 seconds
Started Mar 21 03:17:49 PM PDT 24
Finished Mar 21 03:20:01 PM PDT 24
Peak memory 264524 kb
Host smart-30f145d8-0d7d-439d-9087-06f8aa14567c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611833797 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_o
tp_reset.2611833797
Directory /workspace/21.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_prog_reset.2281720669
Short name T441
Test name
Test status
Simulation time 110600700 ps
CPU time 15.07 seconds
Started Mar 21 03:17:47 PM PDT 24
Finished Mar 21 03:18:02 PM PDT 24
Peak memory 265232 kb
Host smart-5946da19-cf63-4881-8c9c-0124a06dabe4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281720669 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_prog_re
set.2281720669
Directory /workspace/21.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict.3439577698
Short name T951
Test name
Test status
Simulation time 45702500 ps
CPU time 29.05 seconds
Started Mar 21 03:17:48 PM PDT 24
Finished Mar 21 03:18:17 PM PDT 24
Peak memory 273592 kb
Host smart-99d6eb8e-a9c6-4aba-9653-7b3c062bc5fb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439577698 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fl
ash_ctrl_rw_evict.3439577698
Directory /workspace/21.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict_all_en.2607045284
Short name T358
Test name
Test status
Simulation time 30861000 ps
CPU time 28.63 seconds
Started Mar 21 03:17:51 PM PDT 24
Finished Mar 21 03:18:19 PM PDT 24
Peak memory 273556 kb
Host smart-b7f0f68b-1ba1-433e-aa25-2abaa90086ba
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607045284 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict_all_en.2607045284
Directory /workspace/21.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/21.flash_ctrl_sec_info_access.3403702377
Short name T979
Test name
Test status
Simulation time 1725262600 ps
CPU time 58.63 seconds
Started Mar 21 03:17:51 PM PDT 24
Finished Mar 21 03:18:50 PM PDT 24
Peak memory 262992 kb
Host smart-d1d5765d-b4fb-4141-8e3a-b9c8d0a7b7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403702377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.3403702377
Directory /workspace/21.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/21.flash_ctrl_smoke.3477029598
Short name T542
Test name
Test status
Simulation time 137941300 ps
CPU time 173.28 seconds
Started Mar 21 03:17:47 PM PDT 24
Finished Mar 21 03:20:41 PM PDT 24
Peak memory 276504 kb
Host smart-cdde6013-a3aa-41ad-8cba-f41dc27b20a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477029598 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.3477029598
Directory /workspace/21.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/22.flash_ctrl_alert_test.986728338
Short name T463
Test name
Test status
Simulation time 86673900 ps
CPU time 13.76 seconds
Started Mar 21 03:17:57 PM PDT 24
Finished Mar 21 03:18:11 PM PDT 24
Peak memory 258336 kb
Host smart-5075f0d0-c63b-4b53-bc01-8fd653ade1af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986728338 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.986728338
Directory /workspace/22.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.flash_ctrl_connect.2109073265
Short name T762
Test name
Test status
Simulation time 29015200 ps
CPU time 13.58 seconds
Started Mar 21 03:17:59 PM PDT 24
Finished Mar 21 03:18:13 PM PDT 24
Peak memory 275180 kb
Host smart-37ff61b5-9d6a-407f-907d-c170dc8b97b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109073265 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.2109073265
Directory /workspace/22.flash_ctrl_connect/latest

Test location /workspace/coverage/default/22.flash_ctrl_disable.698406227
Short name T376
Test name
Test status
Simulation time 19310600 ps
CPU time 20.62 seconds
Started Mar 21 03:18:03 PM PDT 24
Finished Mar 21 03:18:23 PM PDT 24
Peak memory 273512 kb
Host smart-ce79b458-b8e4-48b7-a322-f2389b5c0d57
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698406227 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.flash_ctrl_disable.698406227
Directory /workspace/22.flash_ctrl_disable/latest

Test location /workspace/coverage/default/22.flash_ctrl_hw_sec_otp.624772001
Short name T628
Test name
Test status
Simulation time 1787216600 ps
CPU time 104.57 seconds
Started Mar 21 03:17:45 PM PDT 24
Finished Mar 21 03:19:30 PM PDT 24
Peak memory 262580 kb
Host smart-4e5aa8ee-8843-44fb-a326-78986c193e75
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624772001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_h
w_sec_otp.624772001
Directory /workspace/22.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd_slow_flash.728086410
Short name T1016
Test name
Test status
Simulation time 16969394800 ps
CPU time 194.24 seconds
Started Mar 21 03:17:49 PM PDT 24
Finished Mar 21 03:21:03 PM PDT 24
Peak memory 289800 kb
Host smart-f8b5b77f-0eef-4e5c-858b-41d67b19fa60
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728086410 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd_slow_flash.728086410
Directory /workspace/22.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/22.flash_ctrl_otp_reset.3149133418
Short name T1034
Test name
Test status
Simulation time 143622000 ps
CPU time 133.74 seconds
Started Mar 21 03:17:48 PM PDT 24
Finished Mar 21 03:20:01 PM PDT 24
Peak memory 264612 kb
Host smart-1813b4f5-9104-433a-81af-7fe0f8eb7c40
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149133418 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_o
tp_reset.3149133418
Directory /workspace/22.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_prog_reset.1569471892
Short name T17
Test name
Test status
Simulation time 33426200 ps
CPU time 13.96 seconds
Started Mar 21 03:18:00 PM PDT 24
Finished Mar 21 03:18:14 PM PDT 24
Peak memory 260116 kb
Host smart-bb4d5f56-6d9b-40c4-96b4-c85dc70ed702
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569471892 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_prog_re
set.1569471892
Directory /workspace/22.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict.522571533
Short name T355
Test name
Test status
Simulation time 28097400 ps
CPU time 29.12 seconds
Started Mar 21 03:17:59 PM PDT 24
Finished Mar 21 03:18:28 PM PDT 24
Peak memory 273544 kb
Host smart-d089873a-f8d5-475f-af67-f6361e74435c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522571533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fla
sh_ctrl_rw_evict.522571533
Directory /workspace/22.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict_all_en.1170406860
Short name T662
Test name
Test status
Simulation time 216524600 ps
CPU time 35.14 seconds
Started Mar 21 03:18:05 PM PDT 24
Finished Mar 21 03:18:41 PM PDT 24
Peak memory 273528 kb
Host smart-3174426b-cd71-4f99-acd5-8170d12a1d5a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170406860 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.flash_ctrl_rw_evict_all_en.1170406860
Directory /workspace/22.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/22.flash_ctrl_sec_info_access.3988542983
Short name T161
Test name
Test status
Simulation time 26252348100 ps
CPU time 84.88 seconds
Started Mar 21 03:18:08 PM PDT 24
Finished Mar 21 03:19:33 PM PDT 24
Peak memory 264028 kb
Host smart-b95f2757-2a76-4263-b866-3c98cc22b3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988542983 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.3988542983
Directory /workspace/22.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/22.flash_ctrl_smoke.2005563559
Short name T722
Test name
Test status
Simulation time 43368000 ps
CPU time 100.13 seconds
Started Mar 21 03:17:47 PM PDT 24
Finished Mar 21 03:19:27 PM PDT 24
Peak memory 275400 kb
Host smart-a77e5ac7-2cb9-47c4-ba53-f4916d892df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005563559 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.2005563559
Directory /workspace/22.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/23.flash_ctrl_alert_test.1052813669
Short name T948
Test name
Test status
Simulation time 38957000 ps
CPU time 13.66 seconds
Started Mar 21 03:18:10 PM PDT 24
Finished Mar 21 03:18:24 PM PDT 24
Peak memory 264608 kb
Host smart-1cc2ad6f-d22d-4eac-8f36-b8b47e493a78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052813669 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.
1052813669
Directory /workspace/23.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.flash_ctrl_connect.2388089140
Short name T490
Test name
Test status
Simulation time 116509600 ps
CPU time 16.17 seconds
Started Mar 21 03:18:07 PM PDT 24
Finished Mar 21 03:18:24 PM PDT 24
Peak memory 275916 kb
Host smart-1644c972-6ec0-4a66-a7fa-1bef1083ca9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388089140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.2388089140
Directory /workspace/23.flash_ctrl_connect/latest

Test location /workspace/coverage/default/23.flash_ctrl_disable.1730626335
Short name T380
Test name
Test status
Simulation time 11314700 ps
CPU time 22.1 seconds
Started Mar 21 03:17:56 PM PDT 24
Finished Mar 21 03:18:19 PM PDT 24
Peak memory 265344 kb
Host smart-bc8aca97-ca95-4ab0-81f0-29a23090ea28
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730626335 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.flash_ctrl_disable.1730626335
Directory /workspace/23.flash_ctrl_disable/latest

Test location /workspace/coverage/default/23.flash_ctrl_hw_sec_otp.2797602127
Short name T967
Test name
Test status
Simulation time 12065309900 ps
CPU time 136.47 seconds
Started Mar 21 03:17:57 PM PDT 24
Finished Mar 21 03:20:14 PM PDT 24
Peak memory 262536 kb
Host smart-d6a28385-8195-46bd-9614-3f0fb325055b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797602127 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_
hw_sec_otp.2797602127
Directory /workspace/23.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.1755915776
Short name T958
Test name
Test status
Simulation time 20443548900 ps
CPU time 225.57 seconds
Started Mar 21 03:18:00 PM PDT 24
Finished Mar 21 03:21:45 PM PDT 24
Peak memory 292936 kb
Host smart-d37bd03b-450d-44e2-9294-388a9d7a116e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755915776 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd_slow_flash.1755915776
Directory /workspace/23.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/23.flash_ctrl_prog_reset.2009956514
Short name T509
Test name
Test status
Simulation time 25121100 ps
CPU time 13.45 seconds
Started Mar 21 03:18:00 PM PDT 24
Finished Mar 21 03:18:13 PM PDT 24
Peak memory 260148 kb
Host smart-a90e42ce-0cc4-4733-b1aa-361d6c0f7ddf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009956514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_prog_re
set.2009956514
Directory /workspace/23.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_rw_evict.4182094172
Short name T609
Test name
Test status
Simulation time 95715400 ps
CPU time 32.75 seconds
Started Mar 21 03:18:04 PM PDT 24
Finished Mar 21 03:18:37 PM PDT 24
Peak memory 273536 kb
Host smart-c8adb7df-da51-4d3c-8f6d-479b0a33d90d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182094172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fl
ash_ctrl_rw_evict.4182094172
Directory /workspace/23.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/23.flash_ctrl_rw_evict_all_en.2732885589
Short name T218
Test name
Test status
Simulation time 337181300 ps
CPU time 29.26 seconds
Started Mar 21 03:17:59 PM PDT 24
Finished Mar 21 03:18:28 PM PDT 24
Peak memory 273576 kb
Host smart-ae65e4cb-bccb-4c17-b84e-26344700b615
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732885589 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict_all_en.2732885589
Directory /workspace/23.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/23.flash_ctrl_sec_info_access.1317696163
Short name T401
Test name
Test status
Simulation time 1825065500 ps
CPU time 65.77 seconds
Started Mar 21 03:17:59 PM PDT 24
Finished Mar 21 03:19:05 PM PDT 24
Peak memory 263260 kb
Host smart-69869e8e-9148-460c-84cd-20cdeb9fe65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317696163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.1317696163
Directory /workspace/23.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/23.flash_ctrl_smoke.1797656180
Short name T585
Test name
Test status
Simulation time 112167900 ps
CPU time 170.4 seconds
Started Mar 21 03:18:05 PM PDT 24
Finished Mar 21 03:20:56 PM PDT 24
Peak memory 276844 kb
Host smart-bd61727b-1290-4b7f-b3dd-f95ad14b123d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797656180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.1797656180
Directory /workspace/23.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/24.flash_ctrl_alert_test.3893928060
Short name T560
Test name
Test status
Simulation time 35156000 ps
CPU time 13.48 seconds
Started Mar 21 03:18:10 PM PDT 24
Finished Mar 21 03:18:24 PM PDT 24
Peak memory 258284 kb
Host smart-1fa04707-f4ff-493e-8859-274cb6d26c50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893928060 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.
3893928060
Directory /workspace/24.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.flash_ctrl_connect.646519978
Short name T501
Test name
Test status
Simulation time 16230700 ps
CPU time 15.61 seconds
Started Mar 21 03:18:08 PM PDT 24
Finished Mar 21 03:18:24 PM PDT 24
Peak memory 275704 kb
Host smart-560b5ae2-ca9f-41cc-b985-603ee16849ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646519978 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.646519978
Directory /workspace/24.flash_ctrl_connect/latest

Test location /workspace/coverage/default/24.flash_ctrl_disable.3694010481
Short name T152
Test name
Test status
Simulation time 35128200 ps
CPU time 22.67 seconds
Started Mar 21 03:18:08 PM PDT 24
Finished Mar 21 03:18:31 PM PDT 24
Peak memory 265236 kb
Host smart-8ca9db86-bc54-4d44-ba50-57ba33567f6e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694010481 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_disable.3694010481
Directory /workspace/24.flash_ctrl_disable/latest

Test location /workspace/coverage/default/24.flash_ctrl_hw_sec_otp.3549396653
Short name T836
Test name
Test status
Simulation time 2627283400 ps
CPU time 110.04 seconds
Started Mar 21 03:18:10 PM PDT 24
Finished Mar 21 03:20:01 PM PDT 24
Peak memory 262456 kb
Host smart-960ca0c8-17d1-4570-b97b-add6a34aad10
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549396653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_
hw_sec_otp.3549396653
Directory /workspace/24.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/24.flash_ctrl_otp_reset.361632336
Short name T895
Test name
Test status
Simulation time 36101000 ps
CPU time 132.08 seconds
Started Mar 21 03:18:09 PM PDT 24
Finished Mar 21 03:20:21 PM PDT 24
Peak memory 264396 kb
Host smart-597b9672-7053-4827-b0bf-69d57ff4cf29
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361632336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_ot
p_reset.361632336
Directory /workspace/24.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_prog_reset.2436156473
Short name T130
Test name
Test status
Simulation time 56509800 ps
CPU time 13.79 seconds
Started Mar 21 03:18:10 PM PDT 24
Finished Mar 21 03:18:24 PM PDT 24
Peak memory 260112 kb
Host smart-39acf042-55ac-4712-bea6-5b0d7924b721
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436156473 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_prog_re
set.2436156473
Directory /workspace/24.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict.1520786817
Short name T854
Test name
Test status
Simulation time 84781700 ps
CPU time 31.19 seconds
Started Mar 21 03:18:07 PM PDT 24
Finished Mar 21 03:18:38 PM PDT 24
Peak memory 274524 kb
Host smart-cee7895e-596f-4bdf-b96d-743d8dcda51e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520786817 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fl
ash_ctrl_rw_evict.1520786817
Directory /workspace/24.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict_all_en.2920508882
Short name T588
Test name
Test status
Simulation time 30225300 ps
CPU time 31.96 seconds
Started Mar 21 03:18:07 PM PDT 24
Finished Mar 21 03:18:40 PM PDT 24
Peak memory 273576 kb
Host smart-df52ab56-aa75-44b3-950b-d32c2d2af54c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920508882 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict_all_en.2920508882
Directory /workspace/24.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/24.flash_ctrl_sec_info_access.4117046539
Short name T955
Test name
Test status
Simulation time 1166650600 ps
CPU time 70.64 seconds
Started Mar 21 03:18:07 PM PDT 24
Finished Mar 21 03:19:19 PM PDT 24
Peak memory 263216 kb
Host smart-1fd4f116-a151-4439-9dd5-8ee1e276cf8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117046539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.4117046539
Directory /workspace/24.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/24.flash_ctrl_smoke.162234078
Short name T777
Test name
Test status
Simulation time 28472900 ps
CPU time 99.07 seconds
Started Mar 21 03:18:07 PM PDT 24
Finished Mar 21 03:19:47 PM PDT 24
Peak memory 275348 kb
Host smart-949caf4e-0097-4a88-9d3a-1b9aba27d107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162234078 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.162234078
Directory /workspace/24.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/25.flash_ctrl_alert_test.1197160972
Short name T980
Test name
Test status
Simulation time 64943100 ps
CPU time 13.89 seconds
Started Mar 21 03:18:17 PM PDT 24
Finished Mar 21 03:18:31 PM PDT 24
Peak memory 258248 kb
Host smart-5e17902d-5f9e-4f7d-b3d2-ae36b46102cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197160972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test.
1197160972
Directory /workspace/25.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.flash_ctrl_connect.2657590563
Short name T671
Test name
Test status
Simulation time 50755400 ps
CPU time 15.93 seconds
Started Mar 21 03:18:17 PM PDT 24
Finished Mar 21 03:18:33 PM PDT 24
Peak memory 275612 kb
Host smart-180fef5f-38a7-482c-a813-6c8fa8465d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657590563 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.2657590563
Directory /workspace/25.flash_ctrl_connect/latest

Test location /workspace/coverage/default/25.flash_ctrl_hw_sec_otp.1525982389
Short name T428
Test name
Test status
Simulation time 2589010300 ps
CPU time 199.7 seconds
Started Mar 21 03:18:18 PM PDT 24
Finished Mar 21 03:21:38 PM PDT 24
Peak memory 262500 kb
Host smart-7b1daa23-166f-4e88-853b-da68d7c7d668
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525982389 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_
hw_sec_otp.1525982389
Directory /workspace/25.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd_slow_flash.1784235896
Short name T364
Test name
Test status
Simulation time 8704013600 ps
CPU time 195.23 seconds
Started Mar 21 03:18:20 PM PDT 24
Finished Mar 21 03:21:35 PM PDT 24
Peak memory 290812 kb
Host smart-0968c60b-a14e-491c-9b8d-31e4928e1e4b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784235896 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd_slow_flash.1784235896
Directory /workspace/25.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/25.flash_ctrl_otp_reset.3393852930
Short name T715
Test name
Test status
Simulation time 234332200 ps
CPU time 133.19 seconds
Started Mar 21 03:18:16 PM PDT 24
Finished Mar 21 03:20:30 PM PDT 24
Peak memory 261076 kb
Host smart-516a2e04-12c2-499e-adc1-2fa3a64ab9d6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393852930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_o
tp_reset.3393852930
Directory /workspace/25.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_prog_reset.1963788286
Short name T738
Test name
Test status
Simulation time 33327600 ps
CPU time 13.56 seconds
Started Mar 21 03:18:17 PM PDT 24
Finished Mar 21 03:18:30 PM PDT 24
Peak memory 260052 kb
Host smart-623c975e-44e8-48dc-864c-d7f841a9ed3f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963788286 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_prog_re
set.1963788286
Directory /workspace/25.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_rw_evict.2274743820
Short name T666
Test name
Test status
Simulation time 33944300 ps
CPU time 29.18 seconds
Started Mar 21 03:18:18 PM PDT 24
Finished Mar 21 03:18:47 PM PDT 24
Peak memory 274584 kb
Host smart-def191d0-e564-45b0-b51f-f6d068350dd2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274743820 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fl
ash_ctrl_rw_evict.2274743820
Directory /workspace/25.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/25.flash_ctrl_rw_evict_all_en.3188262634
Short name T791
Test name
Test status
Simulation time 44212500 ps
CPU time 30.51 seconds
Started Mar 21 03:18:17 PM PDT 24
Finished Mar 21 03:18:48 PM PDT 24
Peak memory 266480 kb
Host smart-377c86f8-383b-41a9-9d87-13c1843943ab
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188262634 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict_all_en.3188262634
Directory /workspace/25.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/25.flash_ctrl_sec_info_access.1691720832
Short name T394
Test name
Test status
Simulation time 20946106100 ps
CPU time 91.83 seconds
Started Mar 21 03:18:19 PM PDT 24
Finished Mar 21 03:19:50 PM PDT 24
Peak memory 264632 kb
Host smart-6683b7f7-3f07-4a19-b082-b6216eb7254e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691720832 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.1691720832
Directory /workspace/25.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/25.flash_ctrl_smoke.1965691457
Short name T845
Test name
Test status
Simulation time 3127803000 ps
CPU time 224.07 seconds
Started Mar 21 03:18:17 PM PDT 24
Finished Mar 21 03:22:01 PM PDT 24
Peak memory 280960 kb
Host smart-63b440c9-a532-454c-bb5e-8107ddff9165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965691457 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.1965691457
Directory /workspace/25.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/26.flash_ctrl_alert_test.2106153344
Short name T262
Test name
Test status
Simulation time 43835700 ps
CPU time 14.59 seconds
Started Mar 21 03:18:27 PM PDT 24
Finished Mar 21 03:18:42 PM PDT 24
Peak memory 265192 kb
Host smart-efcc1a45-655a-4cb1-b467-4217290c3d4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106153344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.
2106153344
Directory /workspace/26.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.flash_ctrl_connect.698925326
Short name T510
Test name
Test status
Simulation time 29504600 ps
CPU time 16.12 seconds
Started Mar 21 03:18:27 PM PDT 24
Finished Mar 21 03:18:43 PM PDT 24
Peak memory 275132 kb
Host smart-16e673ea-a304-4734-9b55-f0ef99db9877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698925326 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.698925326
Directory /workspace/26.flash_ctrl_connect/latest

Test location /workspace/coverage/default/26.flash_ctrl_disable.2755207303
Short name T862
Test name
Test status
Simulation time 11943700 ps
CPU time 21.95 seconds
Started Mar 21 03:18:27 PM PDT 24
Finished Mar 21 03:18:50 PM PDT 24
Peak memory 273568 kb
Host smart-4d4b6bf6-2c4f-4ed7-98e2-901fd5431ba9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755207303 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_disable.2755207303
Directory /workspace/26.flash_ctrl_disable/latest

Test location /workspace/coverage/default/26.flash_ctrl_hw_sec_otp.3638934063
Short name T943
Test name
Test status
Simulation time 16495360900 ps
CPU time 51.48 seconds
Started Mar 21 03:18:19 PM PDT 24
Finished Mar 21 03:19:11 PM PDT 24
Peak memory 262564 kb
Host smart-e91b8945-a980-4bcd-bb30-7b5fe07b1ee2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638934063 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_
hw_sec_otp.3638934063
Directory /workspace/26.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd_slow_flash.1475679991
Short name T344
Test name
Test status
Simulation time 8841347100 ps
CPU time 254.47 seconds
Started Mar 21 03:18:26 PM PDT 24
Finished Mar 21 03:22:41 PM PDT 24
Peak memory 284768 kb
Host smart-45656d16-e9a5-409d-8c44-2a1a4e244b5f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475679991 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd_slow_flash.1475679991
Directory /workspace/26.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/26.flash_ctrl_otp_reset.2868365120
Short name T818
Test name
Test status
Simulation time 157447000 ps
CPU time 112.88 seconds
Started Mar 21 03:18:17 PM PDT 24
Finished Mar 21 03:20:10 PM PDT 24
Peak memory 261100 kb
Host smart-1feda3d3-7e74-4ce7-968c-cf7721604586
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868365120 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_o
tp_reset.2868365120
Directory /workspace/26.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_prog_reset.2506218327
Short name T1022
Test name
Test status
Simulation time 61515600 ps
CPU time 13.75 seconds
Started Mar 21 03:18:27 PM PDT 24
Finished Mar 21 03:18:40 PM PDT 24
Peak memory 260156 kb
Host smart-9b81ee2a-fd80-4100-9400-4a8f5321cae3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506218327 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_prog_re
set.2506218327
Directory /workspace/26.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict.2138035331
Short name T219
Test name
Test status
Simulation time 111876700 ps
CPU time 34.38 seconds
Started Mar 21 03:18:27 PM PDT 24
Finished Mar 21 03:19:01 PM PDT 24
Peak memory 273584 kb
Host smart-b78c3ed2-a112-4322-a9d3-15ecd31be8c1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138035331 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fl
ash_ctrl_rw_evict.2138035331
Directory /workspace/26.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict_all_en.2465527456
Short name T359
Test name
Test status
Simulation time 205899300 ps
CPU time 29.59 seconds
Started Mar 21 03:18:26 PM PDT 24
Finished Mar 21 03:18:56 PM PDT 24
Peak memory 273620 kb
Host smart-f8ca4a18-cc29-49f3-85d1-d898629ba5b3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465527456 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict_all_en.2465527456
Directory /workspace/26.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/26.flash_ctrl_sec_info_access.4238875054
Short name T391
Test name
Test status
Simulation time 498971800 ps
CPU time 60.72 seconds
Started Mar 21 03:18:33 PM PDT 24
Finished Mar 21 03:19:33 PM PDT 24
Peak memory 264564 kb
Host smart-8ce850cd-dcf0-456c-bed3-665d2732ebf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238875054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.4238875054
Directory /workspace/26.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/26.flash_ctrl_smoke.2823032502
Short name T802
Test name
Test status
Simulation time 65291400 ps
CPU time 52.51 seconds
Started Mar 21 03:18:17 PM PDT 24
Finished Mar 21 03:19:10 PM PDT 24
Peak memory 270548 kb
Host smart-48aa9008-4dc0-45a8-9984-bca9f1a224fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823032502 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.2823032502
Directory /workspace/26.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/27.flash_ctrl_alert_test.3893325247
Short name T314
Test name
Test status
Simulation time 63506900 ps
CPU time 13.36 seconds
Started Mar 21 03:18:38 PM PDT 24
Finished Mar 21 03:18:51 PM PDT 24
Peak memory 258212 kb
Host smart-1562b663-068b-4c7c-8960-d68c104aa0f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893325247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.
3893325247
Directory /workspace/27.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.flash_ctrl_connect.2941241857
Short name T487
Test name
Test status
Simulation time 28587400 ps
CPU time 15.99 seconds
Started Mar 21 03:18:31 PM PDT 24
Finished Mar 21 03:18:47 PM PDT 24
Peak memory 275700 kb
Host smart-f1e7cc93-58c1-4c95-9e2c-ae764c774e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941241857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.2941241857
Directory /workspace/27.flash_ctrl_connect/latest

Test location /workspace/coverage/default/27.flash_ctrl_disable.1692518664
Short name T153
Test name
Test status
Simulation time 21330200 ps
CPU time 21.91 seconds
Started Mar 21 03:18:31 PM PDT 24
Finished Mar 21 03:18:53 PM PDT 24
Peak memory 273128 kb
Host smart-8f35642c-92b8-4e59-88f1-dab5e33de323
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692518664 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_disable.1692518664
Directory /workspace/27.flash_ctrl_disable/latest

Test location /workspace/coverage/default/27.flash_ctrl_hw_sec_otp.3923557788
Short name T502
Test name
Test status
Simulation time 7447722800 ps
CPU time 151.45 seconds
Started Mar 21 03:18:29 PM PDT 24
Finished Mar 21 03:21:01 PM PDT 24
Peak memory 262344 kb
Host smart-fb1c955d-8b61-4e27-b4af-f9cd552fccfd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923557788 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_
hw_sec_otp.3923557788
Directory /workspace/27.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.1202492366
Short name T345
Test name
Test status
Simulation time 17024626200 ps
CPU time 220.6 seconds
Started Mar 21 03:18:29 PM PDT 24
Finished Mar 21 03:22:09 PM PDT 24
Peak memory 289812 kb
Host smart-955931ba-2114-480b-9e72-8abac416e788
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202492366 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd_slow_flash.1202492366
Directory /workspace/27.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/27.flash_ctrl_otp_reset.2816287320
Short name T70
Test name
Test status
Simulation time 151581400 ps
CPU time 111.42 seconds
Started Mar 21 03:18:25 PM PDT 24
Finished Mar 21 03:20:16 PM PDT 24
Peak memory 260128 kb
Host smart-400cd0e1-4354-4893-a2e6-202588858561
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816287320 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_o
tp_reset.2816287320
Directory /workspace/27.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_prog_reset.759590466
Short name T86
Test name
Test status
Simulation time 19923300 ps
CPU time 13.61 seconds
Started Mar 21 03:18:28 PM PDT 24
Finished Mar 21 03:18:41 PM PDT 24
Peak memory 260076 kb
Host smart-4c105918-4874-4a36-a792-c03b52738710
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759590466 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_prog_res
et.759590466
Directory /workspace/27.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict.3546780665
Short name T528
Test name
Test status
Simulation time 272340700 ps
CPU time 33.48 seconds
Started Mar 21 03:18:33 PM PDT 24
Finished Mar 21 03:19:06 PM PDT 24
Peak memory 273540 kb
Host smart-001211b3-5ffd-490f-9412-1b5ea73540b2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546780665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fl
ash_ctrl_rw_evict.3546780665
Directory /workspace/27.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict_all_en.3600298391
Short name T764
Test name
Test status
Simulation time 29861400 ps
CPU time 28.54 seconds
Started Mar 21 03:18:26 PM PDT 24
Finished Mar 21 03:18:55 PM PDT 24
Peak memory 274572 kb
Host smart-8aa6a63c-6fef-487c-b2c2-197929dc7d79
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600298391 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict_all_en.3600298391
Directory /workspace/27.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/27.flash_ctrl_sec_info_access.4174643756
Short name T975
Test name
Test status
Simulation time 46952651400 ps
CPU time 128.01 seconds
Started Mar 21 03:18:32 PM PDT 24
Finished Mar 21 03:20:40 PM PDT 24
Peak memory 259884 kb
Host smart-31bcceed-6dc1-4bdd-8ed7-63fa96810b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174643756 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.4174643756
Directory /workspace/27.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/27.flash_ctrl_smoke.714173353
Short name T860
Test name
Test status
Simulation time 23920700 ps
CPU time 49.49 seconds
Started Mar 21 03:18:27 PM PDT 24
Finished Mar 21 03:19:17 PM PDT 24
Peak memory 270616 kb
Host smart-b1111674-ba1a-4593-ac7d-63319d401dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714173353 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.714173353
Directory /workspace/27.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/28.flash_ctrl_alert_test.721072866
Short name T991
Test name
Test status
Simulation time 497321600 ps
CPU time 14.56 seconds
Started Mar 21 03:18:35 PM PDT 24
Finished Mar 21 03:18:50 PM PDT 24
Peak memory 265248 kb
Host smart-f401ea3f-0da9-433a-bd00-ce6dfc846253
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721072866 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.721072866
Directory /workspace/28.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.flash_ctrl_connect.3648792744
Short name T945
Test name
Test status
Simulation time 20587400 ps
CPU time 15.94 seconds
Started Mar 21 03:18:35 PM PDT 24
Finished Mar 21 03:18:51 PM PDT 24
Peak memory 275148 kb
Host smart-128d0cbd-e985-4e39-b468-8ea230889a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648792744 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.3648792744
Directory /workspace/28.flash_ctrl_connect/latest

Test location /workspace/coverage/default/28.flash_ctrl_disable.1677675248
Short name T497
Test name
Test status
Simulation time 12611600 ps
CPU time 21.02 seconds
Started Mar 21 03:18:36 PM PDT 24
Finished Mar 21 03:18:57 PM PDT 24
Peak memory 280444 kb
Host smart-9c9ff5e2-6cc4-42dc-96b2-88c0efdbc82d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677675248 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_disable.1677675248
Directory /workspace/28.flash_ctrl_disable/latest

Test location /workspace/coverage/default/28.flash_ctrl_hw_sec_otp.3848705687
Short name T799
Test name
Test status
Simulation time 6210203400 ps
CPU time 60.51 seconds
Started Mar 21 03:18:37 PM PDT 24
Finished Mar 21 03:19:37 PM PDT 24
Peak memory 262516 kb
Host smart-c1da4f92-ba8f-4668-a30d-a644db200cc6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848705687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_
hw_sec_otp.3848705687
Directory /workspace/28.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/28.flash_ctrl_otp_reset.933043760
Short name T143
Test name
Test status
Simulation time 70843300 ps
CPU time 109.8 seconds
Started Mar 21 03:18:37 PM PDT 24
Finished Mar 21 03:20:27 PM PDT 24
Peak memory 259760 kb
Host smart-2057d072-b189-4a83-8c72-beef4ee843aa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933043760 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_ot
p_reset.933043760
Directory /workspace/28.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_prog_reset.684514979
Short name T38
Test name
Test status
Simulation time 20062800 ps
CPU time 13.65 seconds
Started Mar 21 03:18:38 PM PDT 24
Finished Mar 21 03:18:52 PM PDT 24
Peak memory 260084 kb
Host smart-0b0cf99d-bcad-4367-b1de-a2e988c310f8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684514979 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_prog_res
et.684514979
Directory /workspace/28.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict.1866845547
Short name T331
Test name
Test status
Simulation time 177320200 ps
CPU time 31.32 seconds
Started Mar 21 03:18:35 PM PDT 24
Finished Mar 21 03:19:07 PM PDT 24
Peak memory 273580 kb
Host smart-16d30f93-abd7-41ca-982a-4263151b6015
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866845547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fl
ash_ctrl_rw_evict.1866845547
Directory /workspace/28.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.1736483434
Short name T289
Test name
Test status
Simulation time 125723700 ps
CPU time 30.95 seconds
Started Mar 21 03:18:37 PM PDT 24
Finished Mar 21 03:19:08 PM PDT 24
Peak memory 274596 kb
Host smart-208dcae3-83b7-4ef2-8a40-80804fbe8772
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736483434 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict_all_en.1736483434
Directory /workspace/28.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/28.flash_ctrl_sec_info_access.2863979670
Short name T876
Test name
Test status
Simulation time 2134898700 ps
CPU time 65.49 seconds
Started Mar 21 03:18:35 PM PDT 24
Finished Mar 21 03:19:41 PM PDT 24
Peak memory 262964 kb
Host smart-ebeedfb2-1210-4886-93a0-c3178c31bc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863979670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.2863979670
Directory /workspace/28.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/28.flash_ctrl_smoke.4243472923
Short name T844
Test name
Test status
Simulation time 22961100 ps
CPU time 99.28 seconds
Started Mar 21 03:18:35 PM PDT 24
Finished Mar 21 03:20:15 PM PDT 24
Peak memory 275296 kb
Host smart-c374596c-1332-4a9c-a733-2f624fcd026f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243472923 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.4243472923
Directory /workspace/28.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/29.flash_ctrl_alert_test.2260847306
Short name T455
Test name
Test status
Simulation time 41628600 ps
CPU time 13.8 seconds
Started Mar 21 03:18:47 PM PDT 24
Finished Mar 21 03:19:01 PM PDT 24
Peak memory 265260 kb
Host smart-1dcf9932-1e7b-4646-98e5-8ffd54c6f555
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260847306 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test.
2260847306
Directory /workspace/29.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.flash_ctrl_connect.1674675163
Short name T546
Test name
Test status
Simulation time 55078600 ps
CPU time 15.89 seconds
Started Mar 21 03:18:45 PM PDT 24
Finished Mar 21 03:19:01 PM PDT 24
Peak memory 275216 kb
Host smart-6a1f567e-9b5a-453d-8c48-e4cf537052a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674675163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.1674675163
Directory /workspace/29.flash_ctrl_connect/latest

Test location /workspace/coverage/default/29.flash_ctrl_disable.3621981229
Short name T154
Test name
Test status
Simulation time 21368800 ps
CPU time 23.11 seconds
Started Mar 21 03:18:45 PM PDT 24
Finished Mar 21 03:19:09 PM PDT 24
Peak memory 273540 kb
Host smart-8b25ea16-8b22-4735-837f-3bf5357af0fc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621981229 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_disable.3621981229
Directory /workspace/29.flash_ctrl_disable/latest

Test location /workspace/coverage/default/29.flash_ctrl_hw_sec_otp.2526844131
Short name T739
Test name
Test status
Simulation time 6555237800 ps
CPU time 98.65 seconds
Started Mar 21 03:18:37 PM PDT 24
Finished Mar 21 03:20:16 PM PDT 24
Peak memory 262448 kb
Host smart-6df95c0e-52ec-403b-8390-a027d0d3f702
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526844131 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_
hw_sec_otp.2526844131
Directory /workspace/29.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.2803279481
Short name T603
Test name
Test status
Simulation time 8430154400 ps
CPU time 217.07 seconds
Started Mar 21 03:18:37 PM PDT 24
Finished Mar 21 03:22:14 PM PDT 24
Peak memory 291460 kb
Host smart-8d1597ff-b278-4f21-b9ee-d01b913bc4ec
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803279481 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd_slow_flash.2803279481
Directory /workspace/29.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/29.flash_ctrl_otp_reset.2314966764
Short name T962
Test name
Test status
Simulation time 181514300 ps
CPU time 134.3 seconds
Started Mar 21 03:18:37 PM PDT 24
Finished Mar 21 03:20:51 PM PDT 24
Peak memory 259876 kb
Host smart-986b1fa5-a21b-40ce-9070-e69ef25d5473
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314966764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_o
tp_reset.2314966764
Directory /workspace/29.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_prog_reset.1162084218
Short name T781
Test name
Test status
Simulation time 67895400 ps
CPU time 17.29 seconds
Started Mar 21 03:18:50 PM PDT 24
Finished Mar 21 03:19:08 PM PDT 24
Peak memory 260796 kb
Host smart-c632757e-9b82-40a9-a542-0e1a15392afb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162084218 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_prog_re
set.1162084218
Directory /workspace/29.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict.782269165
Short name T1024
Test name
Test status
Simulation time 110419300 ps
CPU time 31.12 seconds
Started Mar 21 03:18:46 PM PDT 24
Finished Mar 21 03:19:17 PM PDT 24
Peak memory 276876 kb
Host smart-14f2ae48-fb1d-4aef-bb74-fc00db042582
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782269165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fla
sh_ctrl_rw_evict.782269165
Directory /workspace/29.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/29.flash_ctrl_sec_info_access.2281664305
Short name T622
Test name
Test status
Simulation time 3119114400 ps
CPU time 70.2 seconds
Started Mar 21 03:18:45 PM PDT 24
Finished Mar 21 03:19:56 PM PDT 24
Peak memory 264592 kb
Host smart-63a94db6-155a-42d4-8645-fd095e8ff3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281664305 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.2281664305
Directory /workspace/29.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/29.flash_ctrl_smoke.237083043
Short name T377
Test name
Test status
Simulation time 224799600 ps
CPU time 124.03 seconds
Started Mar 21 03:18:36 PM PDT 24
Finished Mar 21 03:20:40 PM PDT 24
Peak memory 278036 kb
Host smart-85f66c23-e451-4b71-82cf-f571a2bcfccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237083043 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.237083043
Directory /workspace/29.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_alert_test.2337858088
Short name T742
Test name
Test status
Simulation time 71110700 ps
CPU time 13.94 seconds
Started Mar 21 03:12:56 PM PDT 24
Finished Mar 21 03:13:11 PM PDT 24
Peak memory 258240 kb
Host smart-7b08d98a-f82f-44b8-aa4d-6b55eab7d8b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337858088 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.2
337858088
Directory /workspace/3.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.flash_ctrl_config_regwen.2577612924
Short name T761
Test name
Test status
Simulation time 63247300 ps
CPU time 14.47 seconds
Started Mar 21 03:12:56 PM PDT 24
Finished Mar 21 03:13:11 PM PDT 24
Peak memory 265152 kb
Host smart-2dcfff94-47cc-48bf-9a98-fdb18bdd4403
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577612924 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.flash_ctrl_config_regwen.2577612924
Directory /workspace/3.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/3.flash_ctrl_connect.1270255901
Short name T614
Test name
Test status
Simulation time 156625600 ps
CPU time 13.5 seconds
Started Mar 21 03:12:57 PM PDT 24
Finished Mar 21 03:13:11 PM PDT 24
Peak memory 275800 kb
Host smart-85fd1569-0468-4caf-b996-ce112086ed02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270255901 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.1270255901
Directory /workspace/3.flash_ctrl_connect/latest

Test location /workspace/coverage/default/3.flash_ctrl_disable.3918722871
Short name T327
Test name
Test status
Simulation time 31523500 ps
CPU time 22.26 seconds
Started Mar 21 03:13:01 PM PDT 24
Finished Mar 21 03:13:23 PM PDT 24
Peak memory 265412 kb
Host smart-75883aec-76ed-4197-8b71-c2b818f36a5e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918722871 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_disable.3918722871
Directory /workspace/3.flash_ctrl_disable/latest

Test location /workspace/coverage/default/3.flash_ctrl_erase_suspend.2155017806
Short name T125
Test name
Test status
Simulation time 6312061700 ps
CPU time 367.48 seconds
Started Mar 21 03:12:36 PM PDT 24
Finished Mar 21 03:18:44 PM PDT 24
Peak memory 261396 kb
Host smart-2e4ab10d-3b01-4e61-b0fe-f7b6629d1fa6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2155017806 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.2155017806
Directory /workspace/3.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_mp.2076988611
Short name T744
Test name
Test status
Simulation time 64982850500 ps
CPU time 2264.55 seconds
Started Mar 21 03:12:31 PM PDT 24
Finished Mar 21 03:50:16 PM PDT 24
Peak memory 265216 kb
Host smart-8a400b41-ba89-4028-9330-c113b6ea08fe
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076988611 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_err
or_mp.2076988611
Directory /workspace/3.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_win.2042400681
Short name T302
Test name
Test status
Simulation time 971995900 ps
CPU time 1271.91 seconds
Started Mar 21 03:12:36 PM PDT 24
Finished Mar 21 03:33:48 PM PDT 24
Peak memory 273260 kb
Host smart-7f42c20d-6464-4ee2-8c24-ee8e0c39b6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042400681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.2042400681
Directory /workspace/3.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/3.flash_ctrl_fetch_code.1342901816
Short name T46
Test name
Test status
Simulation time 555259900 ps
CPU time 22.44 seconds
Started Mar 21 03:12:29 PM PDT 24
Finished Mar 21 03:12:51 PM PDT 24
Peak memory 262072 kb
Host smart-05aea19f-a7f7-4c87-b686-b6f4722aa2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342901816 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetch_code.1342901816
Directory /workspace/3.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/3.flash_ctrl_fs_sup.1254963821
Short name T285
Test name
Test status
Simulation time 577362900 ps
CPU time 37.3 seconds
Started Mar 21 03:12:57 PM PDT 24
Finished Mar 21 03:13:35 PM PDT 24
Peak memory 273436 kb
Host smart-fa3b9942-ccd2-4571-96b8-bc794d6db248
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254963821 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.flash_ctrl_fs_sup.1254963821
Directory /workspace/3.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/3.flash_ctrl_full_mem_access.1179025802
Short name T101
Test name
Test status
Simulation time 97823752000 ps
CPU time 4659.73 seconds
Started Mar 21 03:12:29 PM PDT 24
Finished Mar 21 04:30:10 PM PDT 24
Peak memory 273312 kb
Host smart-34673089-9987-4e9b-a9bb-2f67c8d26f05
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179025802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_c
trl_full_mem_access.1179025802
Directory /workspace/3.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_dir_rd.1814552523
Short name T894
Test name
Test status
Simulation time 189880400 ps
CPU time 82.5 seconds
Started Mar 21 03:12:31 PM PDT 24
Finished Mar 21 03:13:53 PM PDT 24
Peak memory 265232 kb
Host smart-6d492e4b-62fa-4616-a5c5-322386e4c519
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1814552523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.1814552523
Directory /workspace/3.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.2583629292
Short name T229
Test name
Test status
Simulation time 10012118100 ps
CPU time 137.15 seconds
Started Mar 21 03:12:57 PM PDT 24
Finished Mar 21 03:15:15 PM PDT 24
Peak memory 366200 kb
Host smart-1f6a1983-b63b-4f80-83e4-5fe41621f5c8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583629292 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.2583629292
Directory /workspace/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_read_seed_err.839620682
Short name T754
Test name
Test status
Simulation time 26975000 ps
CPU time 13.65 seconds
Started Mar 21 03:12:55 PM PDT 24
Finished Mar 21 03:13:09 PM PDT 24
Peak memory 265240 kb
Host smart-8ab2b096-315c-4c64-b05c-5867e714e3d8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839620682 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_read_seed_err.839620682
Directory /workspace/3.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_rma_reset.3213690191
Short name T157
Test name
Test status
Simulation time 160193904800 ps
CPU time 897.15 seconds
Started Mar 21 03:12:30 PM PDT 24
Finished Mar 21 03:27:28 PM PDT 24
Peak memory 263240 kb
Host smart-b763571d-f45a-4734-9214-eb9a433b5fda
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213690191 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 3.flash_ctrl_hw_rma_reset.3213690191
Directory /workspace/3.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_sec_otp.2427676037
Short name T456
Test name
Test status
Simulation time 3061041500 ps
CPU time 252.69 seconds
Started Mar 21 03:12:31 PM PDT 24
Finished Mar 21 03:16:44 PM PDT 24
Peak memory 262472 kb
Host smart-6abe3c68-cede-477f-aee1-1a09926b6b7d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427676037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_h
w_sec_otp.2427676037
Directory /workspace/3.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.1659675731
Short name T524
Test name
Test status
Simulation time 17135772700 ps
CPU time 204.03 seconds
Started Mar 21 03:12:44 PM PDT 24
Finished Mar 21 03:16:08 PM PDT 24
Peak memory 284680 kb
Host smart-4bf5d03c-b03f-4447-8f9e-d7119cd15b38
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659675731 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd_slow_flash.1659675731
Directory /workspace/3.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr.3201785924
Short name T25
Test name
Test status
Simulation time 11247184800 ps
CPU time 114.58 seconds
Started Mar 21 03:12:44 PM PDT 24
Finished Mar 21 03:14:39 PM PDT 24
Peak memory 265240 kb
Host smart-aefbb9dc-ecd3-444c-a8d3-f18b1855e5df
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201785924 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.flash_ctrl_intr_wr.3201785924
Directory /workspace/3.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr_slow_flash.259135156
Short name T500
Test name
Test status
Simulation time 86021113100 ps
CPU time 336.45 seconds
Started Mar 21 03:12:57 PM PDT 24
Finished Mar 21 03:18:34 PM PDT 24
Peak memory 265312 kb
Host smart-c1f9199c-ae2a-4ce5-8682-574890a2132a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259
135156 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.259135156
Directory /workspace/3.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_invalid_op.2946830956
Short name T745
Test name
Test status
Simulation time 17465872400 ps
CPU time 81.23 seconds
Started Mar 21 03:12:30 PM PDT 24
Finished Mar 21 03:13:52 PM PDT 24
Peak memory 260508 kb
Host smart-a0b3d008-e2a8-4d7c-b85a-a42cd2ded0fe
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946830956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.2946830956
Directory /workspace/3.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_mid_op_rst.743345697
Short name T126
Test name
Test status
Simulation time 3416422000 ps
CPU time 74.01 seconds
Started Mar 21 03:12:31 PM PDT 24
Finished Mar 21 03:13:45 PM PDT 24
Peak memory 265032 kb
Host smart-fba27b4c-a805-4802-b966-aeb37f6d76d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743345697 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.743345697
Directory /workspace/3.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/3.flash_ctrl_mp_regions.2626401896
Short name T95
Test name
Test status
Simulation time 39034727900 ps
CPU time 322.03 seconds
Started Mar 21 03:12:34 PM PDT 24
Finished Mar 21 03:17:56 PM PDT 24
Peak memory 273992 kb
Host smart-36bf254b-1dee-499f-a441-a8c51778d5f1
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626401896 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_mp_regions.2626401896
Directory /workspace/3.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/3.flash_ctrl_otp_reset.3627625320
Short name T630
Test name
Test status
Simulation time 81237100 ps
CPU time 134.35 seconds
Started Mar 21 03:12:30 PM PDT 24
Finished Mar 21 03:14:45 PM PDT 24
Peak memory 260012 kb
Host smart-44aefd66-2c3e-425c-a3ee-7621b5099960
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627625320 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ot
p_reset.3627625320
Directory /workspace/3.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb.3834024495
Short name T236
Test name
Test status
Simulation time 742635500 ps
CPU time 502.15 seconds
Started Mar 21 03:12:32 PM PDT 24
Finished Mar 21 03:20:54 PM PDT 24
Peak memory 262548 kb
Host smart-72db9799-81bf-4279-89ff-2ad8becf71f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3834024495 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.3834024495
Directory /workspace/3.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb_redun.1942063266
Short name T66
Test name
Test status
Simulation time 954140500 ps
CPU time 27.12 seconds
Started Mar 21 03:12:57 PM PDT 24
Finished Mar 21 03:13:25 PM PDT 24
Peak memory 262488 kb
Host smart-1a97add7-35aa-4f88-9774-ab365a6ce45c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942063266 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.1942063266
Directory /workspace/3.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/3.flash_ctrl_prog_reset.2544242071
Short name T659
Test name
Test status
Simulation time 21547100 ps
CPU time 13.67 seconds
Started Mar 21 03:12:57 PM PDT 24
Finished Mar 21 03:13:11 PM PDT 24
Peak memory 265168 kb
Host smart-0c8b90a0-3046-4788-bf1b-b23b7d08fd9b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544242071 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_prog_res
et.2544242071
Directory /workspace/3.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_rand_ops.1309428155
Short name T99
Test name
Test status
Simulation time 9242874700 ps
CPU time 718.63 seconds
Started Mar 21 03:12:31 PM PDT 24
Finished Mar 21 03:24:30 PM PDT 24
Peak memory 283720 kb
Host smart-54bc1128-1d45-43fb-9f53-faf418806778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309428155 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.1309428155
Directory /workspace/3.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/3.flash_ctrl_rd_buff_evict.3265164878
Short name T115
Test name
Test status
Simulation time 89116200 ps
CPU time 104.41 seconds
Started Mar 21 03:12:29 PM PDT 24
Finished Mar 21 03:14:13 PM PDT 24
Peak memory 265220 kb
Host smart-8480ffac-82fd-4a72-a622-9890b94a5904
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3265164878 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.3265164878
Directory /workspace/3.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_re_evict.552246656
Short name T581
Test name
Test status
Simulation time 393921100 ps
CPU time 33.48 seconds
Started Mar 21 03:12:58 PM PDT 24
Finished Mar 21 03:13:32 PM PDT 24
Peak memory 273624 kb
Host smart-4dbd3426-b074-4e42-822d-d0cb2df3d2cb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552246656 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas
h_ctrl_re_evict.552246656
Directory /workspace/3.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_derr.3840184989
Short name T193
Test name
Test status
Simulation time 32326700 ps
CPU time 22.89 seconds
Started Mar 21 03:12:45 PM PDT 24
Finished Mar 21 03:13:09 PM PDT 24
Peak memory 264840 kb
Host smart-272f24fe-879a-40a5-a1aa-73523f82a083
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840184989 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_derr.3840184989
Directory /workspace/3.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_serr.3786264332
Short name T679
Test name
Test status
Simulation time 26625800 ps
CPU time 22.92 seconds
Started Mar 21 03:12:29 PM PDT 24
Finished Mar 21 03:12:52 PM PDT 24
Peak memory 264692 kb
Host smart-a66c9680-5160-480c-9e91-b029731d1aad
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786264332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fl
ash_ctrl_read_word_sweep_serr.3786264332
Directory /workspace/3.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro.4285546630
Short name T617
Test name
Test status
Simulation time 398064000 ps
CPU time 93.56 seconds
Started Mar 21 03:12:36 PM PDT 24
Finished Mar 21 03:14:10 PM PDT 24
Peak memory 281416 kb
Host smart-2f79ccc8-054e-42f3-84e8-5b664d764493
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285546630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.flash_ctrl_ro.4285546630
Directory /workspace/3.flash_ctrl_ro/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw.1420923114
Short name T676
Test name
Test status
Simulation time 3120125900 ps
CPU time 531.74 seconds
Started Mar 21 03:12:34 PM PDT 24
Finished Mar 21 03:21:25 PM PDT 24
Peak memory 314364 kb
Host smart-d8fcb14b-be94-4664-8e7d-9dfc87163fcc
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420923114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ct
rl_rw.1420923114
Directory /workspace/3.flash_ctrl_rw/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict.766092464
Short name T921
Test name
Test status
Simulation time 31479900 ps
CPU time 32.43 seconds
Started Mar 21 03:12:59 PM PDT 24
Finished Mar 21 03:13:32 PM PDT 24
Peak memory 274624 kb
Host smart-08ac0105-cf5a-4058-89a7-650f526fb732
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766092464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas
h_ctrl_rw_evict.766092464
Directory /workspace/3.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_info_access.456115521
Short name T395
Test name
Test status
Simulation time 2060821200 ps
CPU time 76.72 seconds
Started Mar 21 03:12:57 PM PDT 24
Finished Mar 21 03:14:15 PM PDT 24
Peak memory 261452 kb
Host smart-a1fb1d8b-bc36-42f2-ba4d-73e33b6e1e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456115521 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.456115521
Directory /workspace/3.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_address.1858490642
Short name T811
Test name
Test status
Simulation time 1547396300 ps
CPU time 82.24 seconds
Started Mar 21 03:12:43 PM PDT 24
Finished Mar 21 03:14:05 PM PDT 24
Peak memory 265344 kb
Host smart-32b3cae1-b4eb-4483-a10c-2fd7326720ef
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858490642 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_serr_address.1858490642
Directory /workspace/3.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_counter.816555448
Short name T185
Test name
Test status
Simulation time 614419400 ps
CPU time 75.27 seconds
Started Mar 21 03:12:44 PM PDT 24
Finished Mar 21 03:14:00 PM PDT 24
Peak memory 273248 kb
Host smart-feedd0f3-d47b-4e8c-a4ed-f9b16406b22e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816555448 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_serr_counter.816555448
Directory /workspace/3.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke.1109143462
Short name T623
Test name
Test status
Simulation time 16502900 ps
CPU time 54.52 seconds
Started Mar 21 03:12:32 PM PDT 24
Finished Mar 21 03:13:26 PM PDT 24
Peak memory 270680 kb
Host smart-17701ff6-29bd-4864-9e62-8bb903812622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109143462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.1109143462
Directory /workspace/3.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke_hw.1567560271
Short name T705
Test name
Test status
Simulation time 41418000 ps
CPU time 26.58 seconds
Started Mar 21 03:12:31 PM PDT 24
Finished Mar 21 03:12:57 PM PDT 24
Peak memory 259016 kb
Host smart-40e7cd0d-f58f-46ca-afbd-b8e768c73e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567560271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.1567560271
Directory /workspace/3.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/3.flash_ctrl_stress_all.320727634
Short name T116
Test name
Test status
Simulation time 458732800 ps
CPU time 589.21 seconds
Started Mar 21 03:13:01 PM PDT 24
Finished Mar 21 03:22:50 PM PDT 24
Peak memory 282196 kb
Host smart-7a1c110a-3b65-44f7-a6fb-bbeda7ce5ecc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320727634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stress
_all.320727634
Directory /workspace/3.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.flash_ctrl_sw_op.2952911802
Short name T768
Test name
Test status
Simulation time 20740300 ps
CPU time 26.85 seconds
Started Mar 21 03:12:29 PM PDT 24
Finished Mar 21 03:12:56 PM PDT 24
Peak memory 261460 kb
Host smart-123d69e4-1781-4e46-b868-6d2458957cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952911802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.2952911802
Directory /workspace/3.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_wo.396986483
Short name T438
Test name
Test status
Simulation time 9547117600 ps
CPU time 144.8 seconds
Started Mar 21 03:12:31 PM PDT 24
Finished Mar 21 03:14:56 PM PDT 24
Peak memory 259716 kb
Host smart-ae9d9491-b4b4-4e43-8763-ea9725484301
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396986483 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.flash_ctrl_wo.396986483
Directory /workspace/3.flash_ctrl_wo/latest

Test location /workspace/coverage/default/30.flash_ctrl_alert_test.36251927
Short name T1012
Test name
Test status
Simulation time 330093600 ps
CPU time 15.7 seconds
Started Mar 21 03:19:09 PM PDT 24
Finished Mar 21 03:19:25 PM PDT 24
Peak memory 265268 kb
Host smart-4a10c27c-d065-433c-bb69-641c0cc9e995
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36251927 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.36251927
Directory /workspace/30.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.flash_ctrl_connect.3122852382
Short name T484
Test name
Test status
Simulation time 68900100 ps
CPU time 15.85 seconds
Started Mar 21 03:19:06 PM PDT 24
Finished Mar 21 03:19:22 PM PDT 24
Peak memory 275724 kb
Host smart-684d79f0-6eab-4d93-9555-646a9910b21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122852382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.3122852382
Directory /workspace/30.flash_ctrl_connect/latest

Test location /workspace/coverage/default/30.flash_ctrl_disable.600117393
Short name T514
Test name
Test status
Simulation time 39352500 ps
CPU time 22 seconds
Started Mar 21 03:18:46 PM PDT 24
Finished Mar 21 03:19:09 PM PDT 24
Peak memory 273644 kb
Host smart-ef2753b4-be0b-4c02-9a63-26371e33c1a9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600117393 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_disable.600117393
Directory /workspace/30.flash_ctrl_disable/latest

Test location /workspace/coverage/default/30.flash_ctrl_hw_sec_otp.833794160
Short name T1025
Test name
Test status
Simulation time 1562509700 ps
CPU time 114.1 seconds
Started Mar 21 03:18:52 PM PDT 24
Finished Mar 21 03:20:46 PM PDT 24
Peak memory 262428 kb
Host smart-953ce197-3b75-4b38-b469-7f0e7a5b54a0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833794160 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_h
w_sec_otp.833794160
Directory /workspace/30.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd_slow_flash.2349536810
Short name T640
Test name
Test status
Simulation time 14667112700 ps
CPU time 204.88 seconds
Started Mar 21 03:18:47 PM PDT 24
Finished Mar 21 03:22:12 PM PDT 24
Peak memory 284660 kb
Host smart-757b19f1-39a3-41bb-8a9e-453227ce9558
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349536810 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd_slow_flash.2349536810
Directory /workspace/30.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/30.flash_ctrl_otp_reset.1024616300
Short name T69
Test name
Test status
Simulation time 132986100 ps
CPU time 134.27 seconds
Started Mar 21 03:18:47 PM PDT 24
Finished Mar 21 03:21:01 PM PDT 24
Peak memory 259884 kb
Host smart-230e51cf-46a8-47ac-b88f-26fd466f96c5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024616300 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_o
tp_reset.1024616300
Directory /workspace/30.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict.1325172667
Short name T621
Test name
Test status
Simulation time 77715100 ps
CPU time 29.68 seconds
Started Mar 21 03:18:47 PM PDT 24
Finished Mar 21 03:19:17 PM PDT 24
Peak memory 273608 kb
Host smart-e68b0f82-ee27-49c4-9e6d-8e31aa5baca6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325172667 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fl
ash_ctrl_rw_evict.1325172667
Directory /workspace/30.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict_all_en.3215901338
Short name T206
Test name
Test status
Simulation time 33174800 ps
CPU time 30.35 seconds
Started Mar 21 03:18:47 PM PDT 24
Finished Mar 21 03:19:18 PM PDT 24
Peak memory 268500 kb
Host smart-9fb86e93-7af5-4c47-af3e-387aaab93e9a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215901338 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict_all_en.3215901338
Directory /workspace/30.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/30.flash_ctrl_sec_info_access.1986308792
Short name T493
Test name
Test status
Simulation time 2557929300 ps
CPU time 80.09 seconds
Started Mar 21 03:18:46 PM PDT 24
Finished Mar 21 03:20:06 PM PDT 24
Peak memory 262636 kb
Host smart-9a955a7f-88fb-4cef-94c8-8a51bf8aac30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986308792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.1986308792
Directory /workspace/30.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/30.flash_ctrl_smoke.3639221202
Short name T927
Test name
Test status
Simulation time 677068700 ps
CPU time 255.91 seconds
Started Mar 21 03:18:46 PM PDT 24
Finished Mar 21 03:23:02 PM PDT 24
Peak memory 281392 kb
Host smart-52cdce33-0e8d-4c7e-89c2-00c21aae3b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639221202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.3639221202
Directory /workspace/30.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/31.flash_ctrl_alert_test.2524184372
Short name T562
Test name
Test status
Simulation time 54082300 ps
CPU time 14.16 seconds
Started Mar 21 03:19:08 PM PDT 24
Finished Mar 21 03:19:22 PM PDT 24
Peak memory 264652 kb
Host smart-e5bb7c44-32bc-4acf-ad72-9e07cba21591
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524184372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test.
2524184372
Directory /workspace/31.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.flash_ctrl_connect.3490042307
Short name T850
Test name
Test status
Simulation time 16573800 ps
CPU time 15.85 seconds
Started Mar 21 03:19:08 PM PDT 24
Finished Mar 21 03:19:24 PM PDT 24
Peak memory 275704 kb
Host smart-d026f68d-85d2-4805-881e-7dc32e12ff16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490042307 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.3490042307
Directory /workspace/31.flash_ctrl_connect/latest

Test location /workspace/coverage/default/31.flash_ctrl_disable.1765459292
Short name T372
Test name
Test status
Simulation time 11364200 ps
CPU time 22.38 seconds
Started Mar 21 03:19:08 PM PDT 24
Finished Mar 21 03:19:31 PM PDT 24
Peak memory 280784 kb
Host smart-79eb8c9d-3681-4906-b564-a4f6fd651bb8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765459292 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_disable.1765459292
Directory /workspace/31.flash_ctrl_disable/latest

Test location /workspace/coverage/default/31.flash_ctrl_hw_sec_otp.2751233796
Short name T938
Test name
Test status
Simulation time 2112119400 ps
CPU time 43.65 seconds
Started Mar 21 03:19:07 PM PDT 24
Finished Mar 21 03:19:51 PM PDT 24
Peak memory 262552 kb
Host smart-fe7ba0b3-1092-48cd-bd89-930b03c5d2df
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751233796 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_
hw_sec_otp.2751233796
Directory /workspace/31.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd_slow_flash.3871275612
Short name T594
Test name
Test status
Simulation time 11059966200 ps
CPU time 235.99 seconds
Started Mar 21 03:19:09 PM PDT 24
Finished Mar 21 03:23:05 PM PDT 24
Peak memory 284696 kb
Host smart-211a7e1a-96af-41b5-9527-9f730a932484
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871275612 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd_slow_flash.3871275612
Directory /workspace/31.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/31.flash_ctrl_otp_reset.1256051246
Short name T590
Test name
Test status
Simulation time 147092000 ps
CPU time 111.29 seconds
Started Mar 21 03:19:07 PM PDT 24
Finished Mar 21 03:20:59 PM PDT 24
Peak memory 261188 kb
Host smart-21ff64b8-3fa0-49f3-9cc8-bf7bccdd9bb3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256051246 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_o
tp_reset.1256051246
Directory /workspace/31.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict.3465728591
Short name T1043
Test name
Test status
Simulation time 127512100 ps
CPU time 31.28 seconds
Started Mar 21 03:19:08 PM PDT 24
Finished Mar 21 03:19:39 PM PDT 24
Peak memory 273588 kb
Host smart-daf8f86b-c4af-4d86-b08d-8c34a8529c24
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465728591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fl
ash_ctrl_rw_evict.3465728591
Directory /workspace/31.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict_all_en.3765857995
Short name T972
Test name
Test status
Simulation time 43343500 ps
CPU time 31.07 seconds
Started Mar 21 03:19:09 PM PDT 24
Finished Mar 21 03:19:41 PM PDT 24
Peak memory 274572 kb
Host smart-c011d6d4-b52d-4876-9b61-599d7febe07f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765857995 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict_all_en.3765857995
Directory /workspace/31.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/31.flash_ctrl_sec_info_access.2431271214
Short name T780
Test name
Test status
Simulation time 4530933900 ps
CPU time 83.02 seconds
Started Mar 21 03:19:07 PM PDT 24
Finished Mar 21 03:20:31 PM PDT 24
Peak memory 262984 kb
Host smart-221ab0dd-8f8f-4efd-822f-d525984a3bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431271214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.2431271214
Directory /workspace/31.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/31.flash_ctrl_smoke.172126084
Short name T704
Test name
Test status
Simulation time 97238000 ps
CPU time 124.57 seconds
Started Mar 21 03:19:09 PM PDT 24
Finished Mar 21 03:21:13 PM PDT 24
Peak memory 277932 kb
Host smart-b6f95304-adca-4c9f-9013-435c8106f7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172126084 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.172126084
Directory /workspace/31.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/32.flash_ctrl_alert_test.2732709067
Short name T553
Test name
Test status
Simulation time 109510100 ps
CPU time 13.69 seconds
Started Mar 21 03:19:27 PM PDT 24
Finished Mar 21 03:19:40 PM PDT 24
Peak memory 258320 kb
Host smart-fa791d7e-2ba8-4b4d-a977-262a2dd554fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732709067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.
2732709067
Directory /workspace/32.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.flash_ctrl_connect.974646618
Short name T526
Test name
Test status
Simulation time 39887600 ps
CPU time 13.53 seconds
Started Mar 21 03:19:37 PM PDT 24
Finished Mar 21 03:19:51 PM PDT 24
Peak memory 276064 kb
Host smart-ce67f0e1-892e-4cef-81a2-e0b495fd5bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974646618 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.974646618
Directory /workspace/32.flash_ctrl_connect/latest

Test location /workspace/coverage/default/32.flash_ctrl_disable.78648334
Short name T381
Test name
Test status
Simulation time 10367600 ps
CPU time 20.7 seconds
Started Mar 21 03:19:36 PM PDT 24
Finished Mar 21 03:19:59 PM PDT 24
Peak memory 265380 kb
Host smart-ce242ddf-4981-4da0-b0bf-13349082b446
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78648334 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.flash_ctrl_disable.78648334
Directory /workspace/32.flash_ctrl_disable/latest

Test location /workspace/coverage/default/32.flash_ctrl_hw_sec_otp.912830494
Short name T442
Test name
Test status
Simulation time 10640068000 ps
CPU time 107.08 seconds
Started Mar 21 03:19:07 PM PDT 24
Finished Mar 21 03:20:54 PM PDT 24
Peak memory 262568 kb
Host smart-bdc1b69c-4567-4694-ac2f-ab55fbfc7fbb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912830494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_h
w_sec_otp.912830494
Directory /workspace/32.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd_slow_flash.2209000859
Short name T342
Test name
Test status
Simulation time 34589158000 ps
CPU time 209.85 seconds
Started Mar 21 03:19:26 PM PDT 24
Finished Mar 21 03:22:56 PM PDT 24
Peak memory 289760 kb
Host smart-62c0a2fb-7f4c-41bc-bd93-108f3e2accb7
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209000859 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd_slow_flash.2209000859
Directory /workspace/32.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/32.flash_ctrl_otp_reset.1377786596
Short name T1044
Test name
Test status
Simulation time 41978900 ps
CPU time 133.06 seconds
Started Mar 21 03:19:07 PM PDT 24
Finished Mar 21 03:21:20 PM PDT 24
Peak memory 259832 kb
Host smart-1106366c-994e-453d-a950-8f70cd39d899
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377786596 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_o
tp_reset.1377786596
Directory /workspace/32.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict.303835825
Short name T920
Test name
Test status
Simulation time 326808500 ps
CPU time 34.78 seconds
Started Mar 21 03:19:28 PM PDT 24
Finished Mar 21 03:20:03 PM PDT 24
Peak memory 274588 kb
Host smart-4bfefa2a-48fb-48b4-8073-5bc46bde6c18
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303835825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fla
sh_ctrl_rw_evict.303835825
Directory /workspace/32.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict_all_en.2395253302
Short name T217
Test name
Test status
Simulation time 89075300 ps
CPU time 31.66 seconds
Started Mar 21 03:19:27 PM PDT 24
Finished Mar 21 03:19:59 PM PDT 24
Peak memory 267428 kb
Host smart-531a7ff1-c495-400f-8ea9-1515cd52f718
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395253302 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict_all_en.2395253302
Directory /workspace/32.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/32.flash_ctrl_smoke.1033588047
Short name T494
Test name
Test status
Simulation time 130977600 ps
CPU time 123.46 seconds
Started Mar 21 03:19:07 PM PDT 24
Finished Mar 21 03:21:11 PM PDT 24
Peak memory 276908 kb
Host smart-222b4639-0ff1-4506-9ccc-c2d88363e99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033588047 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.1033588047
Directory /workspace/32.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/33.flash_ctrl_alert_test.161546015
Short name T89
Test name
Test status
Simulation time 67424100 ps
CPU time 13.84 seconds
Started Mar 21 03:19:25 PM PDT 24
Finished Mar 21 03:19:39 PM PDT 24
Peak memory 258296 kb
Host smart-91ecb3f2-d866-47d8-97b1-d1022a22abca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161546015 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test.161546015
Directory /workspace/33.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.flash_ctrl_connect.2707743602
Short name T824
Test name
Test status
Simulation time 19559700 ps
CPU time 15.84 seconds
Started Mar 21 03:19:34 PM PDT 24
Finished Mar 21 03:19:51 PM PDT 24
Peak memory 275828 kb
Host smart-d35125b5-c229-40ce-8638-6f248be25d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707743602 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.2707743602
Directory /workspace/33.flash_ctrl_connect/latest

Test location /workspace/coverage/default/33.flash_ctrl_disable.3881187177
Short name T225
Test name
Test status
Simulation time 14038900 ps
CPU time 21.82 seconds
Started Mar 21 03:19:26 PM PDT 24
Finished Mar 21 03:19:48 PM PDT 24
Peak memory 273556 kb
Host smart-43ad5ed1-8e21-4ea3-b33c-78527f2a5e3f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881187177 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.flash_ctrl_disable.3881187177
Directory /workspace/33.flash_ctrl_disable/latest

Test location /workspace/coverage/default/33.flash_ctrl_hw_sec_otp.4115115989
Short name T591
Test name
Test status
Simulation time 4584419000 ps
CPU time 127.65 seconds
Started Mar 21 03:19:29 PM PDT 24
Finished Mar 21 03:21:38 PM PDT 24
Peak memory 262516 kb
Host smart-ddabd7a6-9b41-4cb8-989e-02499581ae5d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115115989 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_
hw_sec_otp.4115115989
Directory /workspace/33.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd_slow_flash.3246877996
Short name T853
Test name
Test status
Simulation time 16540479700 ps
CPU time 204.56 seconds
Started Mar 21 03:19:27 PM PDT 24
Finished Mar 21 03:22:51 PM PDT 24
Peak memory 289860 kb
Host smart-9c8b85e6-10bc-4605-a1c5-e4691ddfb11f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246877996 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd_slow_flash.3246877996
Directory /workspace/33.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/33.flash_ctrl_otp_reset.1802802280
Short name T690
Test name
Test status
Simulation time 118179300 ps
CPU time 111.53 seconds
Started Mar 21 03:19:36 PM PDT 24
Finished Mar 21 03:21:28 PM PDT 24
Peak memory 259892 kb
Host smart-5df8a90c-806b-4088-a8b4-20ee27c04351
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802802280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_o
tp_reset.1802802280
Directory /workspace/33.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict.1500844276
Short name T947
Test name
Test status
Simulation time 87532800 ps
CPU time 31.64 seconds
Started Mar 21 03:19:26 PM PDT 24
Finished Mar 21 03:19:58 PM PDT 24
Peak memory 273556 kb
Host smart-86935b23-3682-4781-a584-64f278d7290e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500844276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fl
ash_ctrl_rw_evict.1500844276
Directory /workspace/33.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict_all_en.1422019995
Short name T998
Test name
Test status
Simulation time 103041200 ps
CPU time 30.77 seconds
Started Mar 21 03:19:27 PM PDT 24
Finished Mar 21 03:19:58 PM PDT 24
Peak memory 273572 kb
Host smart-adcd797b-da1d-4983-a374-d085118d3a88
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422019995 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict_all_en.1422019995
Directory /workspace/33.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/33.flash_ctrl_sec_info_access.2634291839
Short name T396
Test name
Test status
Simulation time 1014591200 ps
CPU time 66.53 seconds
Started Mar 21 03:19:25 PM PDT 24
Finished Mar 21 03:20:32 PM PDT 24
Peak memory 262480 kb
Host smart-0f9cc4c1-fc52-4f61-86e3-910af3eaef85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634291839 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.2634291839
Directory /workspace/33.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/33.flash_ctrl_smoke.602313309
Short name T420
Test name
Test status
Simulation time 22390100 ps
CPU time 51.96 seconds
Started Mar 21 03:19:27 PM PDT 24
Finished Mar 21 03:20:19 PM PDT 24
Peak memory 270592 kb
Host smart-24829bfb-940f-41ec-ab2f-120e36e27e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602313309 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.602313309
Directory /workspace/33.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/34.flash_ctrl_alert_test.1709046135
Short name T405
Test name
Test status
Simulation time 43156400 ps
CPU time 13.63 seconds
Started Mar 21 03:19:27 PM PDT 24
Finished Mar 21 03:19:41 PM PDT 24
Peak memory 265276 kb
Host smart-18b0b17b-c167-410c-89c7-19c58d7a37d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709046135 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.
1709046135
Directory /workspace/34.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.flash_ctrl_connect.4189821386
Short name T675
Test name
Test status
Simulation time 48676400 ps
CPU time 13.81 seconds
Started Mar 21 03:19:25 PM PDT 24
Finished Mar 21 03:19:39 PM PDT 24
Peak memory 275656 kb
Host smart-45d08b5c-753a-4ae6-9401-42cacf0fb50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189821386 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.4189821386
Directory /workspace/34.flash_ctrl_connect/latest

Test location /workspace/coverage/default/34.flash_ctrl_disable.3842841566
Short name T530
Test name
Test status
Simulation time 34265000 ps
CPU time 22 seconds
Started Mar 21 03:19:37 PM PDT 24
Finished Mar 21 03:20:00 PM PDT 24
Peak memory 273624 kb
Host smart-1efe93db-f028-4e15-a287-2e0a6e061db7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842841566 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_disable.3842841566
Directory /workspace/34.flash_ctrl_disable/latest

Test location /workspace/coverage/default/34.flash_ctrl_hw_sec_otp.1856984290
Short name T450
Test name
Test status
Simulation time 1667250400 ps
CPU time 50.51 seconds
Started Mar 21 03:19:28 PM PDT 24
Finished Mar 21 03:20:18 PM PDT 24
Peak memory 262548 kb
Host smart-1751e030-9d55-47b9-889b-be38b9476aba
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856984290 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_
hw_sec_otp.1856984290
Directory /workspace/34.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd_slow_flash.3201167467
Short name T969
Test name
Test status
Simulation time 16843247900 ps
CPU time 191.27 seconds
Started Mar 21 03:19:27 PM PDT 24
Finished Mar 21 03:22:38 PM PDT 24
Peak memory 290788 kb
Host smart-6cbb1cf1-b181-41cb-b84b-daed88ce52f7
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201167467 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd_slow_flash.3201167467
Directory /workspace/34.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/34.flash_ctrl_otp_reset.776020403
Short name T857
Test name
Test status
Simulation time 221945300 ps
CPU time 132.14 seconds
Started Mar 21 03:19:27 PM PDT 24
Finished Mar 21 03:21:39 PM PDT 24
Peak memory 260132 kb
Host smart-606d3ab1-5a56-4ce3-b227-83d588e8b665
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776020403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_ot
p_reset.776020403
Directory /workspace/34.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict.2007643032
Short name T737
Test name
Test status
Simulation time 180468100 ps
CPU time 33.33 seconds
Started Mar 21 03:19:27 PM PDT 24
Finished Mar 21 03:20:00 PM PDT 24
Peak memory 273544 kb
Host smart-edd5b4d5-7485-4280-a9ab-8661eda02997
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007643032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fl
ash_ctrl_rw_evict.2007643032
Directory /workspace/34.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/34.flash_ctrl_sec_info_access.617558495
Short name T629
Test name
Test status
Simulation time 1579529300 ps
CPU time 75.75 seconds
Started Mar 21 03:19:27 PM PDT 24
Finished Mar 21 03:20:43 PM PDT 24
Peak memory 263288 kb
Host smart-e2f4321d-d9e8-4285-bfc2-585729f4859f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617558495 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.617558495
Directory /workspace/34.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/34.flash_ctrl_smoke.1429506842
Short name T934
Test name
Test status
Simulation time 48228600 ps
CPU time 219.99 seconds
Started Mar 21 03:19:29 PM PDT 24
Finished Mar 21 03:23:09 PM PDT 24
Peak memory 280156 kb
Host smart-477c6fb3-0c9e-4b19-b3e7-83e04ceb9611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429506842 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.1429506842
Directory /workspace/34.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/35.flash_ctrl_alert_test.2651874039
Short name T788
Test name
Test status
Simulation time 117014100 ps
CPU time 13.67 seconds
Started Mar 21 03:19:27 PM PDT 24
Finished Mar 21 03:19:41 PM PDT 24
Peak memory 258300 kb
Host smart-d592847f-97e3-44c8-b958-5281c6bf8344
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651874039 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test.
2651874039
Directory /workspace/35.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.flash_ctrl_connect.1087149359
Short name T965
Test name
Test status
Simulation time 44884300 ps
CPU time 13.24 seconds
Started Mar 21 03:19:28 PM PDT 24
Finished Mar 21 03:19:42 PM PDT 24
Peak memory 275076 kb
Host smart-d9bac29b-8983-46f4-b507-987c4eaf81a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087149359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.1087149359
Directory /workspace/35.flash_ctrl_connect/latest

Test location /workspace/coverage/default/35.flash_ctrl_disable.309563141
Short name T52
Test name
Test status
Simulation time 101170400 ps
CPU time 22.23 seconds
Started Mar 21 03:19:27 PM PDT 24
Finished Mar 21 03:19:49 PM PDT 24
Peak memory 273560 kb
Host smart-1e0bd012-d4ac-4af7-ad4b-efcd3e2ff8ae
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309563141 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.flash_ctrl_disable.309563141
Directory /workspace/35.flash_ctrl_disable/latest

Test location /workspace/coverage/default/35.flash_ctrl_hw_sec_otp.542942698
Short name T451
Test name
Test status
Simulation time 4881472000 ps
CPU time 82.8 seconds
Started Mar 21 03:19:26 PM PDT 24
Finished Mar 21 03:20:49 PM PDT 24
Peak memory 261952 kb
Host smart-e79e5eb1-c6f2-48af-a885-39e7eaced394
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542942698 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_h
w_sec_otp.542942698
Directory /workspace/35.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd_slow_flash.3685478141
Short name T30
Test name
Test status
Simulation time 33549282700 ps
CPU time 251.61 seconds
Started Mar 21 03:19:37 PM PDT 24
Finished Mar 21 03:23:50 PM PDT 24
Peak memory 289868 kb
Host smart-e5f42261-809b-43be-88dc-35a0872d59f8
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685478141 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd_slow_flash.3685478141
Directory /workspace/35.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/35.flash_ctrl_otp_reset.2599688670
Short name T138
Test name
Test status
Simulation time 37900300 ps
CPU time 132.34 seconds
Started Mar 21 03:19:33 PM PDT 24
Finished Mar 21 03:21:46 PM PDT 24
Peak memory 260872 kb
Host smart-44fcf241-60ea-42c7-87ac-3c8ab0860d10
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599688670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_o
tp_reset.2599688670
Directory /workspace/35.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict.3249478491
Short name T192
Test name
Test status
Simulation time 65232900 ps
CPU time 31.17 seconds
Started Mar 21 03:19:33 PM PDT 24
Finished Mar 21 03:20:05 PM PDT 24
Peak memory 273608 kb
Host smart-081d0617-df95-4053-afc8-60d6dc802b11
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249478491 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fl
ash_ctrl_rw_evict.3249478491
Directory /workspace/35.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict_all_en.1453045002
Short name T216
Test name
Test status
Simulation time 39658900 ps
CPU time 29.1 seconds
Started Mar 21 03:19:26 PM PDT 24
Finished Mar 21 03:19:55 PM PDT 24
Peak memory 273584 kb
Host smart-d218b82e-bdd0-4467-9ff0-28f4b9ceba35
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453045002 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.flash_ctrl_rw_evict_all_en.1453045002
Directory /workspace/35.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/35.flash_ctrl_smoke.4266076336
Short name T329
Test name
Test status
Simulation time 23487000 ps
CPU time 52.37 seconds
Started Mar 21 03:19:28 PM PDT 24
Finished Mar 21 03:20:21 PM PDT 24
Peak memory 271856 kb
Host smart-f3319caf-9c66-4bbe-9056-3a7996eec5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266076336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.4266076336
Directory /workspace/35.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/36.flash_ctrl_alert_test.2790929011
Short name T406
Test name
Test status
Simulation time 87199200 ps
CPU time 13.53 seconds
Started Mar 21 03:19:39 PM PDT 24
Finished Mar 21 03:19:53 PM PDT 24
Peak memory 258168 kb
Host smart-2432fe45-544a-4b32-8dd6-86e0dcc6498c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790929011 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.
2790929011
Directory /workspace/36.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.flash_ctrl_connect.42145462
Short name T498
Test name
Test status
Simulation time 116638300 ps
CPU time 16.03 seconds
Started Mar 21 03:19:40 PM PDT 24
Finished Mar 21 03:19:56 PM PDT 24
Peak memory 274468 kb
Host smart-59e7b180-704d-4bfa-b14c-716eb077d875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42145462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.42145462
Directory /workspace/36.flash_ctrl_connect/latest

Test location /workspace/coverage/default/36.flash_ctrl_disable.3445668881
Short name T168
Test name
Test status
Simulation time 43042700 ps
CPU time 22.35 seconds
Started Mar 21 03:19:38 PM PDT 24
Finished Mar 21 03:20:01 PM PDT 24
Peak memory 265220 kb
Host smart-dfcbc7bd-52eb-4196-859c-b26c299d063a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445668881 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_disable.3445668881
Directory /workspace/36.flash_ctrl_disable/latest

Test location /workspace/coverage/default/36.flash_ctrl_hw_sec_otp.1577788723
Short name T657
Test name
Test status
Simulation time 78744467000 ps
CPU time 145.81 seconds
Started Mar 21 03:19:35 PM PDT 24
Finished Mar 21 03:22:01 PM PDT 24
Peak memory 262416 kb
Host smart-1e7f5271-9978-452a-a5bb-3a752cb3b56c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577788723 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_
hw_sec_otp.1577788723
Directory /workspace/36.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.2606009878
Short name T347
Test name
Test status
Simulation time 33637649900 ps
CPU time 224.51 seconds
Started Mar 21 03:19:29 PM PDT 24
Finished Mar 21 03:23:15 PM PDT 24
Peak memory 289796 kb
Host smart-db7d8291-6d1a-4375-947a-f7940f770a17
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606009878 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd_slow_flash.2606009878
Directory /workspace/36.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/36.flash_ctrl_otp_reset.1411635683
Short name T686
Test name
Test status
Simulation time 125377300 ps
CPU time 135.85 seconds
Started Mar 21 03:19:26 PM PDT 24
Finished Mar 21 03:21:42 PM PDT 24
Peak memory 259760 kb
Host smart-f7f19246-e0e8-49b5-8749-71b166b7b041
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411635683 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_o
tp_reset.1411635683
Directory /workspace/36.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict.2559311913
Short name T531
Test name
Test status
Simulation time 32169600 ps
CPU time 28.39 seconds
Started Mar 21 03:19:33 PM PDT 24
Finished Mar 21 03:20:02 PM PDT 24
Peak memory 266440 kb
Host smart-59b8d4a9-e802-40e7-9b5e-61346f20b3ee
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559311913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fl
ash_ctrl_rw_evict.2559311913
Directory /workspace/36.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict_all_en.1005198566
Short name T915
Test name
Test status
Simulation time 35230300 ps
CPU time 32.26 seconds
Started Mar 21 03:19:29 PM PDT 24
Finished Mar 21 03:20:03 PM PDT 24
Peak memory 273532 kb
Host smart-b39359b6-8492-4889-b273-f9c48c9253c7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005198566 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict_all_en.1005198566
Directory /workspace/36.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/36.flash_ctrl_smoke.1880479179
Short name T512
Test name
Test status
Simulation time 79600200 ps
CPU time 126.33 seconds
Started Mar 21 03:19:27 PM PDT 24
Finished Mar 21 03:21:33 PM PDT 24
Peak memory 277304 kb
Host smart-755cc3e4-99d2-4f14-b67c-1dba697d3248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880479179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.1880479179
Directory /workspace/36.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/37.flash_ctrl_alert_test.4106488353
Short name T181
Test name
Test status
Simulation time 87360000 ps
CPU time 14.22 seconds
Started Mar 21 03:19:40 PM PDT 24
Finished Mar 21 03:19:54 PM PDT 24
Peak memory 258356 kb
Host smart-8f50734d-eea4-4809-892b-398f9e902d3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106488353 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test.
4106488353
Directory /workspace/37.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.flash_ctrl_connect.902789700
Short name T953
Test name
Test status
Simulation time 14524800 ps
CPU time 13.7 seconds
Started Mar 21 03:19:37 PM PDT 24
Finished Mar 21 03:19:52 PM PDT 24
Peak memory 275952 kb
Host smart-dadf7399-ac54-4e6e-8d32-ea33f4568893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902789700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.902789700
Directory /workspace/37.flash_ctrl_connect/latest

Test location /workspace/coverage/default/37.flash_ctrl_disable.3622823413
Short name T992
Test name
Test status
Simulation time 12973300 ps
CPU time 20.61 seconds
Started Mar 21 03:19:40 PM PDT 24
Finished Mar 21 03:20:01 PM PDT 24
Peak memory 273564 kb
Host smart-9a455ebc-86d4-4764-b611-4fbd38387e6b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622823413 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_disable.3622823413
Directory /workspace/37.flash_ctrl_disable/latest

Test location /workspace/coverage/default/37.flash_ctrl_hw_sec_otp.2230428659
Short name T660
Test name
Test status
Simulation time 1157972600 ps
CPU time 69.1 seconds
Started Mar 21 03:19:40 PM PDT 24
Finished Mar 21 03:20:49 PM PDT 24
Peak memory 262592 kb
Host smart-5b12265a-78a0-4e3e-88ec-f6334f98211e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230428659 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_
hw_sec_otp.2230428659
Directory /workspace/37.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/37.flash_ctrl_otp_reset.1909817394
Short name T993
Test name
Test status
Simulation time 41901500 ps
CPU time 136.43 seconds
Started Mar 21 03:19:36 PM PDT 24
Finished Mar 21 03:21:53 PM PDT 24
Peak memory 261184 kb
Host smart-3a485b2e-3821-4860-b4e8-91cd5876746e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909817394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_o
tp_reset.1909817394
Directory /workspace/37.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict.1255277594
Short name T755
Test name
Test status
Simulation time 29318800 ps
CPU time 32.46 seconds
Started Mar 21 03:19:37 PM PDT 24
Finished Mar 21 03:20:10 PM PDT 24
Peak memory 274544 kb
Host smart-f4040e9a-b32b-4317-9d5c-46fd63d24bb1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255277594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fl
ash_ctrl_rw_evict.1255277594
Directory /workspace/37.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict_all_en.2294413175
Short name T653
Test name
Test status
Simulation time 33861700 ps
CPU time 32.36 seconds
Started Mar 21 03:19:44 PM PDT 24
Finished Mar 21 03:20:17 PM PDT 24
Peak memory 277012 kb
Host smart-af13f338-742b-4676-b6d1-7ef5c93cbea8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294413175 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict_all_en.2294413175
Directory /workspace/37.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/37.flash_ctrl_sec_info_access.1524650823
Short name T1011
Test name
Test status
Simulation time 4657726300 ps
CPU time 74.06 seconds
Started Mar 21 03:19:39 PM PDT 24
Finished Mar 21 03:20:53 PM PDT 24
Peak memory 263260 kb
Host smart-333df5b6-6b69-4fd2-944f-97fd71f25a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524650823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.1524650823
Directory /workspace/37.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/37.flash_ctrl_smoke.955267210
Short name T1026
Test name
Test status
Simulation time 51965700 ps
CPU time 148.23 seconds
Started Mar 21 03:19:44 PM PDT 24
Finished Mar 21 03:22:13 PM PDT 24
Peak memory 276316 kb
Host smart-5d2a3f52-98c4-4c96-a367-320db4790e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955267210 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.955267210
Directory /workspace/37.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/38.flash_ctrl_alert_test.3146262840
Short name T407
Test name
Test status
Simulation time 22405400 ps
CPU time 13.4 seconds
Started Mar 21 03:19:40 PM PDT 24
Finished Mar 21 03:19:54 PM PDT 24
Peak memory 264496 kb
Host smart-bfcb912d-88c8-4f1c-abb7-7e5e5225dadf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146262840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test.
3146262840
Directory /workspace/38.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.flash_ctrl_connect.1717262007
Short name T311
Test name
Test status
Simulation time 32785200 ps
CPU time 13.74 seconds
Started Mar 21 03:19:39 PM PDT 24
Finished Mar 21 03:19:53 PM PDT 24
Peak memory 275064 kb
Host smart-f00acd94-848e-4def-9bf8-2a8f7ed73262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717262007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.1717262007
Directory /workspace/38.flash_ctrl_connect/latest

Test location /workspace/coverage/default/38.flash_ctrl_disable.111254813
Short name T710
Test name
Test status
Simulation time 13468700 ps
CPU time 22.36 seconds
Started Mar 21 03:19:40 PM PDT 24
Finished Mar 21 03:20:02 PM PDT 24
Peak memory 265360 kb
Host smart-04684837-827e-46e0-b492-b863a8a1f900
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111254813 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.flash_ctrl_disable.111254813
Directory /workspace/38.flash_ctrl_disable/latest

Test location /workspace/coverage/default/38.flash_ctrl_hw_sec_otp.144151105
Short name T325
Test name
Test status
Simulation time 3778512900 ps
CPU time 84.7 seconds
Started Mar 21 03:19:41 PM PDT 24
Finished Mar 21 03:21:07 PM PDT 24
Peak memory 262592 kb
Host smart-9792dfb6-0be1-49b6-b303-7f8f8b784233
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144151105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_h
w_sec_otp.144151105
Directory /workspace/38.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd_slow_flash.1424970596
Short name T968
Test name
Test status
Simulation time 149800221500 ps
CPU time 261.79 seconds
Started Mar 21 03:19:40 PM PDT 24
Finished Mar 21 03:24:02 PM PDT 24
Peak memory 284656 kb
Host smart-e80defc1-fdb4-4f5e-acde-47d881829b0c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424970596 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd_slow_flash.1424970596
Directory /workspace/38.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict.4028042306
Short name T681
Test name
Test status
Simulation time 45238100 ps
CPU time 31.06 seconds
Started Mar 21 03:19:40 PM PDT 24
Finished Mar 21 03:20:12 PM PDT 24
Peak memory 273580 kb
Host smart-eae524c1-ed87-46fc-a0db-1f044ae8d0a2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028042306 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fl
ash_ctrl_rw_evict.4028042306
Directory /workspace/38.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict_all_en.2694620804
Short name T626
Test name
Test status
Simulation time 31366400 ps
CPU time 29.23 seconds
Started Mar 21 03:19:40 PM PDT 24
Finished Mar 21 03:20:10 PM PDT 24
Peak memory 274628 kb
Host smart-622ce778-3cac-4ef2-9d61-fb7d2f3a6c45
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694620804 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict_all_en.2694620804
Directory /workspace/38.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/38.flash_ctrl_sec_info_access.266907158
Short name T385
Test name
Test status
Simulation time 1738193200 ps
CPU time 76.68 seconds
Started Mar 21 03:19:41 PM PDT 24
Finished Mar 21 03:20:59 PM PDT 24
Peak memory 263260 kb
Host smart-5962e37a-dc44-4fcc-be84-2dfd9be25290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266907158 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.266907158
Directory /workspace/38.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/38.flash_ctrl_smoke.2370707113
Short name T416
Test name
Test status
Simulation time 104972800 ps
CPU time 224.63 seconds
Started Mar 21 03:19:37 PM PDT 24
Finished Mar 21 03:23:23 PM PDT 24
Peak memory 280672 kb
Host smart-cec83316-592f-46cd-be03-756472a214d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370707113 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.2370707113
Directory /workspace/38.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/39.flash_ctrl_alert_test.3065409976
Short name T637
Test name
Test status
Simulation time 193157000 ps
CPU time 13.93 seconds
Started Mar 21 03:19:40 PM PDT 24
Finished Mar 21 03:19:54 PM PDT 24
Peak memory 258364 kb
Host smart-bbe3f2a0-ac2f-41e3-81cc-e0e64bfeee4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065409976 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test.
3065409976
Directory /workspace/39.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.flash_ctrl_connect.1230828441
Short name T316
Test name
Test status
Simulation time 16416300 ps
CPU time 15.79 seconds
Started Mar 21 03:19:44 PM PDT 24
Finished Mar 21 03:20:00 PM PDT 24
Peak memory 276096 kb
Host smart-79239c65-76d7-43ca-b551-61c1d63772a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230828441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.1230828441
Directory /workspace/39.flash_ctrl_connect/latest

Test location /workspace/coverage/default/39.flash_ctrl_disable.2007895045
Short name T721
Test name
Test status
Simulation time 110008900 ps
CPU time 21.26 seconds
Started Mar 21 03:19:39 PM PDT 24
Finished Mar 21 03:20:01 PM PDT 24
Peak memory 265284 kb
Host smart-2b4ec6e8-507d-454a-bfe3-0358edd58ddd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007895045 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_disable.2007895045
Directory /workspace/39.flash_ctrl_disable/latest

Test location /workspace/coverage/default/39.flash_ctrl_hw_sec_otp.420102557
Short name T719
Test name
Test status
Simulation time 12396793200 ps
CPU time 225.49 seconds
Started Mar 21 03:19:40 PM PDT 24
Finished Mar 21 03:23:26 PM PDT 24
Peak memory 262556 kb
Host smart-449df057-cc4d-4417-b32d-ea90673014f2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420102557 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_h
w_sec_otp.420102557
Directory /workspace/39.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd_slow_flash.2304827406
Short name T720
Test name
Test status
Simulation time 9250415800 ps
CPU time 244.57 seconds
Started Mar 21 03:19:41 PM PDT 24
Finished Mar 21 03:23:45 PM PDT 24
Peak memory 284684 kb
Host smart-e8956693-5e5f-4685-a860-cd8edf9eb6bd
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304827406 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd_slow_flash.2304827406
Directory /workspace/39.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/39.flash_ctrl_otp_reset.3008429407
Short name T555
Test name
Test status
Simulation time 110453400 ps
CPU time 132.92 seconds
Started Mar 21 03:19:37 PM PDT 24
Finished Mar 21 03:21:51 PM PDT 24
Peak memory 259788 kb
Host smart-9a106b85-16b0-41ab-b5e9-1a03bc525bc7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008429407 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_o
tp_reset.3008429407
Directory /workspace/39.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict.1550067893
Short name T35
Test name
Test status
Simulation time 28737000 ps
CPU time 31.88 seconds
Started Mar 21 03:19:37 PM PDT 24
Finished Mar 21 03:20:10 PM PDT 24
Peak memory 273552 kb
Host smart-598c6b39-9cc7-4d89-8437-6e5477a2f2c7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550067893 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fl
ash_ctrl_rw_evict.1550067893
Directory /workspace/39.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict_all_en.1821411393
Short name T49
Test name
Test status
Simulation time 113107100 ps
CPU time 31.35 seconds
Started Mar 21 03:19:41 PM PDT 24
Finished Mar 21 03:20:13 PM PDT 24
Peak memory 273584 kb
Host smart-ab5a2ffc-4b6e-4a4d-8017-12f529b5122a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821411393 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict_all_en.1821411393
Directory /workspace/39.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/39.flash_ctrl_sec_info_access.145123306
Short name T815
Test name
Test status
Simulation time 5710271500 ps
CPU time 78.92 seconds
Started Mar 21 03:19:41 PM PDT 24
Finished Mar 21 03:21:00 PM PDT 24
Peak memory 263024 kb
Host smart-6fa8ae61-99ee-47b7-9cb2-280a2d7a72ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145123306 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.145123306
Directory /workspace/39.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/39.flash_ctrl_smoke.773958448
Short name T912
Test name
Test status
Simulation time 45886700 ps
CPU time 100.51 seconds
Started Mar 21 03:19:40 PM PDT 24
Finished Mar 21 03:21:21 PM PDT 24
Peak memory 276596 kb
Host smart-106d4ae7-aa89-4e67-b933-753ee2b1d827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773958448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.773958448
Directory /workspace/39.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_alert_test.2290068631
Short name T315
Test name
Test status
Simulation time 108312400 ps
CPU time 13.76 seconds
Started Mar 21 03:13:31 PM PDT 24
Finished Mar 21 03:13:47 PM PDT 24
Peak memory 258280 kb
Host smart-0c82cf43-de4c-426c-bf56-bf4300042500
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290068631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.2
290068631
Directory /workspace/4.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.flash_ctrl_config_regwen.2281628124
Short name T265
Test name
Test status
Simulation time 62592000 ps
CPU time 14.12 seconds
Started Mar 21 03:13:30 PM PDT 24
Finished Mar 21 03:13:45 PM PDT 24
Peak memory 261996 kb
Host smart-2d201e13-808b-40f5-bad7-f12c3e321aac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281628124 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.flash_ctrl_config_regwen.2281628124
Directory /workspace/4.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.flash_ctrl_connect.3494953800
Short name T964
Test name
Test status
Simulation time 50252300 ps
CPU time 15.92 seconds
Started Mar 21 03:13:21 PM PDT 24
Finished Mar 21 03:13:37 PM PDT 24
Peak memory 275728 kb
Host smart-140d0278-e4c6-44f6-80c5-1952de77f220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494953800 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.3494953800
Directory /workspace/4.flash_ctrl_connect/latest

Test location /workspace/coverage/default/4.flash_ctrl_disable.3427997283
Short name T71
Test name
Test status
Simulation time 28050200 ps
CPU time 22.29 seconds
Started Mar 21 03:13:20 PM PDT 24
Finished Mar 21 03:13:43 PM PDT 24
Peak memory 273528 kb
Host smart-9e86ddc7-c7db-4e8b-a4fa-1b23cdf1758a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427997283 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_disable.3427997283
Directory /workspace/4.flash_ctrl_disable/latest

Test location /workspace/coverage/default/4.flash_ctrl_erase_suspend.2097883483
Short name T977
Test name
Test status
Simulation time 3846927700 ps
CPU time 431.76 seconds
Started Mar 21 03:13:10 PM PDT 24
Finished Mar 21 03:20:22 PM PDT 24
Peak memory 263084 kb
Host smart-2e069661-c3ac-46ca-b0a4-e342e13228a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2097883483 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.2097883483
Directory /workspace/4.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_mp.1638783069
Short name T233
Test name
Test status
Simulation time 4571486400 ps
CPU time 2293.1 seconds
Started Mar 21 03:13:10 PM PDT 24
Finished Mar 21 03:51:24 PM PDT 24
Peak memory 265204 kb
Host smart-3131f3c1-14e8-4b56-898a-651e179d2e9b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638783069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_err
or_mp.1638783069
Directory /workspace/4.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_type.4114610077
Short name T988
Test name
Test status
Simulation time 691067500 ps
CPU time 1942.31 seconds
Started Mar 21 03:13:10 PM PDT 24
Finished Mar 21 03:45:33 PM PDT 24
Peak memory 265228 kb
Host smart-b6f403c9-06d2-4598-8548-4795468d7ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114610077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_type.4114610077
Directory /workspace/4.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_win.2986878757
Short name T890
Test name
Test status
Simulation time 3037443700 ps
CPU time 1020.84 seconds
Started Mar 21 03:13:11 PM PDT 24
Finished Mar 21 03:30:12 PM PDT 24
Peak memory 273352 kb
Host smart-497db58e-55af-4af8-bc76-aa376d8937af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986878757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.2986878757
Directory /workspace/4.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/4.flash_ctrl_fetch_code.332553880
Short name T538
Test name
Test status
Simulation time 131815700 ps
CPU time 23.12 seconds
Started Mar 21 03:13:12 PM PDT 24
Finished Mar 21 03:13:35 PM PDT 24
Peak memory 265240 kb
Host smart-a3167888-c1fd-4a83-abc3-c472413a5816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332553880 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetch_code.332553880
Directory /workspace/4.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/4.flash_ctrl_fs_sup.1444816141
Short name T288
Test name
Test status
Simulation time 4472716000 ps
CPU time 37.37 seconds
Started Mar 21 03:13:31 PM PDT 24
Finished Mar 21 03:14:10 PM PDT 24
Peak memory 273488 kb
Host smart-24b58094-ece7-4ced-a470-9044c27a7162
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444816141 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.flash_ctrl_fs_sup.1444816141
Directory /workspace/4.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/4.flash_ctrl_full_mem_access.2733095574
Short name T954
Test name
Test status
Simulation time 195641643100 ps
CPU time 4458.36 seconds
Started Mar 21 03:13:09 PM PDT 24
Finished Mar 21 04:27:28 PM PDT 24
Peak memory 265112 kb
Host smart-6f2ae234-e0e4-4ea4-902c-11b10498c3f4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733095574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_c
trl_full_mem_access.2733095574
Directory /workspace/4.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_dir_rd.1132246575
Short name T885
Test name
Test status
Simulation time 117242100 ps
CPU time 92.95 seconds
Started Mar 21 03:13:11 PM PDT 24
Finished Mar 21 03:14:44 PM PDT 24
Peak memory 262572 kb
Host smart-fd607995-9268-43da-a938-a061de92b75f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1132246575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.1132246575
Directory /workspace/4.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.1583678851
Short name T963
Test name
Test status
Simulation time 10012465700 ps
CPU time 346.62 seconds
Started Mar 21 03:13:32 PM PDT 24
Finished Mar 21 03:19:21 PM PDT 24
Peak memory 336208 kb
Host smart-2f739907-9167-42b7-a064-9467c4c12ed6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583678851 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.1583678851
Directory /workspace/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_read_seed_err.395588640
Short name T291
Test name
Test status
Simulation time 15301700 ps
CPU time 13.44 seconds
Started Mar 21 03:13:30 PM PDT 24
Finished Mar 21 03:13:44 PM PDT 24
Peak memory 259264 kb
Host smart-d1b6c077-9e43-4ff7-959e-fa0815c17c54
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395588640 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_seed_err.395588640
Directory /workspace/4.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_rma_reset.2111919308
Short name T769
Test name
Test status
Simulation time 160166642200 ps
CPU time 998.29 seconds
Started Mar 21 03:13:10 PM PDT 24
Finished Mar 21 03:29:48 PM PDT 24
Peak memory 263464 kb
Host smart-52ac46a5-6ea6-4528-a686-5e90d3397f73
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111919308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.flash_ctrl_hw_rma_reset.2111919308
Directory /workspace/4.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_sec_otp.2490323061
Short name T625
Test name
Test status
Simulation time 1169603100 ps
CPU time 61.07 seconds
Started Mar 21 03:13:09 PM PDT 24
Finished Mar 21 03:14:10 PM PDT 24
Peak memory 262588 kb
Host smart-6a3748ab-6150-4b6c-ae32-f3942943e5ea
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490323061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_h
w_sec_otp.2490323061
Directory /workspace/4.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd_slow_flash.4269385460
Short name T343
Test name
Test status
Simulation time 51028855700 ps
CPU time 212.4 seconds
Started Mar 21 03:13:27 PM PDT 24
Finished Mar 21 03:17:00 PM PDT 24
Peak memory 293952 kb
Host smart-2346412b-cee1-46ec-925d-931dc3ac5717
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269385460 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd_slow_flash.4269385460
Directory /workspace/4.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr.1298041892
Short name T891
Test name
Test status
Simulation time 8444255500 ps
CPU time 101.19 seconds
Started Mar 21 03:13:21 PM PDT 24
Finished Mar 21 03:15:02 PM PDT 24
Peak memory 261140 kb
Host smart-b6fd1928-8d18-45c3-8d4c-4ef1fd7a83e0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298041892 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.flash_ctrl_intr_wr.1298041892
Directory /workspace/4.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr_slow_flash.1383379523
Short name T457
Test name
Test status
Simulation time 87675875300 ps
CPU time 414.15 seconds
Started Mar 21 03:13:22 PM PDT 24
Finished Mar 21 03:20:16 PM PDT 24
Peak memory 261340 kb
Host smart-7ab5ce51-93c4-4293-8d64-2547fc6caef2
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138
3379523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.1383379523
Directory /workspace/4.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_lcmgr_intg.941472885
Short name T134
Test name
Test status
Simulation time 48033000 ps
CPU time 13.53 seconds
Started Mar 21 03:13:30 PM PDT 24
Finished Mar 21 03:13:44 PM PDT 24
Peak memory 265204 kb
Host smart-6c31dffd-f37c-48d1-a693-74b376010b45
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941472885 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_lcmgr_intg.941472885
Directory /workspace/4.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/4.flash_ctrl_mp_regions.438249810
Short name T103
Test name
Test status
Simulation time 142143851800 ps
CPU time 516.22 seconds
Started Mar 21 03:13:09 PM PDT 24
Finished Mar 21 03:21:46 PM PDT 24
Peak memory 274392 kb
Host smart-2b469bf4-9918-48cc-b7d9-db07b7e9016d
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438249810 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_mp_regions.438249810
Directory /workspace/4.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/4.flash_ctrl_otp_reset.4010033184
Short name T513
Test name
Test status
Simulation time 132897100 ps
CPU time 112.45 seconds
Started Mar 21 03:13:11 PM PDT 24
Finished Mar 21 03:15:03 PM PDT 24
Peak memory 259868 kb
Host smart-571133ee-8446-41a8-9cbd-1b294c9e45dc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010033184 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ot
p_reset.4010033184
Directory /workspace/4.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_ack_consistency.2313866988
Short name T983
Test name
Test status
Simulation time 32003400 ps
CPU time 14.32 seconds
Started Mar 21 03:13:31 PM PDT 24
Finished Mar 21 03:13:48 PM PDT 24
Peak memory 265472 kb
Host smart-d3d62f15-3846-429c-b3cc-62df755696fa
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2313866988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.2313866988
Directory /workspace/4.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb.549128579
Short name T898
Test name
Test status
Simulation time 2790711900 ps
CPU time 567.62 seconds
Started Mar 21 03:13:10 PM PDT 24
Finished Mar 21 03:22:38 PM PDT 24
Peak memory 265312 kb
Host smart-a741eb16-1f9c-49bf-9b4b-322512ce2e1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=549128579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.549128579
Directory /workspace/4.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb_redun.2710485697
Short name T1002
Test name
Test status
Simulation time 725178300 ps
CPU time 40.42 seconds
Started Mar 21 03:13:32 PM PDT 24
Finished Mar 21 03:14:15 PM PDT 24
Peak memory 265424 kb
Host smart-67de0065-e43f-43e3-b639-1a44fdfa2545
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710485697 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.2710485697
Directory /workspace/4.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_host_grant_err.1806143978
Short name T746
Test name
Test status
Simulation time 14851600 ps
CPU time 14.08 seconds
Started Mar 21 03:13:32 PM PDT 24
Finished Mar 21 03:13:48 PM PDT 24
Peak memory 262268 kb
Host smart-f3c65111-e226-45eb-a75c-9d731535812e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806143978 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.1806143978
Directory /workspace/4.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_prog_reset.2447523827
Short name T875
Test name
Test status
Simulation time 199997400 ps
CPU time 19.16 seconds
Started Mar 21 03:13:20 PM PDT 24
Finished Mar 21 03:13:39 PM PDT 24
Peak memory 260912 kb
Host smart-9af59c8b-94a2-45ba-8e53-d5784dcfb539
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447523827 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_prog_res
et.2447523827
Directory /workspace/4.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_rand_ops.254281155
Short name T109
Test name
Test status
Simulation time 1244978200 ps
CPU time 705.22 seconds
Started Mar 21 03:13:10 PM PDT 24
Finished Mar 21 03:24:56 PM PDT 24
Peak memory 284984 kb
Host smart-0c4c9cc2-1057-4169-81c1-6d04a75773b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254281155 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.254281155
Directory /workspace/4.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/4.flash_ctrl_re_evict.292402599
Short name T725
Test name
Test status
Simulation time 416702400 ps
CPU time 40.48 seconds
Started Mar 21 03:13:21 PM PDT 24
Finished Mar 21 03:14:01 PM PDT 24
Peak memory 273580 kb
Host smart-e399cc8f-bc82-4f34-896a-90433401ce7c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292402599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_re_evict.292402599
Directory /workspace/4.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.1801098762
Short name T32
Test name
Test status
Simulation time 61437300 ps
CPU time 22.97 seconds
Started Mar 21 03:13:19 PM PDT 24
Finished Mar 21 03:13:42 PM PDT 24
Peak memory 265064 kb
Host smart-9bb4fc4b-c11c-48fc-9360-fd9ba979759e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801098762 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_derr.1801098762
Directory /workspace/4.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_serr.584680286
Short name T774
Test name
Test status
Simulation time 23974300 ps
CPU time 22.21 seconds
Started Mar 21 03:13:26 PM PDT 24
Finished Mar 21 03:13:50 PM PDT 24
Peak memory 264528 kb
Host smart-cc5918fc-86b8-47f0-9ee9-b0319653a2bd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584680286 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_read_word_sweep_serr.584680286
Directory /workspace/4.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro.1865509219
Short name T2
Test name
Test status
Simulation time 512176700 ps
CPU time 138.92 seconds
Started Mar 21 03:13:19 PM PDT 24
Finished Mar 21 03:15:39 PM PDT 24
Peak memory 281488 kb
Host smart-c790dc0e-3a43-461f-bbef-164aaf8570d7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865509219 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.flash_ctrl_ro.1865509219
Directory /workspace/4.flash_ctrl_ro/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_serr.3356131379
Short name T203
Test name
Test status
Simulation time 4769523400 ps
CPU time 145.31 seconds
Started Mar 21 03:13:19 PM PDT 24
Finished Mar 21 03:15:44 PM PDT 24
Peak memory 289936 kb
Host smart-b3f42dda-2f28-4424-83d0-9e44930d2099
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356131379 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_ro_serr.3356131379
Directory /workspace/4.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw.3610733967
Short name T186
Test name
Test status
Simulation time 14583942100 ps
CPU time 584.69 seconds
Started Mar 21 03:13:20 PM PDT 24
Finished Mar 21 03:23:05 PM PDT 24
Peak memory 313812 kb
Host smart-3c67a291-3535-4bc7-b32b-1d2edb64589d
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610733967 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ct
rl_rw.3610733967
Directory /workspace/4.flash_ctrl_rw/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict.2080728457
Short name T909
Test name
Test status
Simulation time 89574600 ps
CPU time 30.86 seconds
Started Mar 21 03:13:26 PM PDT 24
Finished Mar 21 03:13:57 PM PDT 24
Peak memory 273568 kb
Host smart-21923f55-1278-4242-b4d1-72602ee0aad8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080728457 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_rw_evict.2080728457
Directory /workspace/4.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict_all_en.619204182
Short name T520
Test name
Test status
Simulation time 32893800 ps
CPU time 31.49 seconds
Started Mar 21 03:13:22 PM PDT 24
Finished Mar 21 03:13:54 PM PDT 24
Peak memory 273604 kb
Host smart-5c5ba630-cd48-4e5c-b862-361aea1ae1b4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619204182 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict_all_en.619204182
Directory /workspace/4.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_info_access.1292370801
Short name T476
Test name
Test status
Simulation time 8935757300 ps
CPU time 85.97 seconds
Started Mar 21 03:13:21 PM PDT 24
Finished Mar 21 03:14:47 PM PDT 24
Peak memory 262920 kb
Host smart-7437ca4e-2ab8-44da-b6f7-fea1a14ed3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292370801 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.1292370801
Directory /workspace/4.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_address.65430190
Short name T812
Test name
Test status
Simulation time 4910123100 ps
CPU time 78.17 seconds
Started Mar 21 03:13:21 PM PDT 24
Finished Mar 21 03:14:40 PM PDT 24
Peak memory 265312 kb
Host smart-a6e6273f-292e-40fc-8349-eae34752d8a5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65430190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_b
ase_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.flash_ctrl_serr_address.65430190
Directory /workspace/4.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_counter.3437199195
Short name T215
Test name
Test status
Simulation time 926733300 ps
CPU time 58.7 seconds
Started Mar 21 03:13:22 PM PDT 24
Finished Mar 21 03:14:21 PM PDT 24
Peak memory 273736 kb
Host smart-0c3186e0-efbb-43e0-991b-f64949ebe42c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437199195 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.flash_ctrl_serr_counter.3437199195
Directory /workspace/4.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke.3088544978
Short name T976
Test name
Test status
Simulation time 47684300 ps
CPU time 174.29 seconds
Started Mar 21 03:13:09 PM PDT 24
Finished Mar 21 03:16:04 PM PDT 24
Peak memory 276692 kb
Host smart-90914d9d-18b6-43c5-88e1-a0ca94c82269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088544978 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.3088544978
Directory /workspace/4.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke_hw.3520892728
Short name T1027
Test name
Test status
Simulation time 15656900 ps
CPU time 23.73 seconds
Started Mar 21 03:13:11 PM PDT 24
Finished Mar 21 03:13:35 PM PDT 24
Peak memory 258972 kb
Host smart-ac1508c2-9f63-4320-8dc5-dcdeacab7761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520892728 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.3520892728
Directory /workspace/4.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/4.flash_ctrl_stress_all.3513193477
Short name T656
Test name
Test status
Simulation time 174734600 ps
CPU time 770.16 seconds
Started Mar 21 03:13:21 PM PDT 24
Finished Mar 21 03:26:11 PM PDT 24
Peak memory 281896 kb
Host smart-d05ce255-9b48-4ab5-9169-5f8a7ca6af63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513193477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stres
s_all.3513193477
Directory /workspace/4.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.flash_ctrl_sw_op.298896059
Short name T1045
Test name
Test status
Simulation time 48793100 ps
CPU time 27.7 seconds
Started Mar 21 03:13:08 PM PDT 24
Finished Mar 21 03:13:36 PM PDT 24
Peak memory 258940 kb
Host smart-c63a49ce-510b-471f-a768-b370fafd44ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298896059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.298896059
Directory /workspace/4.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_wo.2806814652
Short name T589
Test name
Test status
Simulation time 3650406300 ps
CPU time 188.87 seconds
Started Mar 21 03:13:19 PM PDT 24
Finished Mar 21 03:16:29 PM PDT 24
Peak memory 265248 kb
Host smart-0c8f0bcc-b9d2-476c-90ad-f99b4137394e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806814652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.flash_ctrl_wo.2806814652
Directory /workspace/4.flash_ctrl_wo/latest

Test location /workspace/coverage/default/40.flash_ctrl_alert_test.3719349858
Short name T1004
Test name
Test status
Simulation time 87126900 ps
CPU time 13.64 seconds
Started Mar 21 03:19:49 PM PDT 24
Finished Mar 21 03:20:03 PM PDT 24
Peak memory 258376 kb
Host smart-98250b94-7f4c-4755-88ad-1d11c5ba9946
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719349858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test.
3719349858
Directory /workspace/40.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.flash_ctrl_connect.3117322953
Short name T688
Test name
Test status
Simulation time 199278000 ps
CPU time 15.8 seconds
Started Mar 21 03:19:52 PM PDT 24
Finished Mar 21 03:20:08 PM PDT 24
Peak memory 276168 kb
Host smart-140926c6-4803-4382-91ce-66da5f498cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117322953 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.3117322953
Directory /workspace/40.flash_ctrl_connect/latest

Test location /workspace/coverage/default/40.flash_ctrl_disable.2160286493
Short name T522
Test name
Test status
Simulation time 94758700 ps
CPU time 21.95 seconds
Started Mar 21 03:19:39 PM PDT 24
Finished Mar 21 03:20:01 PM PDT 24
Peak memory 280628 kb
Host smart-6f03860f-6c6e-49c7-bb97-114fe26ccc47
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160286493 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.flash_ctrl_disable.2160286493
Directory /workspace/40.flash_ctrl_disable/latest

Test location /workspace/coverage/default/40.flash_ctrl_hw_sec_otp.4036119343
Short name T42
Test name
Test status
Simulation time 2293516400 ps
CPU time 42.41 seconds
Started Mar 21 03:19:40 PM PDT 24
Finished Mar 21 03:20:23 PM PDT 24
Peak memory 262488 kb
Host smart-71db0a33-e0b9-4038-9257-79dfd9b0ffaa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036119343 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_
hw_sec_otp.4036119343
Directory /workspace/40.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/40.flash_ctrl_otp_reset.1159220637
Short name T646
Test name
Test status
Simulation time 76696700 ps
CPU time 131.37 seconds
Started Mar 21 03:19:40 PM PDT 24
Finished Mar 21 03:21:52 PM PDT 24
Peak memory 260996 kb
Host smart-395d180f-2cbb-42a1-a884-04b23e94f511
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159220637 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_o
tp_reset.1159220637
Directory /workspace/40.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/40.flash_ctrl_sec_info_access.425171285
Short name T393
Test name
Test status
Simulation time 3846644100 ps
CPU time 64.22 seconds
Started Mar 21 03:19:39 PM PDT 24
Finished Mar 21 03:20:44 PM PDT 24
Peak memory 262576 kb
Host smart-e230405f-78a6-4674-aeed-0df289318858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425171285 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.425171285
Directory /workspace/40.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/40.flash_ctrl_smoke.2448321839
Short name T800
Test name
Test status
Simulation time 37035000 ps
CPU time 173.12 seconds
Started Mar 21 03:19:44 PM PDT 24
Finished Mar 21 03:22:38 PM PDT 24
Peak memory 276828 kb
Host smart-cd40a144-2cb9-413f-af9d-556d10959374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448321839 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.2448321839
Directory /workspace/40.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/41.flash_ctrl_alert_test.1434184604
Short name T477
Test name
Test status
Simulation time 44273500 ps
CPU time 13.82 seconds
Started Mar 21 03:19:48 PM PDT 24
Finished Mar 21 03:20:02 PM PDT 24
Peak memory 258356 kb
Host smart-433e5546-d9d5-49a9-b2ca-61c407847d7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434184604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test.
1434184604
Directory /workspace/41.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.flash_ctrl_connect.4176665029
Short name T424
Test name
Test status
Simulation time 49300100 ps
CPU time 16.11 seconds
Started Mar 21 03:19:51 PM PDT 24
Finished Mar 21 03:20:07 PM PDT 24
Peak memory 275936 kb
Host smart-b59e5f8f-8b5e-4620-97c3-31c0c4d5c64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176665029 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.4176665029
Directory /workspace/41.flash_ctrl_connect/latest

Test location /workspace/coverage/default/41.flash_ctrl_disable.4168360971
Short name T1005
Test name
Test status
Simulation time 18695000 ps
CPU time 20.75 seconds
Started Mar 21 03:19:51 PM PDT 24
Finished Mar 21 03:20:12 PM PDT 24
Peak memory 280464 kb
Host smart-ed9d96b3-b1a0-4d0f-91b3-3826e2ce6115
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168360971 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.flash_ctrl_disable.4168360971
Directory /workspace/41.flash_ctrl_disable/latest

Test location /workspace/coverage/default/41.flash_ctrl_hw_sec_otp.1807707565
Short name T714
Test name
Test status
Simulation time 3815927500 ps
CPU time 58.6 seconds
Started Mar 21 03:19:48 PM PDT 24
Finished Mar 21 03:20:47 PM PDT 24
Peak memory 262464 kb
Host smart-d6fb4bde-5129-4d74-b06c-cefdce60e876
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807707565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_
hw_sec_otp.1807707565
Directory /workspace/41.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/41.flash_ctrl_otp_reset.2552659395
Short name T961
Test name
Test status
Simulation time 484672500 ps
CPU time 111.84 seconds
Started Mar 21 03:19:51 PM PDT 24
Finished Mar 21 03:21:43 PM PDT 24
Peak memory 261076 kb
Host smart-f1532d9b-4f96-463e-9430-1cc71e55919a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552659395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_o
tp_reset.2552659395
Directory /workspace/41.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/41.flash_ctrl_sec_info_access.68983061
Short name T540
Test name
Test status
Simulation time 401378300 ps
CPU time 53.03 seconds
Started Mar 21 03:19:49 PM PDT 24
Finished Mar 21 03:20:42 PM PDT 24
Peak memory 262972 kb
Host smart-31bb56bc-04e0-4af5-b2da-6e5fda258d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68983061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.68983061
Directory /workspace/41.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/41.flash_ctrl_smoke.3708193338
Short name T558
Test name
Test status
Simulation time 75220000 ps
CPU time 169.29 seconds
Started Mar 21 03:19:50 PM PDT 24
Finished Mar 21 03:22:39 PM PDT 24
Peak memory 278996 kb
Host smart-3a64c4ec-b79a-41e8-8416-b2a8b489ecb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708193338 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.3708193338
Directory /workspace/41.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/42.flash_ctrl_alert_test.2336397727
Short name T472
Test name
Test status
Simulation time 117275200 ps
CPU time 14.27 seconds
Started Mar 21 03:19:52 PM PDT 24
Finished Mar 21 03:20:07 PM PDT 24
Peak memory 259348 kb
Host smart-a264701a-f0ba-4102-b5b1-156339168536
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336397727 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test.
2336397727
Directory /workspace/42.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.flash_ctrl_connect.3449738592
Short name T736
Test name
Test status
Simulation time 36374900 ps
CPU time 15.9 seconds
Started Mar 21 03:19:52 PM PDT 24
Finished Mar 21 03:20:08 PM PDT 24
Peak memory 275652 kb
Host smart-f1e0a25f-4514-4a58-8cdf-eca16a344154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449738592 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.3449738592
Directory /workspace/42.flash_ctrl_connect/latest

Test location /workspace/coverage/default/42.flash_ctrl_disable.2589169866
Short name T914
Test name
Test status
Simulation time 40574000 ps
CPU time 21.85 seconds
Started Mar 21 03:19:48 PM PDT 24
Finished Mar 21 03:20:10 PM PDT 24
Peak memory 273700 kb
Host smart-bc0b1f13-8175-4983-9a4e-6ab178671a07
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589169866 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.flash_ctrl_disable.2589169866
Directory /workspace/42.flash_ctrl_disable/latest

Test location /workspace/coverage/default/42.flash_ctrl_hw_sec_otp.538964985
Short name T820
Test name
Test status
Simulation time 55351285100 ps
CPU time 127.8 seconds
Started Mar 21 03:19:52 PM PDT 24
Finished Mar 21 03:22:00 PM PDT 24
Peak memory 262608 kb
Host smart-c79f70dc-9411-49bd-beb8-2b760b885fd7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538964985 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_h
w_sec_otp.538964985
Directory /workspace/42.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/42.flash_ctrl_otp_reset.2832515937
Short name T147
Test name
Test status
Simulation time 190577800 ps
CPU time 131.76 seconds
Started Mar 21 03:19:50 PM PDT 24
Finished Mar 21 03:22:01 PM PDT 24
Peak memory 260068 kb
Host smart-b2762465-48d6-47e8-803b-c900e5595df9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832515937 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_o
tp_reset.2832515937
Directory /workspace/42.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/42.flash_ctrl_sec_info_access.1796731881
Short name T382
Test name
Test status
Simulation time 1297636600 ps
CPU time 66.37 seconds
Started Mar 21 03:19:48 PM PDT 24
Finished Mar 21 03:20:54 PM PDT 24
Peak memory 263208 kb
Host smart-feefb421-b6b9-45c6-a7f7-3deb7586b9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796731881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.1796731881
Directory /workspace/42.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/42.flash_ctrl_smoke.58109685
Short name T730
Test name
Test status
Simulation time 65180400 ps
CPU time 100.45 seconds
Started Mar 21 03:19:49 PM PDT 24
Finished Mar 21 03:21:29 PM PDT 24
Peak memory 276460 kb
Host smart-599f105d-73bb-436f-8f0e-dd6a73cba39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58109685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.58109685
Directory /workspace/42.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/43.flash_ctrl_alert_test.2519498870
Short name T1008
Test name
Test status
Simulation time 88052200 ps
CPU time 13.64 seconds
Started Mar 21 03:19:49 PM PDT 24
Finished Mar 21 03:20:02 PM PDT 24
Peak memory 258264 kb
Host smart-dc869a44-8c08-479c-ba25-1e586d2defbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519498870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test.
2519498870
Directory /workspace/43.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.flash_ctrl_connect.2194617420
Short name T1009
Test name
Test status
Simulation time 16816500 ps
CPU time 15.92 seconds
Started Mar 21 03:19:48 PM PDT 24
Finished Mar 21 03:20:04 PM PDT 24
Peak memory 275724 kb
Host smart-feb46e34-2af6-4c22-87cb-34f135ddc833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194617420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.2194617420
Directory /workspace/43.flash_ctrl_connect/latest

Test location /workspace/coverage/default/43.flash_ctrl_disable.948613981
Short name T283
Test name
Test status
Simulation time 30246400 ps
CPU time 22.02 seconds
Started Mar 21 03:19:50 PM PDT 24
Finished Mar 21 03:20:12 PM PDT 24
Peak memory 265280 kb
Host smart-4431b954-d003-408c-9fc6-8c0eacdfdaa7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948613981 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.flash_ctrl_disable.948613981
Directory /workspace/43.flash_ctrl_disable/latest

Test location /workspace/coverage/default/43.flash_ctrl_hw_sec_otp.1453508456
Short name T326
Test name
Test status
Simulation time 18981719400 ps
CPU time 134.01 seconds
Started Mar 21 03:19:50 PM PDT 24
Finished Mar 21 03:22:04 PM PDT 24
Peak memory 262384 kb
Host smart-ba026d7d-2c0b-4cca-9d84-f6efa1f772c0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453508456 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_
hw_sec_otp.1453508456
Directory /workspace/43.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/43.flash_ctrl_otp_reset.1058050452
Short name T131
Test name
Test status
Simulation time 214674200 ps
CPU time 134.44 seconds
Started Mar 21 03:19:49 PM PDT 24
Finished Mar 21 03:22:04 PM PDT 24
Peak memory 261016 kb
Host smart-7ae94728-1e6f-4b2e-9a8e-dca7189011d1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058050452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_o
tp_reset.1058050452
Directory /workspace/43.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/43.flash_ctrl_sec_info_access.1577027288
Short name T246
Test name
Test status
Simulation time 5931213400 ps
CPU time 66.11 seconds
Started Mar 21 03:19:50 PM PDT 24
Finished Mar 21 03:20:56 PM PDT 24
Peak memory 263252 kb
Host smart-20391d43-09c0-4a43-98a5-5403bc994a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577027288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.1577027288
Directory /workspace/43.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/43.flash_ctrl_smoke.3151931133
Short name T432
Test name
Test status
Simulation time 30607500 ps
CPU time 76.59 seconds
Started Mar 21 03:19:50 PM PDT 24
Finished Mar 21 03:21:06 PM PDT 24
Peak memory 276100 kb
Host smart-eb104d1a-08e8-4459-8135-124d2402177e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151931133 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.3151931133
Directory /workspace/43.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/44.flash_ctrl_alert_test.2406388365
Short name T445
Test name
Test status
Simulation time 37550500 ps
CPU time 14.02 seconds
Started Mar 21 03:19:58 PM PDT 24
Finished Mar 21 03:20:12 PM PDT 24
Peak memory 258312 kb
Host smart-65b05187-e099-4246-bb26-2d5315fe5628
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406388365 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.
2406388365
Directory /workspace/44.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.flash_ctrl_connect.3075352537
Short name T877
Test name
Test status
Simulation time 16793700 ps
CPU time 16.21 seconds
Started Mar 21 03:19:57 PM PDT 24
Finished Mar 21 03:20:13 PM PDT 24
Peak memory 275140 kb
Host smart-74302082-ef2a-465e-83fe-41feb707ae39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075352537 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.3075352537
Directory /workspace/44.flash_ctrl_connect/latest

Test location /workspace/coverage/default/44.flash_ctrl_hw_sec_otp.3937092350
Short name T701
Test name
Test status
Simulation time 8797734300 ps
CPU time 201.94 seconds
Started Mar 21 03:19:59 PM PDT 24
Finished Mar 21 03:23:22 PM PDT 24
Peak memory 262592 kb
Host smart-b3e9af12-47ee-4f95-9c8e-acb4423c472c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937092350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_
hw_sec_otp.3937092350
Directory /workspace/44.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/44.flash_ctrl_otp_reset.157513765
Short name T638
Test name
Test status
Simulation time 133804100 ps
CPU time 132.25 seconds
Started Mar 21 03:19:58 PM PDT 24
Finished Mar 21 03:22:10 PM PDT 24
Peak memory 259864 kb
Host smart-3c60d7ad-fec4-4b01-88cf-04cde11d2815
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157513765 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_ot
p_reset.157513765
Directory /workspace/44.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/44.flash_ctrl_smoke.3432398142
Short name T773
Test name
Test status
Simulation time 43487000 ps
CPU time 123.74 seconds
Started Mar 21 03:19:58 PM PDT 24
Finished Mar 21 03:22:03 PM PDT 24
Peak memory 275800 kb
Host smart-170f4494-ab70-4550-94d6-c2ab2b4f0be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432398142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.3432398142
Directory /workspace/44.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/45.flash_ctrl_alert_test.1476563530
Short name T1013
Test name
Test status
Simulation time 158201300 ps
CPU time 14.06 seconds
Started Mar 21 03:19:59 PM PDT 24
Finished Mar 21 03:20:14 PM PDT 24
Peak memory 258304 kb
Host smart-e712e952-6d0a-476a-916e-029b95335194
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476563530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.
1476563530
Directory /workspace/45.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.flash_ctrl_connect.533708253
Short name T655
Test name
Test status
Simulation time 16329000 ps
CPU time 15.77 seconds
Started Mar 21 03:20:02 PM PDT 24
Finished Mar 21 03:20:18 PM PDT 24
Peak memory 275212 kb
Host smart-c35cbe31-259d-435d-8e2d-a5c22a29449d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533708253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.533708253
Directory /workspace/45.flash_ctrl_connect/latest

Test location /workspace/coverage/default/45.flash_ctrl_disable.4043589121
Short name T73
Test name
Test status
Simulation time 24683100 ps
CPU time 20.36 seconds
Started Mar 21 03:20:01 PM PDT 24
Finished Mar 21 03:20:21 PM PDT 24
Peak memory 265232 kb
Host smart-b6f1d50b-c400-4f6d-8882-ec9e87c49a80
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043589121 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.flash_ctrl_disable.4043589121
Directory /workspace/45.flash_ctrl_disable/latest

Test location /workspace/coverage/default/45.flash_ctrl_hw_sec_otp.1899894219
Short name T4
Test name
Test status
Simulation time 17608848500 ps
CPU time 136.83 seconds
Started Mar 21 03:19:59 PM PDT 24
Finished Mar 21 03:22:16 PM PDT 24
Peak memory 262396 kb
Host smart-820f89b0-041c-4685-a77c-8a21f147251c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899894219 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_
hw_sec_otp.1899894219
Directory /workspace/45.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/45.flash_ctrl_otp_reset.36979026
Short name T834
Test name
Test status
Simulation time 69879800 ps
CPU time 136.99 seconds
Started Mar 21 03:20:00 PM PDT 24
Finished Mar 21 03:22:18 PM PDT 24
Peak memory 259752 kb
Host smart-f9c63f5e-fa1f-4854-a4a7-23d0d77ca543
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36979026 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_otp
_reset.36979026
Directory /workspace/45.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/45.flash_ctrl_sec_info_access.2956916919
Short name T727
Test name
Test status
Simulation time 1658932600 ps
CPU time 67.2 seconds
Started Mar 21 03:19:59 PM PDT 24
Finished Mar 21 03:21:07 PM PDT 24
Peak memory 261920 kb
Host smart-658061cd-4509-4b5d-9398-5cbca2e47d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956916919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.2956916919
Directory /workspace/45.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/45.flash_ctrl_smoke.1540068036
Short name T183
Test name
Test status
Simulation time 21808400 ps
CPU time 53.6 seconds
Started Mar 21 03:20:00 PM PDT 24
Finished Mar 21 03:20:54 PM PDT 24
Peak memory 271908 kb
Host smart-a798f8e4-1033-4c56-89ad-691daadd8496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540068036 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.1540068036
Directory /workspace/45.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/46.flash_ctrl_alert_test.3959729649
Short name T421
Test name
Test status
Simulation time 112664900 ps
CPU time 13.68 seconds
Started Mar 21 03:19:58 PM PDT 24
Finished Mar 21 03:20:12 PM PDT 24
Peak memory 258292 kb
Host smart-35d076b0-e51c-4607-ae58-4b22ac47d1cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959729649 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.
3959729649
Directory /workspace/46.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.flash_ctrl_disable.2051629540
Short name T511
Test name
Test status
Simulation time 10429700 ps
CPU time 21.42 seconds
Started Mar 21 03:19:58 PM PDT 24
Finished Mar 21 03:20:20 PM PDT 24
Peak memory 265252 kb
Host smart-2f2dad8b-6aa8-4b3a-801e-b44cc4ef517a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051629540 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.flash_ctrl_disable.2051629540
Directory /workspace/46.flash_ctrl_disable/latest

Test location /workspace/coverage/default/46.flash_ctrl_otp_reset.1032861911
Short name T990
Test name
Test status
Simulation time 155711600 ps
CPU time 132.46 seconds
Started Mar 21 03:20:00 PM PDT 24
Finished Mar 21 03:22:12 PM PDT 24
Peak memory 260920 kb
Host smart-6a7373aa-ccf5-4c04-ac78-db2344bdf585
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032861911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_o
tp_reset.1032861911
Directory /workspace/46.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/46.flash_ctrl_sec_info_access.907602865
Short name T634
Test name
Test status
Simulation time 4524587000 ps
CPU time 74.85 seconds
Started Mar 21 03:19:57 PM PDT 24
Finished Mar 21 03:21:13 PM PDT 24
Peak memory 262320 kb
Host smart-0c6c1db8-b782-4e3a-a7e7-7d273042410f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907602865 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.907602865
Directory /workspace/46.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/46.flash_ctrl_smoke.407338601
Short name T809
Test name
Test status
Simulation time 58053200 ps
CPU time 52.06 seconds
Started Mar 21 03:20:02 PM PDT 24
Finished Mar 21 03:20:54 PM PDT 24
Peak memory 270656 kb
Host smart-4e09cc9a-c981-4d45-b821-856f39b9c937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407338601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.407338601
Directory /workspace/46.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/47.flash_ctrl_alert_test.1851656943
Short name T410
Test name
Test status
Simulation time 27913500 ps
CPU time 13.61 seconds
Started Mar 21 03:20:14 PM PDT 24
Finished Mar 21 03:20:28 PM PDT 24
Peak memory 258248 kb
Host smart-8a20e3ba-6633-4505-9601-1ac0ddfec503
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851656943 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test.
1851656943
Directory /workspace/47.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.flash_ctrl_connect.3798447519
Short name T460
Test name
Test status
Simulation time 37341200 ps
CPU time 16.07 seconds
Started Mar 21 03:20:14 PM PDT 24
Finished Mar 21 03:20:30 PM PDT 24
Peak memory 275232 kb
Host smart-369e5aed-551a-4195-bbc4-779c9ee20095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798447519 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.3798447519
Directory /workspace/47.flash_ctrl_connect/latest

Test location /workspace/coverage/default/47.flash_ctrl_disable.22950707
Short name T55
Test name
Test status
Simulation time 13062800 ps
CPU time 20.74 seconds
Started Mar 21 03:20:13 PM PDT 24
Finished Mar 21 03:20:33 PM PDT 24
Peak memory 265372 kb
Host smart-075671f0-a18f-4f03-8c92-fd54f7dad302
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22950707 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 47.flash_ctrl_disable.22950707
Directory /workspace/47.flash_ctrl_disable/latest

Test location /workspace/coverage/default/47.flash_ctrl_hw_sec_otp.2982634634
Short name T806
Test name
Test status
Simulation time 9173547500 ps
CPU time 48.64 seconds
Started Mar 21 03:20:12 PM PDT 24
Finished Mar 21 03:21:01 PM PDT 24
Peak memory 262712 kb
Host smart-d391bd3c-4b3f-48ff-a6ac-501a06636f1b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982634634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_
hw_sec_otp.2982634634
Directory /workspace/47.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/47.flash_ctrl_sec_info_access.2083318246
Short name T636
Test name
Test status
Simulation time 2477784900 ps
CPU time 67.28 seconds
Started Mar 21 03:20:14 PM PDT 24
Finished Mar 21 03:21:21 PM PDT 24
Peak memory 262536 kb
Host smart-3f7b0fe6-9497-4995-98ed-f266af3af963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083318246 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.2083318246
Directory /workspace/47.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/47.flash_ctrl_smoke.844065248
Short name T516
Test name
Test status
Simulation time 56745400 ps
CPU time 104.16 seconds
Started Mar 21 03:20:00 PM PDT 24
Finished Mar 21 03:21:45 PM PDT 24
Peak memory 275232 kb
Host smart-c352423f-cc62-4c7e-b30e-7e88c91acc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844065248 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.844065248
Directory /workspace/47.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/48.flash_ctrl_alert_test.1774749248
Short name T1007
Test name
Test status
Simulation time 105911400 ps
CPU time 14.1 seconds
Started Mar 21 03:20:13 PM PDT 24
Finished Mar 21 03:20:27 PM PDT 24
Peak memory 258124 kb
Host smart-179d8ed7-8cf3-459f-8db7-d6589cfb3003
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774749248 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.
1774749248
Directory /workspace/48.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.flash_ctrl_connect.3521492245
Short name T175
Test name
Test status
Simulation time 133644700 ps
CPU time 13.49 seconds
Started Mar 21 03:20:13 PM PDT 24
Finished Mar 21 03:20:26 PM PDT 24
Peak memory 275032 kb
Host smart-a6837a43-6abf-42ea-92a6-19946155e49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521492245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.3521492245
Directory /workspace/48.flash_ctrl_connect/latest

Test location /workspace/coverage/default/48.flash_ctrl_disable.456140963
Short name T1037
Test name
Test status
Simulation time 21753800 ps
CPU time 22.84 seconds
Started Mar 21 03:20:13 PM PDT 24
Finished Mar 21 03:20:36 PM PDT 24
Peak memory 273676 kb
Host smart-a17c2b5e-f451-4468-8426-c4eaeb20b039
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456140963 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.flash_ctrl_disable.456140963
Directory /workspace/48.flash_ctrl_disable/latest

Test location /workspace/coverage/default/48.flash_ctrl_hw_sec_otp.964898013
Short name T328
Test name
Test status
Simulation time 8013730700 ps
CPU time 132.52 seconds
Started Mar 21 03:20:14 PM PDT 24
Finished Mar 21 03:22:26 PM PDT 24
Peak memory 262444 kb
Host smart-86211133-071d-4144-8ea6-73fd5559b5e9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964898013 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_h
w_sec_otp.964898013
Directory /workspace/48.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/48.flash_ctrl_otp_reset.3766071757
Short name T136
Test name
Test status
Simulation time 57801100 ps
CPU time 113.11 seconds
Started Mar 21 03:20:15 PM PDT 24
Finished Mar 21 03:22:08 PM PDT 24
Peak memory 259796 kb
Host smart-0ab85561-8bad-43d4-ac49-29aea2e92e3f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766071757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_o
tp_reset.3766071757
Directory /workspace/48.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/48.flash_ctrl_sec_info_access.1175310471
Short name T892
Test name
Test status
Simulation time 12862611600 ps
CPU time 78.13 seconds
Started Mar 21 03:20:15 PM PDT 24
Finished Mar 21 03:21:33 PM PDT 24
Peak memory 264068 kb
Host smart-32050059-045a-4afa-a04c-32cafe1b1505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175310471 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.1175310471
Directory /workspace/48.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/48.flash_ctrl_smoke.1557462529
Short name T482
Test name
Test status
Simulation time 47194200 ps
CPU time 74.98 seconds
Started Mar 21 03:20:15 PM PDT 24
Finished Mar 21 03:21:30 PM PDT 24
Peak memory 275204 kb
Host smart-94675277-6cdf-4b6c-8f2d-6df11fd526d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557462529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.1557462529
Directory /workspace/48.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/49.flash_ctrl_alert_test.615277726
Short name T492
Test name
Test status
Simulation time 70067400 ps
CPU time 14.14 seconds
Started Mar 21 03:20:28 PM PDT 24
Finished Mar 21 03:20:42 PM PDT 24
Peak memory 265272 kb
Host smart-3a1e396b-1bc4-4f5c-a260-a416f8eb011a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615277726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.615277726
Directory /workspace/49.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.flash_ctrl_connect.1474253461
Short name T575
Test name
Test status
Simulation time 15185800 ps
CPU time 13.46 seconds
Started Mar 21 03:20:25 PM PDT 24
Finished Mar 21 03:20:39 PM PDT 24
Peak memory 275164 kb
Host smart-33191594-7ed4-4514-a30c-33cb0782cec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474253461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.1474253461
Directory /workspace/49.flash_ctrl_connect/latest

Test location /workspace/coverage/default/49.flash_ctrl_hw_sec_otp.1641222939
Short name T839
Test name
Test status
Simulation time 8926284600 ps
CPU time 71.02 seconds
Started Mar 21 03:20:15 PM PDT 24
Finished Mar 21 03:21:26 PM PDT 24
Peak memory 261908 kb
Host smart-db8042a6-02ee-4fc8-8f3a-6deb8610e53c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641222939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_
hw_sec_otp.1641222939
Directory /workspace/49.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/49.flash_ctrl_otp_reset.911428376
Short name T452
Test name
Test status
Simulation time 42304600 ps
CPU time 131.54 seconds
Started Mar 21 03:20:15 PM PDT 24
Finished Mar 21 03:22:27 PM PDT 24
Peak memory 259680 kb
Host smart-a8eafb5b-8a7d-4326-8cd8-8a21a364e041
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911428376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_ot
p_reset.911428376
Directory /workspace/49.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/49.flash_ctrl_sec_info_access.411049587
Short name T386
Test name
Test status
Simulation time 3323798100 ps
CPU time 76.01 seconds
Started Mar 21 03:20:13 PM PDT 24
Finished Mar 21 03:21:29 PM PDT 24
Peak memory 262696 kb
Host smart-3d898e5c-3e06-455a-bf46-0c80f1d7e3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411049587 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.411049587
Directory /workspace/49.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/49.flash_ctrl_smoke.644887169
Short name T56
Test name
Test status
Simulation time 97763800 ps
CPU time 76.78 seconds
Started Mar 21 03:20:15 PM PDT 24
Finished Mar 21 03:21:32 PM PDT 24
Peak memory 275220 kb
Host smart-75c8310e-7a4b-485d-a0a9-36a9e60ba676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644887169 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.644887169
Directory /workspace/49.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_connect.1227775533
Short name T94
Test name
Test status
Simulation time 47476400 ps
CPU time 16 seconds
Started Mar 21 03:13:42 PM PDT 24
Finished Mar 21 03:13:58 PM PDT 24
Peak memory 275704 kb
Host smart-d8e01ee0-1c8e-42f2-b469-e51daf818bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227775533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.1227775533
Directory /workspace/5.flash_ctrl_connect/latest

Test location /workspace/coverage/default/5.flash_ctrl_disable.4060842379
Short name T987
Test name
Test status
Simulation time 21279000 ps
CPU time 21.11 seconds
Started Mar 21 03:13:42 PM PDT 24
Finished Mar 21 03:14:04 PM PDT 24
Peak memory 265220 kb
Host smart-c101a868-6882-4ca1-90ed-d569363ba5a4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060842379 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_disable.4060842379
Directory /workspace/5.flash_ctrl_disable/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_mp.593011526
Short name T235
Test name
Test status
Simulation time 3856238600 ps
CPU time 2143.69 seconds
Started Mar 21 03:13:33 PM PDT 24
Finished Mar 21 03:49:18 PM PDT 24
Peak memory 264672 kb
Host smart-b6ceb686-efd0-4b7d-a8e7-97ff9bff51b5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593011526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_erro
r_mp.593011526
Directory /workspace/5.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_prog_win.2191435424
Short name T652
Test name
Test status
Simulation time 732191100 ps
CPU time 837.12 seconds
Started Mar 21 03:13:33 PM PDT 24
Finished Mar 21 03:27:31 PM PDT 24
Peak memory 273436 kb
Host smart-64a8c49e-7d05-4a4c-9e6b-687b29d4185b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191435424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.2191435424
Directory /workspace/5.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/5.flash_ctrl_fetch_code.29226623
Short name T47
Test name
Test status
Simulation time 517189300 ps
CPU time 22.03 seconds
Started Mar 21 03:13:32 PM PDT 24
Finished Mar 21 03:13:56 PM PDT 24
Peak memory 265152 kb
Host smart-183e0dad-1de3-4616-9d0e-3caabd4b1ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29226623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetch_code.29226623
Directory /workspace/5.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.2273636925
Short name T144
Test name
Test status
Simulation time 10012096800 ps
CPU time 137.54 seconds
Started Mar 21 03:13:47 PM PDT 24
Finished Mar 21 03:16:04 PM PDT 24
Peak memory 329732 kb
Host smart-31fd840f-ecda-4e5f-a329-1e5d9c6664bb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273636925 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.2273636925
Directory /workspace/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_read_seed_err.610976061
Short name T362
Test name
Test status
Simulation time 16026600 ps
CPU time 13.5 seconds
Started Mar 21 03:13:47 PM PDT 24
Finished Mar 21 03:14:00 PM PDT 24
Peak memory 265208 kb
Host smart-6c2ee8d1-94e1-47bd-b283-a67f759d22d3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610976061 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_seed_err.610976061
Directory /workspace/5.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_rma_reset.1835650097
Short name T580
Test name
Test status
Simulation time 40123646900 ps
CPU time 871.02 seconds
Started Mar 21 03:13:31 PM PDT 24
Finished Mar 21 03:28:02 PM PDT 24
Peak memory 264468 kb
Host smart-a2e88d4f-eecb-4b1d-a636-76342fe4cd33
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835650097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 5.flash_ctrl_hw_rma_reset.1835650097
Directory /workspace/5.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_sec_otp.607090848
Short name T1042
Test name
Test status
Simulation time 4581083200 ps
CPU time 115.94 seconds
Started Mar 21 03:13:31 PM PDT 24
Finished Mar 21 03:15:27 PM PDT 24
Peak memory 262480 kb
Host smart-e62557cc-1237-4ec4-8fa9-e40d6de93740
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607090848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw
_sec_otp.607090848
Directory /workspace/5.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd_slow_flash.4137681732
Short name T332
Test name
Test status
Simulation time 22312323000 ps
CPU time 280.12 seconds
Started Mar 21 03:13:42 PM PDT 24
Finished Mar 21 03:18:23 PM PDT 24
Peak memory 289852 kb
Host smart-12b4f9dc-bf2c-4af1-bf0a-d9e4fba9eebe
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137681732 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd_slow_flash.4137681732
Directory /workspace/5.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr.1777032044
Short name T486
Test name
Test status
Simulation time 14585670200 ps
CPU time 93.05 seconds
Started Mar 21 03:13:45 PM PDT 24
Finished Mar 21 03:15:18 PM PDT 24
Peak memory 265240 kb
Host smart-5da35246-3b9a-49a2-a4ad-dbbd5bcee835
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777032044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.flash_ctrl_intr_wr.1777032044
Directory /workspace/5.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr_slow_flash.1479427386
Short name T936
Test name
Test status
Simulation time 44833504100 ps
CPU time 336.74 seconds
Started Mar 21 03:13:42 PM PDT 24
Finished Mar 21 03:19:19 PM PDT 24
Peak memory 261428 kb
Host smart-3e3dcd58-76f5-47ef-999d-8f189663415a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147
9427386 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.1479427386
Directory /workspace/5.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_invalid_op.1177971058
Short name T554
Test name
Test status
Simulation time 1182666200 ps
CPU time 86.38 seconds
Started Mar 21 03:13:31 PM PDT 24
Finished Mar 21 03:14:57 PM PDT 24
Peak memory 263352 kb
Host smart-03c5dbf4-87c1-4b35-aa48-97fda071471d
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177971058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.1177971058
Directory /workspace/5.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/5.flash_ctrl_lcmgr_intg.771499464
Short name T790
Test name
Test status
Simulation time 26442700 ps
CPU time 13.62 seconds
Started Mar 21 03:13:42 PM PDT 24
Finished Mar 21 03:13:56 PM PDT 24
Peak memory 265276 kb
Host smart-42a4c829-24b3-4122-8766-0429f99f128c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771499464 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.flash_ctrl_lcmgr_intg.771499464
Directory /workspace/5.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/5.flash_ctrl_mp_regions.737865195
Short name T635
Test name
Test status
Simulation time 4602502000 ps
CPU time 209.61 seconds
Started Mar 21 03:13:31 PM PDT 24
Finished Mar 21 03:17:02 PM PDT 24
Peak memory 262292 kb
Host smart-d536de16-5f2f-4aea-87a2-6801c657fe71
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737865195 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 5.flash_ctrl_mp_regions.737865195
Directory /workspace/5.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/5.flash_ctrl_otp_reset.856889342
Short name T837
Test name
Test status
Simulation time 82618600 ps
CPU time 133.5 seconds
Started Mar 21 03:13:31 PM PDT 24
Finished Mar 21 03:15:46 PM PDT 24
Peak memory 260076 kb
Host smart-8c1fed4f-673a-4dea-8d61-65cc206a676a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856889342 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_otp
_reset.856889342
Directory /workspace/5.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_phy_arb.17662110
Short name T118
Test name
Test status
Simulation time 198045800 ps
CPU time 240.65 seconds
Started Mar 21 03:13:32 PM PDT 24
Finished Mar 21 03:17:34 PM PDT 24
Peak memory 265232 kb
Host smart-51dc0078-41fd-4960-8eaf-2aff2b9b46d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=17662110 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.17662110
Directory /workspace/5.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/5.flash_ctrl_prog_reset.3736471614
Short name T740
Test name
Test status
Simulation time 43237800 ps
CPU time 13.7 seconds
Started Mar 21 03:13:42 PM PDT 24
Finished Mar 21 03:13:56 PM PDT 24
Peak memory 260140 kb
Host smart-2aa2df18-7a45-44bf-8252-83716a9cbaa1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736471614 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_prog_res
et.3736471614
Directory /workspace/5.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_rand_ops.1552504404
Short name T789
Test name
Test status
Simulation time 9410700600 ps
CPU time 933.26 seconds
Started Mar 21 03:13:31 PM PDT 24
Finished Mar 21 03:29:04 PM PDT 24
Peak memory 285404 kb
Host smart-cb0a9a28-c506-4f94-a59e-e73dd5bda9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552504404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.1552504404
Directory /workspace/5.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/5.flash_ctrl_re_evict.3253893867
Short name T932
Test name
Test status
Simulation time 170905900 ps
CPU time 35.23 seconds
Started Mar 21 03:13:42 PM PDT 24
Finished Mar 21 03:14:18 PM PDT 24
Peak memory 273596 kb
Host smart-06b5667a-98f5-4f52-99d1-9cbde1460fb7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253893867 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla
sh_ctrl_re_evict.3253893867
Directory /workspace/5.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro.2219193433
Short name T758
Test name
Test status
Simulation time 1087515600 ps
CPU time 129.18 seconds
Started Mar 21 03:13:32 PM PDT 24
Finished Mar 21 03:15:43 PM PDT 24
Peak memory 280992 kb
Host smart-f0bec9c1-72e2-4eef-9309-781f2925ebb3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219193433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.flash_ctrl_ro.2219193433
Directory /workspace/5.flash_ctrl_ro/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw.201546916
Short name T213
Test name
Test status
Simulation time 18174677900 ps
CPU time 512.33 seconds
Started Mar 21 03:13:33 PM PDT 24
Finished Mar 21 03:22:07 PM PDT 24
Peak memory 314440 kb
Host smart-d2bbbe05-2c25-4e12-8d73-9b572ad59b9c
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201546916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctr
l_rw.201546916
Directory /workspace/5.flash_ctrl_rw/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict.1887318903
Short name T534
Test name
Test status
Simulation time 184112700 ps
CPU time 31.93 seconds
Started Mar 21 03:13:43 PM PDT 24
Finished Mar 21 03:14:15 PM PDT 24
Peak memory 268144 kb
Host smart-7d93381c-c78b-408f-a648-4b5bee2395fe
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887318903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla
sh_ctrl_rw_evict.1887318903
Directory /workspace/5.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict_all_en.2677552646
Short name T923
Test name
Test status
Simulation time 28940300 ps
CPU time 31.96 seconds
Started Mar 21 03:13:41 PM PDT 24
Finished Mar 21 03:14:14 PM PDT 24
Peak memory 273588 kb
Host smart-15a157b1-adf2-4093-8e98-aca525a52eb9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677552646 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict_all_en.2677552646
Directory /workspace/5.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/5.flash_ctrl_sec_info_access.3257297830
Short name T692
Test name
Test status
Simulation time 7553590500 ps
CPU time 78.6 seconds
Started Mar 21 03:13:41 PM PDT 24
Finished Mar 21 03:14:59 PM PDT 24
Peak memory 263820 kb
Host smart-ac4d0e40-3a1c-4af7-b690-06e117f40194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257297830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.3257297830
Directory /workspace/5.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/5.flash_ctrl_smoke.2136965142
Short name T674
Test name
Test status
Simulation time 18679200 ps
CPU time 101.41 seconds
Started Mar 21 03:13:31 PM PDT 24
Finished Mar 21 03:15:14 PM PDT 24
Peak memory 276656 kb
Host smart-39a87930-a063-4f56-9ee3-5e055cd65b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136965142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.2136965142
Directory /workspace/5.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_wo.3421717245
Short name T861
Test name
Test status
Simulation time 17846600 ps
CPU time 14.03 seconds
Started Mar 21 03:13:30 PM PDT 24
Finished Mar 21 03:13:45 PM PDT 24
Peak memory 265188 kb
Host smart-d3eb10ed-9361-4d60-890b-c105ffd49116
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421717245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.flash_ctrl_wo.3421717245
Directory /workspace/5.flash_ctrl_wo/latest

Test location /workspace/coverage/default/50.flash_ctrl_connect.2605894509
Short name T446
Test name
Test status
Simulation time 57076400 ps
CPU time 15.82 seconds
Started Mar 21 03:20:25 PM PDT 24
Finished Mar 21 03:20:41 PM PDT 24
Peak memory 275712 kb
Host smart-26135682-9ad9-42eb-984e-f7cf29e839e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605894509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.2605894509
Directory /workspace/50.flash_ctrl_connect/latest

Test location /workspace/coverage/default/50.flash_ctrl_otp_reset.3676064126
Short name T613
Test name
Test status
Simulation time 67712300 ps
CPU time 110.56 seconds
Started Mar 21 03:20:33 PM PDT 24
Finished Mar 21 03:22:24 PM PDT 24
Peak memory 261116 kb
Host smart-02c9ec03-ae0e-42ca-b5e1-bebb060c6cbc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676064126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_o
tp_reset.3676064126
Directory /workspace/50.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/51.flash_ctrl_connect.1666135684
Short name T610
Test name
Test status
Simulation time 39862000 ps
CPU time 15.79 seconds
Started Mar 21 03:20:25 PM PDT 24
Finished Mar 21 03:20:41 PM PDT 24
Peak memory 275748 kb
Host smart-05057fee-a2b6-496a-8abc-d6609513f596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666135684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.1666135684
Directory /workspace/51.flash_ctrl_connect/latest

Test location /workspace/coverage/default/51.flash_ctrl_otp_reset.4186408078
Short name T461
Test name
Test status
Simulation time 104472600 ps
CPU time 111.81 seconds
Started Mar 21 03:20:25 PM PDT 24
Finished Mar 21 03:22:16 PM PDT 24
Peak memory 260968 kb
Host smart-01f01b0e-c9f0-411c-b3d2-be076a8c2a7b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186408078 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_o
tp_reset.4186408078
Directory /workspace/51.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/52.flash_ctrl_connect.2331489450
Short name T1010
Test name
Test status
Simulation time 24452500 ps
CPU time 15.79 seconds
Started Mar 21 03:20:26 PM PDT 24
Finished Mar 21 03:20:41 PM PDT 24
Peak memory 275072 kb
Host smart-f8efef13-bfbf-47cb-a1f3-81646b7c1113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331489450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.2331489450
Directory /workspace/52.flash_ctrl_connect/latest

Test location /workspace/coverage/default/52.flash_ctrl_otp_reset.944018818
Short name T669
Test name
Test status
Simulation time 40764900 ps
CPU time 111.73 seconds
Started Mar 21 03:20:25 PM PDT 24
Finished Mar 21 03:22:17 PM PDT 24
Peak memory 264520 kb
Host smart-2bb96845-717c-4f8c-80ce-4e6402391b88
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944018818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_ot
p_reset.944018818
Directory /workspace/52.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/53.flash_ctrl_connect.2847799568
Short name T310
Test name
Test status
Simulation time 24699000 ps
CPU time 16.45 seconds
Started Mar 21 03:20:31 PM PDT 24
Finished Mar 21 03:20:47 PM PDT 24
Peak memory 275076 kb
Host smart-b6ddb95a-7b52-444d-ae0f-8d8d2f1cf86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847799568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.2847799568
Directory /workspace/53.flash_ctrl_connect/latest

Test location /workspace/coverage/default/53.flash_ctrl_otp_reset.791179754
Short name T641
Test name
Test status
Simulation time 366276300 ps
CPU time 131.47 seconds
Started Mar 21 03:20:33 PM PDT 24
Finished Mar 21 03:22:45 PM PDT 24
Peak memory 261144 kb
Host smart-b02ca072-1612-47bc-b28d-b42803142f9f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791179754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_ot
p_reset.791179754
Directory /workspace/53.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/54.flash_ctrl_connect.1616304223
Short name T261
Test name
Test status
Simulation time 15861900 ps
CPU time 15.91 seconds
Started Mar 21 03:20:25 PM PDT 24
Finished Mar 21 03:20:41 PM PDT 24
Peak memory 275240 kb
Host smart-cc30c373-df9d-4879-ac58-bb65e759e2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616304223 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.1616304223
Directory /workspace/54.flash_ctrl_connect/latest

Test location /workspace/coverage/default/54.flash_ctrl_otp_reset.456186414
Short name T699
Test name
Test status
Simulation time 258080400 ps
CPU time 111.32 seconds
Started Mar 21 03:20:26 PM PDT 24
Finished Mar 21 03:22:18 PM PDT 24
Peak memory 260036 kb
Host smart-5f9911f4-9472-4a34-b4c3-48fd9a8c7fe1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456186414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_ot
p_reset.456186414
Directory /workspace/54.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/55.flash_ctrl_connect.4184024082
Short name T881
Test name
Test status
Simulation time 13120200 ps
CPU time 13.43 seconds
Started Mar 21 03:20:26 PM PDT 24
Finished Mar 21 03:20:39 PM PDT 24
Peak memory 275116 kb
Host smart-2bbf6537-c30f-4c9d-8592-f21f398f56e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184024082 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.4184024082
Directory /workspace/55.flash_ctrl_connect/latest

Test location /workspace/coverage/default/55.flash_ctrl_otp_reset.2767860747
Short name T616
Test name
Test status
Simulation time 152747000 ps
CPU time 115.08 seconds
Started Mar 21 03:20:26 PM PDT 24
Finished Mar 21 03:22:21 PM PDT 24
Peak memory 262244 kb
Host smart-d49b4566-1629-48c9-aff5-917b6eb5e3e1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767860747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_o
tp_reset.2767860747
Directory /workspace/55.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/56.flash_ctrl_connect.2234896688
Short name T414
Test name
Test status
Simulation time 16922800 ps
CPU time 15.68 seconds
Started Mar 21 03:20:26 PM PDT 24
Finished Mar 21 03:20:42 PM PDT 24
Peak memory 275748 kb
Host smart-f9b17764-fcae-4aed-a7f8-9e8e404f19fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234896688 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.2234896688
Directory /workspace/56.flash_ctrl_connect/latest

Test location /workspace/coverage/default/56.flash_ctrl_otp_reset.1638763040
Short name T146
Test name
Test status
Simulation time 44334900 ps
CPU time 113.07 seconds
Started Mar 21 03:20:27 PM PDT 24
Finished Mar 21 03:22:20 PM PDT 24
Peak memory 259908 kb
Host smart-2b0b189e-481d-498d-93d8-efb1653bd0fd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638763040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_o
tp_reset.1638763040
Directory /workspace/56.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/57.flash_ctrl_connect.2643559043
Short name T830
Test name
Test status
Simulation time 48882900 ps
CPU time 16.06 seconds
Started Mar 21 03:20:25 PM PDT 24
Finished Mar 21 03:20:42 PM PDT 24
Peak memory 275720 kb
Host smart-efb18ea7-22b3-4718-b5e5-89cbf7bf317a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643559043 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.2643559043
Directory /workspace/57.flash_ctrl_connect/latest

Test location /workspace/coverage/default/57.flash_ctrl_otp_reset.2968070812
Short name T795
Test name
Test status
Simulation time 39638500 ps
CPU time 133.24 seconds
Started Mar 21 03:20:25 PM PDT 24
Finished Mar 21 03:22:39 PM PDT 24
Peak memory 259864 kb
Host smart-919f1a75-2375-4414-94b1-afd1fbd0101d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968070812 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_o
tp_reset.2968070812
Directory /workspace/57.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/58.flash_ctrl_connect.215119001
Short name T527
Test name
Test status
Simulation time 15753900 ps
CPU time 16.36 seconds
Started Mar 21 03:20:25 PM PDT 24
Finished Mar 21 03:20:42 PM PDT 24
Peak memory 275120 kb
Host smart-4ec8fd1a-c0f3-428b-956b-0e12264c8393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215119001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.215119001
Directory /workspace/58.flash_ctrl_connect/latest

Test location /workspace/coverage/default/58.flash_ctrl_otp_reset.1940648634
Short name T978
Test name
Test status
Simulation time 142549400 ps
CPU time 131.39 seconds
Started Mar 21 03:20:27 PM PDT 24
Finished Mar 21 03:22:39 PM PDT 24
Peak memory 264240 kb
Host smart-1d9d6014-a5ba-4156-830a-96d3268a9593
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940648634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_o
tp_reset.1940648634
Directory /workspace/58.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/59.flash_ctrl_connect.2082580599
Short name T1036
Test name
Test status
Simulation time 187568800 ps
CPU time 15.92 seconds
Started Mar 21 03:20:27 PM PDT 24
Finished Mar 21 03:20:43 PM PDT 24
Peak memory 275236 kb
Host smart-f11226e7-bca3-4154-ab27-a405cb891852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082580599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.2082580599
Directory /workspace/59.flash_ctrl_connect/latest

Test location /workspace/coverage/default/59.flash_ctrl_otp_reset.3777896909
Short name T649
Test name
Test status
Simulation time 251376400 ps
CPU time 134.82 seconds
Started Mar 21 03:20:26 PM PDT 24
Finished Mar 21 03:22:41 PM PDT 24
Peak memory 260044 kb
Host smart-fa3eedb7-dafa-4518-ad58-4e6188de31b3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777896909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_o
tp_reset.3777896909
Directory /workspace/59.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_alert_test.3007372705
Short name T829
Test name
Test status
Simulation time 35456700 ps
CPU time 13.81 seconds
Started Mar 21 03:14:22 PM PDT 24
Finished Mar 21 03:14:36 PM PDT 24
Peak memory 258304 kb
Host smart-ba6547a9-6793-4c83-bcdb-31a7e50cd364
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007372705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.3
007372705
Directory /workspace/6.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.flash_ctrl_connect.512714986
Short name T944
Test name
Test status
Simulation time 236733800 ps
CPU time 13.47 seconds
Started Mar 21 03:14:22 PM PDT 24
Finished Mar 21 03:14:36 PM PDT 24
Peak memory 275968 kb
Host smart-0315eb7e-b806-4b64-bc20-17908dd6f9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512714986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.512714986
Directory /workspace/6.flash_ctrl_connect/latest

Test location /workspace/coverage/default/6.flash_ctrl_disable.1524541220
Short name T77
Test name
Test status
Simulation time 10355400 ps
CPU time 22.03 seconds
Started Mar 21 03:14:19 PM PDT 24
Finished Mar 21 03:14:41 PM PDT 24
Peak memory 273584 kb
Host smart-a8d70d89-022d-4f5c-bafe-1aac724213c8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524541220 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_disable.1524541220
Directory /workspace/6.flash_ctrl_disable/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_mp.247244356
Short name T917
Test name
Test status
Simulation time 14263226100 ps
CPU time 2103.74 seconds
Started Mar 21 03:14:01 PM PDT 24
Finished Mar 21 03:49:05 PM PDT 24
Peak memory 263944 kb
Host smart-cf938728-0958-4d64-a03c-e11420456de9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247244356 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_erro
r_mp.247244356
Directory /workspace/6.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_prog_win.2594301241
Short name T578
Test name
Test status
Simulation time 1701886000 ps
CPU time 881.74 seconds
Started Mar 21 03:14:01 PM PDT 24
Finished Mar 21 03:28:43 PM PDT 24
Peak memory 273404 kb
Host smart-ed04184f-2062-4d19-b568-1afeb3db08d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594301241 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.2594301241
Directory /workspace/6.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/6.flash_ctrl_fetch_code.3645693541
Short name T678
Test name
Test status
Simulation time 315459600 ps
CPU time 23.19 seconds
Started Mar 21 03:14:03 PM PDT 24
Finished Mar 21 03:14:26 PM PDT 24
Peak memory 265180 kb
Host smart-caf87f1e-e492-40b1-93d6-cce47b5bdbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645693541 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetch_code.3645693541
Directory /workspace/6.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.71201838
Short name T871
Test name
Test status
Simulation time 10012678900 ps
CPU time 142.74 seconds
Started Mar 21 03:14:18 PM PDT 24
Finished Mar 21 03:16:41 PM PDT 24
Peak memory 375376 kb
Host smart-bd55f6e4-50c0-49de-ada7-27e38bb014ac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71201838 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.71201838
Directory /workspace/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_read_seed_err.937081251
Short name T132
Test name
Test status
Simulation time 37119600 ps
CPU time 13.68 seconds
Started Mar 21 03:14:16 PM PDT 24
Finished Mar 21 03:14:30 PM PDT 24
Peak memory 265304 kb
Host smart-839bfc23-1b7c-423e-8514-327255ffba21
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937081251 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_seed_err.937081251
Directory /workspace/6.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_rma_reset.1743616069
Short name T156
Test name
Test status
Simulation time 40119675800 ps
CPU time 817.78 seconds
Started Mar 21 03:14:02 PM PDT 24
Finished Mar 21 03:27:40 PM PDT 24
Peak memory 264556 kb
Host smart-892b4625-f7c2-48cd-ac37-16f5dfb810a8
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743616069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.flash_ctrl_hw_rma_reset.1743616069
Directory /workspace/6.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_sec_otp.149970912
Short name T320
Test name
Test status
Simulation time 2153462400 ps
CPU time 97.27 seconds
Started Mar 21 03:14:06 PM PDT 24
Finished Mar 21 03:15:43 PM PDT 24
Peak memory 262680 kb
Host smart-cc303f49-6d6b-40d2-a63e-7d8764ac157e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149970912 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw
_sec_otp.149970912
Directory /workspace/6.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd_slow_flash.2150233285
Short name T587
Test name
Test status
Simulation time 8575394200 ps
CPU time 205.49 seconds
Started Mar 21 03:14:03 PM PDT 24
Finished Mar 21 03:17:29 PM PDT 24
Peak memory 284644 kb
Host smart-0f04c0a9-ad3e-429f-bfec-729f28a5d83c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150233285 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd_slow_flash.2150233285
Directory /workspace/6.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr.1692217642
Short name T668
Test name
Test status
Simulation time 4332090100 ps
CPU time 107.51 seconds
Started Mar 21 03:14:04 PM PDT 24
Finished Mar 21 03:15:51 PM PDT 24
Peak memory 260900 kb
Host smart-4fd684d0-bce9-498c-a2ec-7116874141bd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692217642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.flash_ctrl_intr_wr.1692217642
Directory /workspace/6.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.4046190847
Short name T605
Test name
Test status
Simulation time 90095660200 ps
CPU time 363.79 seconds
Started Mar 21 03:14:01 PM PDT 24
Finished Mar 21 03:20:05 PM PDT 24
Peak memory 261152 kb
Host smart-cf809b27-c107-4368-b260-5a4427dcc6f7
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404
6190847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.4046190847
Directory /workspace/6.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_invalid_op.1116644382
Short name T402
Test name
Test status
Simulation time 1698883200 ps
CPU time 79.78 seconds
Started Mar 21 03:14:06 PM PDT 24
Finished Mar 21 03:15:26 PM PDT 24
Peak memory 259968 kb
Host smart-894520b1-acd6-45ab-b4bd-db338fc6aa4d
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116644382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.1116644382
Directory /workspace/6.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/6.flash_ctrl_mp_regions.1260080172
Short name T27
Test name
Test status
Simulation time 65797150400 ps
CPU time 314.99 seconds
Started Mar 21 03:14:03 PM PDT 24
Finished Mar 21 03:19:18 PM PDT 24
Peak memory 274092 kb
Host smart-1275962d-8df2-4563-92a3-746213e177d6
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260080172 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 6.flash_ctrl_mp_regions.1260080172
Directory /workspace/6.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/6.flash_ctrl_otp_reset.1477057266
Short name T698
Test name
Test status
Simulation time 132008500 ps
CPU time 131.28 seconds
Started Mar 21 03:14:05 PM PDT 24
Finished Mar 21 03:16:16 PM PDT 24
Peak memory 259620 kb
Host smart-7c5bc451-84c9-46d4-9589-fae73eea8bf8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477057266 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ot
p_reset.1477057266
Directory /workspace/6.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_phy_arb.1505548505
Short name T593
Test name
Test status
Simulation time 53260100 ps
CPU time 154.81 seconds
Started Mar 21 03:14:05 PM PDT 24
Finished Mar 21 03:16:40 PM PDT 24
Peak memory 265168 kb
Host smart-0f3ef515-5759-4b7f-8d58-1bac8fd91ad5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1505548505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.1505548505
Directory /workspace/6.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/6.flash_ctrl_prog_reset.2156829371
Short name T776
Test name
Test status
Simulation time 59651500 ps
CPU time 14.67 seconds
Started Mar 21 03:14:05 PM PDT 24
Finished Mar 21 03:14:20 PM PDT 24
Peak memory 260660 kb
Host smart-5ecdb1cf-5412-4670-b0ad-00c4142548a8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156829371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_prog_res
et.2156829371
Directory /workspace/6.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_rand_ops.1911338448
Short name T471
Test name
Test status
Simulation time 82438300 ps
CPU time 401.53 seconds
Started Mar 21 03:14:03 PM PDT 24
Finished Mar 21 03:20:45 PM PDT 24
Peak memory 278920 kb
Host smart-8c6e499f-65a7-435a-b317-723aa2c6408a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911338448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.1911338448
Directory /workspace/6.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/6.flash_ctrl_re_evict.927988388
Short name T680
Test name
Test status
Simulation time 441852000 ps
CPU time 36.8 seconds
Started Mar 21 03:14:15 PM PDT 24
Finished Mar 21 03:14:52 PM PDT 24
Peak memory 273532 kb
Host smart-d8e58847-5b88-41e7-9940-e34465c97d5a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927988388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas
h_ctrl_re_evict.927988388
Directory /workspace/6.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro.755550407
Short name T53
Test name
Test status
Simulation time 416211800 ps
CPU time 119.99 seconds
Started Mar 21 03:14:05 PM PDT 24
Finished Mar 21 03:16:05 PM PDT 24
Peak memory 281052 kb
Host smart-752635f9-e125-42c3-9c48-e0eaeb4806ed
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755550407 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.flash_ctrl_ro.755550407
Directory /workspace/6.flash_ctrl_ro/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_derr.1351111008
Short name T195
Test name
Test status
Simulation time 1872909700 ps
CPU time 135.51 seconds
Started Mar 21 03:14:01 PM PDT 24
Finished Mar 21 03:16:17 PM PDT 24
Peak memory 281792 kb
Host smart-92d33d09-83d0-4a0b-9fb6-de7a29dc3042
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1351111008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.1351111008
Directory /workspace/6.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_serr.3470766675
Short name T110
Test name
Test status
Simulation time 2193908200 ps
CPU time 131.91 seconds
Started Mar 21 03:14:02 PM PDT 24
Finished Mar 21 03:16:14 PM PDT 24
Peak memory 290036 kb
Host smart-21407f94-68bf-41fc-8afc-c120075ca1f3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470766675 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.flash_ctrl_ro_serr.3470766675
Directory /workspace/6.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw.1874181008
Short name T643
Test name
Test status
Simulation time 37372297400 ps
CPU time 581.23 seconds
Started Mar 21 03:14:03 PM PDT 24
Finished Mar 21 03:23:44 PM PDT 24
Peak memory 314452 kb
Host smart-a5c6a875-e549-4c0b-9c73-846b18b61530
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874181008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ct
rl_rw.1874181008
Directory /workspace/6.flash_ctrl_rw/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict.519457745
Short name T1001
Test name
Test status
Simulation time 54329900 ps
CPU time 31.51 seconds
Started Mar 21 03:14:15 PM PDT 24
Finished Mar 21 03:14:47 PM PDT 24
Peak memory 266544 kb
Host smart-5554431a-295c-4fd0-8f2d-aedfc800efbb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519457745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas
h_ctrl_rw_evict.519457745
Directory /workspace/6.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict_all_en.103348444
Short name T952
Test name
Test status
Simulation time 132950800 ps
CPU time 30.66 seconds
Started Mar 21 03:14:16 PM PDT 24
Finished Mar 21 03:14:47 PM PDT 24
Peak memory 266464 kb
Host smart-d1ace5c3-b228-4c65-b3f2-e141a9935261
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103348444 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict_all_en.103348444
Directory /workspace/6.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_serr.149176808
Short name T204
Test name
Test status
Simulation time 7932519400 ps
CPU time 471.52 seconds
Started Mar 21 03:14:02 PM PDT 24
Finished Mar 21 03:21:54 PM PDT 24
Peak memory 320352 kb
Host smart-c10382c4-0dbc-4afb-8588-585c716b5bda
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149176808 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_se
rr.149176808
Directory /workspace/6.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_sec_info_access.3621414545
Short name T572
Test name
Test status
Simulation time 4758657500 ps
CPU time 63.91 seconds
Started Mar 21 03:14:18 PM PDT 24
Finished Mar 21 03:15:22 PM PDT 24
Peak memory 263312 kb
Host smart-2ca774cf-0784-402b-b778-73042d4dd7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621414545 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.3621414545
Directory /workspace/6.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/6.flash_ctrl_smoke.4242690825
Short name T665
Test name
Test status
Simulation time 686105600 ps
CPU time 139.9 seconds
Started Mar 21 03:14:03 PM PDT 24
Finished Mar 21 03:16:23 PM PDT 24
Peak memory 281528 kb
Host smart-18ddbffa-cf52-4d7d-9998-c7dd5991bb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242690825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.4242690825
Directory /workspace/6.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/6.flash_ctrl_wo.707070206
Short name T1003
Test name
Test status
Simulation time 1800063700 ps
CPU time 133.02 seconds
Started Mar 21 03:14:01 PM PDT 24
Finished Mar 21 03:16:14 PM PDT 24
Peak memory 259108 kb
Host smart-fa759790-6bee-44c6-9d39-93d9f4efc234
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707070206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.flash_ctrl_wo.707070206
Directory /workspace/6.flash_ctrl_wo/latest

Test location /workspace/coverage/default/60.flash_ctrl_connect.1490932618
Short name T615
Test name
Test status
Simulation time 79612700 ps
CPU time 15.82 seconds
Started Mar 21 03:20:37 PM PDT 24
Finished Mar 21 03:20:54 PM PDT 24
Peak memory 275716 kb
Host smart-a084359a-da25-41a1-8b3e-1e2c3add1c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490932618 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.1490932618
Directory /workspace/60.flash_ctrl_connect/latest

Test location /workspace/coverage/default/60.flash_ctrl_otp_reset.2856402760
Short name T551
Test name
Test status
Simulation time 68209000 ps
CPU time 133.77 seconds
Started Mar 21 03:20:28 PM PDT 24
Finished Mar 21 03:22:42 PM PDT 24
Peak memory 263616 kb
Host smart-61838247-ecc7-4a54-8dab-3fdca2be582c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856402760 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_o
tp_reset.2856402760
Directory /workspace/60.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/61.flash_ctrl_connect.2187011779
Short name T176
Test name
Test status
Simulation time 38113300 ps
CPU time 16.07 seconds
Started Mar 21 03:20:38 PM PDT 24
Finished Mar 21 03:20:55 PM PDT 24
Peak memory 275804 kb
Host smart-b4f2c400-0fce-4f86-90f8-a4ae7575d225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187011779 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.2187011779
Directory /workspace/61.flash_ctrl_connect/latest

Test location /workspace/coverage/default/61.flash_ctrl_otp_reset.2512998114
Short name T489
Test name
Test status
Simulation time 182193900 ps
CPU time 133.49 seconds
Started Mar 21 03:20:37 PM PDT 24
Finished Mar 21 03:22:51 PM PDT 24
Peak memory 261104 kb
Host smart-95734684-b3ae-4a17-b4b9-c27fb849062c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512998114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_o
tp_reset.2512998114
Directory /workspace/61.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/62.flash_ctrl_connect.2337999202
Short name T481
Test name
Test status
Simulation time 26115000 ps
CPU time 13.79 seconds
Started Mar 21 03:20:39 PM PDT 24
Finished Mar 21 03:20:54 PM PDT 24
Peak memory 275172 kb
Host smart-3a6fba7c-13a0-45a4-8d76-0837b32bed93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337999202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.2337999202
Directory /workspace/62.flash_ctrl_connect/latest

Test location /workspace/coverage/default/62.flash_ctrl_otp_reset.1864603523
Short name T751
Test name
Test status
Simulation time 43782600 ps
CPU time 134.63 seconds
Started Mar 21 03:20:38 PM PDT 24
Finished Mar 21 03:22:53 PM PDT 24
Peak memory 263528 kb
Host smart-080371bd-cee6-425f-8db5-dfeee2d4a385
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864603523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_o
tp_reset.1864603523
Directory /workspace/62.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/63.flash_ctrl_connect.342153352
Short name T889
Test name
Test status
Simulation time 26277700 ps
CPU time 15.69 seconds
Started Mar 21 03:20:39 PM PDT 24
Finished Mar 21 03:20:55 PM PDT 24
Peak memory 275120 kb
Host smart-b95e30d3-d87d-42d6-a37b-3d70f43ece30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342153352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.342153352
Directory /workspace/63.flash_ctrl_connect/latest

Test location /workspace/coverage/default/63.flash_ctrl_otp_reset.1527115539
Short name T321
Test name
Test status
Simulation time 41642700 ps
CPU time 137.47 seconds
Started Mar 21 03:20:40 PM PDT 24
Finished Mar 21 03:22:58 PM PDT 24
Peak memory 261088 kb
Host smart-a2910dcd-8c73-48e9-8d9c-1bad72b55286
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527115539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_o
tp_reset.1527115539
Directory /workspace/63.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/64.flash_ctrl_connect.1974609514
Short name T415
Test name
Test status
Simulation time 27143700 ps
CPU time 16.07 seconds
Started Mar 21 03:20:43 PM PDT 24
Finished Mar 21 03:20:59 PM PDT 24
Peak memory 275712 kb
Host smart-3546a0f2-e175-4e90-bc34-44a7252143f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974609514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.1974609514
Directory /workspace/64.flash_ctrl_connect/latest

Test location /workspace/coverage/default/64.flash_ctrl_otp_reset.2032496906
Short name T712
Test name
Test status
Simulation time 176281200 ps
CPU time 132.67 seconds
Started Mar 21 03:20:39 PM PDT 24
Finished Mar 21 03:22:52 PM PDT 24
Peak memory 259696 kb
Host smart-e6783a69-e682-4f73-9e1b-a4fdb4b5d5ae
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032496906 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_o
tp_reset.2032496906
Directory /workspace/64.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/65.flash_ctrl_connect.2261100417
Short name T574
Test name
Test status
Simulation time 16543000 ps
CPU time 15.63 seconds
Started Mar 21 03:20:38 PM PDT 24
Finished Mar 21 03:20:54 PM PDT 24
Peak memory 276052 kb
Host smart-03c17208-8d80-45c0-ba90-c789aeab8c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261100417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.2261100417
Directory /workspace/65.flash_ctrl_connect/latest

Test location /workspace/coverage/default/65.flash_ctrl_otp_reset.1885220213
Short name T88
Test name
Test status
Simulation time 72444200 ps
CPU time 132.06 seconds
Started Mar 21 03:20:40 PM PDT 24
Finished Mar 21 03:22:53 PM PDT 24
Peak memory 264672 kb
Host smart-5964b5c0-008e-4a53-bba2-3804ea67cb84
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885220213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_o
tp_reset.1885220213
Directory /workspace/65.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/66.flash_ctrl_connect.2112385928
Short name T479
Test name
Test status
Simulation time 16009200 ps
CPU time 16.17 seconds
Started Mar 21 03:20:39 PM PDT 24
Finished Mar 21 03:20:57 PM PDT 24
Peak memory 275156 kb
Host smart-f45c2ac9-0bfe-4f4a-a50a-190804abb19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112385928 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.2112385928
Directory /workspace/66.flash_ctrl_connect/latest

Test location /workspace/coverage/default/66.flash_ctrl_otp_reset.3379878672
Short name T796
Test name
Test status
Simulation time 63373400 ps
CPU time 131.78 seconds
Started Mar 21 03:20:38 PM PDT 24
Finished Mar 21 03:22:50 PM PDT 24
Peak memory 260088 kb
Host smart-9fee39d1-d68f-4d93-961f-c3fb880f0f25
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379878672 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_o
tp_reset.3379878672
Directory /workspace/66.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/67.flash_ctrl_connect.1385756129
Short name T654
Test name
Test status
Simulation time 13725100 ps
CPU time 15.79 seconds
Started Mar 21 03:20:38 PM PDT 24
Finished Mar 21 03:20:54 PM PDT 24
Peak memory 275724 kb
Host smart-b8d70e02-06a8-4fd8-8700-6be9bad14571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385756129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.1385756129
Directory /workspace/67.flash_ctrl_connect/latest

Test location /workspace/coverage/default/67.flash_ctrl_otp_reset.1428052796
Short name T956
Test name
Test status
Simulation time 53206600 ps
CPU time 113.22 seconds
Started Mar 21 03:20:38 PM PDT 24
Finished Mar 21 03:22:32 PM PDT 24
Peak memory 261008 kb
Host smart-665935a2-48f7-4d5c-9f28-b56704ed2334
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428052796 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_o
tp_reset.1428052796
Directory /workspace/67.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/68.flash_ctrl_connect.1332661459
Short name T1014
Test name
Test status
Simulation time 48880200 ps
CPU time 15.72 seconds
Started Mar 21 03:20:38 PM PDT 24
Finished Mar 21 03:20:54 PM PDT 24
Peak memory 275220 kb
Host smart-2f59040b-105c-476a-b38c-78b8c1d527e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332661459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.1332661459
Directory /workspace/68.flash_ctrl_connect/latest

Test location /workspace/coverage/default/68.flash_ctrl_otp_reset.587827515
Short name T783
Test name
Test status
Simulation time 139755600 ps
CPU time 133.07 seconds
Started Mar 21 03:20:37 PM PDT 24
Finished Mar 21 03:22:51 PM PDT 24
Peak memory 259900 kb
Host smart-86a2c3a5-aba1-43d4-bc80-2e512d926f9f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587827515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_ot
p_reset.587827515
Directory /workspace/68.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/69.flash_ctrl_connect.673418330
Short name T607
Test name
Test status
Simulation time 25738500 ps
CPU time 16.25 seconds
Started Mar 21 03:20:43 PM PDT 24
Finished Mar 21 03:21:00 PM PDT 24
Peak memory 275296 kb
Host smart-24af3724-74e7-41c6-989e-ab14b2035f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673418330 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.673418330
Directory /workspace/69.flash_ctrl_connect/latest

Test location /workspace/coverage/default/69.flash_ctrl_otp_reset.89001920
Short name T519
Test name
Test status
Simulation time 79778900 ps
CPU time 112.01 seconds
Started Mar 21 03:20:37 PM PDT 24
Finished Mar 21 03:22:30 PM PDT 24
Peak memory 259748 kb
Host smart-28cff418-cbbc-4a84-a850-ac499c6043b6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89001920 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_otp
_reset.89001920
Directory /workspace/69.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_alert_test.4127118668
Short name T543
Test name
Test status
Simulation time 257057700 ps
CPU time 15.4 seconds
Started Mar 21 03:14:27 PM PDT 24
Finished Mar 21 03:14:43 PM PDT 24
Peak memory 259168 kb
Host smart-f76bfeaf-6866-4301-bb3e-acd891409eb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127118668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.4
127118668
Directory /workspace/7.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.flash_ctrl_connect.2861005321
Short name T434
Test name
Test status
Simulation time 42518900 ps
CPU time 16.64 seconds
Started Mar 21 03:14:25 PM PDT 24
Finished Mar 21 03:14:42 PM PDT 24
Peak memory 275640 kb
Host smart-1a909e14-4bd5-4c08-93bc-28be00a443b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861005321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.2861005321
Directory /workspace/7.flash_ctrl_connect/latest

Test location /workspace/coverage/default/7.flash_ctrl_disable.540409288
Short name T40
Test name
Test status
Simulation time 80173900 ps
CPU time 22.66 seconds
Started Mar 21 03:14:23 PM PDT 24
Finished Mar 21 03:14:46 PM PDT 24
Peak memory 265260 kb
Host smart-c025bbcf-11b1-4c22-8847-497c125acd3e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540409288 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_disable.540409288
Directory /workspace/7.flash_ctrl_disable/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_mp.738915687
Short name T232
Test name
Test status
Simulation time 14025159700 ps
CPU time 2333.26 seconds
Started Mar 21 03:14:16 PM PDT 24
Finished Mar 21 03:53:09 PM PDT 24
Peak memory 262092 kb
Host smart-6eee1baf-0086-478b-8235-4c7c10199e06
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738915687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_erro
r_mp.738915687
Directory /workspace/7.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_prog_win.3967419481
Short name T831
Test name
Test status
Simulation time 1272610500 ps
CPU time 803.6 seconds
Started Mar 21 03:14:19 PM PDT 24
Finished Mar 21 03:27:43 PM PDT 24
Peak memory 265200 kb
Host smart-36bbb198-6d98-41cf-af97-239bede5e4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967419481 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.3967419481
Directory /workspace/7.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/7.flash_ctrl_fetch_code.2450813561
Short name T565
Test name
Test status
Simulation time 884612300 ps
CPU time 26.23 seconds
Started Mar 21 03:14:16 PM PDT 24
Finished Mar 21 03:14:43 PM PDT 24
Peak memory 265224 kb
Host smart-ca20d0f7-7b70-48f4-b4df-6264cfe1efa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450813561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetch_code.2450813561
Directory /workspace/7.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.3950886778
Short name T523
Test name
Test status
Simulation time 10025598800 ps
CPU time 145.72 seconds
Started Mar 21 03:14:23 PM PDT 24
Finished Mar 21 03:16:49 PM PDT 24
Peak memory 285552 kb
Host smart-d5d14c9e-161a-4072-9980-d173314e5044
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950886778 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.3950886778
Directory /workspace/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_read_seed_err.280363993
Short name T916
Test name
Test status
Simulation time 127693200 ps
CPU time 14 seconds
Started Mar 21 03:14:22 PM PDT 24
Finished Mar 21 03:14:36 PM PDT 24
Peak memory 265304 kb
Host smart-a71bf4ba-dbab-49a1-ae3d-84f81829f96a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280363993 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_read_seed_err.280363993
Directory /workspace/7.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_rma_reset.799312998
Short name T504
Test name
Test status
Simulation time 50127139300 ps
CPU time 971.28 seconds
Started Mar 21 03:14:18 PM PDT 24
Finished Mar 21 03:30:29 PM PDT 24
Peak memory 263848 kb
Host smart-58b6a063-52cf-4850-88d1-410cfe89d4bb
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799312998 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.flash_ctrl_hw_rma_reset.799312998
Directory /workspace/7.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_sec_otp.1511091937
Short name T822
Test name
Test status
Simulation time 5739027300 ps
CPU time 204.91 seconds
Started Mar 21 03:14:15 PM PDT 24
Finished Mar 21 03:17:41 PM PDT 24
Peak memory 262484 kb
Host smart-20884c6b-efb7-4e00-af64-bcbfa515a0a7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511091937 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_h
w_sec_otp.1511091937
Directory /workspace/7.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd.2719735451
Short name T1006
Test name
Test status
Simulation time 4317353400 ps
CPU time 168.31 seconds
Started Mar 21 03:14:25 PM PDT 24
Finished Mar 21 03:17:13 PM PDT 24
Peak memory 294052 kb
Host smart-8427d215-51b7-4276-86ec-180030f77419
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719735451 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas
h_ctrl_intr_rd.2719735451
Directory /workspace/7.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd_slow_flash.3768750755
Short name T529
Test name
Test status
Simulation time 16832768300 ps
CPU time 195.22 seconds
Started Mar 21 03:14:29 PM PDT 24
Finished Mar 21 03:17:44 PM PDT 24
Peak memory 289800 kb
Host smart-73c77bd6-fa8e-4db3-b31b-7af0331003d9
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768750755 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd_slow_flash.3768750755
Directory /workspace/7.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr.190691809
Short name T787
Test name
Test status
Simulation time 3179721400 ps
CPU time 78.8 seconds
Started Mar 21 03:14:25 PM PDT 24
Finished Mar 21 03:15:44 PM PDT 24
Peak memory 261008 kb
Host smart-d505bc04-4f88-440f-9e7d-d635441a8f8a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190691809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 7.flash_ctrl_intr_wr.190691809
Directory /workspace/7.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr_slow_flash.2718997949
Short name T485
Test name
Test status
Simulation time 46814313200 ps
CPU time 377.02 seconds
Started Mar 21 03:14:24 PM PDT 24
Finished Mar 21 03:20:42 PM PDT 24
Peak memory 261436 kb
Host smart-1d4568a9-1d1e-44da-9138-3c763f2d4744
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271
8997949 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.2718997949
Directory /workspace/7.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_invalid_op.3827847948
Short name T535
Test name
Test status
Simulation time 4294499300 ps
CPU time 67.87 seconds
Started Mar 21 03:14:20 PM PDT 24
Finished Mar 21 03:15:28 PM PDT 24
Peak memory 263528 kb
Host smart-b0709f60-e941-4317-8b99-b04077e49463
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827847948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.3827847948
Directory /workspace/7.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/7.flash_ctrl_lcmgr_intg.3819245734
Short name T631
Test name
Test status
Simulation time 47795500 ps
CPU time 13.61 seconds
Started Mar 21 03:14:26 PM PDT 24
Finished Mar 21 03:14:39 PM PDT 24
Peak memory 265160 kb
Host smart-b9492255-7daa-4e47-8a85-5c32ecb2fa0d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819245734 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.flash_ctrl_lcmgr_intg.3819245734
Directory /workspace/7.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/7.flash_ctrl_mp_regions.2794546290
Short name T695
Test name
Test status
Simulation time 8793350400 ps
CPU time 287.05 seconds
Started Mar 21 03:14:16 PM PDT 24
Finished Mar 21 03:19:03 PM PDT 24
Peak memory 273912 kb
Host smart-147b36ad-36bf-4141-9814-44ffa8f25cf6
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794546290 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 7.flash_ctrl_mp_regions.2794546290
Directory /workspace/7.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/7.flash_ctrl_otp_reset.579902929
Short name T835
Test name
Test status
Simulation time 142725300 ps
CPU time 136.35 seconds
Started Mar 21 03:14:18 PM PDT 24
Finished Mar 21 03:16:34 PM PDT 24
Peak memory 264036 kb
Host smart-f1907c61-20f9-4ddb-91c0-83c5dd36cb91
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579902929 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_otp
_reset.579902929
Directory /workspace/7.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_phy_arb.2248016417
Short name T61
Test name
Test status
Simulation time 1371922600 ps
CPU time 450.65 seconds
Started Mar 21 03:14:16 PM PDT 24
Finished Mar 21 03:21:47 PM PDT 24
Peak memory 261504 kb
Host smart-409340d0-75ff-4f1f-8ce5-58b43349c17c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2248016417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.2248016417
Directory /workspace/7.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/7.flash_ctrl_prog_reset.2822292743
Short name T859
Test name
Test status
Simulation time 38110400 ps
CPU time 13.56 seconds
Started Mar 21 03:14:23 PM PDT 24
Finished Mar 21 03:14:37 PM PDT 24
Peak memory 265164 kb
Host smart-25bd4deb-51fc-4b19-b8cb-9a0de645eb8e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822292743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_prog_res
et.2822292743
Directory /workspace/7.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_rand_ops.3365663380
Short name T508
Test name
Test status
Simulation time 268470700 ps
CPU time 1052.62 seconds
Started Mar 21 03:14:19 PM PDT 24
Finished Mar 21 03:31:52 PM PDT 24
Peak memory 288476 kb
Host smart-fdfd0746-e912-4a78-8966-18d2d5e9f5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365663380 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.3365663380
Directory /workspace/7.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/7.flash_ctrl_re_evict.276745408
Short name T436
Test name
Test status
Simulation time 235236800 ps
CPU time 38.18 seconds
Started Mar 21 03:14:27 PM PDT 24
Finished Mar 21 03:15:05 PM PDT 24
Peak memory 266400 kb
Host smart-539f08b7-8d57-4cec-b369-128dd7dcade2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276745408 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas
h_ctrl_re_evict.276745408
Directory /workspace/7.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro.3288496772
Short name T1
Test name
Test status
Simulation time 1791524900 ps
CPU time 97.88 seconds
Started Mar 21 03:14:19 PM PDT 24
Finished Mar 21 03:15:57 PM PDT 24
Peak memory 281112 kb
Host smart-bff5ebeb-dfa7-4e77-a04e-190db9b2400b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288496772 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.flash_ctrl_ro.3288496772
Directory /workspace/7.flash_ctrl_ro/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw.1008281616
Short name T756
Test name
Test status
Simulation time 17346965600 ps
CPU time 545.48 seconds
Started Mar 21 03:14:18 PM PDT 24
Finished Mar 21 03:23:24 PM PDT 24
Peak memory 314256 kb
Host smart-b86de6d6-5832-440c-889b-5b8b93317889
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008281616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ct
rl_rw.1008281616
Directory /workspace/7.flash_ctrl_rw/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict.698070631
Short name T209
Test name
Test status
Simulation time 46996200 ps
CPU time 31.51 seconds
Started Mar 21 03:14:24 PM PDT 24
Finished Mar 21 03:14:56 PM PDT 24
Peak memory 273560 kb
Host smart-ede4f9ac-7351-4a9f-8b5a-6d09e8a6866a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698070631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas
h_ctrl_rw_evict.698070631
Directory /workspace/7.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict_all_en.2688630342
Short name T997
Test name
Test status
Simulation time 39320500 ps
CPU time 30.64 seconds
Started Mar 21 03:14:24 PM PDT 24
Finished Mar 21 03:14:55 PM PDT 24
Peak memory 273560 kb
Host smart-3de1383c-8416-4c34-bfea-8ffc701e1ac4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688630342 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict_all_en.2688630342
Directory /workspace/7.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/7.flash_ctrl_sec_info_access.1259037462
Short name T468
Test name
Test status
Simulation time 411868700 ps
CPU time 56.02 seconds
Started Mar 21 03:14:25 PM PDT 24
Finished Mar 21 03:15:21 PM PDT 24
Peak memory 263272 kb
Host smart-26504c77-1d92-47e8-a173-b5b3bb02b2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259037462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.1259037462
Directory /workspace/7.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/7.flash_ctrl_smoke.3157770454
Short name T867
Test name
Test status
Simulation time 112177800 ps
CPU time 122.96 seconds
Started Mar 21 03:14:15 PM PDT 24
Finished Mar 21 03:16:18 PM PDT 24
Peak memory 275692 kb
Host smart-2a90b51c-d023-40fb-af93-dc1db389490e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157770454 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.3157770454
Directory /workspace/7.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/7.flash_ctrl_wo.1122393485
Short name T711
Test name
Test status
Simulation time 7790097200 ps
CPU time 179.61 seconds
Started Mar 21 03:14:15 PM PDT 24
Finished Mar 21 03:17:15 PM PDT 24
Peak memory 259072 kb
Host smart-58410d3c-9d9d-496e-85d9-92af7b929dde
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122393485 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.flash_ctrl_wo.1122393485
Directory /workspace/7.flash_ctrl_wo/latest

Test location /workspace/coverage/default/70.flash_ctrl_connect.3642640144
Short name T425
Test name
Test status
Simulation time 22363900 ps
CPU time 16.14 seconds
Started Mar 21 03:20:38 PM PDT 24
Finished Mar 21 03:20:55 PM PDT 24
Peak memory 275684 kb
Host smart-1e9a672a-4440-45fe-bd39-ae478c31fde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642640144 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.3642640144
Directory /workspace/70.flash_ctrl_connect/latest

Test location /workspace/coverage/default/70.flash_ctrl_otp_reset.3448022130
Short name T702
Test name
Test status
Simulation time 699189400 ps
CPU time 132.26 seconds
Started Mar 21 03:20:38 PM PDT 24
Finished Mar 21 03:22:51 PM PDT 24
Peak memory 261116 kb
Host smart-262f19ea-04b2-41ee-9d0f-95143df07fcb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448022130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_o
tp_reset.3448022130
Directory /workspace/70.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/71.flash_ctrl_connect.323037180
Short name T759
Test name
Test status
Simulation time 14927300 ps
CPU time 16.46 seconds
Started Mar 21 03:20:38 PM PDT 24
Finished Mar 21 03:20:55 PM PDT 24
Peak memory 275704 kb
Host smart-0d4dfb3b-b06e-454f-a0f9-1753c2f50e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323037180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.323037180
Directory /workspace/71.flash_ctrl_connect/latest

Test location /workspace/coverage/default/71.flash_ctrl_otp_reset.4244667051
Short name T1041
Test name
Test status
Simulation time 65151500 ps
CPU time 134.85 seconds
Started Mar 21 03:20:39 PM PDT 24
Finished Mar 21 03:22:55 PM PDT 24
Peak memory 259856 kb
Host smart-dac03d26-096d-4aa6-8e93-c16671695ebd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244667051 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_o
tp_reset.4244667051
Directory /workspace/71.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/72.flash_ctrl_connect.15086696
Short name T429
Test name
Test status
Simulation time 28115600 ps
CPU time 13.74 seconds
Started Mar 21 03:20:37 PM PDT 24
Finished Mar 21 03:20:52 PM PDT 24
Peak memory 275156 kb
Host smart-0886b5bd-e4d9-43f3-a9b2-1388852c802f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15086696 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.15086696
Directory /workspace/72.flash_ctrl_connect/latest

Test location /workspace/coverage/default/72.flash_ctrl_otp_reset.947363937
Short name T821
Test name
Test status
Simulation time 75178300 ps
CPU time 113.8 seconds
Started Mar 21 03:20:40 PM PDT 24
Finished Mar 21 03:22:34 PM PDT 24
Peak memory 261052 kb
Host smart-6740c6c3-7b68-4552-858e-e0fcfdca15ed
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947363937 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_ot
p_reset.947363937
Directory /workspace/72.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/73.flash_ctrl_connect.1733523882
Short name T946
Test name
Test status
Simulation time 41590600 ps
CPU time 16.12 seconds
Started Mar 21 03:20:42 PM PDT 24
Finished Mar 21 03:20:59 PM PDT 24
Peak memory 276032 kb
Host smart-41e471df-e2e8-48bf-8f1a-d8d90aa37c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733523882 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.1733523882
Directory /workspace/73.flash_ctrl_connect/latest

Test location /workspace/coverage/default/73.flash_ctrl_otp_reset.1329182415
Short name T408
Test name
Test status
Simulation time 227708500 ps
CPU time 113.36 seconds
Started Mar 21 03:20:39 PM PDT 24
Finished Mar 21 03:22:33 PM PDT 24
Peak memory 259856 kb
Host smart-32ce5cef-fe0c-4892-b1ec-7f5e9999bac4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329182415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_o
tp_reset.1329182415
Directory /workspace/73.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/74.flash_ctrl_connect.1986696475
Short name T1038
Test name
Test status
Simulation time 40039300 ps
CPU time 15.57 seconds
Started Mar 21 03:20:49 PM PDT 24
Finished Mar 21 03:21:05 PM PDT 24
Peak memory 275808 kb
Host smart-a40d77e0-8e30-4bc6-b816-c35c7b2e95ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986696475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.1986696475
Directory /workspace/74.flash_ctrl_connect/latest

Test location /workspace/coverage/default/74.flash_ctrl_otp_reset.701612139
Short name T582
Test name
Test status
Simulation time 83005600 ps
CPU time 135.11 seconds
Started Mar 21 03:20:49 PM PDT 24
Finished Mar 21 03:23:05 PM PDT 24
Peak memory 261152 kb
Host smart-71395be8-cf7b-4ee8-8545-4c59ea2e370c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701612139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_ot
p_reset.701612139
Directory /workspace/74.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/75.flash_ctrl_connect.136480890
Short name T817
Test name
Test status
Simulation time 21343900 ps
CPU time 15.86 seconds
Started Mar 21 03:20:50 PM PDT 24
Finished Mar 21 03:21:06 PM PDT 24
Peak memory 275028 kb
Host smart-6fbaffda-a18a-42e8-9c73-794e96ea8d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136480890 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.136480890
Directory /workspace/75.flash_ctrl_connect/latest

Test location /workspace/coverage/default/75.flash_ctrl_otp_reset.4268032321
Short name T499
Test name
Test status
Simulation time 42667300 ps
CPU time 133.48 seconds
Started Mar 21 03:20:48 PM PDT 24
Finished Mar 21 03:23:02 PM PDT 24
Peak memory 261060 kb
Host smart-4c798d57-5cf4-4674-a78b-265f1e9e6395
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268032321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_o
tp_reset.4268032321
Directory /workspace/75.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/76.flash_ctrl_connect.3398455155
Short name T706
Test name
Test status
Simulation time 51238800 ps
CPU time 13.56 seconds
Started Mar 21 03:20:48 PM PDT 24
Finished Mar 21 03:21:02 PM PDT 24
Peak memory 275604 kb
Host smart-24db148d-79c9-4c0d-b4e8-b9a8e9c82354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398455155 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.3398455155
Directory /workspace/76.flash_ctrl_connect/latest

Test location /workspace/coverage/default/76.flash_ctrl_otp_reset.3225882325
Short name T478
Test name
Test status
Simulation time 38519100 ps
CPU time 131.07 seconds
Started Mar 21 03:20:47 PM PDT 24
Finished Mar 21 03:22:59 PM PDT 24
Peak memory 263552 kb
Host smart-1e720502-b9f8-4a09-b678-7ec57ab28c48
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225882325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_o
tp_reset.3225882325
Directory /workspace/76.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/77.flash_ctrl_connect.3340244302
Short name T435
Test name
Test status
Simulation time 49829200 ps
CPU time 13.32 seconds
Started Mar 21 03:20:48 PM PDT 24
Finished Mar 21 03:21:02 PM PDT 24
Peak memory 276036 kb
Host smart-afd93d6d-2dc7-4a18-bdcd-7fde52c32b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340244302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.3340244302
Directory /workspace/77.flash_ctrl_connect/latest

Test location /workspace/coverage/default/77.flash_ctrl_otp_reset.2456433102
Short name T470
Test name
Test status
Simulation time 39833200 ps
CPU time 133.33 seconds
Started Mar 21 03:20:50 PM PDT 24
Finished Mar 21 03:23:04 PM PDT 24
Peak memory 259960 kb
Host smart-404d82ab-d51b-43e5-a4c2-52c710d3e394
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456433102 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_o
tp_reset.2456433102
Directory /workspace/77.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/78.flash_ctrl_connect.22186467
Short name T437
Test name
Test status
Simulation time 36016300 ps
CPU time 16 seconds
Started Mar 21 03:20:50 PM PDT 24
Finished Mar 21 03:21:06 PM PDT 24
Peak memory 275584 kb
Host smart-d7833bdb-fa72-4a20-b954-d9f8045fba4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22186467 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.22186467
Directory /workspace/78.flash_ctrl_connect/latest

Test location /workspace/coverage/default/79.flash_ctrl_connect.82659860
Short name T559
Test name
Test status
Simulation time 15847900 ps
CPU time 16.29 seconds
Started Mar 21 03:20:48 PM PDT 24
Finished Mar 21 03:21:04 PM PDT 24
Peak memory 275228 kb
Host smart-c9a4ab63-d299-4112-8736-69345916563e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82659860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.82659860
Directory /workspace/79.flash_ctrl_connect/latest

Test location /workspace/coverage/default/79.flash_ctrl_otp_reset.934017423
Short name T378
Test name
Test status
Simulation time 76364200 ps
CPU time 136.41 seconds
Started Mar 21 03:20:47 PM PDT 24
Finished Mar 21 03:23:04 PM PDT 24
Peak memory 264108 kb
Host smart-ca708b57-5c30-4187-9e2a-85247de770c2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934017423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_ot
p_reset.934017423
Directory /workspace/79.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_alert_test.1220068948
Short name T893
Test name
Test status
Simulation time 161007500 ps
CPU time 13.9 seconds
Started Mar 21 03:14:47 PM PDT 24
Finished Mar 21 03:15:02 PM PDT 24
Peak memory 258320 kb
Host smart-51e209f0-19ec-4650-9f8d-03fedf498184
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220068948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.1
220068948
Directory /workspace/8.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.flash_ctrl_connect.2072621393
Short name T1000
Test name
Test status
Simulation time 15928500 ps
CPU time 13.66 seconds
Started Mar 21 03:14:48 PM PDT 24
Finished Mar 21 03:15:01 PM PDT 24
Peak memory 275232 kb
Host smart-2e249732-7518-4961-a92a-e2ee83849a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072621393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.2072621393
Directory /workspace/8.flash_ctrl_connect/latest

Test location /workspace/coverage/default/8.flash_ctrl_disable.980147613
Short name T491
Test name
Test status
Simulation time 86611000 ps
CPU time 21.39 seconds
Started Mar 21 03:14:36 PM PDT 24
Finished Mar 21 03:14:58 PM PDT 24
Peak memory 273692 kb
Host smart-1013d87b-bcd9-43e5-a80e-358641a8a79b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980147613 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_disable.980147613
Directory /workspace/8.flash_ctrl_disable/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_mp.4082200366
Short name T677
Test name
Test status
Simulation time 24925039000 ps
CPU time 2244.73 seconds
Started Mar 21 03:14:25 PM PDT 24
Finished Mar 21 03:51:51 PM PDT 24
Peak memory 265152 kb
Host smart-cdbc31b1-ce8c-4a56-b6e8-19f8576e2606
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082200366 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_err
or_mp.4082200366
Directory /workspace/8.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_prog_win.204100274
Short name T160
Test name
Test status
Simulation time 1330676800 ps
CPU time 797.43 seconds
Started Mar 21 03:14:24 PM PDT 24
Finished Mar 21 03:27:42 PM PDT 24
Peak memory 265200 kb
Host smart-af56d446-bdad-4ae9-952b-634d68641484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204100274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.204100274
Directory /workspace/8.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.3760271488
Short name T729
Test name
Test status
Simulation time 10018388900 ps
CPU time 87.97 seconds
Started Mar 21 03:14:45 PM PDT 24
Finished Mar 21 03:16:13 PM PDT 24
Peak memory 291876 kb
Host smart-176f7c5d-9549-4154-815c-d3d4fbd062ee
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760271488 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.3760271488
Directory /workspace/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.3759731301
Short name T986
Test name
Test status
Simulation time 25339500 ps
CPU time 13.6 seconds
Started Mar 21 03:14:44 PM PDT 24
Finished Mar 21 03:14:58 PM PDT 24
Peak memory 265372 kb
Host smart-1c61ac0e-4073-4567-8ddc-76788f9a5494
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759731301 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_seed_err.3759731301
Directory /workspace/8.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_rma_reset.2020315846
Short name T597
Test name
Test status
Simulation time 80140498900 ps
CPU time 812.83 seconds
Started Mar 21 03:14:27 PM PDT 24
Finished Mar 21 03:28:00 PM PDT 24
Peak memory 264560 kb
Host smart-b9cdc833-3038-4b54-a8ad-1e7779b38da4
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020315846 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.flash_ctrl_hw_rma_reset.2020315846
Directory /workspace/8.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_sec_otp.2488884056
Short name T971
Test name
Test status
Simulation time 975783800 ps
CPU time 33.9 seconds
Started Mar 21 03:14:22 PM PDT 24
Finished Mar 21 03:14:56 PM PDT 24
Peak memory 262416 kb
Host smart-df5456a3-5b2d-4458-98c3-23b6c1cde6ab
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488884056 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_h
w_sec_otp.2488884056
Directory /workspace/8.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.3948974447
Short name T573
Test name
Test status
Simulation time 35880946500 ps
CPU time 230.74 seconds
Started Mar 21 03:14:33 PM PDT 24
Finished Mar 21 03:18:24 PM PDT 24
Peak memory 289892 kb
Host smart-7f13ba28-18b7-40d3-8bf3-3467b3e7f703
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948974447 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd_slow_flash.3948974447
Directory /workspace/8.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr.4020519806
Short name T748
Test name
Test status
Simulation time 13477391800 ps
CPU time 107.2 seconds
Started Mar 21 03:14:37 PM PDT 24
Finished Mar 21 03:16:25 PM PDT 24
Peak memory 265216 kb
Host smart-37bae3f4-b57f-497a-850c-0e1d39e42167
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020519806 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.flash_ctrl_intr_wr.4020519806
Directory /workspace/8.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr_slow_flash.2792572164
Short name T950
Test name
Test status
Simulation time 111035034300 ps
CPU time 418.89 seconds
Started Mar 21 03:14:33 PM PDT 24
Finished Mar 21 03:21:32 PM PDT 24
Peak memory 265300 kb
Host smart-1786f021-a958-44a4-8eca-44fc733378b0
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279
2572164 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.2792572164
Directory /workspace/8.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_invalid_op.2557963984
Short name T96
Test name
Test status
Simulation time 3842641000 ps
CPU time 79.36 seconds
Started Mar 21 03:14:27 PM PDT 24
Finished Mar 21 03:15:47 PM PDT 24
Peak memory 259876 kb
Host smart-284a6343-4490-4294-bc96-1e31f783d563
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557963984 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.2557963984
Directory /workspace/8.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/8.flash_ctrl_lcmgr_intg.2514733126
Short name T995
Test name
Test status
Simulation time 58979800 ps
CPU time 13.52 seconds
Started Mar 21 03:14:46 PM PDT 24
Finished Mar 21 03:15:00 PM PDT 24
Peak memory 265232 kb
Host smart-fc704160-5584-4af0-b04e-c62921dae174
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514733126 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.flash_ctrl_lcmgr_intg.2514733126
Directory /workspace/8.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/8.flash_ctrl_mp_regions.4263907032
Short name T79
Test name
Test status
Simulation time 29931695800 ps
CPU time 536.31 seconds
Started Mar 21 03:14:23 PM PDT 24
Finished Mar 21 03:23:19 PM PDT 24
Peak memory 273948 kb
Host smart-52630a71-ad98-40dd-8c6d-8357770d66e0
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263907032 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 8.flash_ctrl_mp_regions.4263907032
Directory /workspace/8.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/8.flash_ctrl_otp_reset.3242291944
Short name T868
Test name
Test status
Simulation time 37272300 ps
CPU time 132.6 seconds
Started Mar 21 03:14:24 PM PDT 24
Finished Mar 21 03:16:36 PM PDT 24
Peak memory 259700 kb
Host smart-75022d10-2382-49e4-aff4-1d6c570ecf1b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242291944 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ot
p_reset.3242291944
Directory /workspace/8.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_phy_arb.3211875494
Short name T697
Test name
Test status
Simulation time 11865155500 ps
CPU time 400.7 seconds
Started Mar 21 03:14:25 PM PDT 24
Finished Mar 21 03:21:05 PM PDT 24
Peak memory 261532 kb
Host smart-23d14e75-b208-4b68-9a52-bd3460173de7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3211875494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.3211875494
Directory /workspace/8.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/8.flash_ctrl_prog_reset.120388776
Short name T913
Test name
Test status
Simulation time 38105300 ps
CPU time 13.78 seconds
Started Mar 21 03:14:34 PM PDT 24
Finished Mar 21 03:14:48 PM PDT 24
Peak memory 260308 kb
Host smart-90984505-6766-44e3-9f3f-07f9ba28144e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120388776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_prog_rese
t.120388776
Directory /workspace/8.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_rand_ops.1107809496
Short name T439
Test name
Test status
Simulation time 361334700 ps
CPU time 248.72 seconds
Started Mar 21 03:14:22 PM PDT 24
Finished Mar 21 03:18:31 PM PDT 24
Peak memory 279768 kb
Host smart-1e6b0c4f-8b31-4676-ad1f-d38793b5c495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107809496 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.1107809496
Directory /workspace/8.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/8.flash_ctrl_re_evict.250360366
Short name T663
Test name
Test status
Simulation time 44246400 ps
CPU time 32.5 seconds
Started Mar 21 03:14:32 PM PDT 24
Finished Mar 21 03:15:04 PM PDT 24
Peak memory 273584 kb
Host smart-52c28f47-f592-4c1f-980e-af12bf13b167
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250360366 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas
h_ctrl_re_evict.250360366
Directory /workspace/8.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro.4153238940
Short name T627
Test name
Test status
Simulation time 871184800 ps
CPU time 104.27 seconds
Started Mar 21 03:14:32 PM PDT 24
Finished Mar 21 03:16:16 PM PDT 24
Peak memory 281056 kb
Host smart-3d19a661-dbea-4052-a5ef-a400961885f4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153238940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.flash_ctrl_ro.4153238940
Directory /workspace/8.flash_ctrl_ro/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_derr.745982236
Short name T197
Test name
Test status
Simulation time 1044416500 ps
CPU time 130.76 seconds
Started Mar 21 03:14:33 PM PDT 24
Finished Mar 21 03:16:44 PM PDT 24
Peak memory 281812 kb
Host smart-25b3479a-def0-435c-98b7-7e02a4fabd4c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
745982236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.745982236
Directory /workspace/8.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw.105816656
Short name T931
Test name
Test status
Simulation time 13319894500 ps
CPU time 518.13 seconds
Started Mar 21 03:14:33 PM PDT 24
Finished Mar 21 03:23:11 PM PDT 24
Peak memory 314408 kb
Host smart-3f9b9875-63ca-4460-83b6-5fb28b742d6c
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105816656 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctr
l_rw.105816656
Directory /workspace/8.flash_ctrl_rw/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict.3505766212
Short name T422
Test name
Test status
Simulation time 97143600 ps
CPU time 32.84 seconds
Started Mar 21 03:14:37 PM PDT 24
Finished Mar 21 03:15:10 PM PDT 24
Peak memory 274560 kb
Host smart-474452ba-d042-43b2-966e-a6a3b2d2afa7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505766212 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla
sh_ctrl_rw_evict.3505766212
Directory /workspace/8.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict_all_en.4195146833
Short name T290
Test name
Test status
Simulation time 88322700 ps
CPU time 31.86 seconds
Started Mar 21 03:14:34 PM PDT 24
Finished Mar 21 03:15:06 PM PDT 24
Peak memory 273548 kb
Host smart-94c8398e-0fe1-433c-83fe-6d6b47870a08
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195146833 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict_all_en.4195146833
Directory /workspace/8.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/8.flash_ctrl_sec_info_access.1498833390
Short name T390
Test name
Test status
Simulation time 1445762700 ps
CPU time 69.66 seconds
Started Mar 21 03:14:36 PM PDT 24
Finished Mar 21 03:15:47 PM PDT 24
Peak memory 262696 kb
Host smart-3715530b-a0c9-4ca8-bb53-4df8138e6b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498833390 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.1498833390
Directory /workspace/8.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/8.flash_ctrl_smoke.1599329354
Short name T518
Test name
Test status
Simulation time 52159900 ps
CPU time 147.86 seconds
Started Mar 21 03:14:23 PM PDT 24
Finished Mar 21 03:16:51 PM PDT 24
Peak memory 277548 kb
Host smart-dccc3c07-97b9-4950-8887-05253dab56d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599329354 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.1599329354
Directory /workspace/8.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/8.flash_ctrl_wo.3873256136
Short name T707
Test name
Test status
Simulation time 2513128900 ps
CPU time 176.4 seconds
Started Mar 21 03:14:36 PM PDT 24
Finished Mar 21 03:17:33 PM PDT 24
Peak memory 265248 kb
Host smart-f3bff369-e847-4066-adb1-c3277338a93b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873256136 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.flash_ctrl_wo.3873256136
Directory /workspace/8.flash_ctrl_wo/latest

Test location /workspace/coverage/default/9.flash_ctrl_alert_test.2766518429
Short name T444
Test name
Test status
Simulation time 372007300 ps
CPU time 14.26 seconds
Started Mar 21 03:15:22 PM PDT 24
Finished Mar 21 03:15:36 PM PDT 24
Peak memory 265240 kb
Host smart-f890b617-2c97-4510-95a5-caab573f41c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766518429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.2
766518429
Directory /workspace/9.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.flash_ctrl_connect.2046501066
Short name T611
Test name
Test status
Simulation time 21473500 ps
CPU time 13.24 seconds
Started Mar 21 03:15:03 PM PDT 24
Finished Mar 21 03:15:17 PM PDT 24
Peak memory 275716 kb
Host smart-daa3cbb2-612b-428f-9bc8-71ae465e345a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046501066 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.2046501066
Directory /workspace/9.flash_ctrl_connect/latest

Test location /workspace/coverage/default/9.flash_ctrl_disable.2942667218
Short name T557
Test name
Test status
Simulation time 29327100 ps
CPU time 21.8 seconds
Started Mar 21 03:15:04 PM PDT 24
Finished Mar 21 03:15:26 PM PDT 24
Peak memory 280716 kb
Host smart-babd92a1-a9e6-4e0f-b1a4-beaaae257261
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942667218 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_disable.2942667218
Directory /workspace/9.flash_ctrl_disable/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_mp.3048248825
Short name T856
Test name
Test status
Simulation time 2517460400 ps
CPU time 2272.02 seconds
Started Mar 21 03:14:45 PM PDT 24
Finished Mar 21 03:52:38 PM PDT 24
Peak memory 262596 kb
Host smart-31dad361-db8f-481e-9200-b1225c37c51e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048248825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_err
or_mp.3048248825
Directory /workspace/9.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_prog_win.3468208802
Short name T301
Test name
Test status
Simulation time 2557740900 ps
CPU time 845.6 seconds
Started Mar 21 03:14:43 PM PDT 24
Finished Mar 21 03:28:49 PM PDT 24
Peak memory 273436 kb
Host smart-2d9ddf46-d86b-4765-89ed-6bad2bbd5989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468208802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.3468208802
Directory /workspace/9.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/9.flash_ctrl_fetch_code.701551665
Short name T51
Test name
Test status
Simulation time 408786200 ps
CPU time 27.65 seconds
Started Mar 21 03:14:45 PM PDT 24
Finished Mar 21 03:15:13 PM PDT 24
Peak memory 265188 kb
Host smart-76c08a9c-576c-4c44-94f3-e09464ca3f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701551665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetch_code.701551665
Directory /workspace/9.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.3850874755
Short name T925
Test name
Test status
Simulation time 10012578600 ps
CPU time 279.03 seconds
Started Mar 21 03:15:21 PM PDT 24
Finished Mar 21 03:20:00 PM PDT 24
Peak memory 264300 kb
Host smart-4b9a4ad3-e632-4787-ae0f-f9df84c381ed
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850874755 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.3850874755
Directory /workspace/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.4034728792
Short name T747
Test name
Test status
Simulation time 46095500 ps
CPU time 13.84 seconds
Started Mar 21 03:15:21 PM PDT 24
Finished Mar 21 03:15:35 PM PDT 24
Peak memory 265196 kb
Host smart-932b7727-178b-4a71-8d73-849a9d7f2bf9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034728792 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_seed_err.4034728792
Directory /workspace/9.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_rma_reset.2126967870
Short name T318
Test name
Test status
Simulation time 120147333400 ps
CPU time 834.73 seconds
Started Mar 21 03:14:45 PM PDT 24
Finished Mar 21 03:28:40 PM PDT 24
Peak memory 263420 kb
Host smart-48283691-c8b5-44dc-b25d-706d1d08f658
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126967870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.flash_ctrl_hw_rma_reset.2126967870
Directory /workspace/9.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_sec_otp.853432753
Short name T647
Test name
Test status
Simulation time 7260418300 ps
CPU time 72.54 seconds
Started Mar 21 03:14:46 PM PDT 24
Finished Mar 21 03:15:58 PM PDT 24
Peak memory 262580 kb
Host smart-fd715091-e5e9-42d8-b62a-57a42c48dca6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853432753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw
_sec_otp.853432753
Directory /workspace/9.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.2635323419
Short name T231
Test name
Test status
Simulation time 17596371800 ps
CPU time 239.08 seconds
Started Mar 21 03:15:07 PM PDT 24
Finished Mar 21 03:19:06 PM PDT 24
Peak memory 294100 kb
Host smart-e71ac023-0ddd-430a-9f42-a5651786b496
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635323419 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd_slow_flash.2635323419
Directory /workspace/9.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr.3995476310
Short name T1020
Test name
Test status
Simulation time 4377550000 ps
CPU time 107.53 seconds
Started Mar 21 03:15:04 PM PDT 24
Finished Mar 21 03:16:52 PM PDT 24
Peak memory 260884 kb
Host smart-4296c641-71cd-4150-b76b-bd682aff9e95
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995476310 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.flash_ctrl_intr_wr.3995476310
Directory /workspace/9.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr_slow_flash.674361622
Short name T547
Test name
Test status
Simulation time 131839726400 ps
CPU time 337.36 seconds
Started Mar 21 03:15:06 PM PDT 24
Finished Mar 21 03:20:43 PM PDT 24
Peak memory 265244 kb
Host smart-fb393ba4-1dc2-4714-95bc-a56db45cae7c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674
361622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.674361622
Directory /workspace/9.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_lcmgr_intg.942343866
Short name T297
Test name
Test status
Simulation time 27124300 ps
CPU time 14.1 seconds
Started Mar 21 03:15:05 PM PDT 24
Finished Mar 21 03:15:20 PM PDT 24
Peak memory 265232 kb
Host smart-d5f4add9-06f5-44e4-8c48-2b201e748c76
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942343866 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.flash_ctrl_lcmgr_intg.942343866
Directory /workspace/9.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/9.flash_ctrl_mp_regions.1235569870
Short name T84
Test name
Test status
Simulation time 36363931000 ps
CPU time 753.88 seconds
Started Mar 21 03:14:46 PM PDT 24
Finished Mar 21 03:27:21 PM PDT 24
Peak memory 273240 kb
Host smart-6a9bf034-9d7b-416f-936a-c1a7c7184832
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235569870 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.flash_ctrl_mp_regions.1235569870
Directory /workspace/9.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/9.flash_ctrl_otp_reset.1996000298
Short name T473
Test name
Test status
Simulation time 41772700 ps
CPU time 134.22 seconds
Started Mar 21 03:14:45 PM PDT 24
Finished Mar 21 03:16:59 PM PDT 24
Peak memory 261140 kb
Host smart-dfd40845-a13b-4112-9366-f2db1d9c8491
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996000298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ot
p_reset.1996000298
Directory /workspace/9.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_phy_arb.2496140756
Short name T648
Test name
Test status
Simulation time 286821200 ps
CPU time 335.29 seconds
Started Mar 21 03:14:46 PM PDT 24
Finished Mar 21 03:20:22 PM PDT 24
Peak memory 262340 kb
Host smart-0d8874ec-6d62-4545-94e2-cd133b2fcbd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2496140756 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.2496140756
Directory /workspace/9.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/9.flash_ctrl_prog_reset.3446728576
Short name T128
Test name
Test status
Simulation time 60026000 ps
CPU time 14.96 seconds
Started Mar 21 03:15:05 PM PDT 24
Finished Mar 21 03:15:21 PM PDT 24
Peak memory 265236 kb
Host smart-385206cc-9dd4-49cc-b944-37c3cdfc2fb7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446728576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_prog_res
et.3446728576
Directory /workspace/9.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_rand_ops.4023248093
Short name T98
Test name
Test status
Simulation time 1483626800 ps
CPU time 586.51 seconds
Started Mar 21 03:14:46 PM PDT 24
Finished Mar 21 03:24:33 PM PDT 24
Peak memory 285748 kb
Host smart-5ee8d596-aba9-4f31-a6b8-a39fb4f305f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023248093 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.4023248093
Directory /workspace/9.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/9.flash_ctrl_re_evict.3761825510
Short name T735
Test name
Test status
Simulation time 70069700 ps
CPU time 33.38 seconds
Started Mar 21 03:15:07 PM PDT 24
Finished Mar 21 03:15:41 PM PDT 24
Peak memory 273520 kb
Host smart-29044fbe-7d3f-4e8d-a62a-45e6e451f826
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761825510 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla
sh_ctrl_re_evict.3761825510
Directory /workspace/9.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro.4028380454
Short name T5
Test name
Test status
Simulation time 1929737700 ps
CPU time 103.29 seconds
Started Mar 21 03:14:45 PM PDT 24
Finished Mar 21 03:16:28 PM PDT 24
Peak memory 280984 kb
Host smart-7848a846-fb67-4d6f-9ebf-ec2d3c41c864
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028380454 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.flash_ctrl_ro.4028380454
Directory /workspace/9.flash_ctrl_ro/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw.2531596048
Short name T879
Test name
Test status
Simulation time 15606098900 ps
CPU time 513.43 seconds
Started Mar 21 03:15:07 PM PDT 24
Finished Mar 21 03:23:41 PM PDT 24
Peak memory 314312 kb
Host smart-4201461d-7754-46b1-9d7a-d8e298c49915
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531596048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ct
rl_rw.2531596048
Directory /workspace/9.flash_ctrl_rw/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict.2585096403
Short name T1039
Test name
Test status
Simulation time 581898000 ps
CPU time 30.59 seconds
Started Mar 21 03:15:05 PM PDT 24
Finished Mar 21 03:15:35 PM PDT 24
Peak memory 266376 kb
Host smart-dd7410a7-a726-4101-b1a9-e2f372d0b096
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585096403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla
sh_ctrl_rw_evict.2585096403
Directory /workspace/9.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict_all_en.827671213
Short name T687
Test name
Test status
Simulation time 30820900 ps
CPU time 31.66 seconds
Started Mar 21 03:15:03 PM PDT 24
Finished Mar 21 03:15:35 PM PDT 24
Peak memory 266396 kb
Host smart-97494e0f-a2c9-43e4-8fe7-be0a228e4a3a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827671213 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict_all_en.827671213
Directory /workspace/9.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/9.flash_ctrl_sec_info_access.1418801858
Short name T389
Test name
Test status
Simulation time 709612000 ps
CPU time 60.32 seconds
Started Mar 21 03:15:06 PM PDT 24
Finished Mar 21 03:16:06 PM PDT 24
Peak memory 263292 kb
Host smart-55b88454-7c7e-43bf-9b86-04e0dcd6e8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418801858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.1418801858
Directory /workspace/9.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/9.flash_ctrl_smoke.1173601854
Short name T533
Test name
Test status
Simulation time 30390500 ps
CPU time 54.17 seconds
Started Mar 21 03:14:48 PM PDT 24
Finished Mar 21 03:15:42 PM PDT 24
Peak memory 270612 kb
Host smart-f0eff0d6-d381-463b-acd1-5f2d6c9c5aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173601854 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.1173601854
Directory /workspace/9.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/9.flash_ctrl_wo.2124379965
Short name T330
Test name
Test status
Simulation time 2274016800 ps
CPU time 161.19 seconds
Started Mar 21 03:14:48 PM PDT 24
Finished Mar 21 03:17:29 PM PDT 24
Peak memory 259024 kb
Host smart-5813e203-aeb6-46a3-b6e8-33e2fb9ea107
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124379965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.flash_ctrl_wo.2124379965
Directory /workspace/9.flash_ctrl_wo/latest
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