Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	160866	1		T1	1		T2	2		T3	1
all_values[1]	160866	1		T1	1		T2	2		T3	1
all_values[2]	160866	1		T1	1		T2	2		T3	1
all_values[3]	160866	1		T1	1		T2	2		T3	1
all_values[4]	160866	1		T1	1		T2	2		T3	1
all_values[5]	160866	1		T1	1		T2	2		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	327654	1		T1	6		T2	12		T3	6
auto[1]	637542	1		T4	6304		T22	3884		T31	7904

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	475496	1		T1	4		T2	7		T3	4
auto[1]	489700	1		T1	2		T2	5		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	160682	1		T1	1		T2	2		T3	1
all_values[0]	auto[1]	auto[1]	184	1		T269	4		T270	8		T342	5
all_values[1]	auto[0]	auto[1]	160693	1		T1	1		T2	2		T3	1
all_values[1]	auto[1]	auto[1]	173	1		T269	1		T270	2		T342	2
all_values[2]	auto[0]	auto[0]	1506	1		T1	1		T2	2		T3	1
all_values[2]	auto[0]	auto[1]	59	1		T269	1		T270	1		T342	1
all_values[2]	auto[1]	auto[0]	159259	1		T4	1576		T22	971		T31	1976
all_values[2]	auto[1]	auto[1]	42	1		T270	1		T344	1		T343	2
all_values[3]	auto[0]	auto[0]	1509	1		T1	1		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	58	1		T269	2		T270	1		T342	1
all_values[3]	auto[1]	auto[0]	52025	1		T4	788		T22	971		T31	988
all_values[3]	auto[1]	auto[1]	107274	1		T4	788		T31	988		T32	2022
all_values[4]	auto[0]	auto[0]	1068	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	504	1		T2	1		T5	1		T16	1
all_values[4]	auto[1]	auto[0]	99422	1		T4	788		T22	1		T31	988
all_values[4]	auto[1]	auto[1]	59872	1		T4	788		T22	970		T31	988
all_values[5]	auto[0]	auto[0]	1469	1		T1	1		T2	2		T3	1
all_values[5]	auto[0]	auto[1]	106	1		T33	1		T34	1		T35	1
all_values[5]	auto[1]	auto[0]	159238	1		T4	1576		T22	971		T31	1976
all_values[5]	auto[1]	auto[1]	53	1		T270	1		T344	2		T346	2