Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T15 |
1 |
|
T26 |
5 |
|
T35 |
1 |
| others[1] |
232 |
1 |
|
T17 |
1 |
|
T26 |
9 |
|
T77 |
13 |
| others[2] |
196 |
1 |
|
T26 |
5 |
|
T77 |
4 |
|
T23 |
1 |
| others[3] |
374 |
1 |
|
T16 |
1 |
|
T26 |
18 |
|
T77 |
17 |
| false |
106 |
1 |
|
T26 |
4 |
|
T77 |
3 |
|
T78 |
3 |
| true |
13041 |
1 |
|
T1 |
239 |
|
T2 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8634 |
1 |
|
T1 |
239 |
|
T5 |
1 |
|
T11 |
2 |
| others[1] |
1260 |
1 |
|
T16 |
1 |
|
T6 |
4 |
|
T26 |
20 |
| others[2] |
1250 |
1 |
|
T4 |
1 |
|
T6 |
4 |
|
T26 |
16 |
| others[3] |
2021 |
1 |
|
T26 |
34 |
|
T39 |
20 |
|
T158 |
4 |
| false |
633 |
1 |
|
T6 |
1 |
|
T26 |
16 |
|
T39 |
3 |
| true |
369 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8641 |
1 |
|
T1 |
239 |
|
T5 |
1 |
|
T11 |
2 |
| others[1] |
1224 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T18 |
1 |
| others[2] |
1243 |
1 |
|
T6 |
3 |
|
T26 |
20 |
|
T54 |
1 |
| others[3] |
2057 |
1 |
|
T6 |
4 |
|
T26 |
32 |
|
T19 |
1 |
| false |
659 |
1 |
|
T6 |
1 |
|
T26 |
8 |
|
T39 |
8 |
| true |
343 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
116 |
1 |
|
T26 |
6 |
|
T77 |
5 |
|
T78 |
5 |
| others[1] |
108 |
1 |
|
T16 |
1 |
|
T26 |
4 |
|
T54 |
1 |
| others[2] |
119 |
1 |
|
T26 |
3 |
|
T77 |
6 |
|
T78 |
7 |
| others[3] |
181 |
1 |
|
T26 |
6 |
|
T54 |
1 |
|
T77 |
9 |
| false |
49 |
1 |
|
T26 |
2 |
|
T77 |
2 |
|
T78 |
3 |
| true |
13594 |
1 |
|
T1 |
239 |
|
T2 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T26 |
10 |
|
T33 |
1 |
|
T77 |
7 |
| others[1] |
238 |
1 |
|
T26 |
6 |
|
T54 |
1 |
|
T20 |
1 |
| others[2] |
220 |
1 |
|
T26 |
8 |
|
T77 |
11 |
|
T78 |
14 |
| others[3] |
428 |
1 |
|
T26 |
12 |
|
T77 |
16 |
|
T207 |
1 |
| false |
110 |
1 |
|
T26 |
7 |
|
T77 |
5 |
|
T78 |
4 |
| true |
12943 |
1 |
|
T1 |
239 |
|
T2 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8509 |
1 |
|
T1 |
239 |
|
T11 |
2 |
|
T40 |
114 |
| others[1] |
1051 |
1 |
|
T5 |
1 |
|
T6 |
4 |
|
T26 |
21 |
| others[2] |
1045 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T6 |
2 |
| others[3] |
1662 |
1 |
|
T6 |
5 |
|
T26 |
19 |
|
T39 |
15 |
| false |
523 |
1 |
|
T6 |
2 |
|
T26 |
15 |
|
T39 |
1 |
| true |
1377 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
236 |
1 |
|
T26 |
10 |
|
T54 |
1 |
|
T77 |
10 |
| others[1] |
232 |
1 |
|
T17 |
1 |
|
T26 |
12 |
|
T77 |
9 |
| others[2] |
218 |
1 |
|
T15 |
1 |
|
T26 |
8 |
|
T77 |
12 |
| others[3] |
362 |
1 |
|
T26 |
11 |
|
T77 |
16 |
|
T21 |
1 |
| false |
111 |
1 |
|
T26 |
3 |
|
T77 |
4 |
|
T78 |
2 |
| true |
13008 |
1 |
|
T1 |
239 |
|
T2 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T26 |
10 |
|
T77 |
9 |
|
T7 |
2 |
| others[1] |
214 |
1 |
|
T17 |
1 |
|
T26 |
8 |
|
T77 |
10 |
| others[2] |
231 |
1 |
|
T26 |
7 |
|
T22 |
1 |
|
T77 |
13 |
| others[3] |
344 |
1 |
|
T26 |
13 |
|
T35 |
1 |
|
T77 |
14 |
| false |
115 |
1 |
|
T26 |
6 |
|
T77 |
8 |
|
T23 |
1 |
| true |
13039 |
1 |
|
T1 |
239 |
|
T2 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8623 |
1 |
|
T1 |
239 |
|
T5 |
1 |
|
T11 |
2 |
| others[1] |
1229 |
1 |
|
T6 |
1 |
|
T26 |
21 |
|
T54 |
1 |
| others[2] |
1243 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T16 |
1 |
| others[3] |
2063 |
1 |
|
T6 |
7 |
|
T26 |
40 |
|
T54 |
1 |
| false |
631 |
1 |
|
T26 |
7 |
|
T39 |
6 |
|
T158 |
1 |
| true |
378 |
1 |
|
T10 |
1 |
|
T15 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1185 |
1 |
|
T6 |
4 |
|
T26 |
18 |
|
T54 |
2 |
| others[1] |
1255 |
1 |
|
T6 |
2 |
|
T26 |
22 |
|
T39 |
5 |
| others[2] |
1214 |
1 |
|
T16 |
1 |
|
T6 |
5 |
|
T26 |
19 |
| others[3] |
2063 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T26 |
33 |
| false |
659 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T26 |
9 |
| true |
350 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
113 |
1 |
|
T54 |
1 |
|
T77 |
5 |
|
T78 |
4 |
| others[1] |
102 |
1 |
|
T26 |
3 |
|
T77 |
3 |
|
T78 |
1 |
| others[2] |
124 |
1 |
|
T26 |
3 |
|
T54 |
1 |
|
T77 |
3 |
| others[3] |
171 |
1 |
|
T26 |
11 |
|
T77 |
3 |
|
T78 |
10 |
| false |
45 |
1 |
|
T26 |
2 |
|
T77 |
2 |
|
T78 |
2 |
| true |
6171 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
238 |
1 |
|
T15 |
1 |
|
T16 |
1 |
|
T26 |
10 |
| others[1] |
223 |
1 |
|
T26 |
8 |
|
T35 |
1 |
|
T77 |
7 |
| others[2] |
239 |
1 |
|
T26 |
10 |
|
T77 |
9 |
|
T7 |
2 |
| others[3] |
374 |
1 |
|
T18 |
1 |
|
T26 |
19 |
|
T77 |
11 |
| false |
116 |
1 |
|
T26 |
4 |
|
T54 |
1 |
|
T77 |
5 |
| true |
5536 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1013 |
1 |
|
T16 |
1 |
|
T6 |
3 |
|
T26 |
18 |
| others[1] |
1057 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T6 |
1 |
| others[2] |
1052 |
1 |
|
T2 |
1 |
|
T18 |
1 |
|
T6 |
3 |
| others[3] |
1747 |
1 |
|
T5 |
1 |
|
T6 |
4 |
|
T26 |
32 |
| false |
548 |
1 |
|
T6 |
2 |
|
T26 |
8 |
|
T39 |
2 |
| true |
1309 |
1 |
|
T15 |
1 |
|
T17 |
1 |
|
T39 |
31 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
264 |
1 |
|
T15 |
1 |
|
T26 |
12 |
|
T33 |
1 |
| others[1] |
194 |
1 |
|
T26 |
10 |
|
T77 |
9 |
|
T78 |
10 |
| others[2] |
205 |
1 |
|
T26 |
2 |
|
T22 |
1 |
|
T77 |
6 |
| others[3] |
345 |
1 |
|
T26 |
20 |
|
T54 |
2 |
|
T77 |
14 |
| false |
122 |
1 |
|
T26 |
6 |
|
T77 |
6 |
|
T78 |
7 |
| true |
5596 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
211 |
1 |
|
T15 |
1 |
|
T26 |
10 |
|
T77 |
5 |
| others[1] |
222 |
1 |
|
T26 |
9 |
|
T54 |
1 |
|
T77 |
14 |
| others[2] |
205 |
1 |
|
T26 |
11 |
|
T77 |
10 |
|
T7 |
1 |
| others[3] |
380 |
1 |
|
T17 |
1 |
|
T26 |
19 |
|
T77 |
19 |
| false |
116 |
1 |
|
T26 |
4 |
|
T77 |
3 |
|
T78 |
6 |
| true |
5592 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1182 |
1 |
|
T6 |
2 |
|
T26 |
15 |
|
T39 |
10 |
| others[1] |
1198 |
1 |
|
T6 |
1 |
|
T26 |
17 |
|
T54 |
1 |
| others[2] |
1260 |
1 |
|
T6 |
5 |
|
T26 |
26 |
|
T19 |
1 |
| others[3] |
2096 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T16 |
1 |
| false |
620 |
1 |
|
T5 |
1 |
|
T26 |
11 |
|
T39 |
7 |
| true |
370 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1200 |
1 |
|
T6 |
2 |
|
T26 |
14 |
|
T39 |
10 |
| others[1] |
1255 |
1 |
|
T16 |
1 |
|
T6 |
5 |
|
T26 |
21 |
| others[2] |
1290 |
1 |
|
T5 |
1 |
|
T6 |
3 |
|
T26 |
20 |
| others[3] |
2051 |
1 |
|
T4 |
1 |
|
T18 |
1 |
|
T6 |
3 |
| false |
584 |
1 |
|
T26 |
10 |
|
T39 |
10 |
|
T158 |
1 |
| true |
346 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
108 |
1 |
|
T26 |
4 |
|
T77 |
2 |
|
T78 |
9 |
| others[1] |
92 |
1 |
|
T16 |
1 |
|
T26 |
5 |
|
T54 |
1 |
| others[2] |
107 |
1 |
|
T26 |
3 |
|
T77 |
2 |
|
T78 |
3 |
| others[3] |
199 |
1 |
|
T26 |
9 |
|
T77 |
8 |
|
T78 |
12 |
| false |
59 |
1 |
|
T15 |
1 |
|
T26 |
2 |
|
T54 |
1 |
| true |
6161 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T17 |
1 |
|
T26 |
6 |
|
T77 |
8 |
| others[1] |
238 |
1 |
|
T26 |
9 |
|
T54 |
1 |
|
T77 |
10 |
| others[2] |
236 |
1 |
|
T26 |
12 |
|
T77 |
8 |
|
T7 |
1 |
| others[3] |
371 |
1 |
|
T15 |
1 |
|
T26 |
14 |
|
T22 |
1 |
| false |
122 |
1 |
|
T26 |
8 |
|
T77 |
5 |
|
T36 |
1 |
| true |
5520 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1044 |
1 |
|
T6 |
1 |
|
T26 |
14 |
|
T39 |
8 |
| others[1] |
1059 |
1 |
|
T10 |
1 |
|
T6 |
5 |
|
T26 |
21 |
| others[2] |
1043 |
1 |
|
T4 |
1 |
|
T18 |
1 |
|
T6 |
1 |
| others[3] |
1688 |
1 |
|
T5 |
1 |
|
T16 |
1 |
|
T6 |
5 |
| false |
544 |
1 |
|
T6 |
1 |
|
T26 |
9 |
|
T54 |
1 |
| true |
1348 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
215 |
1 |
|
T16 |
1 |
|
T17 |
1 |
|
T18 |
1 |
| others[1] |
237 |
1 |
|
T26 |
12 |
|
T54 |
1 |
|
T77 |
11 |
| others[2] |
237 |
1 |
|
T26 |
3 |
|
T77 |
10 |
|
T371 |
1 |
| others[3] |
339 |
1 |
|
T15 |
1 |
|
T26 |
18 |
|
T22 |
1 |
| false |
116 |
1 |
|
T26 |
2 |
|
T77 |
8 |
|
T78 |
4 |
| true |
5582 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
193 |
1 |
|
T26 |
10 |
|
T54 |
1 |
|
T77 |
10 |
| others[1] |
224 |
1 |
|
T26 |
8 |
|
T77 |
11 |
|
T23 |
1 |
| others[2] |
229 |
1 |
|
T26 |
16 |
|
T33 |
1 |
|
T77 |
7 |
| others[3] |
380 |
1 |
|
T26 |
15 |
|
T54 |
1 |
|
T22 |
1 |
| false |
104 |
1 |
|
T26 |
5 |
|
T77 |
8 |
|
T78 |
3 |
| true |
5596 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1270 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T26 |
17 |
| others[1] |
1228 |
1 |
|
T6 |
5 |
|
T26 |
18 |
|
T19 |
1 |
| others[2] |
1153 |
1 |
|
T6 |
3 |
|
T26 |
18 |
|
T54 |
1 |
| others[3] |
2067 |
1 |
|
T6 |
3 |
|
T26 |
32 |
|
T54 |
1 |
| false |
643 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T6 |
1 |
| true |
365 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1246 |
1 |
|
T4 |
1 |
|
T6 |
6 |
|
T26 |
15 |
| others[1] |
1218 |
1 |
|
T26 |
22 |
|
T39 |
7 |
|
T99 |
1 |
| others[2] |
1255 |
1 |
|
T6 |
3 |
|
T26 |
26 |
|
T39 |
20 |
| others[3] |
2043 |
1 |
|
T10 |
1 |
|
T5 |
1 |
|
T16 |
1 |
| false |
611 |
1 |
|
T6 |
1 |
|
T26 |
7 |
|
T54 |
1 |
| true |
353 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
107 |
1 |
|
T26 |
2 |
|
T54 |
2 |
|
T77 |
6 |
| others[1] |
97 |
1 |
|
T26 |
3 |
|
T77 |
4 |
|
T78 |
4 |
| others[2] |
96 |
1 |
|
T26 |
6 |
|
T77 |
4 |
|
T78 |
3 |
| others[3] |
166 |
1 |
|
T26 |
11 |
|
T77 |
3 |
|
T78 |
5 |
| false |
50 |
1 |
|
T15 |
1 |
|
T26 |
1 |
|
T77 |
2 |
| true |
6210 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
247 |
1 |
|
T26 |
9 |
|
T77 |
13 |
|
T7 |
1 |
| others[1] |
215 |
1 |
|
T26 |
6 |
|
T35 |
1 |
|
T77 |
6 |
| others[2] |
245 |
1 |
|
T26 |
7 |
|
T77 |
7 |
|
T7 |
1 |
| others[3] |
370 |
1 |
|
T16 |
1 |
|
T18 |
1 |
|
T26 |
17 |
| false |
116 |
1 |
|
T15 |
1 |
|
T26 |
5 |
|
T77 |
6 |
| true |
5533 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1008 |
1 |
|
T6 |
2 |
|
T26 |
16 |
|
T54 |
2 |
| others[1] |
1068 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T6 |
4 |
| others[2] |
1056 |
1 |
|
T6 |
2 |
|
T26 |
23 |
|
T39 |
11 |
| others[3] |
1761 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T5 |
1 |
| false |
522 |
1 |
|
T6 |
2 |
|
T26 |
9 |
|
T39 |
2 |
| true |
1311 |
1 |
|
T17 |
1 |
|
T18 |
1 |
|
T39 |
31 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T26 |
8 |
|
T77 |
9 |
|
T23 |
1 |
| others[1] |
202 |
1 |
|
T26 |
12 |
|
T77 |
12 |
|
T78 |
10 |
| others[2] |
227 |
1 |
|
T15 |
1 |
|
T26 |
11 |
|
T33 |
1 |
| others[3] |
422 |
1 |
|
T17 |
1 |
|
T26 |
22 |
|
T77 |
13 |
| false |
105 |
1 |
|
T18 |
1 |
|
T26 |
5 |
|
T77 |
4 |
| true |
5542 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
217 |
1 |
|
T26 |
9 |
|
T77 |
9 |
|
T78 |
14 |
| others[1] |
197 |
1 |
|
T26 |
8 |
|
T54 |
1 |
|
T77 |
11 |
| others[2] |
212 |
1 |
|
T16 |
1 |
|
T26 |
12 |
|
T35 |
1 |
| others[3] |
357 |
1 |
|
T26 |
20 |
|
T33 |
1 |
|
T22 |
1 |
| false |
119 |
1 |
|
T26 |
2 |
|
T77 |
3 |
|
T78 |
4 |
| true |
5624 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1190 |
1 |
|
T18 |
1 |
|
T6 |
4 |
|
T26 |
22 |
| others[1] |
1231 |
1 |
|
T6 |
4 |
|
T26 |
16 |
|
T19 |
1 |
| others[2] |
1247 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T6 |
1 |
| others[3] |
2058 |
1 |
|
T5 |
1 |
|
T16 |
1 |
|
T6 |
3 |
| false |
625 |
1 |
|
T6 |
1 |
|
T26 |
13 |
|
T39 |
10 |
| true |
375 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1247 |
1 |
|
T6 |
1 |
|
T26 |
20 |
|
T54 |
1 |
| others[1] |
1261 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
| others[2] |
1167 |
1 |
|
T16 |
1 |
|
T6 |
5 |
|
T26 |
14 |
| others[3] |
2064 |
1 |
|
T6 |
5 |
|
T26 |
34 |
|
T19 |
1 |
| false |
638 |
1 |
|
T6 |
1 |
|
T26 |
11 |
|
T54 |
1 |
| true |
349 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |