Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
117 |
1 |
|
T26 |
4 |
|
T77 |
3 |
|
T78 |
3 |
| others[1] |
114 |
1 |
|
T26 |
8 |
|
T77 |
2 |
|
T78 |
6 |
| others[2] |
108 |
1 |
|
T26 |
4 |
|
T77 |
6 |
|
T78 |
5 |
| others[3] |
190 |
1 |
|
T16 |
1 |
|
T26 |
9 |
|
T54 |
2 |
| false |
50 |
1 |
|
T26 |
1 |
|
T77 |
1 |
|
T78 |
1 |
| true |
6147 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T26 |
7 |
|
T33 |
1 |
|
T77 |
10 |
| others[1] |
185 |
1 |
|
T26 |
7 |
|
T54 |
1 |
|
T77 |
6 |
| others[2] |
245 |
1 |
|
T26 |
9 |
|
T20 |
1 |
|
T77 |
13 |
| others[3] |
373 |
1 |
|
T26 |
17 |
|
T22 |
1 |
|
T35 |
1 |
| false |
106 |
1 |
|
T18 |
1 |
|
T26 |
6 |
|
T54 |
1 |
| true |
5584 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1057 |
1 |
|
T4 |
1 |
|
T6 |
2 |
|
T26 |
20 |
| others[1] |
1016 |
1 |
|
T5 |
1 |
|
T16 |
1 |
|
T6 |
2 |
| others[2] |
1064 |
1 |
|
T6 |
5 |
|
T26 |
15 |
|
T54 |
1 |
| others[3] |
1727 |
1 |
|
T18 |
1 |
|
T6 |
3 |
|
T26 |
38 |
| false |
546 |
1 |
|
T6 |
1 |
|
T26 |
9 |
|
T39 |
2 |
| true |
1316 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T26 |
9 |
|
T77 |
6 |
|
T21 |
1 |
| others[1] |
226 |
1 |
|
T26 |
9 |
|
T77 |
16 |
|
T78 |
4 |
| others[2] |
219 |
1 |
|
T26 |
15 |
|
T35 |
1 |
|
T77 |
13 |
| others[3] |
376 |
1 |
|
T26 |
14 |
|
T54 |
1 |
|
T77 |
10 |
| false |
122 |
1 |
|
T26 |
4 |
|
T54 |
1 |
|
T77 |
6 |
| true |
5562 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
215 |
1 |
|
T26 |
15 |
|
T77 |
10 |
|
T78 |
8 |
| others[1] |
211 |
1 |
|
T26 |
11 |
|
T77 |
13 |
|
T7 |
1 |
| others[2] |
239 |
1 |
|
T16 |
1 |
|
T26 |
14 |
|
T54 |
1 |
| others[3] |
374 |
1 |
|
T26 |
10 |
|
T22 |
1 |
|
T35 |
1 |
| false |
118 |
1 |
|
T26 |
7 |
|
T77 |
6 |
|
T7 |
1 |
| true |
5569 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1172 |
1 |
|
T5 |
1 |
|
T6 |
3 |
|
T26 |
18 |
| others[1] |
1220 |
1 |
|
T16 |
1 |
|
T6 |
2 |
|
T26 |
18 |
| others[2] |
1256 |
1 |
|
T4 |
1 |
|
T6 |
2 |
|
T26 |
20 |
| others[3] |
2054 |
1 |
|
T6 |
5 |
|
T26 |
36 |
|
T54 |
1 |
| false |
659 |
1 |
|
T6 |
1 |
|
T26 |
9 |
|
T39 |
12 |
| true |
365 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1226 |
1 |
|
T10 |
1 |
|
T6 |
5 |
|
T26 |
28 |
| others[1] |
1194 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
3 |
| others[2] |
1228 |
1 |
|
T16 |
1 |
|
T6 |
1 |
|
T26 |
12 |
| others[3] |
2109 |
1 |
|
T6 |
4 |
|
T26 |
32 |
|
T39 |
24 |
| false |
622 |
1 |
|
T26 |
7 |
|
T39 |
6 |
|
T158 |
1 |
| true |
347 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
93 |
1 |
|
T26 |
4 |
|
T77 |
3 |
|
T78 |
3 |
| others[1] |
86 |
1 |
|
T26 |
3 |
|
T77 |
4 |
|
T78 |
5 |
| others[2] |
108 |
1 |
|
T26 |
6 |
|
T77 |
3 |
|
T78 |
4 |
| others[3] |
176 |
1 |
|
T16 |
1 |
|
T26 |
8 |
|
T54 |
2 |
| false |
59 |
1 |
|
T26 |
1 |
|
T77 |
2 |
|
T78 |
1 |
| true |
6204 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
199 |
1 |
|
T26 |
9 |
|
T54 |
1 |
|
T77 |
12 |
| others[1] |
229 |
1 |
|
T26 |
11 |
|
T35 |
1 |
|
T77 |
12 |
| others[2] |
227 |
1 |
|
T26 |
9 |
|
T20 |
1 |
|
T77 |
6 |
| others[3] |
385 |
1 |
|
T17 |
1 |
|
T26 |
20 |
|
T77 |
14 |
| false |
118 |
1 |
|
T26 |
2 |
|
T77 |
7 |
|
T78 |
6 |
| true |
5568 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1046 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T6 |
2 |
| others[1] |
1036 |
1 |
|
T17 |
1 |
|
T6 |
2 |
|
T26 |
20 |
| others[2] |
1012 |
1 |
|
T2 |
1 |
|
T6 |
2 |
|
T26 |
19 |
| others[3] |
1729 |
1 |
|
T5 |
1 |
|
T15 |
1 |
|
T6 |
6 |
| false |
542 |
1 |
|
T6 |
1 |
|
T26 |
9 |
|
T39 |
4 |
| true |
1361 |
1 |
|
T10 |
1 |
|
T18 |
1 |
|
T39 |
29 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
235 |
1 |
|
T16 |
1 |
|
T26 |
9 |
|
T35 |
1 |
| others[1] |
224 |
1 |
|
T26 |
11 |
|
T77 |
4 |
|
T78 |
9 |
| others[2] |
195 |
1 |
|
T18 |
1 |
|
T26 |
11 |
|
T77 |
7 |
| others[3] |
390 |
1 |
|
T26 |
15 |
|
T33 |
1 |
|
T77 |
12 |
| false |
120 |
1 |
|
T26 |
4 |
|
T77 |
4 |
|
T78 |
4 |
| true |
5562 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
211 |
1 |
|
T26 |
8 |
|
T77 |
9 |
|
T7 |
1 |
| others[1] |
204 |
1 |
|
T26 |
10 |
|
T77 |
6 |
|
T7 |
1 |
| others[2] |
214 |
1 |
|
T15 |
1 |
|
T26 |
10 |
|
T54 |
1 |
| others[3] |
346 |
1 |
|
T26 |
16 |
|
T33 |
1 |
|
T77 |
9 |
| false |
119 |
1 |
|
T16 |
1 |
|
T26 |
5 |
|
T35 |
1 |
| true |
5632 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1237 |
1 |
|
T6 |
3 |
|
T26 |
20 |
|
T54 |
2 |
| others[1] |
1211 |
1 |
|
T5 |
1 |
|
T16 |
1 |
|
T6 |
2 |
| others[2] |
1236 |
1 |
|
T4 |
1 |
|
T6 |
3 |
|
T26 |
19 |
| others[3] |
2004 |
1 |
|
T6 |
4 |
|
T26 |
30 |
|
T39 |
15 |
| false |
663 |
1 |
|
T6 |
1 |
|
T26 |
6 |
|
T39 |
9 |
| true |
375 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1228 |
1 |
|
T6 |
3 |
|
T26 |
24 |
|
T54 |
1 |
| others[1] |
1223 |
1 |
|
T6 |
3 |
|
T26 |
18 |
|
T39 |
19 |
| others[2] |
1272 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T26 |
20 |
| others[3] |
2061 |
1 |
|
T5 |
1 |
|
T16 |
1 |
|
T6 |
5 |
| false |
588 |
1 |
|
T6 |
1 |
|
T26 |
4 |
|
T19 |
1 |
| true |
354 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
95 |
1 |
|
T26 |
1 |
|
T77 |
3 |
|
T78 |
8 |
| others[1] |
103 |
1 |
|
T26 |
2 |
|
T54 |
1 |
|
T77 |
3 |
| others[2] |
104 |
1 |
|
T16 |
1 |
|
T26 |
4 |
|
T54 |
1 |
| others[3] |
188 |
1 |
|
T26 |
10 |
|
T77 |
7 |
|
T78 |
11 |
| false |
59 |
1 |
|
T26 |
6 |
|
T77 |
4 |
|
T78 |
3 |
| true |
6177 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
209 |
1 |
|
T26 |
8 |
|
T77 |
12 |
|
T21 |
1 |
| others[1] |
242 |
1 |
|
T26 |
11 |
|
T77 |
9 |
|
T7 |
2 |
| others[2] |
233 |
1 |
|
T18 |
1 |
|
T26 |
8 |
|
T22 |
1 |
| others[3] |
375 |
1 |
|
T26 |
17 |
|
T54 |
2 |
|
T20 |
1 |
| false |
111 |
1 |
|
T16 |
1 |
|
T26 |
9 |
|
T77 |
6 |
| true |
5556 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1052 |
1 |
|
T16 |
1 |
|
T6 |
1 |
|
T26 |
24 |
| others[1] |
1045 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T18 |
1 |
| others[2] |
992 |
1 |
|
T15 |
1 |
|
T6 |
3 |
|
T26 |
20 |
| others[3] |
1766 |
1 |
|
T6 |
4 |
|
T26 |
28 |
|
T39 |
8 |
| false |
556 |
1 |
|
T5 |
1 |
|
T6 |
2 |
|
T26 |
10 |
| true |
1315 |
1 |
|
T10 |
1 |
|
T17 |
1 |
|
T39 |
30 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
222 |
1 |
|
T17 |
1 |
|
T26 |
13 |
|
T54 |
1 |
| others[1] |
214 |
1 |
|
T18 |
1 |
|
T26 |
9 |
|
T77 |
10 |
| others[2] |
221 |
1 |
|
T26 |
16 |
|
T22 |
1 |
|
T77 |
11 |
| others[3] |
370 |
1 |
|
T26 |
19 |
|
T77 |
19 |
|
T23 |
1 |
| false |
100 |
1 |
|
T26 |
1 |
|
T77 |
4 |
|
T78 |
8 |
| true |
5599 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T26 |
12 |
|
T77 |
9 |
|
T78 |
16 |
| others[1] |
218 |
1 |
|
T17 |
1 |
|
T26 |
7 |
|
T33 |
1 |
| others[2] |
219 |
1 |
|
T15 |
1 |
|
T16 |
1 |
|
T26 |
8 |
| others[3] |
340 |
1 |
|
T26 |
12 |
|
T54 |
1 |
|
T22 |
1 |
| false |
124 |
1 |
|
T26 |
7 |
|
T77 |
3 |
|
T78 |
6 |
| true |
5596 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1260 |
1 |
|
T6 |
3 |
|
T26 |
18 |
|
T39 |
7 |
| others[1] |
1196 |
1 |
|
T6 |
2 |
|
T26 |
16 |
|
T39 |
9 |
| others[2] |
1189 |
1 |
|
T5 |
1 |
|
T6 |
3 |
|
T26 |
20 |
| others[3] |
2092 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T16 |
1 |
| false |
617 |
1 |
|
T26 |
6 |
|
T54 |
1 |
|
T39 |
4 |
| true |
372 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1264 |
1 |
|
T16 |
1 |
|
T6 |
1 |
|
T26 |
17 |
| others[1] |
1179 |
1 |
|
T5 |
1 |
|
T6 |
4 |
|
T26 |
21 |
| others[2] |
1216 |
1 |
|
T6 |
2 |
|
T26 |
17 |
|
T54 |
1 |
| others[3] |
2071 |
1 |
|
T4 |
1 |
|
T6 |
3 |
|
T26 |
36 |
| false |
646 |
1 |
|
T6 |
3 |
|
T26 |
10 |
|
T39 |
4 |
| true |
350 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
89 |
1 |
|
T26 |
3 |
|
T77 |
5 |
|
T78 |
4 |
| others[1] |
96 |
1 |
|
T77 |
5 |
|
T78 |
3 |
|
T232 |
4 |
| others[2] |
102 |
1 |
|
T26 |
2 |
|
T54 |
1 |
|
T77 |
2 |
| others[3] |
167 |
1 |
|
T16 |
1 |
|
T26 |
7 |
|
T54 |
1 |
| false |
41 |
1 |
|
T26 |
2 |
|
T77 |
2 |
|
T78 |
1 |
| true |
6231 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T26 |
5 |
|
T77 |
8 |
|
T78 |
9 |
| others[1] |
231 |
1 |
|
T15 |
1 |
|
T26 |
12 |
|
T77 |
7 |
| others[2] |
222 |
1 |
|
T26 |
10 |
|
T20 |
1 |
|
T77 |
12 |
| others[3] |
393 |
1 |
|
T16 |
1 |
|
T26 |
15 |
|
T77 |
15 |
| false |
127 |
1 |
|
T17 |
1 |
|
T26 |
9 |
|
T77 |
5 |
| true |
5524 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1056 |
1 |
|
T6 |
2 |
|
T26 |
24 |
|
T54 |
1 |
| others[1] |
1058 |
1 |
|
T6 |
2 |
|
T26 |
17 |
|
T54 |
1 |
| others[2] |
1019 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T16 |
1 |
| others[3] |
1702 |
1 |
|
T15 |
1 |
|
T18 |
1 |
|
T6 |
2 |
| false |
523 |
1 |
|
T5 |
1 |
|
T6 |
2 |
|
T26 |
9 |
| true |
1368 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T39 |
31 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T26 |
7 |
|
T77 |
9 |
|
T207 |
1 |
| others[1] |
221 |
1 |
|
T17 |
1 |
|
T26 |
7 |
|
T54 |
1 |
| others[2] |
241 |
1 |
|
T26 |
8 |
|
T77 |
9 |
|
T23 |
1 |
| others[3] |
387 |
1 |
|
T16 |
1 |
|
T26 |
10 |
|
T54 |
1 |
| false |
110 |
1 |
|
T26 |
6 |
|
T77 |
7 |
|
T78 |
7 |
| true |
5538 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
206 |
1 |
|
T26 |
3 |
|
T77 |
10 |
|
T78 |
9 |
| others[1] |
203 |
1 |
|
T17 |
1 |
|
T26 |
11 |
|
T77 |
11 |
| others[2] |
220 |
1 |
|
T16 |
1 |
|
T26 |
6 |
|
T77 |
10 |
| others[3] |
363 |
1 |
|
T26 |
14 |
|
T54 |
2 |
|
T35 |
1 |
| false |
94 |
1 |
|
T26 |
7 |
|
T77 |
5 |
|
T78 |
1 |
| true |
5640 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1197 |
1 |
|
T16 |
1 |
|
T26 |
15 |
|
T39 |
15 |
| others[1] |
1215 |
1 |
|
T5 |
1 |
|
T6 |
4 |
|
T26 |
23 |
| others[2] |
1232 |
1 |
|
T6 |
1 |
|
T26 |
17 |
|
T54 |
1 |
| others[3] |
2093 |
1 |
|
T4 |
1 |
|
T6 |
8 |
|
T26 |
39 |
| false |
624 |
1 |
|
T26 |
7 |
|
T54 |
1 |
|
T39 |
4 |
| true |
365 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1218 |
1 |
|
T6 |
2 |
|
T26 |
14 |
|
T19 |
1 |
| others[1] |
1249 |
1 |
|
T4 |
1 |
|
T6 |
2 |
|
T26 |
24 |
| others[2] |
1279 |
1 |
|
T16 |
1 |
|
T6 |
3 |
|
T26 |
20 |
| others[3] |
2003 |
1 |
|
T5 |
1 |
|
T6 |
5 |
|
T26 |
35 |
| false |
626 |
1 |
|
T6 |
1 |
|
T26 |
8 |
|
T39 |
8 |
| true |
351 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
109 |
1 |
|
T26 |
1 |
|
T77 |
2 |
|
T78 |
4 |
| others[1] |
90 |
1 |
|
T26 |
2 |
|
T77 |
5 |
|
T78 |
4 |
| others[2] |
98 |
1 |
|
T26 |
3 |
|
T77 |
1 |
|
T78 |
4 |
| others[3] |
179 |
1 |
|
T26 |
3 |
|
T54 |
2 |
|
T77 |
11 |
| false |
61 |
1 |
|
T77 |
1 |
|
T78 |
2 |
|
T372 |
1 |
| true |
6189 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
230 |
1 |
|
T26 |
13 |
|
T35 |
1 |
|
T77 |
13 |
| others[1] |
245 |
1 |
|
T26 |
10 |
|
T77 |
9 |
|
T7 |
1 |
| others[2] |
233 |
1 |
|
T26 |
9 |
|
T77 |
8 |
|
T371 |
1 |
| others[3] |
359 |
1 |
|
T17 |
1 |
|
T26 |
16 |
|
T33 |
1 |
| false |
112 |
1 |
|
T26 |
3 |
|
T22 |
1 |
|
T77 |
6 |
| true |
5547 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1029 |
1 |
|
T18 |
1 |
|
T6 |
4 |
|
T26 |
21 |
| others[1] |
1024 |
1 |
|
T15 |
1 |
|
T6 |
2 |
|
T26 |
20 |
| others[2] |
1042 |
1 |
|
T6 |
4 |
|
T26 |
13 |
|
T19 |
1 |
| others[3] |
1723 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T5 |
1 |
| false |
569 |
1 |
|
T6 |
2 |
|
T26 |
12 |
|
T39 |
7 |
| true |
1339 |
1 |
|
T2 |
1 |
|
T39 |
32 |
|
T55 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |