Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T26 |
15 |
|
T35 |
1 |
|
T77 |
9 |
| others[1] |
240 |
1 |
|
T26 |
8 |
|
T77 |
6 |
|
T78 |
10 |
| others[2] |
214 |
1 |
|
T26 |
7 |
|
T77 |
9 |
|
T207 |
1 |
| others[3] |
380 |
1 |
|
T26 |
20 |
|
T77 |
22 |
|
T371 |
1 |
| false |
119 |
1 |
|
T16 |
1 |
|
T26 |
5 |
|
T77 |
2 |
| true |
5552 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
208 |
1 |
|
T16 |
1 |
|
T26 |
8 |
|
T54 |
1 |
| others[1] |
244 |
1 |
|
T26 |
11 |
|
T77 |
7 |
|
T78 |
10 |
| others[2] |
222 |
1 |
|
T26 |
9 |
|
T77 |
7 |
|
T7 |
1 |
| others[3] |
349 |
1 |
|
T15 |
1 |
|
T26 |
25 |
|
T77 |
20 |
| false |
123 |
1 |
|
T26 |
4 |
|
T22 |
1 |
|
T77 |
8 |
| true |
5580 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1234 |
1 |
|
T5 |
1 |
|
T6 |
2 |
|
T26 |
19 |
| others[1] |
1194 |
1 |
|
T26 |
21 |
|
T39 |
14 |
|
T99 |
1 |
| others[2] |
1298 |
1 |
|
T2 |
1 |
|
T6 |
5 |
|
T26 |
17 |
| others[3] |
2003 |
1 |
|
T4 |
1 |
|
T6 |
5 |
|
T26 |
39 |
| false |
628 |
1 |
|
T16 |
1 |
|
T6 |
1 |
|
T26 |
5 |
| true |
369 |
1 |
|
T10 |
1 |
|
T15 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1257 |
1 |
|
T6 |
3 |
|
T26 |
20 |
|
T39 |
11 |
| others[1] |
1219 |
1 |
|
T5 |
1 |
|
T26 |
26 |
|
T39 |
13 |
| others[2] |
1197 |
1 |
|
T4 |
1 |
|
T6 |
4 |
|
T26 |
10 |
| others[3] |
2039 |
1 |
|
T16 |
1 |
|
T6 |
3 |
|
T26 |
30 |
| false |
657 |
1 |
|
T6 |
3 |
|
T26 |
15 |
|
T39 |
7 |
| true |
357 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
109 |
1 |
|
T26 |
1 |
|
T77 |
5 |
|
T78 |
4 |
| others[1] |
118 |
1 |
|
T16 |
1 |
|
T26 |
8 |
|
T54 |
1 |
| others[2] |
88 |
1 |
|
T26 |
5 |
|
T35 |
1 |
|
T77 |
2 |
| others[3] |
182 |
1 |
|
T26 |
9 |
|
T77 |
11 |
|
T78 |
6 |
| false |
59 |
1 |
|
T54 |
1 |
|
T77 |
4 |
|
T78 |
2 |
| true |
6170 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
253 |
1 |
|
T26 |
19 |
|
T77 |
13 |
|
T23 |
1 |
| others[1] |
216 |
1 |
|
T17 |
1 |
|
T26 |
3 |
|
T22 |
1 |
| others[2] |
230 |
1 |
|
T26 |
10 |
|
T33 |
1 |
|
T77 |
7 |
| others[3] |
360 |
1 |
|
T15 |
1 |
|
T16 |
1 |
|
T18 |
1 |
| false |
127 |
1 |
|
T26 |
9 |
|
T77 |
8 |
|
T78 |
7 |
| true |
5540 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1061 |
1 |
|
T6 |
1 |
|
T26 |
16 |
|
T39 |
4 |
| others[1] |
1026 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T6 |
1 |
| others[2] |
1024 |
1 |
|
T26 |
18 |
|
T54 |
1 |
|
T39 |
6 |
| others[3] |
1727 |
1 |
|
T10 |
1 |
|
T5 |
1 |
|
T15 |
1 |
| false |
530 |
1 |
|
T6 |
2 |
|
T26 |
7 |
|
T39 |
5 |
| true |
1358 |
1 |
|
T2 |
1 |
|
T18 |
1 |
|
T39 |
22 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
211 |
1 |
|
T26 |
11 |
|
T22 |
1 |
|
T77 |
14 |
| others[1] |
230 |
1 |
|
T18 |
1 |
|
T26 |
12 |
|
T77 |
13 |
| others[2] |
245 |
1 |
|
T17 |
1 |
|
T26 |
9 |
|
T33 |
1 |
| others[3] |
369 |
1 |
|
T15 |
1 |
|
T26 |
13 |
|
T77 |
21 |
| false |
101 |
1 |
|
T26 |
4 |
|
T77 |
5 |
|
T78 |
5 |
| true |
5570 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
217 |
1 |
|
T15 |
1 |
|
T26 |
9 |
|
T77 |
7 |
| others[1] |
221 |
1 |
|
T16 |
1 |
|
T26 |
15 |
|
T77 |
14 |
| others[2] |
211 |
1 |
|
T26 |
5 |
|
T33 |
1 |
|
T77 |
11 |
| others[3] |
352 |
1 |
|
T17 |
1 |
|
T26 |
18 |
|
T54 |
1 |
| false |
110 |
1 |
|
T26 |
6 |
|
T77 |
4 |
|
T78 |
6 |
| true |
5615 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1269 |
1 |
|
T6 |
3 |
|
T26 |
28 |
|
T54 |
1 |
| others[1] |
1199 |
1 |
|
T5 |
1 |
|
T6 |
4 |
|
T26 |
20 |
| others[2] |
1238 |
1 |
|
T26 |
19 |
|
T54 |
1 |
|
T39 |
10 |
| others[3] |
2017 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T16 |
1 |
| false |
629 |
1 |
|
T26 |
4 |
|
T39 |
8 |
|
T158 |
1 |
| true |
374 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1218 |
1 |
|
T16 |
1 |
|
T6 |
3 |
|
T26 |
23 |
| others[1] |
1258 |
1 |
|
T6 |
2 |
|
T26 |
19 |
|
T54 |
1 |
| others[2] |
1227 |
1 |
|
T6 |
1 |
|
T26 |
25 |
|
T39 |
14 |
| others[3] |
2005 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
7 |
| false |
676 |
1 |
|
T26 |
6 |
|
T39 |
4 |
|
T158 |
1 |
| true |
342 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
104 |
1 |
|
T26 |
5 |
|
T54 |
1 |
|
T77 |
5 |
| others[1] |
91 |
1 |
|
T26 |
4 |
|
T77 |
6 |
|
T78 |
7 |
| others[2] |
111 |
1 |
|
T16 |
1 |
|
T26 |
2 |
|
T54 |
1 |
| others[3] |
173 |
1 |
|
T26 |
8 |
|
T77 |
8 |
|
T78 |
5 |
| false |
47 |
1 |
|
T26 |
1 |
|
T78 |
4 |
|
T183 |
1 |
| true |
6200 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T26 |
5 |
|
T77 |
4 |
|
T78 |
10 |
| others[1] |
230 |
1 |
|
T17 |
1 |
|
T26 |
9 |
|
T77 |
10 |
| others[2] |
214 |
1 |
|
T26 |
13 |
|
T33 |
1 |
|
T77 |
11 |
| others[3] |
384 |
1 |
|
T26 |
17 |
|
T35 |
1 |
|
T77 |
20 |
| false |
120 |
1 |
|
T26 |
5 |
|
T54 |
1 |
|
T77 |
7 |
| true |
5554 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1022 |
1 |
|
T4 |
1 |
|
T26 |
21 |
|
T39 |
8 |
| others[1] |
1053 |
1 |
|
T6 |
3 |
|
T26 |
24 |
|
T54 |
1 |
| others[2] |
1080 |
1 |
|
T15 |
1 |
|
T16 |
1 |
|
T6 |
1 |
| others[3] |
1701 |
1 |
|
T5 |
1 |
|
T6 |
5 |
|
T26 |
29 |
| false |
513 |
1 |
|
T6 |
4 |
|
T26 |
14 |
|
T19 |
1 |
| true |
1357 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
243 |
1 |
|
T26 |
16 |
|
T54 |
1 |
|
T77 |
6 |
| others[1] |
227 |
1 |
|
T16 |
1 |
|
T26 |
9 |
|
T77 |
8 |
| others[2] |
233 |
1 |
|
T26 |
11 |
|
T77 |
8 |
|
T78 |
11 |
| others[3] |
365 |
1 |
|
T26 |
13 |
|
T77 |
11 |
|
T371 |
1 |
| false |
112 |
1 |
|
T26 |
3 |
|
T77 |
7 |
|
T78 |
5 |
| true |
5546 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
186 |
1 |
|
T26 |
6 |
|
T77 |
13 |
|
T78 |
6 |
| others[1] |
210 |
1 |
|
T26 |
8 |
|
T77 |
11 |
|
T78 |
11 |
| others[2] |
227 |
1 |
|
T15 |
1 |
|
T26 |
9 |
|
T54 |
1 |
| others[3] |
371 |
1 |
|
T26 |
17 |
|
T33 |
1 |
|
T77 |
16 |
| false |
95 |
1 |
|
T26 |
5 |
|
T77 |
5 |
|
T78 |
5 |
| true |
5637 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1253 |
1 |
|
T4 |
1 |
|
T6 |
2 |
|
T26 |
19 |
| others[1] |
1220 |
1 |
|
T16 |
1 |
|
T6 |
3 |
|
T26 |
21 |
| others[2] |
1237 |
1 |
|
T5 |
1 |
|
T26 |
19 |
|
T39 |
7 |
| others[3] |
1970 |
1 |
|
T6 |
6 |
|
T26 |
37 |
|
T19 |
1 |
| false |
665 |
1 |
|
T6 |
2 |
|
T26 |
5 |
|
T39 |
6 |
| true |
381 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1194 |
1 |
|
T6 |
1 |
|
T26 |
19 |
|
T54 |
1 |
| others[1] |
1251 |
1 |
|
T6 |
3 |
|
T26 |
18 |
|
T39 |
12 |
| others[2] |
1256 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T6 |
3 |
| others[3] |
2071 |
1 |
|
T5 |
1 |
|
T6 |
5 |
|
T26 |
32 |
| false |
610 |
1 |
|
T6 |
1 |
|
T26 |
15 |
|
T39 |
4 |
| true |
344 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
102 |
1 |
|
T26 |
3 |
|
T77 |
3 |
|
T78 |
6 |
| others[1] |
106 |
1 |
|
T26 |
9 |
|
T77 |
3 |
|
T78 |
4 |
| others[2] |
115 |
1 |
|
T26 |
5 |
|
T54 |
1 |
|
T77 |
5 |
| others[3] |
186 |
1 |
|
T26 |
4 |
|
T54 |
1 |
|
T77 |
10 |
| false |
39 |
1 |
|
T26 |
1 |
|
T77 |
3 |
|
T78 |
2 |
| true |
6178 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
237 |
1 |
|
T26 |
5 |
|
T22 |
1 |
|
T77 |
14 |
| others[1] |
200 |
1 |
|
T26 |
8 |
|
T20 |
1 |
|
T77 |
14 |
| others[2] |
211 |
1 |
|
T26 |
4 |
|
T35 |
1 |
|
T77 |
5 |
| others[3] |
372 |
1 |
|
T26 |
19 |
|
T77 |
14 |
|
T36 |
1 |
| false |
123 |
1 |
|
T26 |
6 |
|
T77 |
1 |
|
T23 |
1 |
| true |
5583 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1029 |
1 |
|
T6 |
2 |
|
T26 |
16 |
|
T39 |
12 |
| others[1] |
1083 |
1 |
|
T4 |
1 |
|
T6 |
3 |
|
T26 |
22 |
| others[2] |
1002 |
1 |
|
T16 |
1 |
|
T17 |
1 |
|
T6 |
1 |
| others[3] |
1762 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T6 |
3 |
| false |
519 |
1 |
|
T5 |
1 |
|
T6 |
4 |
|
T26 |
15 |
| true |
1331 |
1 |
|
T10 |
1 |
|
T18 |
1 |
|
T39 |
22 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T15 |
1 |
|
T26 |
8 |
|
T77 |
13 |
| others[1] |
216 |
1 |
|
T17 |
1 |
|
T26 |
10 |
|
T22 |
1 |
| others[2] |
230 |
1 |
|
T16 |
1 |
|
T26 |
9 |
|
T77 |
11 |
| others[3] |
343 |
1 |
|
T26 |
21 |
|
T33 |
1 |
|
T77 |
11 |
| false |
115 |
1 |
|
T26 |
6 |
|
T54 |
1 |
|
T77 |
2 |
| true |
5593 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
208 |
1 |
|
T26 |
12 |
|
T77 |
4 |
|
T7 |
2 |
| others[1] |
211 |
1 |
|
T26 |
7 |
|
T54 |
1 |
|
T77 |
9 |
| others[2] |
236 |
1 |
|
T15 |
1 |
|
T17 |
1 |
|
T26 |
11 |
| others[3] |
385 |
1 |
|
T26 |
19 |
|
T35 |
1 |
|
T77 |
18 |
| false |
110 |
1 |
|
T26 |
4 |
|
T77 |
3 |
|
T7 |
1 |
| true |
5576 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1246 |
1 |
|
T18 |
1 |
|
T26 |
20 |
|
T39 |
11 |
| others[1] |
1215 |
1 |
|
T6 |
2 |
|
T26 |
20 |
|
T39 |
13 |
| others[2] |
1254 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T26 |
16 |
| others[3] |
2043 |
1 |
|
T16 |
1 |
|
T6 |
6 |
|
T26 |
33 |
| false |
590 |
1 |
|
T5 |
1 |
|
T6 |
4 |
|
T26 |
12 |
| true |
378 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1285 |
1 |
|
T4 |
1 |
|
T6 |
2 |
|
T26 |
26 |
| others[1] |
1197 |
1 |
|
T6 |
4 |
|
T26 |
20 |
|
T39 |
10 |
| others[2] |
1266 |
1 |
|
T5 |
1 |
|
T6 |
2 |
|
T26 |
18 |
| others[3] |
1984 |
1 |
|
T10 |
1 |
|
T16 |
1 |
|
T6 |
3 |
| false |
645 |
1 |
|
T6 |
2 |
|
T26 |
16 |
|
T39 |
7 |
| true |
349 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
117 |
1 |
|
T26 |
8 |
|
T77 |
7 |
|
T78 |
3 |
| others[1] |
107 |
1 |
|
T16 |
1 |
|
T26 |
5 |
|
T77 |
6 |
| others[2] |
134 |
1 |
|
T26 |
4 |
|
T54 |
1 |
|
T77 |
5 |
| others[3] |
180 |
1 |
|
T26 |
12 |
|
T54 |
1 |
|
T77 |
4 |
| false |
55 |
1 |
|
T77 |
4 |
|
T78 |
1 |
|
T372 |
1 |
| true |
6133 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T17 |
1 |
|
T26 |
11 |
|
T20 |
1 |
| others[1] |
241 |
1 |
|
T26 |
10 |
|
T77 |
4 |
|
T90 |
1 |
| others[2] |
209 |
1 |
|
T26 |
5 |
|
T77 |
11 |
|
T23 |
1 |
| others[3] |
374 |
1 |
|
T26 |
15 |
|
T54 |
1 |
|
T33 |
1 |
| false |
125 |
1 |
|
T26 |
5 |
|
T77 |
7 |
|
T21 |
1 |
| true |
5545 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1022 |
1 |
|
T6 |
3 |
|
T26 |
17 |
|
T54 |
2 |
| others[1] |
1066 |
1 |
|
T5 |
1 |
|
T16 |
1 |
|
T6 |
3 |
| others[2] |
1074 |
1 |
|
T15 |
1 |
|
T17 |
1 |
|
T6 |
1 |
| others[3] |
1697 |
1 |
|
T10 |
1 |
|
T6 |
4 |
|
T26 |
34 |
| false |
563 |
1 |
|
T4 |
1 |
|
T6 |
2 |
|
T26 |
13 |
| true |
1304 |
1 |
|
T2 |
1 |
|
T18 |
1 |
|
T39 |
39 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T17 |
1 |
|
T26 |
11 |
|
T77 |
8 |
| others[1] |
227 |
1 |
|
T26 |
12 |
|
T54 |
1 |
|
T77 |
12 |
| others[2] |
221 |
1 |
|
T16 |
1 |
|
T26 |
11 |
|
T77 |
13 |
| others[3] |
418 |
1 |
|
T26 |
18 |
|
T33 |
1 |
|
T77 |
17 |
| false |
116 |
1 |
|
T26 |
4 |
|
T77 |
5 |
|
T78 |
7 |
| true |
5518 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T16 |
1 |
|
T26 |
10 |
|
T77 |
11 |
| others[1] |
240 |
1 |
|
T26 |
7 |
|
T54 |
1 |
|
T35 |
1 |
| others[2] |
202 |
1 |
|
T26 |
8 |
|
T54 |
1 |
|
T33 |
1 |
| others[3] |
364 |
1 |
|
T17 |
1 |
|
T26 |
16 |
|
T77 |
11 |
| false |
132 |
1 |
|
T26 |
7 |
|
T77 |
7 |
|
T78 |
2 |
| true |
5561 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1166 |
1 |
|
T6 |
5 |
|
T26 |
19 |
|
T39 |
10 |
| others[1] |
1290 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T26 |
19 |
| others[2] |
1235 |
1 |
|
T16 |
1 |
|
T6 |
4 |
|
T26 |
25 |
| others[3] |
1993 |
1 |
|
T5 |
1 |
|
T6 |
2 |
|
T26 |
26 |
| false |
658 |
1 |
|
T6 |
1 |
|
T26 |
12 |
|
T39 |
10 |
| true |
384 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |