Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1247 |
1 |
|
T5 |
1 |
|
T6 |
3 |
|
T26 |
25 |
| others[1] |
1235 |
1 |
|
T16 |
1 |
|
T6 |
2 |
|
T26 |
21 |
| others[2] |
1246 |
1 |
|
T6 |
5 |
|
T26 |
23 |
|
T39 |
12 |
| others[3] |
2001 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T6 |
2 |
| false |
642 |
1 |
|
T6 |
1 |
|
T26 |
8 |
|
T39 |
3 |
| true |
355 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
91 |
1 |
|
T26 |
4 |
|
T54 |
1 |
|
T77 |
5 |
| others[1] |
114 |
1 |
|
T16 |
1 |
|
T26 |
8 |
|
T54 |
1 |
| others[2] |
103 |
1 |
|
T77 |
6 |
|
T78 |
2 |
|
T373 |
1 |
| others[3] |
151 |
1 |
|
T26 |
7 |
|
T77 |
6 |
|
T78 |
4 |
| false |
56 |
1 |
|
T26 |
2 |
|
T77 |
2 |
|
T78 |
6 |
| true |
6211 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
214 |
1 |
|
T26 |
13 |
|
T77 |
7 |
|
T21 |
1 |
| others[1] |
220 |
1 |
|
T26 |
10 |
|
T77 |
9 |
|
T23 |
1 |
| others[2] |
242 |
1 |
|
T18 |
1 |
|
T26 |
7 |
|
T54 |
1 |
| others[3] |
388 |
1 |
|
T15 |
1 |
|
T26 |
23 |
|
T54 |
1 |
| false |
107 |
1 |
|
T26 |
5 |
|
T20 |
1 |
|
T77 |
6 |
| true |
5555 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
998 |
1 |
|
T10 |
1 |
|
T6 |
1 |
|
T26 |
24 |
| others[1] |
1043 |
1 |
|
T4 |
1 |
|
T6 |
6 |
|
T26 |
16 |
| others[2] |
1048 |
1 |
|
T17 |
1 |
|
T6 |
2 |
|
T26 |
19 |
| others[3] |
1745 |
1 |
|
T16 |
1 |
|
T6 |
2 |
|
T26 |
33 |
| false |
545 |
1 |
|
T5 |
1 |
|
T6 |
2 |
|
T26 |
9 |
| true |
1347 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T26 |
14 |
|
T77 |
10 |
|
T78 |
9 |
| others[1] |
241 |
1 |
|
T26 |
9 |
|
T77 |
20 |
|
T78 |
10 |
| others[2] |
246 |
1 |
|
T17 |
1 |
|
T26 |
5 |
|
T22 |
1 |
| others[3] |
354 |
1 |
|
T15 |
1 |
|
T18 |
1 |
|
T26 |
13 |
| false |
124 |
1 |
|
T26 |
6 |
|
T33 |
1 |
|
T77 |
7 |
| true |
5545 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T26 |
11 |
|
T77 |
11 |
|
T78 |
11 |
| others[1] |
215 |
1 |
|
T26 |
6 |
|
T35 |
1 |
|
T77 |
6 |
| others[2] |
212 |
1 |
|
T17 |
1 |
|
T26 |
5 |
|
T77 |
5 |
| others[3] |
347 |
1 |
|
T26 |
17 |
|
T77 |
20 |
|
T78 |
16 |
| false |
108 |
1 |
|
T26 |
4 |
|
T77 |
5 |
|
T78 |
7 |
| true |
5611 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1203 |
1 |
|
T2 |
1 |
|
T6 |
2 |
|
T26 |
25 |
| others[1] |
1199 |
1 |
|
T5 |
1 |
|
T6 |
3 |
|
T26 |
18 |
| others[2] |
1284 |
1 |
|
T6 |
1 |
|
T26 |
21 |
|
T39 |
9 |
| others[3] |
2038 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T6 |
6 |
| false |
643 |
1 |
|
T6 |
1 |
|
T26 |
7 |
|
T39 |
10 |
| true |
359 |
1 |
|
T10 |
1 |
|
T15 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1189 |
1 |
|
T16 |
1 |
|
T6 |
3 |
|
T26 |
25 |
| others[1] |
1269 |
1 |
|
T5 |
1 |
|
T6 |
2 |
|
T26 |
25 |
| others[2] |
1263 |
1 |
|
T4 |
1 |
|
T6 |
4 |
|
T26 |
11 |
| others[3] |
2004 |
1 |
|
T6 |
4 |
|
T26 |
27 |
|
T54 |
1 |
| false |
647 |
1 |
|
T26 |
13 |
|
T39 |
10 |
|
T158 |
2 |
| true |
354 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
107 |
1 |
|
T26 |
4 |
|
T54 |
1 |
|
T77 |
8 |
| others[1] |
106 |
1 |
|
T26 |
5 |
|
T77 |
2 |
|
T78 |
3 |
| others[2] |
119 |
1 |
|
T16 |
1 |
|
T26 |
5 |
|
T77 |
2 |
| others[3] |
164 |
1 |
|
T15 |
1 |
|
T26 |
4 |
|
T54 |
1 |
| false |
51 |
1 |
|
T77 |
1 |
|
T78 |
2 |
|
T374 |
1 |
| true |
6179 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T26 |
11 |
|
T77 |
7 |
|
T78 |
9 |
| others[1] |
265 |
1 |
|
T26 |
7 |
|
T54 |
1 |
|
T77 |
8 |
| others[2] |
207 |
1 |
|
T26 |
7 |
|
T77 |
14 |
|
T21 |
1 |
| others[3] |
397 |
1 |
|
T16 |
1 |
|
T26 |
21 |
|
T20 |
1 |
| false |
120 |
1 |
|
T26 |
3 |
|
T77 |
5 |
|
T7 |
1 |
| true |
5516 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1059 |
1 |
|
T15 |
1 |
|
T6 |
3 |
|
T26 |
20 |
| others[1] |
1053 |
1 |
|
T6 |
1 |
|
T26 |
22 |
|
T39 |
10 |
| others[2] |
1024 |
1 |
|
T10 |
1 |
|
T5 |
1 |
|
T17 |
1 |
| others[3] |
1699 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T18 |
1 |
| false |
566 |
1 |
|
T6 |
3 |
|
T26 |
10 |
|
T158 |
2 |
| true |
1325 |
1 |
|
T2 |
1 |
|
T39 |
32 |
|
T55 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T16 |
1 |
|
T26 |
11 |
|
T77 |
10 |
| others[1] |
213 |
1 |
|
T26 |
11 |
|
T35 |
1 |
|
T77 |
9 |
| others[2] |
233 |
1 |
|
T26 |
7 |
|
T54 |
1 |
|
T22 |
1 |
| others[3] |
373 |
1 |
|
T17 |
1 |
|
T26 |
15 |
|
T77 |
15 |
| false |
118 |
1 |
|
T26 |
9 |
|
T77 |
5 |
|
T78 |
3 |
| true |
5564 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
237 |
1 |
|
T26 |
6 |
|
T77 |
10 |
|
T78 |
11 |
| others[1] |
233 |
1 |
|
T26 |
13 |
|
T77 |
9 |
|
T78 |
6 |
| others[2] |
206 |
1 |
|
T26 |
13 |
|
T35 |
1 |
|
T77 |
7 |
| others[3] |
384 |
1 |
|
T17 |
1 |
|
T26 |
17 |
|
T77 |
23 |
| false |
117 |
1 |
|
T26 |
6 |
|
T33 |
1 |
|
T77 |
6 |
| true |
5549 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1272 |
1 |
|
T10 |
1 |
|
T5 |
1 |
|
T16 |
1 |
| others[1] |
1201 |
1 |
|
T6 |
1 |
|
T26 |
16 |
|
T19 |
1 |
| others[2] |
1224 |
1 |
|
T6 |
4 |
|
T26 |
20 |
|
T39 |
10 |
| others[3] |
2032 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T6 |
6 |
| false |
629 |
1 |
|
T6 |
1 |
|
T26 |
6 |
|
T39 |
5 |
| true |
368 |
1 |
|
T15 |
1 |
|
T17 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1170 |
1 |
|
T6 |
2 |
|
T26 |
19 |
|
T54 |
1 |
| others[1] |
1240 |
1 |
|
T6 |
3 |
|
T26 |
21 |
|
T39 |
12 |
| others[2] |
1181 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
| others[3] |
2098 |
1 |
|
T16 |
1 |
|
T6 |
6 |
|
T26 |
37 |
| false |
687 |
1 |
|
T6 |
1 |
|
T26 |
13 |
|
T39 |
5 |
| true |
350 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
92 |
1 |
|
T26 |
3 |
|
T77 |
2 |
|
T78 |
4 |
| others[1] |
110 |
1 |
|
T26 |
9 |
|
T54 |
1 |
|
T77 |
3 |
| others[2] |
88 |
1 |
|
T26 |
3 |
|
T77 |
4 |
|
T78 |
2 |
| others[3] |
166 |
1 |
|
T26 |
5 |
|
T54 |
1 |
|
T77 |
7 |
| false |
65 |
1 |
|
T77 |
1 |
|
T78 |
1 |
|
T105 |
1 |
| true |
6205 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
219 |
1 |
|
T17 |
1 |
|
T26 |
10 |
|
T33 |
1 |
| others[1] |
238 |
1 |
|
T26 |
10 |
|
T77 |
10 |
|
T90 |
1 |
| others[2] |
229 |
1 |
|
T26 |
7 |
|
T77 |
8 |
|
T207 |
1 |
| others[3] |
375 |
1 |
|
T26 |
19 |
|
T35 |
1 |
|
T77 |
16 |
| false |
106 |
1 |
|
T26 |
3 |
|
T77 |
5 |
|
T78 |
4 |
| true |
5559 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1027 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T16 |
1 |
| others[1] |
1064 |
1 |
|
T6 |
1 |
|
T26 |
20 |
|
T39 |
7 |
| others[2] |
1018 |
1 |
|
T15 |
1 |
|
T6 |
6 |
|
T26 |
18 |
| others[3] |
1726 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T18 |
1 |
| false |
541 |
1 |
|
T6 |
1 |
|
T26 |
9 |
|
T19 |
1 |
| true |
1350 |
1 |
|
T17 |
1 |
|
T39 |
38 |
|
T55 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
214 |
1 |
|
T26 |
11 |
|
T77 |
9 |
|
T207 |
1 |
| others[1] |
247 |
1 |
|
T15 |
1 |
|
T26 |
4 |
|
T77 |
7 |
| others[2] |
215 |
1 |
|
T16 |
1 |
|
T26 |
6 |
|
T54 |
1 |
| others[3] |
381 |
1 |
|
T26 |
11 |
|
T33 |
1 |
|
T77 |
21 |
| false |
125 |
1 |
|
T18 |
1 |
|
T26 |
7 |
|
T35 |
1 |
| true |
5544 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
188 |
1 |
|
T26 |
9 |
|
T77 |
5 |
|
T78 |
12 |
| others[1] |
205 |
1 |
|
T26 |
8 |
|
T77 |
10 |
|
T7 |
2 |
| others[2] |
212 |
1 |
|
T26 |
14 |
|
T54 |
1 |
|
T77 |
7 |
| others[3] |
382 |
1 |
|
T26 |
16 |
|
T77 |
14 |
|
T23 |
1 |
| false |
106 |
1 |
|
T26 |
1 |
|
T77 |
4 |
|
T78 |
4 |
| true |
5633 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1265 |
1 |
|
T4 |
1 |
|
T6 |
3 |
|
T26 |
29 |
| others[1] |
1179 |
1 |
|
T6 |
1 |
|
T26 |
12 |
|
T39 |
12 |
| others[2] |
1238 |
1 |
|
T5 |
1 |
|
T16 |
1 |
|
T6 |
2 |
| others[3] |
2048 |
1 |
|
T6 |
3 |
|
T26 |
25 |
|
T54 |
2 |
| false |
622 |
1 |
|
T6 |
4 |
|
T26 |
16 |
|
T39 |
10 |
| true |
374 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1294 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T6 |
2 |
| others[1] |
1262 |
1 |
|
T5 |
1 |
|
T6 |
5 |
|
T26 |
19 |
| others[2] |
1166 |
1 |
|
T6 |
1 |
|
T26 |
16 |
|
T39 |
5 |
| others[3] |
2013 |
1 |
|
T6 |
2 |
|
T26 |
29 |
|
T39 |
26 |
| false |
646 |
1 |
|
T6 |
3 |
|
T26 |
9 |
|
T54 |
1 |
| true |
345 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
108 |
1 |
|
T26 |
4 |
|
T77 |
5 |
|
T187 |
1 |
| others[1] |
100 |
1 |
|
T26 |
2 |
|
T77 |
2 |
|
T78 |
1 |
| others[2] |
110 |
1 |
|
T26 |
4 |
|
T54 |
2 |
|
T77 |
6 |
| others[3] |
172 |
1 |
|
T26 |
9 |
|
T77 |
8 |
|
T78 |
9 |
| false |
50 |
1 |
|
T77 |
2 |
|
T372 |
1 |
|
T375 |
1 |
| true |
6186 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T26 |
6 |
|
T20 |
1 |
|
T35 |
1 |
| others[1] |
210 |
1 |
|
T15 |
1 |
|
T26 |
9 |
|
T77 |
7 |
| others[2] |
247 |
1 |
|
T26 |
12 |
|
T77 |
16 |
|
T78 |
9 |
| others[3] |
388 |
1 |
|
T17 |
1 |
|
T26 |
14 |
|
T77 |
20 |
| false |
118 |
1 |
|
T26 |
3 |
|
T77 |
4 |
|
T7 |
1 |
| true |
5535 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1035 |
1 |
|
T2 |
1 |
|
T6 |
5 |
|
T26 |
17 |
| others[1] |
1063 |
1 |
|
T6 |
1 |
|
T26 |
15 |
|
T54 |
1 |
| others[2] |
1090 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T18 |
1 |
| others[3] |
1650 |
1 |
|
T5 |
1 |
|
T15 |
1 |
|
T6 |
3 |
| false |
522 |
1 |
|
T6 |
2 |
|
T26 |
7 |
|
T39 |
5 |
| true |
1366 |
1 |
|
T10 |
1 |
|
T17 |
1 |
|
T39 |
32 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
211 |
1 |
|
T26 |
8 |
|
T54 |
1 |
|
T33 |
1 |
| others[1] |
253 |
1 |
|
T17 |
1 |
|
T26 |
7 |
|
T77 |
8 |
| others[2] |
236 |
1 |
|
T26 |
7 |
|
T77 |
11 |
|
T78 |
10 |
| others[3] |
352 |
1 |
|
T26 |
16 |
|
T77 |
20 |
|
T78 |
22 |
| false |
101 |
1 |
|
T26 |
2 |
|
T77 |
4 |
|
T78 |
5 |
| true |
5573 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
214 |
1 |
|
T15 |
1 |
|
T16 |
1 |
|
T26 |
5 |
| others[1] |
226 |
1 |
|
T26 |
9 |
|
T77 |
12 |
|
T7 |
1 |
| others[2] |
209 |
1 |
|
T26 |
15 |
|
T77 |
16 |
|
T23 |
1 |
| others[3] |
324 |
1 |
|
T17 |
1 |
|
T26 |
18 |
|
T77 |
14 |
| false |
115 |
1 |
|
T26 |
3 |
|
T22 |
1 |
|
T77 |
5 |
| true |
5638 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1190 |
1 |
|
T6 |
2 |
|
T26 |
23 |
|
T39 |
8 |
| others[1] |
1219 |
1 |
|
T6 |
2 |
|
T26 |
18 |
|
T54 |
1 |
| others[2] |
1240 |
1 |
|
T6 |
4 |
|
T26 |
27 |
|
T39 |
12 |
| others[3] |
2093 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T6 |
3 |
| false |
615 |
1 |
|
T5 |
1 |
|
T6 |
2 |
|
T26 |
7 |
| true |
369 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
3 |
1 |
|
T2 |
1 |
|
T228 |
1 |
|
T376 |
1 |
| others[1] |
7 |
1 |
|
T89 |
1 |
|
T143 |
1 |
|
T377 |
1 |
| others[2] |
11 |
1 |
|
T152 |
1 |
|
T378 |
1 |
|
T147 |
1 |
| others[3] |
17 |
1 |
|
T74 |
1 |
|
T142 |
1 |
|
T85 |
1 |
| false |
7 |
1 |
|
T75 |
1 |
|
T379 |
1 |
|
T380 |
1 |
| true |
54 |
1 |
|
T80 |
1 |
|
T85 |
1 |
|
T83 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
4 |
1 |
|
T381 |
1 |
|
T382 |
1 |
|
T383 |
1 |
| others[1] |
3 |
1 |
|
T384 |
1 |
|
T385 |
1 |
|
T386 |
1 |
| others[2] |
2 |
1 |
|
T27 |
1 |
|
T387 |
1 |
|
- |
- |
| others[3] |
4 |
1 |
|
T369 |
1 |
|
T388 |
1 |
|
T389 |
1 |
| false |
8 |
1 |
|
T25 |
1 |
|
T390 |
1 |
|
T391 |
1 |
| true |
26 |
1 |
|
T164 |
1 |
|
T370 |
1 |
|
T392 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
3 |
1 |
|
T393 |
1 |
|
T394 |
1 |
|
T395 |
1 |
| others[1] |
4 |
1 |
|
T392 |
1 |
|
T396 |
1 |
|
T390 |
1 |
| others[2] |
3 |
1 |
|
T25 |
1 |
|
T391 |
1 |
|
T397 |
1 |
| others[3] |
5 |
1 |
|
T398 |
1 |
|
T399 |
1 |
|
T382 |
1 |
| false |
8 |
1 |
|
T164 |
1 |
|
T400 |
1 |
|
T401 |
1 |
| true |
24 |
1 |
|
T27 |
1 |
|
T370 |
1 |
|
T369 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |