Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10533 |
1 |
|
T1 |
239 |
|
T11 |
2 |
|
T6 |
5 |
| others[1] |
785 |
1 |
|
T6 |
2 |
|
T26 |
31 |
|
T99 |
1 |
| others[2] |
758 |
1 |
|
T16 |
1 |
|
T6 |
1 |
|
T26 |
19 |
| others[3] |
1285 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
4 |
| false |
440 |
1 |
|
T6 |
1 |
|
T26 |
11 |
|
T158 |
3 |
| true |
462 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2470 |
1 |
|
T1 |
40 |
|
T5 |
1 |
|
T11 |
1 |
| others[1] |
2369 |
1 |
|
T1 |
49 |
|
T4 |
1 |
|
T15 |
1 |
| others[2] |
2466 |
1 |
|
T1 |
36 |
|
T6 |
4 |
|
T40 |
20 |
| others[3] |
4100 |
1 |
|
T1 |
85 |
|
T6 |
3 |
|
T40 |
38 |
| false |
1297 |
1 |
|
T1 |
29 |
|
T11 |
1 |
|
T6 |
1 |
| true |
1561 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10020 |
1 |
|
T1 |
239 |
|
T11 |
2 |
|
T40 |
114 |
| others[1] |
284 |
1 |
|
T26 |
11 |
|
T77 |
6 |
|
T23 |
1 |
| others[2] |
281 |
1 |
|
T5 |
1 |
|
T26 |
7 |
|
T35 |
1 |
| others[3] |
478 |
1 |
|
T4 |
1 |
|
T15 |
1 |
|
T17 |
1 |
| false |
125 |
1 |
|
T18 |
1 |
|
T26 |
3 |
|
T77 |
5 |
| true |
3075 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10233 |
1 |
|
T1 |
239 |
|
T10 |
1 |
|
T11 |
2 |
| others[1] |
445 |
1 |
|
T6 |
3 |
|
T26 |
2 |
|
T159 |
4 |
| others[2] |
454 |
1 |
|
T2 |
1 |
|
T6 |
1 |
|
T26 |
13 |
| others[3] |
753 |
1 |
|
T5 |
1 |
|
T15 |
1 |
|
T6 |
3 |
| false |
261 |
1 |
|
T17 |
1 |
|
T6 |
1 |
|
T26 |
7 |
| true |
2117 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10017 |
1 |
|
T1 |
239 |
|
T15 |
1 |
|
T11 |
2 |
| others[1] |
245 |
1 |
|
T5 |
1 |
|
T26 |
9 |
|
T22 |
1 |
| others[2] |
249 |
1 |
|
T16 |
1 |
|
T26 |
12 |
|
T77 |
4 |
| others[3] |
402 |
1 |
|
T26 |
14 |
|
T19 |
1 |
|
T35 |
1 |
| false |
127 |
1 |
|
T26 |
8 |
|
T33 |
1 |
|
T77 |
6 |
| true |
3223 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10002 |
1 |
|
T1 |
239 |
|
T11 |
2 |
|
T40 |
114 |
| others[1] |
276 |
1 |
|
T5 |
1 |
|
T17 |
1 |
|
T26 |
14 |
| others[2] |
252 |
1 |
|
T16 |
1 |
|
T26 |
13 |
|
T77 |
10 |
| others[3] |
433 |
1 |
|
T26 |
16 |
|
T35 |
1 |
|
T77 |
11 |
| false |
128 |
1 |
|
T26 |
4 |
|
T54 |
1 |
|
T99 |
1 |
| true |
3172 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10556 |
1 |
|
T1 |
239 |
|
T11 |
2 |
|
T6 |
2 |
| others[1] |
774 |
1 |
|
T6 |
3 |
|
T26 |
22 |
|
T19 |
1 |
| others[2] |
794 |
1 |
|
T6 |
2 |
|
T26 |
17 |
|
T158 |
1 |
| others[3] |
1320 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T16 |
1 |
| false |
389 |
1 |
|
T26 |
7 |
|
T158 |
2 |
|
T159 |
1 |
| true |
430 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10576 |
1 |
|
T1 |
239 |
|
T11 |
2 |
|
T6 |
4 |
| others[1] |
799 |
1 |
|
T6 |
5 |
|
T26 |
26 |
|
T19 |
1 |
| others[2] |
730 |
1 |
|
T26 |
13 |
|
T158 |
1 |
|
T159 |
2 |
| others[3] |
1267 |
1 |
|
T6 |
3 |
|
T26 |
28 |
|
T99 |
1 |
| false |
432 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T16 |
1 |
| true |
431 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2429 |
1 |
|
T1 |
57 |
|
T5 |
1 |
|
T6 |
3 |
| others[1] |
2492 |
1 |
|
T1 |
47 |
|
T6 |
3 |
|
T40 |
25 |
| others[2] |
2404 |
1 |
|
T1 |
45 |
|
T4 |
1 |
|
T6 |
2 |
| others[3] |
4178 |
1 |
|
T1 |
77 |
|
T15 |
1 |
|
T11 |
2 |
| false |
1257 |
1 |
|
T1 |
13 |
|
T6 |
2 |
|
T40 |
14 |
| true |
1475 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9980 |
1 |
|
T1 |
239 |
|
T11 |
2 |
|
T40 |
114 |
| others[1] |
272 |
1 |
|
T17 |
1 |
|
T26 |
10 |
|
T22 |
1 |
| others[2] |
275 |
1 |
|
T26 |
8 |
|
T33 |
1 |
|
T77 |
9 |
| others[3] |
435 |
1 |
|
T26 |
9 |
|
T99 |
1 |
|
T77 |
15 |
| false |
155 |
1 |
|
T26 |
6 |
|
T77 |
5 |
|
T23 |
1 |
| true |
3118 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10200 |
1 |
|
T1 |
239 |
|
T4 |
1 |
|
T17 |
1 |
| others[1] |
416 |
1 |
|
T6 |
1 |
|
T26 |
7 |
|
T77 |
10 |
| others[2] |
424 |
1 |
|
T6 |
1 |
|
T26 |
13 |
|
T19 |
1 |
| others[3] |
754 |
1 |
|
T5 |
1 |
|
T18 |
1 |
|
T6 |
2 |
| false |
245 |
1 |
|
T10 |
1 |
|
T6 |
2 |
|
T26 |
5 |
| true |
2196 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10017 |
1 |
|
T1 |
239 |
|
T11 |
2 |
|
T40 |
114 |
| others[1] |
250 |
1 |
|
T5 |
1 |
|
T26 |
11 |
|
T77 |
6 |
| others[2] |
239 |
1 |
|
T16 |
1 |
|
T26 |
8 |
|
T77 |
6 |
| others[3] |
414 |
1 |
|
T15 |
1 |
|
T17 |
1 |
|
T18 |
1 |
| false |
138 |
1 |
|
T26 |
6 |
|
T77 |
7 |
|
T69 |
1 |
| true |
3177 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9976 |
1 |
|
T1 |
239 |
|
T11 |
2 |
|
T40 |
114 |
| others[1] |
257 |
1 |
|
T5 |
1 |
|
T17 |
1 |
|
T26 |
14 |
| others[2] |
252 |
1 |
|
T77 |
14 |
|
T7 |
1 |
|
T78 |
11 |
| others[3] |
397 |
1 |
|
T26 |
23 |
|
T19 |
1 |
|
T35 |
1 |
| false |
125 |
1 |
|
T26 |
6 |
|
T77 |
1 |
|
T70 |
1 |
| true |
3228 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10562 |
1 |
|
T1 |
239 |
|
T11 |
2 |
|
T6 |
3 |
| others[1] |
774 |
1 |
|
T5 |
1 |
|
T16 |
1 |
|
T6 |
3 |
| others[2] |
762 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T6 |
1 |
| others[3] |
1302 |
1 |
|
T6 |
3 |
|
T26 |
37 |
|
T158 |
1 |
| false |
404 |
1 |
|
T6 |
3 |
|
T26 |
11 |
|
T34 |
1 |
| true |
431 |
1 |
|
T10 |
1 |
|
T15 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10518 |
1 |
|
T1 |
239 |
|
T11 |
2 |
|
T6 |
3 |
| others[1] |
717 |
1 |
|
T6 |
2 |
|
T26 |
23 |
|
T56 |
1 |
| others[2] |
758 |
1 |
|
T5 |
1 |
|
T6 |
2 |
|
T26 |
15 |
| others[3] |
1410 |
1 |
|
T4 |
1 |
|
T6 |
5 |
|
T26 |
39 |
| false |
395 |
1 |
|
T16 |
1 |
|
T6 |
1 |
|
T26 |
7 |
| true |
437 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2437 |
1 |
|
T1 |
46 |
|
T11 |
1 |
|
T6 |
1 |
| others[1] |
2392 |
1 |
|
T1 |
55 |
|
T6 |
3 |
|
T40 |
24 |
| others[2] |
2477 |
1 |
|
T1 |
46 |
|
T5 |
1 |
|
T16 |
1 |
| others[3] |
4148 |
1 |
|
T1 |
68 |
|
T4 |
1 |
|
T11 |
1 |
| false |
1287 |
1 |
|
T1 |
24 |
|
T6 |
1 |
|
T40 |
10 |
| true |
1494 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10052 |
1 |
|
T1 |
239 |
|
T11 |
2 |
|
T40 |
114 |
| others[1] |
293 |
1 |
|
T26 |
8 |
|
T22 |
1 |
|
T77 |
12 |
| others[2] |
256 |
1 |
|
T17 |
1 |
|
T26 |
10 |
|
T77 |
13 |
| others[3] |
410 |
1 |
|
T16 |
1 |
|
T26 |
18 |
|
T35 |
1 |
| false |
134 |
1 |
|
T26 |
4 |
|
T77 |
4 |
|
T78 |
6 |
| true |
3090 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10238 |
1 |
|
T1 |
239 |
|
T15 |
1 |
|
T11 |
2 |
| others[1] |
454 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T26 |
6 |
| others[2] |
446 |
1 |
|
T2 |
1 |
|
T26 |
14 |
|
T54 |
1 |
| others[3] |
761 |
1 |
|
T10 |
1 |
|
T5 |
1 |
|
T6 |
4 |
| false |
249 |
1 |
|
T18 |
1 |
|
T26 |
8 |
|
T77 |
6 |
| true |
2087 |
1 |
|
T16 |
1 |
|
T17 |
1 |
|
T6 |
8 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10019 |
1 |
|
T1 |
239 |
|
T11 |
2 |
|
T18 |
1 |
| others[1] |
247 |
1 |
|
T17 |
1 |
|
T26 |
13 |
|
T77 |
4 |
| others[2] |
264 |
1 |
|
T26 |
10 |
|
T19 |
1 |
|
T77 |
11 |
| others[3] |
407 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T26 |
17 |
| false |
124 |
1 |
|
T26 |
3 |
|
T33 |
1 |
|
T77 |
4 |
| true |
3174 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10018 |
1 |
|
T1 |
239 |
|
T11 |
2 |
|
T40 |
114 |
| others[1] |
276 |
1 |
|
T5 |
1 |
|
T26 |
9 |
|
T77 |
9 |
| others[2] |
251 |
1 |
|
T26 |
11 |
|
T54 |
1 |
|
T33 |
1 |
| others[3] |
384 |
1 |
|
T17 |
1 |
|
T26 |
19 |
|
T22 |
1 |
| false |
137 |
1 |
|
T26 |
8 |
|
T77 |
4 |
|
T202 |
1 |
| true |
3169 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10570 |
1 |
|
T1 |
239 |
|
T11 |
2 |
|
T6 |
4 |
| others[1] |
781 |
1 |
|
T26 |
19 |
|
T19 |
1 |
|
T99 |
1 |
| others[2] |
763 |
1 |
|
T6 |
1 |
|
T26 |
18 |
|
T158 |
3 |
| others[3] |
1338 |
1 |
|
T5 |
1 |
|
T16 |
1 |
|
T18 |
1 |
| false |
368 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T26 |
8 |
| true |
415 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10554 |
1 |
|
T1 |
239 |
|
T11 |
2 |
|
T6 |
2 |
| others[1] |
766 |
1 |
|
T6 |
1 |
|
T26 |
20 |
|
T99 |
1 |
| others[2] |
767 |
1 |
|
T6 |
1 |
|
T26 |
15 |
|
T158 |
2 |
| others[3] |
1323 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T5 |
1 |
| false |
396 |
1 |
|
T6 |
3 |
|
T26 |
10 |
|
T158 |
2 |
| true |
429 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2472 |
1 |
|
T1 |
49 |
|
T11 |
1 |
|
T6 |
2 |
| others[1] |
2477 |
1 |
|
T1 |
36 |
|
T5 |
1 |
|
T11 |
1 |
| others[2] |
2545 |
1 |
|
T1 |
40 |
|
T4 |
1 |
|
T6 |
3 |
| others[3] |
4055 |
1 |
|
T1 |
91 |
|
T15 |
1 |
|
T6 |
4 |
| false |
1230 |
1 |
|
T1 |
23 |
|
T6 |
1 |
|
T40 |
11 |
| true |
1456 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10005 |
1 |
|
T1 |
239 |
|
T11 |
2 |
|
T40 |
114 |
| others[1] |
275 |
1 |
|
T26 |
8 |
|
T99 |
1 |
|
T77 |
9 |
| others[2] |
268 |
1 |
|
T26 |
10 |
|
T22 |
1 |
|
T77 |
3 |
| others[3] |
425 |
1 |
|
T15 |
1 |
|
T26 |
18 |
|
T19 |
1 |
| false |
128 |
1 |
|
T5 |
1 |
|
T26 |
4 |
|
T20 |
1 |
| true |
3134 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10226 |
1 |
|
T1 |
239 |
|
T11 |
2 |
|
T6 |
2 |
| others[1] |
470 |
1 |
|
T5 |
1 |
|
T26 |
9 |
|
T54 |
1 |
| others[2] |
429 |
1 |
|
T4 |
1 |
|
T15 |
1 |
|
T6 |
2 |
| others[3] |
719 |
1 |
|
T17 |
1 |
|
T6 |
2 |
|
T26 |
17 |
| false |
210 |
1 |
|
T10 |
1 |
|
T26 |
6 |
|
T159 |
1 |
| true |
2181 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10010 |
1 |
|
T1 |
239 |
|
T17 |
1 |
|
T11 |
2 |
| others[1] |
269 |
1 |
|
T5 |
1 |
|
T26 |
14 |
|
T35 |
1 |
| others[2] |
261 |
1 |
|
T26 |
8 |
|
T77 |
8 |
|
T32 |
1 |
| others[3] |
406 |
1 |
|
T18 |
1 |
|
T26 |
21 |
|
T54 |
1 |
| false |
131 |
1 |
|
T26 |
3 |
|
T99 |
1 |
|
T77 |
3 |
| true |
3158 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9994 |
1 |
|
T1 |
239 |
|
T11 |
2 |
|
T40 |
114 |
| others[1] |
257 |
1 |
|
T26 |
14 |
|
T33 |
1 |
|
T77 |
13 |
| others[2] |
257 |
1 |
|
T26 |
10 |
|
T77 |
16 |
|
T165 |
1 |
| others[3] |
409 |
1 |
|
T5 |
1 |
|
T26 |
21 |
|
T19 |
1 |
| false |
131 |
1 |
|
T26 |
6 |
|
T77 |
4 |
|
T32 |
1 |
| true |
3187 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10502 |
1 |
|
T1 |
239 |
|
T11 |
2 |
|
T6 |
1 |
| others[1] |
825 |
1 |
|
T10 |
1 |
|
T5 |
1 |
|
T6 |
2 |
| others[2] |
805 |
1 |
|
T6 |
5 |
|
T26 |
17 |
|
T54 |
1 |
| others[3] |
1270 |
1 |
|
T4 |
1 |
|
T6 |
4 |
|
T26 |
33 |
| false |
399 |
1 |
|
T16 |
1 |
|
T6 |
1 |
|
T26 |
9 |
| true |
434 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10477 |
1 |
|
T1 |
239 |
|
T11 |
2 |
|
T6 |
2 |
| others[1] |
803 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
4 |
| others[2] |
773 |
1 |
|
T16 |
1 |
|
T6 |
2 |
|
T26 |
19 |
| others[3] |
1338 |
1 |
|
T6 |
5 |
|
T26 |
34 |
|
T19 |
1 |
| false |
400 |
1 |
|
T26 |
9 |
|
T158 |
1 |
|
T77 |
8 |
| true |
444 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2393 |
1 |
|
T1 |
37 |
|
T4 |
1 |
|
T6 |
3 |
| others[1] |
2432 |
1 |
|
T1 |
46 |
|
T11 |
1 |
|
T6 |
2 |
| others[2] |
2480 |
1 |
|
T1 |
51 |
|
T6 |
2 |
|
T40 |
19 |
| others[3] |
4165 |
1 |
|
T1 |
85 |
|
T5 |
1 |
|
T11 |
1 |
| false |
1254 |
1 |
|
T1 |
20 |
|
T40 |
10 |
|
T26 |
3 |
| true |
1511 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10045 |
1 |
|
T1 |
239 |
|
T11 |
2 |
|
T40 |
114 |
| others[1] |
247 |
1 |
|
T17 |
1 |
|
T26 |
9 |
|
T35 |
1 |
| others[2] |
261 |
1 |
|
T18 |
1 |
|
T26 |
14 |
|
T54 |
1 |
| others[3] |
408 |
1 |
|
T26 |
13 |
|
T54 |
1 |
|
T22 |
1 |
| false |
134 |
1 |
|
T26 |
3 |
|
T77 |
6 |
|
T166 |
1 |
| true |
3140 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |