Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10231 |
1 |
|
T1 |
239 |
|
T5 |
1 |
|
T11 |
2 |
| others[1] |
422 |
1 |
|
T6 |
2 |
|
T26 |
14 |
|
T100 |
1 |
| others[2] |
453 |
1 |
|
T10 |
1 |
|
T6 |
1 |
|
T26 |
13 |
| others[3] |
770 |
1 |
|
T6 |
1 |
|
T26 |
12 |
|
T99 |
1 |
| false |
228 |
1 |
|
T15 |
1 |
|
T26 |
4 |
|
T54 |
1 |
| true |
2131 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10029 |
1 |
|
T1 |
239 |
|
T11 |
2 |
|
T40 |
114 |
| others[1] |
231 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T26 |
7 |
| others[2] |
261 |
1 |
|
T26 |
9 |
|
T77 |
9 |
|
T165 |
1 |
| others[3] |
442 |
1 |
|
T16 |
1 |
|
T26 |
20 |
|
T77 |
22 |
| false |
118 |
1 |
|
T15 |
1 |
|
T26 |
5 |
|
T19 |
1 |
| true |
3154 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10005 |
1 |
|
T1 |
239 |
|
T4 |
1 |
|
T11 |
2 |
| others[1] |
253 |
1 |
|
T5 |
1 |
|
T26 |
12 |
|
T33 |
1 |
| others[2] |
214 |
1 |
|
T26 |
7 |
|
T77 |
6 |
|
T63 |
1 |
| others[3] |
441 |
1 |
|
T26 |
19 |
|
T99 |
1 |
|
T77 |
11 |
| false |
110 |
1 |
|
T16 |
1 |
|
T26 |
3 |
|
T77 |
5 |
| true |
3212 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10490 |
1 |
|
T1 |
239 |
|
T16 |
1 |
|
T11 |
2 |
| others[1] |
791 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T6 |
3 |
| others[2] |
774 |
1 |
|
T5 |
1 |
|
T6 |
4 |
|
T26 |
25 |
| others[3] |
1304 |
1 |
|
T6 |
5 |
|
T26 |
26 |
|
T56 |
1 |
| false |
429 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T26 |
11 |
| true |
447 |
1 |
|
T15 |
1 |
|
T17 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10584 |
1 |
|
T1 |
239 |
|
T11 |
2 |
|
T6 |
2 |
| others[1] |
754 |
1 |
|
T5 |
1 |
|
T6 |
3 |
|
T26 |
15 |
| others[2] |
753 |
1 |
|
T6 |
4 |
|
T26 |
25 |
|
T54 |
1 |
| others[3] |
1307 |
1 |
|
T4 |
1 |
|
T6 |
4 |
|
T26 |
31 |
| false |
394 |
1 |
|
T16 |
1 |
|
T26 |
8 |
|
T158 |
2 |
| true |
443 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2458 |
1 |
|
T1 |
44 |
|
T11 |
1 |
|
T6 |
3 |
| others[1] |
2447 |
1 |
|
T1 |
40 |
|
T4 |
1 |
|
T6 |
2 |
| others[2] |
2499 |
1 |
|
T1 |
55 |
|
T15 |
1 |
|
T6 |
6 |
| others[3] |
4058 |
1 |
|
T1 |
71 |
|
T11 |
1 |
|
T6 |
2 |
| false |
1298 |
1 |
|
T1 |
29 |
|
T5 |
1 |
|
T40 |
17 |
| true |
1475 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10034 |
1 |
|
T1 |
239 |
|
T11 |
2 |
|
T40 |
114 |
| others[1] |
275 |
1 |
|
T26 |
6 |
|
T77 |
8 |
|
T23 |
1 |
| others[2] |
269 |
1 |
|
T26 |
13 |
|
T99 |
1 |
|
T33 |
1 |
| others[3] |
454 |
1 |
|
T17 |
1 |
|
T18 |
1 |
|
T26 |
16 |
| false |
125 |
1 |
|
T26 |
3 |
|
T77 |
6 |
|
T78 |
6 |
| true |
3078 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10216 |
1 |
|
T1 |
239 |
|
T4 |
1 |
|
T15 |
1 |
| others[1] |
431 |
1 |
|
T18 |
1 |
|
T6 |
1 |
|
T26 |
10 |
| others[2] |
428 |
1 |
|
T26 |
7 |
|
T54 |
1 |
|
T19 |
1 |
| others[3] |
744 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T6 |
2 |
| false |
264 |
1 |
|
T10 |
1 |
|
T6 |
1 |
|
T26 |
3 |
| true |
2152 |
1 |
|
T5 |
1 |
|
T17 |
1 |
|
T6 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9994 |
1 |
|
T1 |
239 |
|
T5 |
1 |
|
T11 |
2 |
| others[1] |
264 |
1 |
|
T4 |
1 |
|
T18 |
1 |
|
T26 |
7 |
| others[2] |
251 |
1 |
|
T26 |
5 |
|
T99 |
1 |
|
T77 |
12 |
| others[3] |
446 |
1 |
|
T16 |
1 |
|
T26 |
21 |
|
T54 |
1 |
| false |
121 |
1 |
|
T26 |
4 |
|
T77 |
4 |
|
T165 |
1 |
| true |
3159 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10000 |
1 |
|
T1 |
239 |
|
T11 |
2 |
|
T40 |
114 |
| others[1] |
258 |
1 |
|
T26 |
7 |
|
T77 |
8 |
|
T63 |
1 |
| others[2] |
242 |
1 |
|
T17 |
1 |
|
T26 |
10 |
|
T77 |
9 |
| others[3] |
404 |
1 |
|
T16 |
1 |
|
T26 |
10 |
|
T19 |
1 |
| false |
128 |
1 |
|
T5 |
1 |
|
T26 |
5 |
|
T33 |
1 |
| true |
3203 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10606 |
1 |
|
T1 |
239 |
|
T4 |
1 |
|
T11 |
2 |
| others[1] |
774 |
1 |
|
T5 |
1 |
|
T6 |
3 |
|
T26 |
16 |
| others[2] |
762 |
1 |
|
T16 |
1 |
|
T6 |
2 |
|
T26 |
20 |
| others[3] |
1250 |
1 |
|
T6 |
4 |
|
T26 |
32 |
|
T54 |
1 |
| false |
413 |
1 |
|
T6 |
2 |
|
T26 |
12 |
|
T99 |
1 |
| true |
430 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10546 |
1 |
|
T1 |
239 |
|
T16 |
1 |
|
T11 |
2 |
| others[1] |
811 |
1 |
|
T5 |
1 |
|
T6 |
1 |
|
T26 |
21 |
| others[2] |
783 |
1 |
|
T26 |
17 |
|
T19 |
1 |
|
T99 |
1 |
| others[3] |
1265 |
1 |
|
T6 |
5 |
|
T26 |
34 |
|
T100 |
1 |
| false |
384 |
1 |
|
T4 |
1 |
|
T26 |
12 |
|
T158 |
1 |
| true |
446 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2447 |
1 |
|
T1 |
37 |
|
T6 |
2 |
|
T40 |
19 |
| others[1] |
2458 |
1 |
|
T1 |
39 |
|
T4 |
1 |
|
T11 |
1 |
| others[2] |
2400 |
1 |
|
T1 |
53 |
|
T11 |
1 |
|
T6 |
3 |
| others[3] |
4121 |
1 |
|
T1 |
80 |
|
T5 |
1 |
|
T15 |
1 |
| false |
1313 |
1 |
|
T1 |
30 |
|
T6 |
1 |
|
T40 |
11 |
| true |
1496 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9998 |
1 |
|
T1 |
239 |
|
T11 |
2 |
|
T40 |
114 |
| others[1] |
264 |
1 |
|
T26 |
10 |
|
T77 |
7 |
|
T202 |
1 |
| others[2] |
269 |
1 |
|
T26 |
10 |
|
T33 |
1 |
|
T22 |
1 |
| others[3] |
435 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T18 |
1 |
| false |
151 |
1 |
|
T17 |
1 |
|
T26 |
7 |
|
T20 |
1 |
| true |
3118 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10220 |
1 |
|
T1 |
239 |
|
T17 |
1 |
|
T11 |
2 |
| others[1] |
438 |
1 |
|
T4 |
1 |
|
T6 |
2 |
|
T26 |
8 |
| others[2] |
416 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T26 |
9 |
| others[3] |
743 |
1 |
|
T5 |
1 |
|
T6 |
2 |
|
T26 |
26 |
| false |
247 |
1 |
|
T18 |
1 |
|
T6 |
3 |
|
T26 |
7 |
| true |
2171 |
1 |
|
T15 |
1 |
|
T16 |
1 |
|
T6 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9995 |
1 |
|
T1 |
239 |
|
T16 |
1 |
|
T11 |
2 |
| others[1] |
260 |
1 |
|
T26 |
10 |
|
T54 |
1 |
|
T35 |
1 |
| others[2] |
286 |
1 |
|
T26 |
12 |
|
T77 |
8 |
|
T165 |
1 |
| others[3] |
425 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T26 |
15 |
| false |
115 |
1 |
|
T26 |
6 |
|
T22 |
1 |
|
T77 |
2 |
| true |
3154 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9984 |
1 |
|
T1 |
239 |
|
T17 |
1 |
|
T11 |
2 |
| others[1] |
218 |
1 |
|
T26 |
9 |
|
T54 |
1 |
|
T77 |
10 |
| others[2] |
293 |
1 |
|
T26 |
13 |
|
T77 |
8 |
|
T32 |
1 |
| others[3] |
440 |
1 |
|
T15 |
1 |
|
T16 |
1 |
|
T26 |
11 |
| false |
123 |
1 |
|
T5 |
1 |
|
T26 |
4 |
|
T77 |
4 |
| true |
3177 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10525 |
1 |
|
T1 |
239 |
|
T11 |
2 |
|
T6 |
3 |
| others[1] |
791 |
1 |
|
T6 |
2 |
|
T26 |
17 |
|
T158 |
1 |
| others[2] |
755 |
1 |
|
T6 |
2 |
|
T26 |
28 |
|
T158 |
1 |
| others[3] |
1322 |
1 |
|
T10 |
1 |
|
T4 |
1 |
|
T5 |
1 |
| false |
423 |
1 |
|
T16 |
1 |
|
T6 |
4 |
|
T26 |
15 |
| true |
419 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10527 |
1 |
|
T1 |
239 |
|
T10 |
1 |
|
T5 |
1 |
| others[1] |
770 |
1 |
|
T16 |
1 |
|
T6 |
3 |
|
T26 |
23 |
| others[2] |
811 |
1 |
|
T4 |
1 |
|
T6 |
2 |
|
T26 |
14 |
| others[3] |
1276 |
1 |
|
T6 |
3 |
|
T26 |
34 |
|
T19 |
1 |
| false |
400 |
1 |
|
T6 |
2 |
|
T26 |
9 |
|
T158 |
1 |
| true |
451 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2549 |
1 |
|
T1 |
40 |
|
T6 |
4 |
|
T40 |
20 |
| others[1] |
2429 |
1 |
|
T1 |
48 |
|
T4 |
1 |
|
T15 |
1 |
| others[2] |
2405 |
1 |
|
T1 |
47 |
|
T6 |
2 |
|
T40 |
27 |
| others[3] |
4045 |
1 |
|
T1 |
79 |
|
T5 |
1 |
|
T11 |
1 |
| false |
1317 |
1 |
|
T1 |
25 |
|
T6 |
2 |
|
T40 |
11 |
| true |
1490 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9993 |
1 |
|
T1 |
239 |
|
T15 |
1 |
|
T11 |
2 |
| others[1] |
265 |
1 |
|
T16 |
1 |
|
T17 |
1 |
|
T26 |
10 |
| others[2] |
280 |
1 |
|
T26 |
10 |
|
T77 |
8 |
|
T36 |
1 |
| others[3] |
418 |
1 |
|
T26 |
8 |
|
T20 |
1 |
|
T77 |
14 |
| false |
143 |
1 |
|
T26 |
5 |
|
T77 |
4 |
|
T63 |
1 |
| true |
3136 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10199 |
1 |
|
T1 |
239 |
|
T15 |
1 |
|
T17 |
1 |
| others[1] |
445 |
1 |
|
T6 |
2 |
|
T26 |
8 |
|
T158 |
1 |
| others[2] |
425 |
1 |
|
T4 |
1 |
|
T6 |
3 |
|
T26 |
12 |
| others[3] |
720 |
1 |
|
T10 |
1 |
|
T18 |
1 |
|
T26 |
13 |
| false |
239 |
1 |
|
T5 |
1 |
|
T26 |
8 |
|
T158 |
1 |
| true |
2207 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T6 |
8 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10030 |
1 |
|
T1 |
239 |
|
T4 |
1 |
|
T5 |
1 |
| others[1] |
254 |
1 |
|
T26 |
11 |
|
T99 |
1 |
|
T77 |
14 |
| others[2] |
265 |
1 |
|
T16 |
1 |
|
T26 |
9 |
|
T77 |
7 |
| others[3] |
392 |
1 |
|
T26 |
13 |
|
T54 |
1 |
|
T33 |
1 |
| false |
142 |
1 |
|
T26 |
3 |
|
T77 |
7 |
|
T78 |
2 |
| true |
3152 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10021 |
1 |
|
T1 |
239 |
|
T17 |
1 |
|
T11 |
2 |
| others[1] |
228 |
1 |
|
T5 |
1 |
|
T26 |
11 |
|
T54 |
1 |
| others[2] |
236 |
1 |
|
T26 |
9 |
|
T54 |
1 |
|
T77 |
12 |
| others[3] |
409 |
1 |
|
T16 |
1 |
|
T26 |
15 |
|
T33 |
1 |
| false |
138 |
1 |
|
T15 |
1 |
|
T26 |
7 |
|
T99 |
1 |
| true |
3203 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10573 |
1 |
|
T1 |
239 |
|
T5 |
1 |
|
T11 |
2 |
| others[1] |
755 |
1 |
|
T26 |
17 |
|
T158 |
3 |
|
T34 |
1 |
| others[2] |
774 |
1 |
|
T4 |
1 |
|
T6 |
3 |
|
T26 |
25 |
| others[3] |
1270 |
1 |
|
T6 |
4 |
|
T26 |
32 |
|
T19 |
1 |
| false |
438 |
1 |
|
T16 |
1 |
|
T26 |
6 |
|
T159 |
1 |
| true |
425 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |