Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	163590	1		T1	1448		T2	2		T4	320
auto[FlashEraseBank]	191930	1		T4	468		T5	1142		T15	19

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	172826	1		T1	726		T4	788		T5	791
auto[FlashOpProgram]	162595	1		T1	361		T5	1535		T15	34
auto[FlashOpErase]	16099	1		T1	361		T2	2		T16	30
auto[FlashOpInvalid]	4000	1		T217	200		T218	200		T219	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	172826	1		T1	726		T4	788		T5	791
op[FlashOpProgram]	162595	1		T1	361		T5	1535		T15	34
op[FlashOpErase]	16099	1		T1	361		T2	2		T16	30
read_erase_read	726	1		T16	6		T25	1		T26	5
read_prog_read	1176	1		T5	4		T16	11		T18	29

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	241673	1		T2	1		T4	788		T5	1935
auto[FlashPartInfo]	110918	1		T1	1448		T2	1		T5	371
auto[FlashPartInfo1]	708	1		T5	4		T19	1		T77	1
auto[FlashPartInfo2]	2221	1		T5	16		T18	2		T19	14

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	128710	1		T4	788		T5	780		T16	80
auto[FlashPartData]	auto[FlashOpProgram]	105361	1		T5	1155		T15	2		T16	86
auto[FlashPartData]	auto[FlashOpErase]	3686	1		T2	1		T16	30		T6	2
auto[FlashPartData]	auto[FlashOpInvalid]	3916	1		T217	200		T218	194		T219	200
auto[FlashPartInfo]	auto[FlashOpRead]	42408	1		T1	726		T16	1		T18	38
auto[FlashPartInfo]	auto[FlashOpProgram]	56054	1		T1	361		T5	371		T15	32
auto[FlashPartInfo]	auto[FlashOpErase]	12394	1		T1	361		T2	1		T25	12
auto[FlashPartInfo]	auto[FlashOpInvalid]	62	1		T218	4		T111	4		T403	12
auto[FlashPartInfo1]	auto[FlashOpRead]	530	1		T5	4		T19	1		T63	4
auto[FlashPartInfo1]	auto[FlashOpProgram]	167	1		T93	32		T68	32		T96	1
auto[FlashPartInfo1]	auto[FlashOpErase]	5	1		T77	1		T94	1		T111	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	6	1		T111	2		T403	2		T404	2
auto[FlashPartInfo2]	auto[FlashOpRead]	1178	1		T5	7		T18	2		T19	5
auto[FlashPartInfo2]	auto[FlashOpProgram]	1013	1		T5	9		T19	9		T35	1
auto[FlashPartInfo2]	auto[FlashOpErase]	14	1		T218	1		T107	1		T96	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	16	1		T218	2		T403	2		T405	2