Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
78.57	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	9	23	71.88

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	9	23	71.88	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31066	1		T1	700		T5	1		T16	20
auto[1]	3	1		T92	1		T334	1		T335	1
auto[2]	169	1		T336	9		T198	1		T337	22
auto[3]	236	1		T21	1		T36	1		T207	24

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7912	1		T1	175		T16	5		T25	1
evic_idx[1]	7868	1		T1	175		T16	5		T25	1
evic_idx[2]	7848	1		T1	175		T5	1		T16	5
evic_idx[3]	7846	1		T1	175		T16	5		T25	1

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	30399	1		T1	700		T25	4		T40	344
evic_op[2]	503	1		T5	1		T56	16		T77	4

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	9	23	71.88	9

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[0]]	[evic_op[1]]	[auto[1] - auto[2]]	--	--	2
[evic_idx[1]]	[evic_op[1]]	[auto[1] - auto[2]]	--	--	2
[evic_idx[1]]	[evic_op[2]]	[auto[1]]	0	1	1
[evic_idx[2] , evic_idx[3]]	[evic_op[1]]	[auto[1] - auto[2]]	--	--	4

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7556	1		T1	175		T25	1		T40	86
evic_idx[0]	evic_op[1]	auto[3]	80	1		T207	9		T338	39		T339	30
evic_idx[0]	evic_op[2]	auto[0]	71	1		T56	4		T77	1		T232	1
evic_idx[0]	evic_op[2]	auto[1]	1	1		T334	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[2]	43	1		T336	5		T198	1		T337	6
evic_idx[0]	evic_op[2]	auto[3]	18	1		T36	1		T90	1		T38	1
evic_idx[1]	evic_op[1]	auto[0]	7556	1		T1	175		T25	1		T40	86
evic_idx[1]	evic_op[1]	auto[3]	37	1		T207	6		T338	22		T339	9
evic_idx[1]	evic_op[2]	auto[0]	77	1		T56	4		T77	1		T69	1
evic_idx[1]	evic_op[2]	auto[2]	37	1		T336	2		T337	7		T340	9
evic_idx[1]	evic_op[2]	auto[3]	18	1		T197	1		T38	1		T198	1
evic_idx[2]	evic_op[1]	auto[0]	7555	1		T1	175		T25	1		T40	86
evic_idx[2]	evic_op[1]	auto[3]	30	1		T207	3		T338	15		T339	9
evic_idx[2]	evic_op[2]	auto[0]	78	1		T5	1		T56	4		T77	1
evic_idx[2]	evic_op[2]	auto[1]	1	1		T335	1		-	-		-	-
evic_idx[2]	evic_op[2]	auto[2]	29	1		T336	1		T337	4		T341	1
evic_idx[2]	evic_op[2]	auto[3]	12	1		T50	1		T37	1		T279	1
evic_idx[3]	evic_op[1]	auto[0]	7557	1		T1	175		T25	1		T40	86
evic_idx[3]	evic_op[1]	auto[3]	28	1		T207	6		T338	12		T339	7
evic_idx[3]	evic_op[2]	auto[0]	76	1		T56	4		T77	1		T232	1
evic_idx[3]	evic_op[2]	auto[1]	1	1		T92	1		-	-		-	-
evic_idx[3]	evic_op[2]	auto[2]	28	1		T336	1		T337	5		T340	8
evic_idx[3]	evic_op[2]	auto[3]	13	1		T21	1		T200	1		T224	1