Summary for Variable instr_type_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
3 | 
0 | 
3 | 
100.00 | 
User Defined Bins for instr_type_cp
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others | 
5620 | 
1 | 
 | 
T47 | 
82 | 
 | 
T44 | 
1 | 
 | 
T48 | 
116 | 
| instr_types[0] | 
6584 | 
1 | 
 | 
T47 | 
282 | 
 | 
T48 | 
200 | 
 | 
T49 | 
133 | 
| instr_types[1] | 
2669413 | 
1 | 
 | 
T4 | 
16420 | 
 | 
T5 | 
41474 | 
 | 
T18 | 
9 | 
Summary for Variable key_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for key_cp
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
2679901 | 
1 | 
 | 
T4 | 
16420 | 
 | 
T5 | 
41474 | 
 | 
T18 | 
9 | 
| auto[1] | 
1716 | 
1 | 
 | 
T47 | 
91 | 
 | 
T48 | 
194 | 
 | 
T49 | 
124 | 
Summary for Cross key_instr_cross
Samples crossed: key_cp instr_type_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
6 | 
0 | 
6 | 
100.00 | 
 | 
Automatically Generated Cross Bins for key_instr_cross
Bins
| key_cp | instr_type_cp | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
others | 
5207 | 
1 | 
 | 
T47 | 
67 | 
 | 
T44 | 
1 | 
 | 
T48 | 
80 | 
| auto[0] | 
instr_types[0] | 
5921 | 
1 | 
 | 
T47 | 
254 | 
 | 
T48 | 
126 | 
 | 
T49 | 
120 | 
| auto[0] | 
instr_types[1] | 
2668773 | 
1 | 
 | 
T4 | 
16420 | 
 | 
T5 | 
41474 | 
 | 
T18 | 
9 | 
| auto[1] | 
others | 
413 | 
1 | 
 | 
T47 | 
15 | 
 | 
T48 | 
36 | 
 | 
T49 | 
40 | 
| auto[1] | 
instr_types[0] | 
663 | 
1 | 
 | 
T47 | 
28 | 
 | 
T48 | 
74 | 
 | 
T49 | 
13 | 
| auto[1] | 
instr_types[1] | 
640 | 
1 | 
 | 
T47 | 
48 | 
 | 
T48 | 
84 | 
 | 
T49 | 
71 |