Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
77.78	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	4	14	77.78

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	1	14	93.33	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	1	14	93.33

User Defined Bins for rd_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
rd_lvl[1]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[2]	31245	1		T186	7561		T320	5548		T321	6330
rd_lvl[3]	12614	1		T186	498		T195	2809		T320	354
rd_lvl[4]	18828	1		T186	2		T195	1806		T322	1663
rd_lvl[5]	8938	1		T186	2		T323	1458		T324	1
rd_lvl[6]	6669	1		T32	1479		T64	420		T323	915
rd_lvl[7]	4421	1		T32	543		T64	887		T325	1148
rd_lvl[8]	3992	1		T64	715		T325	724		T326	1195
rd_lvl[9]	1538	1		T64	13		T327	539		T326	167
rd_lvl[10]	1731	1		T31	630		T186	1		T64	14
rd_lvl[11]	1226	1		T31	358		T328	291		T329	577
rd_lvl[12]	2241	1		T186	1		T28	243		T330	535
rd_lvl[13]	3590	1		T4	563		T28	788		T331	581
rd_lvl[14]	3469	1		T4	225		T331	497		T332	521
rd_lvl[15]	2834	1		T28	40		T332	357		T333	269