Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	160866	1		T1	1		T2	2		T3	1
all_pins[1]	160866	1		T1	1		T2	2		T3	1
all_pins[2]	160866	1		T1	1		T2	2		T3	1
all_pins[3]	160866	1		T1	1		T2	2		T3	1
all_pins[4]	160866	1		T1	1		T2	2		T3	1
all_pins[5]	160866	1		T1	1		T2	2		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	794400	1		T1	6		T2	12		T3	6
values[0x1]	170796	1		T4	1576		T22	970		T31	1976
transitions[0x0=>0x1]	157317	1		T4	1576		T22	970		T31	1976
transitions[0x1=>0x0]	157295	1		T4	1576		T22	970		T31	1976

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	160682	1		T1	1		T2	2		T3	1
all_pins[0]	values[0x1]	184	1		T269	4		T270	8		T342	5
all_pins[0]	transitions[0x0=>0x1]	85	1		T269	3		T270	6		T342	4
all_pins[0]	transitions[0x1=>0x0]	74	1		T342	1		T344	1		T343	3
all_pins[1]	values[0x0]	160693	1		T1	1		T2	2		T3	1
all_pins[1]	values[0x1]	173	1		T269	1		T270	2		T342	2
all_pins[1]	transitions[0x0=>0x1]	150	1		T269	1		T270	2		T342	2
all_pins[1]	transitions[0x1=>0x0]	1436	1		T29	428		T352	401		T353	588
all_pins[2]	values[0x0]	159407	1		T1	1		T2	2		T3	1
all_pins[2]	values[0x1]	1459	1		T29	428		T352	401		T353	588
all_pins[2]	transitions[0x0=>0x1]	32	1		T270	1		T343	2		T346	2
all_pins[2]	transitions[0x1=>0x0]	103659	1		T4	788		T31	988		T32	2022
all_pins[3]	values[0x0]	55780	1		T1	1		T2	2		T3	1
all_pins[3]	values[0x1]	105086	1		T4	788		T31	988		T32	2022
all_pins[3]	transitions[0x0=>0x1]	93201	1		T4	788		T31	988		T32	2022
all_pins[3]	transitions[0x1=>0x0]	51956	1		T4	788		T22	970		T31	988
all_pins[4]	values[0x0]	97025	1		T1	1		T2	2		T3	1
all_pins[4]	values[0x1]	63841	1		T4	788		T22	970		T31	988
all_pins[4]	transitions[0x0=>0x1]	63832	1		T4	788		T22	970		T31	988
all_pins[4]	transitions[0x1=>0x0]	44	1		T344	2		T346	2		T349	1
all_pins[5]	values[0x0]	160813	1		T1	1		T2	2		T3	1
all_pins[5]	values[0x1]	53	1		T270	1		T344	2		T346	2
all_pins[5]	transitions[0x0=>0x1]	17	1		T344	1		T354	1		T355	2
all_pins[5]	transitions[0x1=>0x0]	126	1		T269	3		T270	6		T342	4