Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	269	1		T269	4		T270	7		T342	7
all_values[1]	269	1		T269	4		T270	7		T342	7
all_values[2]	269	1		T269	4		T270	7		T342	7
all_values[3]	269	1		T269	4		T270	7		T342	7
all_values[4]	269	1		T269	4		T270	7		T342	7
all_values[5]	269	1		T269	4		T270	7		T342	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	913	1		T269	13		T270	28		T342	21
auto[1]	701	1		T269	11		T270	14		T342	21

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	543	1		T269	8		T270	15		T342	13
auto[1]	1071	1		T269	16		T270	27		T342	29

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	963	1		T269	15		T270	28		T342	24
auto[1]	651	1		T269	9		T270	14		T342	18

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	68	1		T269	1		T342	1		T343	2
all_values[0]	auto[0]	auto[1]	auto[1]	88	1		T269	2		T270	5		T342	2
all_values[0]	auto[1]	auto[0]	auto[1]	59	1		T342	3		T344	2		T343	1
all_values[0]	auto[1]	auto[1]	auto[1]	54	1		T269	1		T270	2		T342	1
all_values[1]	auto[0]	auto[0]	auto[1]	84	1		T269	2		T270	4		T342	3
all_values[1]	auto[0]	auto[1]	auto[1]	79	1		T342	1		T344	2		T343	1
all_values[1]	auto[1]	auto[0]	auto[1]	58	1		T269	1		T270	2		T342	1
all_values[1]	auto[1]	auto[1]	auto[1]	48	1		T269	1		T270	1		T342	2
all_values[2]	auto[0]	auto[0]	auto[0]	99	1		T269	2		T270	5		T342	3
all_values[2]	auto[0]	auto[1]	auto[0]	69	1		T269	1		T342	3		T344	1
all_values[2]	auto[1]	auto[0]	auto[1]	63	1		T269	1		T270	1		T343	1
all_values[2]	auto[1]	auto[1]	auto[1]	38	1		T270	1		T342	1		T344	1
all_values[3]	auto[0]	auto[0]	auto[0]	96	1		T269	2		T270	6		T342	2
all_values[3]	auto[0]	auto[1]	auto[0]	66	1		T342	2		T344	1		T343	5
all_values[3]	auto[1]	auto[0]	auto[1]	65	1		T269	2		T270	1		T345	1
all_values[3]	auto[1]	auto[1]	auto[1]	42	1		T342	3		T344	3		T343	1
all_values[4]	auto[0]	auto[0]	auto[0]	62	1		T343	1		T346	3		T347	3
all_values[4]	auto[0]	auto[0]	auto[1]	31	1		T342	1		T343	2		T348	1
all_values[4]	auto[0]	auto[1]	auto[0]	38	1		T269	1		T270	2		T344	3
all_values[4]	auto[0]	auto[1]	auto[1]	23	1		T269	1		T270	1		T342	1
all_values[4]	auto[1]	auto[0]	auto[1]	72	1		T270	3		T342	4		T343	2
all_values[4]	auto[1]	auto[1]	auto[1]	43	1		T269	2		T270	1		T342	1
all_values[5]	auto[0]	auto[0]	auto[0]	66	1		T270	2		T342	1		T344	1
all_values[5]	auto[0]	auto[0]	auto[1]	26	1		T269	1		T270	2		T342	2
all_values[5]	auto[0]	auto[1]	auto[0]	47	1		T269	2		T342	2		T343	2
all_values[5]	auto[0]	auto[1]	auto[1]	21	1		T270	1		T344	2		T346	1
all_values[5]	auto[1]	auto[0]	auto[1]	64	1		T269	1		T270	2		T344	1
all_values[5]	auto[1]	auto[1]	auto[1]	45	1		T342	2		T346	1		T349	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal