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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.47 95.76 94.10 98.85 92.52 98.14 98.01 97.90


Total test records in report: 1196
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T344 /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.1062606211 Mar 24 12:39:10 PM PDT 24 Mar 24 12:39:23 PM PDT 24 53401600 ps
T225 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1443947416 Mar 24 12:38:55 PM PDT 24 Mar 24 12:39:12 PM PDT 24 29244400 ps
T343 /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.2053217355 Mar 24 12:38:57 PM PDT 24 Mar 24 12:39:10 PM PDT 24 59055700 ps
T226 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.186164287 Mar 24 12:38:51 PM PDT 24 Mar 24 12:53:39 PM PDT 24 719349900 ps
T258 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.2600568054 Mar 24 12:39:02 PM PDT 24 Mar 24 12:39:17 PM PDT 24 27947700 ps
T345 /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.4237416233 Mar 24 12:38:57 PM PDT 24 Mar 24 12:39:10 PM PDT 24 16245300 ps
T346 /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.54168305 Mar 24 12:38:55 PM PDT 24 Mar 24 12:39:08 PM PDT 24 30868300 ps
T243 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1695636456 Mar 24 12:38:58 PM PDT 24 Mar 24 12:46:27 PM PDT 24 178986800 ps
T259 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.4283007 Mar 24 12:38:58 PM PDT 24 Mar 24 12:39:15 PM PDT 24 52973500 ps
T238 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.340897838 Mar 24 12:38:55 PM PDT 24 Mar 24 12:39:14 PM PDT 24 27173300 ps
T239 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.1840854255 Mar 24 12:38:57 PM PDT 24 Mar 24 12:53:47 PM PDT 24 873903600 ps
T240 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.2839442510 Mar 24 12:38:48 PM PDT 24 Mar 24 12:39:04 PM PDT 24 320042100 ps
T241 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2530775401 Mar 24 12:38:59 PM PDT 24 Mar 24 12:39:16 PM PDT 24 26578600 ps
T244 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.114357576 Mar 24 12:38:36 PM PDT 24 Mar 24 12:51:00 PM PDT 24 369808400 ps
T1061 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2987017424 Mar 24 12:38:38 PM PDT 24 Mar 24 12:39:37 PM PDT 24 1270163300 ps
T347 /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.120965073 Mar 24 12:39:05 PM PDT 24 Mar 24 12:39:20 PM PDT 24 16243400 ps
T1062 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.1874116260 Mar 24 12:38:51 PM PDT 24 Mar 24 12:39:06 PM PDT 24 42881500 ps
T1063 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.4046967523 Mar 24 12:38:52 PM PDT 24 Mar 24 12:39:09 PM PDT 24 14616500 ps
T1064 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1856500301 Mar 24 12:38:47 PM PDT 24 Mar 24 12:39:00 PM PDT 24 42406600 ps
T1065 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.3822586642 Mar 24 12:38:49 PM PDT 24 Mar 24 12:39:05 PM PDT 24 33070800 ps
T348 /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.2235315417 Mar 24 12:38:56 PM PDT 24 Mar 24 12:39:10 PM PDT 24 26244600 ps
T260 /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3043931080 Mar 24 12:38:38 PM PDT 24 Mar 24 12:38:55 PM PDT 24 39071000 ps
T1066 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.4150308768 Mar 24 12:38:48 PM PDT 24 Mar 24 12:39:02 PM PDT 24 27458200 ps
T261 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.388544475 Mar 24 12:38:41 PM PDT 24 Mar 24 12:38:59 PM PDT 24 59617700 ps
T1067 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2476144138 Mar 24 12:38:36 PM PDT 24 Mar 24 12:38:50 PM PDT 24 41927000 ps
T242 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.13724697 Mar 24 12:38:47 PM PDT 24 Mar 24 12:39:07 PM PDT 24 25554800 ps
T1068 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.790826498 Mar 24 12:38:32 PM PDT 24 Mar 24 12:39:39 PM PDT 24 1293006200 ps
T301 /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2218726154 Mar 24 12:38:48 PM PDT 24 Mar 24 12:39:07 PM PDT 24 453479900 ps
T245 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.677099585 Mar 24 12:38:49 PM PDT 24 Mar 24 12:39:07 PM PDT 24 295455300 ps
T1069 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.3849943221 Mar 24 12:38:41 PM PDT 24 Mar 24 12:38:54 PM PDT 24 19403800 ps
T302 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.265283267 Mar 24 12:38:33 PM PDT 24 Mar 24 12:39:44 PM PDT 24 11607017600 ps
T303 /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.311734524 Mar 24 12:38:54 PM PDT 24 Mar 24 12:39:12 PM PDT 24 245927600 ps
T1070 /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.3647445891 Mar 24 12:38:57 PM PDT 24 Mar 24 12:39:15 PM PDT 24 162193200 ps
T349 /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.718159647 Mar 24 12:38:40 PM PDT 24 Mar 24 12:38:54 PM PDT 24 47884400 ps
T1071 /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.302744944 Mar 24 12:39:13 PM PDT 24 Mar 24 12:39:26 PM PDT 24 123257400 ps
T1072 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.4076773187 Mar 24 12:38:54 PM PDT 24 Mar 24 12:39:07 PM PDT 24 17919900 ps
T354 /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.3609952671 Mar 24 12:38:29 PM PDT 24 Mar 24 12:38:43 PM PDT 24 45699800 ps
T246 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.1605774288 Mar 24 12:38:45 PM PDT 24 Mar 24 12:39:03 PM PDT 24 168065900 ps
T1073 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.3313284614 Mar 24 12:38:55 PM PDT 24 Mar 24 12:39:10 PM PDT 24 25627900 ps
T1074 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.705299212 Mar 24 12:38:53 PM PDT 24 Mar 24 12:39:09 PM PDT 24 14174200 ps
T1075 /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3383165247 Mar 24 12:38:51 PM PDT 24 Mar 24 12:39:04 PM PDT 24 16154500 ps
T1076 /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.192682163 Mar 24 12:39:00 PM PDT 24 Mar 24 12:39:13 PM PDT 24 16651800 ps
T1077 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.137769605 Mar 24 12:39:04 PM PDT 24 Mar 24 12:39:18 PM PDT 24 34458700 ps
T268 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.3585283786 Mar 24 12:39:15 PM PDT 24 Mar 24 12:39:34 PM PDT 24 54214200 ps
T278 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.477693391 Mar 24 12:38:53 PM PDT 24 Mar 24 12:53:44 PM PDT 24 822269000 ps
T271 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.2016581807 Mar 24 12:38:49 PM PDT 24 Mar 24 12:53:52 PM PDT 24 487340000 ps
T1078 /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2615978643 Mar 24 12:38:50 PM PDT 24 Mar 24 12:39:08 PM PDT 24 73206400 ps
T275 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.477570661 Mar 24 12:38:49 PM PDT 24 Mar 24 12:39:05 PM PDT 24 49706800 ps
T250 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.3681866032 Mar 24 12:38:34 PM PDT 24 Mar 24 12:38:47 PM PDT 24 45189200 ps
T1079 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.798429768 Mar 24 12:39:08 PM PDT 24 Mar 24 12:39:24 PM PDT 24 148134300 ps
T304 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.2417950888 Mar 24 12:38:25 PM PDT 24 Mar 24 12:39:00 PM PDT 24 2551890300 ps
T1080 /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.139883332 Mar 24 12:38:56 PM PDT 24 Mar 24 12:39:10 PM PDT 24 25339500 ps
T1081 /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.4194140343 Mar 24 12:38:53 PM PDT 24 Mar 24 12:39:08 PM PDT 24 37613900 ps
T1082 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.1837478494 Mar 24 12:38:40 PM PDT 24 Mar 24 12:38:56 PM PDT 24 41642500 ps
T305 /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3682321619 Mar 24 12:38:31 PM PDT 24 Mar 24 12:38:49 PM PDT 24 645420500 ps
T267 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.880720221 Mar 24 12:38:41 PM PDT 24 Mar 24 12:39:00 PM PDT 24 107356800 ps
T1083 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.807072692 Mar 24 12:38:46 PM PDT 24 Mar 24 12:39:03 PM PDT 24 36574500 ps
T1084 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.2322283524 Mar 24 12:38:36 PM PDT 24 Mar 24 12:38:49 PM PDT 24 20624400 ps
T1085 /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3814400077 Mar 24 12:39:00 PM PDT 24 Mar 24 12:39:17 PM PDT 24 38433100 ps
T1086 /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3545550376 Mar 24 12:39:02 PM PDT 24 Mar 24 12:39:15 PM PDT 24 66901300 ps
T355 /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.1281786270 Mar 24 12:39:10 PM PDT 24 Mar 24 12:39:29 PM PDT 24 60175400 ps
T1087 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1846048499 Mar 24 12:38:46 PM PDT 24 Mar 24 12:38:59 PM PDT 24 50241800 ps
T1088 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.4193193038 Mar 24 12:39:08 PM PDT 24 Mar 24 12:39:24 PM PDT 24 19944700 ps
T1089 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3968767186 Mar 24 12:39:09 PM PDT 24 Mar 24 12:39:28 PM PDT 24 39216700 ps
T1090 /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2376314128 Mar 24 12:39:17 PM PDT 24 Mar 24 12:39:30 PM PDT 24 44551900 ps
T1091 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.3216336823 Mar 24 12:38:31 PM PDT 24 Mar 24 12:38:47 PM PDT 24 69895200 ps
T1092 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.3444947998 Mar 24 12:38:44 PM PDT 24 Mar 24 12:39:01 PM PDT 24 183096800 ps
T1093 /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.1083557208 Mar 24 12:38:41 PM PDT 24 Mar 24 12:38:55 PM PDT 24 55739800 ps
T306 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.1812070173 Mar 24 12:38:41 PM PDT 24 Mar 24 12:46:14 PM PDT 24 456608100 ps
T251 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.3737312185 Mar 24 12:38:35 PM PDT 24 Mar 24 12:38:54 PM PDT 24 17939100 ps
T1094 /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2409284958 Mar 24 12:38:46 PM PDT 24 Mar 24 12:38:59 PM PDT 24 33796300 ps
T1095 /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.2693255549 Mar 24 12:38:53 PM PDT 24 Mar 24 12:39:11 PM PDT 24 294164400 ps
T1096 /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.314161031 Mar 24 12:39:03 PM PDT 24 Mar 24 12:39:22 PM PDT 24 220062300 ps
T276 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.260219197 Mar 24 12:38:49 PM PDT 24 Mar 24 12:39:06 PM PDT 24 116773900 ps
T1097 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.321537353 Mar 24 12:38:41 PM PDT 24 Mar 24 12:38:54 PM PDT 24 19802400 ps
T1098 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.2809097641 Mar 24 12:38:37 PM PDT 24 Mar 24 12:38:52 PM PDT 24 20555600 ps
T1099 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.4091421422 Mar 24 12:38:37 PM PDT 24 Mar 24 12:38:52 PM PDT 24 180070500 ps
T1100 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.3510663574 Mar 24 12:38:54 PM PDT 24 Mar 24 12:39:13 PM PDT 24 163439800 ps
T1101 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.2464196854 Mar 24 12:38:53 PM PDT 24 Mar 24 12:39:10 PM PDT 24 143110700 ps
T272 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.1224320352 Mar 24 12:38:48 PM PDT 24 Mar 24 12:39:07 PM PDT 24 59858500 ps
T1102 /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.402326140 Mar 24 12:39:04 PM PDT 24 Mar 24 12:39:18 PM PDT 24 44194300 ps
T1103 /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.38908367 Mar 24 12:38:57 PM PDT 24 Mar 24 12:39:11 PM PDT 24 57477100 ps
T307 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.935285231 Mar 24 12:38:50 PM PDT 24 Mar 24 12:39:07 PM PDT 24 41571500 ps
T1104 /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.1123149361 Mar 24 12:38:36 PM PDT 24 Mar 24 12:38:50 PM PDT 24 15841600 ps
T308 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.296224544 Mar 24 12:38:30 PM PDT 24 Mar 24 12:39:00 PM PDT 24 150532700 ps
T1105 /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3761322023 Mar 24 12:38:38 PM PDT 24 Mar 24 12:38:56 PM PDT 24 135592100 ps
T1106 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3778006003 Mar 24 12:38:45 PM PDT 24 Mar 24 12:39:00 PM PDT 24 32952300 ps
T362 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.3583994988 Mar 24 12:38:45 PM PDT 24 Mar 24 12:53:42 PM PDT 24 670070000 ps
T1107 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1290309252 Mar 24 12:38:50 PM PDT 24 Mar 24 12:39:05 PM PDT 24 319420300 ps
T1108 /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.2905959461 Mar 24 12:39:06 PM PDT 24 Mar 24 12:39:19 PM PDT 24 45077100 ps
T1109 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.659523588 Mar 24 12:38:57 PM PDT 24 Mar 24 12:39:10 PM PDT 24 15447500 ps
T1110 /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.448251895 Mar 24 12:38:57 PM PDT 24 Mar 24 12:39:10 PM PDT 24 15124700 ps
T309 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2287272326 Mar 24 12:38:54 PM PDT 24 Mar 24 12:46:47 PM PDT 24 1736092700 ps
T277 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1186845055 Mar 24 12:38:43 PM PDT 24 Mar 24 12:39:03 PM PDT 24 60803100 ps
T1111 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.648049825 Mar 24 12:39:03 PM PDT 24 Mar 24 12:39:18 PM PDT 24 44438300 ps
T1112 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.4114006590 Mar 24 12:39:02 PM PDT 24 Mar 24 12:39:18 PM PDT 24 23556600 ps
T310 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.3343159606 Mar 24 12:39:00 PM PDT 24 Mar 24 12:39:17 PM PDT 24 74486100 ps
T1113 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.2314254261 Mar 24 12:38:40 PM PDT 24 Mar 24 12:39:10 PM PDT 24 52440100 ps
T1114 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.455196086 Mar 24 12:38:35 PM PDT 24 Mar 24 12:38:48 PM PDT 24 47161300 ps
T1115 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1160185103 Mar 24 12:38:34 PM PDT 24 Mar 24 12:38:47 PM PDT 24 63663500 ps
T1116 /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.186416714 Mar 24 12:39:01 PM PDT 24 Mar 24 12:39:15 PM PDT 24 52227800 ps
T363 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2652674280 Mar 24 12:38:47 PM PDT 24 Mar 24 12:46:20 PM PDT 24 241240700 ps
T1117 /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.3278147744 Mar 24 12:38:53 PM PDT 24 Mar 24 12:39:06 PM PDT 24 17740600 ps
T1118 /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.2111055469 Mar 24 12:38:44 PM PDT 24 Mar 24 12:39:18 PM PDT 24 578438600 ps
T1119 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1837452422 Mar 24 12:38:41 PM PDT 24 Mar 24 12:38:59 PM PDT 24 128143300 ps
T1120 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2008365573 Mar 24 12:38:59 PM PDT 24 Mar 24 12:39:12 PM PDT 24 12622700 ps
T311 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.2026000720 Mar 24 12:38:35 PM PDT 24 Mar 24 12:38:53 PM PDT 24 212487300 ps
T1121 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2439246259 Mar 24 12:38:41 PM PDT 24 Mar 24 12:39:02 PM PDT 24 205316500 ps
T1122 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.878119069 Mar 24 12:38:56 PM PDT 24 Mar 24 12:39:13 PM PDT 24 128073300 ps
T1123 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1555423533 Mar 24 12:38:56 PM PDT 24 Mar 24 12:39:10 PM PDT 24 41878600 ps
T358 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.3536635093 Mar 24 12:38:58 PM PDT 24 Mar 24 12:46:37 PM PDT 24 1631748200 ps
T1124 /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3088878268 Mar 24 12:39:14 PM PDT 24 Mar 24 12:39:28 PM PDT 24 25838200 ps
T1125 /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1975215068 Mar 24 12:38:46 PM PDT 24 Mar 24 12:39:04 PM PDT 24 473790000 ps
T1126 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1488102052 Mar 24 12:38:53 PM PDT 24 Mar 24 12:39:06 PM PDT 24 14352300 ps
T1127 /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.50409615 Mar 24 12:38:46 PM PDT 24 Mar 24 12:38:59 PM PDT 24 20516100 ps
T1128 /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.2319515909 Mar 24 12:39:00 PM PDT 24 Mar 24 12:39:13 PM PDT 24 14648200 ps
T357 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.3321070213 Mar 24 12:38:50 PM PDT 24 Mar 24 12:53:40 PM PDT 24 3879800900 ps
T1129 /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1879350985 Mar 24 12:39:07 PM PDT 24 Mar 24 12:39:21 PM PDT 24 14636500 ps
T359 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1222627500 Mar 24 12:38:41 PM PDT 24 Mar 24 12:51:12 PM PDT 24 866516400 ps
T1130 /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.2056277215 Mar 24 12:38:44 PM PDT 24 Mar 24 12:38:58 PM PDT 24 16337000 ps
T312 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.694803514 Mar 24 12:38:52 PM PDT 24 Mar 24 12:39:10 PM PDT 24 291353500 ps
T1131 /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.2490255888 Mar 24 12:38:52 PM PDT 24 Mar 24 12:39:06 PM PDT 24 52500500 ps
T360 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.439136267 Mar 24 12:38:54 PM PDT 24 Mar 24 12:53:51 PM PDT 24 5305826000 ps
T1132 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3146349789 Mar 24 12:38:33 PM PDT 24 Mar 24 12:38:49 PM PDT 24 184327500 ps
T1133 /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.1990056308 Mar 24 12:39:00 PM PDT 24 Mar 24 12:39:14 PM PDT 24 105786000 ps
T1134 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3566964485 Mar 24 12:38:47 PM PDT 24 Mar 24 12:39:01 PM PDT 24 28320000 ps
T1135 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2230489555 Mar 24 12:39:08 PM PDT 24 Mar 24 12:39:21 PM PDT 24 26775800 ps
T273 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.809863742 Mar 24 12:38:41 PM PDT 24 Mar 24 12:38:58 PM PDT 24 36899500 ps
T1136 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.1154941947 Mar 24 12:38:29 PM PDT 24 Mar 24 12:39:31 PM PDT 24 3923029900 ps
T1137 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.737778374 Mar 24 12:39:13 PM PDT 24 Mar 24 12:39:29 PM PDT 24 28043900 ps
T1138 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.594444012 Mar 24 12:38:49 PM PDT 24 Mar 24 12:39:05 PM PDT 24 18824300 ps
T1139 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.2047264438 Mar 24 12:39:15 PM PDT 24 Mar 24 12:39:31 PM PDT 24 37685400 ps
T1140 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3502404120 Mar 24 12:38:58 PM PDT 24 Mar 24 12:39:11 PM PDT 24 12568800 ps
T1141 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.2187033524 Mar 24 12:38:55 PM PDT 24 Mar 24 12:39:13 PM PDT 24 50151000 ps
T1142 /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.626880007 Mar 24 12:39:03 PM PDT 24 Mar 24 12:39:19 PM PDT 24 72362100 ps
T1143 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.620726252 Mar 24 12:38:42 PM PDT 24 Mar 24 12:39:54 PM PDT 24 2190042100 ps
T1144 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.1734138577 Mar 24 12:38:46 PM PDT 24 Mar 24 12:39:03 PM PDT 24 40285600 ps
T1145 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.3092799027 Mar 24 12:38:58 PM PDT 24 Mar 24 12:39:14 PM PDT 24 133709900 ps
T1146 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.3860900037 Mar 24 12:38:54 PM PDT 24 Mar 24 12:39:11 PM PDT 24 228006500 ps
T274 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1623290498 Mar 24 12:39:01 PM PDT 24 Mar 24 12:46:37 PM PDT 24 335242000 ps
T1147 /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.2016267101 Mar 24 12:38:59 PM PDT 24 Mar 24 12:39:12 PM PDT 24 17401100 ps
T1148 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.1185759025 Mar 24 12:38:47 PM PDT 24 Mar 24 12:39:02 PM PDT 24 19575500 ps
T1149 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.4088631831 Mar 24 12:38:54 PM PDT 24 Mar 24 12:39:11 PM PDT 24 88115800 ps
T1150 /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1566882995 Mar 24 12:38:46 PM PDT 24 Mar 24 12:39:04 PM PDT 24 76008700 ps
T1151 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.2405836130 Mar 24 12:38:45 PM PDT 24 Mar 24 12:39:50 PM PDT 24 10514592000 ps
T1152 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.500682889 Mar 24 12:38:45 PM PDT 24 Mar 24 12:39:04 PM PDT 24 78254400 ps
T1153 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1757100751 Mar 24 12:38:56 PM PDT 24 Mar 24 12:39:10 PM PDT 24 60335200 ps
T1154 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.635506994 Mar 24 12:39:26 PM PDT 24 Mar 24 12:39:41 PM PDT 24 57530200 ps
T1155 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.2599537022 Mar 24 12:38:48 PM PDT 24 Mar 24 12:39:04 PM PDT 24 189107800 ps
T1156 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.3601886312 Mar 24 12:38:51 PM PDT 24 Mar 24 12:39:04 PM PDT 24 51228600 ps
T1157 /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.833453558 Mar 24 12:38:42 PM PDT 24 Mar 24 12:38:55 PM PDT 24 17719600 ps
T1158 /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.1471550196 Mar 24 12:38:54 PM PDT 24 Mar 24 12:39:08 PM PDT 24 45306200 ps
T1159 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1252510886 Mar 24 12:38:50 PM PDT 24 Mar 24 12:39:06 PM PDT 24 570483700 ps
T1160 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3105236437 Mar 24 12:38:40 PM PDT 24 Mar 24 12:38:56 PM PDT 24 28117900 ps
T1161 /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.3360679156 Mar 24 12:38:50 PM PDT 24 Mar 24 12:39:04 PM PDT 24 29401700 ps
T1162 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1284108390 Mar 24 12:38:55 PM PDT 24 Mar 24 12:39:11 PM PDT 24 12617600 ps
T1163 /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2940999004 Mar 24 12:38:38 PM PDT 24 Mar 24 12:38:58 PM PDT 24 1518462300 ps
T252 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3110175334 Mar 24 12:38:34 PM PDT 24 Mar 24 12:38:48 PM PDT 24 31387100 ps
T1164 /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.2579300975 Mar 24 12:38:39 PM PDT 24 Mar 24 12:38:53 PM PDT 24 25011400 ps
T1165 /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.2685389109 Mar 24 12:38:52 PM PDT 24 Mar 24 12:39:06 PM PDT 24 49240300 ps
T1166 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3407174785 Mar 24 12:38:40 PM PDT 24 Mar 24 12:38:55 PM PDT 24 25258400 ps
T1167 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.147298432 Mar 24 12:38:37 PM PDT 24 Mar 24 12:46:21 PM PDT 24 898015800 ps
T1168 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.944800298 Mar 24 12:38:46 PM PDT 24 Mar 24 12:39:07 PM PDT 24 28264300 ps
T356 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.1772111639 Mar 24 12:38:48 PM PDT 24 Mar 24 12:45:15 PM PDT 24 351805000 ps
T361 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.4220467294 Mar 24 12:38:47 PM PDT 24 Mar 24 12:45:11 PM PDT 24 2009387800 ps
T1169 /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.1218505975 Mar 24 12:39:08 PM PDT 24 Mar 24 12:39:21 PM PDT 24 70369100 ps
T1170 /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.3114585818 Mar 24 12:38:59 PM PDT 24 Mar 24 12:39:12 PM PDT 24 15963700 ps
T1171 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.4106826823 Mar 24 12:38:44 PM PDT 24 Mar 24 12:39:00 PM PDT 24 18842100 ps
T1172 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.4166270963 Mar 24 12:38:47 PM PDT 24 Mar 24 12:39:19 PM PDT 24 339141400 ps
T1173 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.3501694758 Mar 24 12:38:56 PM PDT 24 Mar 24 12:39:12 PM PDT 24 25965400 ps
T1174 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.3888061795 Mar 24 12:38:44 PM PDT 24 Mar 24 12:38:58 PM PDT 24 14726100 ps
T313 /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2204313397 Mar 24 12:38:35 PM PDT 24 Mar 24 12:39:10 PM PDT 24 214258700 ps
T1175 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2399755494 Mar 24 12:38:54 PM PDT 24 Mar 24 12:39:10 PM PDT 24 58220000 ps
T1176 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.263062465 Mar 24 12:38:30 PM PDT 24 Mar 24 12:38:47 PM PDT 24 116343400 ps
T1177 /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3992010353 Mar 24 12:38:50 PM PDT 24 Mar 24 12:39:04 PM PDT 24 31473700 ps
T1178 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.2993835081 Mar 24 12:38:39 PM PDT 24 Mar 24 12:38:56 PM PDT 24 962672100 ps
T314 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.4152528930 Mar 24 12:38:48 PM PDT 24 Mar 24 12:39:07 PM PDT 24 115335300 ps
T1179 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.372577322 Mar 24 12:38:50 PM PDT 24 Mar 24 12:46:25 PM PDT 24 777020000 ps
T1180 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.4012743055 Mar 24 12:38:45 PM PDT 24 Mar 24 12:39:02 PM PDT 24 189369800 ps
T1181 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.269294217 Mar 24 12:38:36 PM PDT 24 Mar 24 12:39:22 PM PDT 24 5949536900 ps
T1182 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.1445004942 Mar 24 12:39:06 PM PDT 24 Mar 24 12:39:25 PM PDT 24 311698000 ps
T1183 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.2101122053 Mar 24 12:38:57 PM PDT 24 Mar 24 12:39:10 PM PDT 24 36318500 ps
T1184 /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.44255753 Mar 24 12:38:49 PM PDT 24 Mar 24 12:39:03 PM PDT 24 16592700 ps
T253 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.854353126 Mar 24 12:38:43 PM PDT 24 Mar 24 12:38:57 PM PDT 24 23965400 ps
T1185 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.2774990235 Mar 24 12:38:48 PM PDT 24 Mar 24 12:39:01 PM PDT 24 20928000 ps
T1186 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3380228870 Mar 24 12:38:43 PM PDT 24 Mar 24 12:39:52 PM PDT 24 5968768900 ps
T1187 /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.3555812027 Mar 24 12:39:11 PM PDT 24 Mar 24 12:39:25 PM PDT 24 70610400 ps
T1188 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.1861276007 Mar 24 12:38:49 PM PDT 24 Mar 24 12:39:03 PM PDT 24 88021100 ps
T1189 /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.3825008833 Mar 24 12:38:35 PM PDT 24 Mar 24 12:38:48 PM PDT 24 56452800 ps
T1190 /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.1987534843 Mar 24 12:39:03 PM PDT 24 Mar 24 12:39:16 PM PDT 24 210895000 ps
T1191 /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3265648955 Mar 24 12:38:59 PM PDT 24 Mar 24 12:39:13 PM PDT 24 52255600 ps
T1192 /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.375986105 Mar 24 12:39:19 PM PDT 24 Mar 24 12:39:32 PM PDT 24 25332100 ps
T1193 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.332328038 Mar 24 12:39:00 PM PDT 24 Mar 24 12:39:19 PM PDT 24 152636600 ps
T1194 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.231697402 Mar 24 12:38:37 PM PDT 24 Mar 24 12:38:54 PM PDT 24 185049600 ps
T1195 /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.3153630971 Mar 24 12:39:06 PM PDT 24 Mar 24 12:39:19 PM PDT 24 16846500 ps
T1196 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1236621803 Mar 24 12:38:51 PM PDT 24 Mar 24 12:39:06 PM PDT 24 128882800 ps

Test location /workspace/coverage/default/5.flash_ctrl_rw.4008062599
Short name T5
Test name
Test status
Simulation time 7070358900 ps
CPU time 418.87 seconds
Started Mar 24 02:21:12 PM PDT 24
Finished Mar 24 02:28:11 PM PDT 24
Peak memory 314408 kb
Host smart-ca4540ea-ffa2-4cb0-aad1-91ce24f3fbf4
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008062599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ct
rl_rw.4008062599
Directory /workspace/5.flash_ctrl_rw/latest

Test location /workspace/coverage/default/13.flash_ctrl_mp_regions.3501447771
Short name T26
Test name
Test status
Simulation time 47866167600 ps
CPU time 455.42 seconds
Started Mar 24 02:25:18 PM PDT 24
Finished Mar 24 02:32:54 PM PDT 24
Peak memory 273936 kb
Host smart-fc2e9976-ff9b-4da9-891f-fcd6586eec56
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501447771 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 13.flash_ctrl_mp_regions.3501447771
Directory /workspace/13.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2113564541
Short name T60
Test name
Test status
Simulation time 1280304200 ps
CPU time 892.1 seconds
Started Mar 24 12:38:16 PM PDT 24
Finished Mar 24 12:53:09 PM PDT 24
Peak memory 263664 kb
Host smart-1f6ebb0a-cd86-421b-9078-f3f26252f80e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113564541 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl
_tl_intg_err.2113564541
Directory /workspace/0.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_rma_reset.2439624895
Short name T67
Test name
Test status
Simulation time 260202169200 ps
CPU time 1060.66 seconds
Started Mar 24 02:26:03 PM PDT 24
Finished Mar 24 02:43:44 PM PDT 24
Peak memory 263968 kb
Host smart-893a6179-540d-424f-9895-25ff653bf1df
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439624895 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.flash_ctrl_hw_rma_reset.2439624895
Directory /workspace/15.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_cm.1879823505
Short name T12
Test name
Test status
Simulation time 3843839600 ps
CPU time 4797.2 seconds
Started Mar 24 02:16:33 PM PDT 24
Finished Mar 24 03:36:31 PM PDT 24
Peak memory 281772 kb
Host smart-f510e418-b454-4477-9831-623162ef6393
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879823505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.1879823505
Directory /workspace/1.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_sec_otp.1318809573
Short name T43
Test name
Test status
Simulation time 26532423500 ps
CPU time 148.71 seconds
Started Mar 24 02:27:00 PM PDT 24
Finished Mar 24 02:29:29 PM PDT 24
Peak memory 262360 kb
Host smart-39430795-f411-4598-b474-01dab7e20f2d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318809573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_
hw_sec_otp.1318809573
Directory /workspace/18.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.3435230029
Short name T174
Test name
Test status
Simulation time 220200300 ps
CPU time 18.86 seconds
Started Mar 24 12:38:48 PM PDT 24
Finished Mar 24 12:39:07 PM PDT 24
Peak memory 271920 kb
Host smart-e6be3872-1839-474c-aaae-cc89e58f201a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435230029 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.3435230029
Directory /workspace/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_mid_op_rst.1441731419
Short name T39
Test name
Test status
Simulation time 805340700 ps
CPU time 70.35 seconds
Started Mar 24 02:18:51 PM PDT 24
Finished Mar 24 02:20:01 PM PDT 24
Peak memory 259636 kb
Host smart-e2b28794-db8b-4921-b570-653b3b38e6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441731419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.1441731419
Directory /workspace/3.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.282187908
Short name T10
Test name
Test status
Simulation time 10058333400 ps
CPU time 46.96 seconds
Started Mar 24 02:23:59 PM PDT 24
Finished Mar 24 02:24:46 PM PDT 24
Peak memory 272812 kb
Host smart-a3add76c-2c22-4584-8430-119951d05f2d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282187908 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.282187908
Directory /workspace/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict_all_en.479294075
Short name T90
Test name
Test status
Simulation time 62595200 ps
CPU time 31.08 seconds
Started Mar 24 02:25:50 PM PDT 24
Finished Mar 24 02:26:21 PM PDT 24
Peak memory 273312 kb
Host smart-278a7bcb-9821-4db1-b05e-d1dfb9ea5305
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479294075 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict_all_en.479294075
Directory /workspace/14.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd_slow_flash.172599086
Short name T4
Test name
Test status
Simulation time 58429037700 ps
CPU time 252.42 seconds
Started Mar 24 02:24:59 PM PDT 24
Finished Mar 24 02:29:11 PM PDT 24
Peak memory 289536 kb
Host smart-b49090ac-3ec6-4086-97d0-7fdfbe45d655
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172599086 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd_slow_flash.172599086
Directory /workspace/12.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_erase_suspend.1958288596
Short name T119
Test name
Test status
Simulation time 3486383200 ps
CPU time 555.04 seconds
Started Mar 24 02:15:49 PM PDT 24
Finished Mar 24 02:25:04 PM PDT 24
Peak memory 261060 kb
Host smart-3bf7e1fd-6800-4f7c-b13e-f92b187dcbdf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1958288596 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.1958288596
Directory /workspace/1.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/25.flash_ctrl_otp_reset.3138521298
Short name T142
Test name
Test status
Simulation time 67233300 ps
CPU time 110.83 seconds
Started Mar 24 02:28:29 PM PDT 24
Finished Mar 24 02:30:21 PM PDT 24
Peak memory 264588 kb
Host smart-1194ad8c-ac75-49f8-b55c-d96fd35aa3a6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138521298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_o
tp_reset.3138521298
Directory /workspace/25.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_host_grant_err.1025215574
Short name T9
Test name
Test status
Simulation time 43494100 ps
CPU time 13.64 seconds
Started Mar 24 02:20:37 PM PDT 24
Finished Mar 24 02:20:50 PM PDT 24
Peak memory 265104 kb
Host smart-6deecc6a-5103-4359-aaf6-dd4da8e963ea
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025215574 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.1025215574
Directory /workspace/4.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/64.flash_ctrl_otp_reset.1836478765
Short name T83
Test name
Test status
Simulation time 69557900 ps
CPU time 114.14 seconds
Started Mar 24 02:31:00 PM PDT 24
Finished Mar 24 02:32:55 PM PDT 24
Peak memory 259668 kb
Host smart-269015eb-9fce-432a-a323-fe50b90758fb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836478765 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_o
tp_reset.1836478765
Directory /workspace/64.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_otp_reset.1582962053
Short name T85
Test name
Test status
Simulation time 156630900 ps
CPU time 131.56 seconds
Started Mar 24 02:27:51 PM PDT 24
Finished Mar 24 02:30:02 PM PDT 24
Peak memory 263344 kb
Host smart-fa3704af-86b4-48ce-b75f-d6217f89c125
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582962053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_o
tp_reset.1582962053
Directory /workspace/21.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.2053217355
Short name T343
Test name
Test status
Simulation time 59055700 ps
CPU time 13.42 seconds
Started Mar 24 12:38:57 PM PDT 24
Finished Mar 24 12:39:10 PM PDT 24
Peak memory 262104 kb
Host smart-84eaed05-39fa-4a92-bd6f-ca09e5df5681
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053217355 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.
2053217355
Directory /workspace/15.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/4.flash_ctrl_fs_sup.3708164981
Short name T34
Test name
Test status
Simulation time 1908395400 ps
CPU time 35.87 seconds
Started Mar 24 02:20:37 PM PDT 24
Finished Mar 24 02:21:13 PM PDT 24
Peak memory 273060 kb
Host smart-0b1bd12d-81c1-4176-88e2-bc68b75e3877
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708164981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.flash_ctrl_fs_sup.3708164981
Directory /workspace/4.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/2.flash_ctrl_rma_err.2653484945
Short name T137
Test name
Test status
Simulation time 85813792700 ps
CPU time 1003.86 seconds
Started Mar 24 02:18:13 PM PDT 24
Finished Mar 24 02:34:57 PM PDT 24
Peak memory 259164 kb
Host smart-6655e6d4-42a5-46d3-b3f7-2db590b2b1e5
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653484945 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rma_err.2653484945
Directory /workspace/2.flash_ctrl_rma_err/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.2907664484
Short name T173
Test name
Test status
Simulation time 48617700 ps
CPU time 18.69 seconds
Started Mar 24 12:38:43 PM PDT 24
Finished Mar 24 12:39:01 PM PDT 24
Peak memory 263628 kb
Host smart-9cc40841-81c9-4b7a-b947-50bcd6b96ed2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907664484 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.2
907664484
Directory /workspace/1.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.1387757099
Short name T122
Test name
Test status
Simulation time 10019371900 ps
CPU time 166.33 seconds
Started Mar 24 02:25:35 PM PDT 24
Finished Mar 24 02:28:21 PM PDT 24
Peak memory 265260 kb
Host smart-49e9e9b6-70a5-4e6a-bedb-29c73df5931c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387757099 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.1387757099
Directory /workspace/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_wr_intg.3798904770
Short name T7
Test name
Test status
Simulation time 87058400 ps
CPU time 14.74 seconds
Started Mar 24 02:16:41 PM PDT 24
Finished Mar 24 02:16:56 PM PDT 24
Peak memory 260088 kb
Host smart-121efa91-54ad-42bb-80b5-ae7b06db38e7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798904770 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wr_intg.3798904770
Directory /workspace/1.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/11.flash_ctrl_otp_reset.1567359886
Short name T146
Test name
Test status
Simulation time 38016000 ps
CPU time 131.02 seconds
Started Mar 24 02:24:36 PM PDT 24
Finished Mar 24 02:26:47 PM PDT 24
Peak memory 263848 kb
Host smart-150310a6-c666-464b-9334-7389c02ecfe4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567359886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_o
tp_reset.1567359886
Directory /workspace/11.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_alert_test.3319820455
Short name T165
Test name
Test status
Simulation time 131868100 ps
CPU time 13.44 seconds
Started Mar 24 02:24:53 PM PDT 24
Finished Mar 24 02:25:06 PM PDT 24
Peak memory 257888 kb
Host smart-b303aa90-f339-462e-b28c-cd691845707f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319820455 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test.
3319820455
Directory /workspace/11.flash_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.186164287
Short name T226
Test name
Test status
Simulation time 719349900 ps
CPU time 888.18 seconds
Started Mar 24 12:38:51 PM PDT 24
Finished Mar 24 12:53:39 PM PDT 24
Peak memory 263604 kb
Host smart-81556508-6eb4-4c85-8cd8-503d0270e1ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186164287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_
tl_intg_err.186164287
Directory /workspace/4.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_ctrl_arb.1368740920
Short name T148
Test name
Test status
Simulation time 590521279800 ps
CPU time 2197.28 seconds
Started Mar 24 02:17:18 PM PDT 24
Finished Mar 24 02:53:55 PM PDT 24
Peak memory 264768 kb
Host smart-628e20e6-957c-4e4f-b19b-0c69d1d192b9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368740920 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.flash_ctrl_host_ctrl_arb.1368740920
Directory /workspace/2.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb_redun.3553228002
Short name T128
Test name
Test status
Simulation time 694239800 ps
CPU time 40.69 seconds
Started Mar 24 02:15:18 PM PDT 24
Finished Mar 24 02:15:59 PM PDT 24
Peak memory 264232 kb
Host smart-3b6c9960-ec94-4853-bb72-c3ea2134b082
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553228002 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.3553228002
Directory /workspace/0.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/33.flash_ctrl_sec_info_access.4042656236
Short name T25
Test name
Test status
Simulation time 2670506700 ps
CPU time 71.81 seconds
Started Mar 24 02:29:30 PM PDT 24
Finished Mar 24 02:30:42 PM PDT 24
Peak memory 262660 kb
Host smart-5c78659e-5b17-41d8-b66e-91386565af90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042656236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.4042656236
Directory /workspace/33.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/8.flash_ctrl_fetch_code.746452186
Short name T52
Test name
Test status
Simulation time 389547100 ps
CPU time 25.13 seconds
Started Mar 24 02:23:04 PM PDT 24
Finished Mar 24 02:23:29 PM PDT 24
Peak memory 264788 kb
Host smart-54b4af18-f861-4ffb-a502-72f7aa8be9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746452186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetch_code.746452186
Directory /workspace/8.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/1.flash_ctrl_mid_op_rst.4200236574
Short name T124
Test name
Test status
Simulation time 1894265400 ps
CPU time 76.28 seconds
Started Mar 24 02:16:00 PM PDT 24
Finished Mar 24 02:17:16 PM PDT 24
Peak memory 260460 kb
Host smart-619b46c8-cb67-4328-a935-f0c806243d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200236574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.4200236574
Directory /workspace/1.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_ack_consistency.1096260292
Short name T55
Test name
Test status
Simulation time 15336700 ps
CPU time 14.26 seconds
Started Mar 24 02:15:20 PM PDT 24
Finished Mar 24 02:15:34 PM PDT 24
Peak memory 265060 kb
Host smart-0f9f22cf-6057-41f0-a9bc-7c249cd4c5f4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1096260292 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.1096260292
Directory /workspace/0.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/3.flash_ctrl_mp_regions.140406059
Short name T77
Test name
Test status
Simulation time 17034239400 ps
CPU time 900.68 seconds
Started Mar 24 02:18:46 PM PDT 24
Finished Mar 24 02:33:47 PM PDT 24
Peak memory 273952 kb
Host smart-b7922677-2b05-4671-9870-009513241b10
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140406059 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_mp_regions.140406059
Directory /workspace/3.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/11.flash_ctrl_lcmgr_intg.2063560694
Short name T132
Test name
Test status
Simulation time 15579900 ps
CPU time 13.45 seconds
Started Mar 24 02:24:48 PM PDT 24
Finished Mar 24 02:25:03 PM PDT 24
Peak memory 259408 kb
Host smart-cec44d0f-27ee-4fd8-a158-67b3d7f04f58
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063560694 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.flash_ctrl_lcmgr_intg.2063560694
Directory /workspace/11.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/17.flash_ctrl_invalid_op.3743928314
Short name T403
Test name
Test status
Simulation time 1889900800 ps
CPU time 78.62 seconds
Started Mar 24 02:26:37 PM PDT 24
Finished Mar 24 02:27:56 PM PDT 24
Peak memory 260764 kb
Host smart-7aabb103-19bd-4ce8-a4f1-9e20b94585ca
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743928314 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.3
743928314
Directory /workspace/17.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.854353126
Short name T253
Test name
Test status
Simulation time 23965400 ps
CPU time 13.6 seconds
Started Mar 24 12:38:43 PM PDT 24
Finished Mar 24 12:38:57 PM PDT 24
Peak memory 263556 kb
Host smart-12c34a4c-be9d-44b6-84cd-b659f07ddc57
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854353126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flas
h_ctrl_mem_partial_access.854353126
Directory /workspace/1.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd_slow_flash.2609293758
Short name T186
Test name
Test status
Simulation time 39031387700 ps
CPU time 282.67 seconds
Started Mar 24 02:21:18 PM PDT 24
Finished Mar 24 02:26:01 PM PDT 24
Peak memory 294712 kb
Host smart-9f049c5a-8a2d-494a-a4a0-50a01e566e0e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609293758 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd_slow_flash.2609293758
Directory /workspace/5.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_intg.3084404931
Short name T201
Test name
Test status
Simulation time 680402700 ps
CPU time 32.92 seconds
Started Mar 24 02:17:57 PM PDT 24
Finished Mar 24 02:18:30 PM PDT 24
Peak memory 279856 kb
Host smart-df097363-dd10-4fe6-ac96-d95808785362
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084404931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_rd_intg.3084404931
Directory /workspace/2.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.3585283786
Short name T268
Test name
Test status
Simulation time 54214200 ps
CPU time 18.53 seconds
Started Mar 24 12:39:15 PM PDT 24
Finished Mar 24 12:39:34 PM PDT 24
Peak memory 263636 kb
Host smart-64a400aa-a381-4581-bf31-651059cbfcb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585283786 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.
3585283786
Directory /workspace/19.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd.1253610695
Short name T64
Test name
Test status
Simulation time 1903640200 ps
CPU time 157.55 seconds
Started Mar 24 02:29:57 PM PDT 24
Finished Mar 24 02:32:35 PM PDT 24
Peak memory 293748 kb
Host smart-b4558202-e782-49b1-a980-a3a7e36f31e4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253610695 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fla
sh_ctrl_intr_rd.1253610695
Directory /workspace/38.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.3609952671
Short name T354
Test name
Test status
Simulation time 45699800 ps
CPU time 13.24 seconds
Started Mar 24 12:38:29 PM PDT 24
Finished Mar 24 12:38:43 PM PDT 24
Peak memory 262092 kb
Host smart-a85d7d47-1ce0-4a17-8f28-8b44a9ec5502
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609952671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.3
609952671
Directory /workspace/3.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/0.flash_ctrl_oversize_error.1247370183
Short name T71
Test name
Test status
Simulation time 3934866200 ps
CPU time 218.65 seconds
Started Mar 24 02:14:35 PM PDT 24
Finished Mar 24 02:18:13 PM PDT 24
Peak memory 281424 kb
Host smart-46ab7c5c-a29e-479d-a4f6-d588f7c80a10
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247370183 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_oversize_error.1247370183
Directory /workspace/0.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_rma_reset.1663637530
Short name T11
Test name
Test status
Simulation time 90155961500 ps
CPU time 898.64 seconds
Started Mar 24 02:22:18 PM PDT 24
Finished Mar 24 02:37:17 PM PDT 24
Peak memory 262620 kb
Host smart-1062b008-4dc3-4daf-b51d-370ea98b6974
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663637530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.flash_ctrl_hw_rma_reset.1663637530
Directory /workspace/7.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/46.flash_ctrl_disable.1821327314
Short name T171
Test name
Test status
Simulation time 22315600 ps
CPU time 20.77 seconds
Started Mar 24 02:30:33 PM PDT 24
Finished Mar 24 02:30:54 PM PDT 24
Peak memory 265088 kb
Host smart-21b27a9d-5287-45a2-a9ea-07627d3755d9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821327314 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.flash_ctrl_disable.1821327314
Directory /workspace/46.flash_ctrl_disable/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd.2166911040
Short name T28
Test name
Test status
Simulation time 2524612200 ps
CPU time 149.97 seconds
Started Mar 24 02:29:28 PM PDT 24
Finished Mar 24 02:31:58 PM PDT 24
Peak memory 292892 kb
Host smart-ac1e014d-1240-4472-b4f1-14b9b02262b8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166911040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fla
sh_ctrl_intr_rd.2166911040
Directory /workspace/33.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict.2252128954
Short name T37
Test name
Test status
Simulation time 70541000 ps
CPU time 30.9 seconds
Started Mar 24 02:20:21 PM PDT 24
Finished Mar 24 02:20:52 PM PDT 24
Peak memory 267388 kb
Host smart-8cb184c1-b3ed-47dc-b117-3175f08bb4ae
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252128954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_rw_evict.2252128954
Directory /workspace/4.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.2016581807
Short name T271
Test name
Test status
Simulation time 487340000 ps
CPU time 902.29 seconds
Started Mar 24 12:38:49 PM PDT 24
Finished Mar 24 12:53:52 PM PDT 24
Peak memory 263724 kb
Host smart-efe2b39f-8ebc-4d58-97d8-ced56ad06ab0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016581807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctr
l_tl_intg_err.2016581807
Directory /workspace/13.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict.3951387013
Short name T337
Test name
Test status
Simulation time 289380500 ps
CPU time 35.84 seconds
Started Mar 24 02:24:36 PM PDT 24
Finished Mar 24 02:25:12 PM PDT 24
Peak memory 273260 kb
Host smart-22ca252a-2e44-42f7-95a4-4d20fc2d304c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951387013 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl
ash_ctrl_rw_evict.3951387013
Directory /workspace/11.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_read_seed_err.382968504
Short name T350
Test name
Test status
Simulation time 16110100 ps
CPU time 13.9 seconds
Started Mar 24 02:25:58 PM PDT 24
Finished Mar 24 02:26:12 PM PDT 24
Peak memory 264096 kb
Host smart-8bfa238d-2787-4ff4-b6b7-477ac2cf8b8b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382968504 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_read_seed_err.382968504
Directory /workspace/14.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_re_evict.2617875889
Short name T338
Test name
Test status
Simulation time 1471477500 ps
CPU time 40.09 seconds
Started Mar 24 02:25:52 PM PDT 24
Finished Mar 24 02:26:32 PM PDT 24
Peak memory 267012 kb
Host smart-91b868af-fb11-488e-8e4e-4c6fed2af2d7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617875889 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_re_evict.2617875889
Directory /workspace/14.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_fs_sup.925890816
Short name T92
Test name
Test status
Simulation time 1913698700 ps
CPU time 38.92 seconds
Started Mar 24 02:19:19 PM PDT 24
Finished Mar 24 02:19:58 PM PDT 24
Peak memory 276348 kb
Host smart-8c891f53-3b36-461f-85f7-89ae4d1e88cd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925890816 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_fs_sup.925890816
Directory /workspace/3.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/8.flash_ctrl_lcmgr_intg.2717241733
Short name T609
Test name
Test status
Simulation time 58299200 ps
CPU time 14.36 seconds
Started Mar 24 02:23:17 PM PDT 24
Finished Mar 24 02:23:32 PM PDT 24
Peak memory 264968 kb
Host smart-9a71730a-2452-4ce6-91ea-c771fe61da45
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717241733 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.flash_ctrl_lcmgr_intg.2717241733
Directory /workspace/8.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3043931080
Short name T260
Test name
Test status
Simulation time 39071000 ps
CPU time 17.69 seconds
Started Mar 24 12:38:38 PM PDT 24
Finished Mar 24 12:38:55 PM PDT 24
Peak memory 261684 kb
Host smart-79a91a9a-5147-4886-aff3-c9cfc0ddf450
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043931080 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.flash_ctrl_same_csr_outstanding.3043931080
Directory /workspace/0.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_read_seed_err.1180974679
Short name T660
Test name
Test status
Simulation time 16073400 ps
CPU time 13.73 seconds
Started Mar 24 02:22:41 PM PDT 24
Finished Mar 24 02:22:55 PM PDT 24
Peak memory 258288 kb
Host smart-ffb8f9a0-430b-4923-a5c4-535b12a87d79
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180974679 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_read_seed_err.1180974679
Directory /workspace/7.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_cm.4616934
Short name T180
Test name
Test status
Simulation time 2866795700 ps
CPU time 4759.68 seconds
Started Mar 24 02:14:53 PM PDT 24
Finished Mar 24 03:34:15 PM PDT 24
Peak memory 287064 kb
Host smart-99c34d43-d8ad-43cc-aa5d-4f4defbab15d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4616934 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.4616934
Directory /workspace/0.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro.2094846015
Short name T402
Test name
Test status
Simulation time 906821200 ps
CPU time 108.96 seconds
Started Mar 24 02:14:23 PM PDT 24
Finished Mar 24 02:16:13 PM PDT 24
Peak memory 280812 kb
Host smart-2f842c04-4e93-47ed-8c95-9ccac5a95126
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094846015 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_ro.2094846015
Directory /workspace/0.flash_ctrl_ro/latest

Test location /workspace/coverage/default/49.flash_ctrl_connect.1288716626
Short name T177
Test name
Test status
Simulation time 42195600 ps
CPU time 15.81 seconds
Started Mar 24 02:30:51 PM PDT 24
Finished Mar 24 02:31:07 PM PDT 24
Peak memory 275208 kb
Host smart-1d8f1427-eeb3-4874-bcc1-8dde7622fec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288716626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.1288716626
Directory /workspace/49.flash_ctrl_connect/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_serr.2644911952
Short name T168
Test name
Test status
Simulation time 2291886200 ps
CPU time 126.43 seconds
Started Mar 24 02:16:03 PM PDT 24
Finished Mar 24 02:18:10 PM PDT 24
Peak memory 294304 kb
Host smart-aae1a505-72b7-4b58-9b8f-a50e2d4d28bc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644911952 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_ro_serr.2644911952
Directory /workspace/1.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_type.578520051
Short name T158
Test name
Test status
Simulation time 1427392800 ps
CPU time 1855.59 seconds
Started Mar 24 02:13:57 PM PDT 24
Finished Mar 24 02:44:53 PM PDT 24
Peak memory 264748 kb
Host smart-04ed785e-8af5-4e2c-9b6f-2aae3c4c29e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578520051 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_type.578520051
Directory /workspace/0.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_host_grant_err.4050917693
Short name T51
Test name
Test status
Simulation time 79510000 ps
CPU time 14.08 seconds
Started Mar 24 02:15:21 PM PDT 24
Finished Mar 24 02:15:35 PM PDT 24
Peak memory 264972 kb
Host smart-c3d0c193-ee62-4ffb-8067-b1dcc762a48a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050917693 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.4050917693
Directory /workspace/0.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb_redun.4238068648
Short name T72
Test name
Test status
Simulation time 774805300 ps
CPU time 42.25 seconds
Started Mar 24 02:20:38 PM PDT 24
Finished Mar 24 02:21:20 PM PDT 24
Peak memory 264300 kb
Host smart-d64cd4f9-f4ef-4011-9801-0a316474837a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238068648 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.4238068648
Directory /workspace/4.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.2557622786
Short name T293
Test name
Test status
Simulation time 10019708400 ps
CPU time 81.86 seconds
Started Mar 24 02:15:29 PM PDT 24
Finished Mar 24 02:16:51 PM PDT 24
Peak memory 291736 kb
Host smart-291b338f-7611-41e1-a8f9-8317dff4d4a4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557622786 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.2557622786
Directory /workspace/0.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.477693391
Short name T278
Test name
Test status
Simulation time 822269000 ps
CPU time 890.76 seconds
Started Mar 24 12:38:53 PM PDT 24
Finished Mar 24 12:53:44 PM PDT 24
Peak memory 261168 kb
Host smart-dd0dc3fc-add3-4a12-bc82-671411c0ac2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477693391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl
_tl_intg_err.477693391
Directory /workspace/16.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.114357576
Short name T244
Test name
Test status
Simulation time 369808400 ps
CPU time 744.26 seconds
Started Mar 24 12:38:36 PM PDT 24
Finished Mar 24 12:51:00 PM PDT 24
Peak memory 263704 kb
Host smart-a8c941bd-7905-4fc5-90dd-43df65f0ef6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114357576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_
tl_intg_err.114357576
Directory /workspace/3.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_info_access.3063890934
Short name T399
Test name
Test status
Simulation time 408957100 ps
CPU time 58.44 seconds
Started Mar 24 02:15:04 PM PDT 24
Finished Mar 24 02:16:02 PM PDT 24
Peak memory 263052 kb
Host smart-9ae170bc-31c6-4887-887e-9697998f6e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063890934 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.3063890934
Directory /workspace/0.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/10.flash_ctrl_sec_info_access.283747616
Short name T383
Test name
Test status
Simulation time 1611040100 ps
CPU time 66.38 seconds
Started Mar 24 02:24:21 PM PDT 24
Finished Mar 24 02:25:27 PM PDT 24
Peak memory 264792 kb
Host smart-b8f50d0c-60c5-4c06-9f09-bd2e479c3b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283747616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.283747616
Directory /workspace/10.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/12.flash_ctrl_sec_info_access.3043407095
Short name T384
Test name
Test status
Simulation time 23339343300 ps
CPU time 74.52 seconds
Started Mar 24 02:25:15 PM PDT 24
Finished Mar 24 02:26:29 PM PDT 24
Peak memory 262888 kb
Host smart-e7be6d5f-bc42-48c4-920f-87a187e5f885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043407095 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.3043407095
Directory /workspace/12.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.470260397
Short name T566
Test name
Test status
Simulation time 93007800 ps
CPU time 30.69 seconds
Started Mar 24 02:26:12 PM PDT 24
Finished Mar 24 02:26:42 PM PDT 24
Peak memory 273288 kb
Host smart-c50f2e70-40ca-499c-a7f6-6e2a8e915145
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470260397 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict_all_en.470260397
Directory /workspace/15.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/16.flash_ctrl_sec_info_access.3991849372
Short name T394
Test name
Test status
Simulation time 5109388400 ps
CPU time 68.83 seconds
Started Mar 24 02:26:27 PM PDT 24
Finished Mar 24 02:27:36 PM PDT 24
Peak memory 262732 kb
Host smart-6a905c78-3ed1-40d2-b749-8d8c6138c1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991849372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.3991849372
Directory /workspace/16.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/55.flash_ctrl_otp_reset.2491585442
Short name T889
Test name
Test status
Simulation time 44938500 ps
CPU time 134.19 seconds
Started Mar 24 02:30:56 PM PDT 24
Finished Mar 24 02:33:10 PM PDT 24
Peak memory 264184 kb
Host smart-665e2f25-0ebb-4803-b98d-645b66d68b34
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491585442 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_o
tp_reset.2491585442
Directory /workspace/55.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_config_regwen.1018227627
Short name T100
Test name
Test status
Simulation time 110883100 ps
CPU time 14.52 seconds
Started Mar 24 02:18:09 PM PDT 24
Finished Mar 24 02:18:24 PM PDT 24
Peak memory 261648 kb
Host smart-3f2aeb7b-4b9e-4d85-8556-ef6b3e27eee0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018227627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.flash_ctrl_config_regwen.1018227627
Directory /workspace/2.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/0.flash_ctrl_access_after_disable.4275620646
Short name T45
Test name
Test status
Simulation time 128437700 ps
CPU time 13.63 seconds
Started Mar 24 02:15:18 PM PDT 24
Finished Mar 24 02:15:32 PM PDT 24
Peak memory 261552 kb
Host smart-d17a438d-856c-4c23-ad85-f3fb02b737c7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275620646 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.4275620646
Directory /workspace/0.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_ack_consistency.3453633652
Short name T66
Test name
Test status
Simulation time 44924800 ps
CPU time 13.83 seconds
Started Mar 24 02:16:51 PM PDT 24
Finished Mar 24 02:17:05 PM PDT 24
Peak memory 276592 kb
Host smart-8ca9252b-1c30-4e2d-a44f-65e0cff146c3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3453633652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.3453633652
Directory /workspace/1.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/11.flash_ctrl_disable.4080087164
Short name T2
Test name
Test status
Simulation time 36842600 ps
CPU time 21.87 seconds
Started Mar 24 02:24:42 PM PDT 24
Finished Mar 24 02:25:05 PM PDT 24
Peak memory 264844 kb
Host smart-1d240010-c1d8-4e52-a769-2523b5f37e3d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080087164 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_disable.4080087164
Directory /workspace/11.flash_ctrl_disable/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_dir_rd.3491157911
Short name T955
Test name
Test status
Simulation time 66375000 ps
CPU time 89.15 seconds
Started Mar 24 02:18:30 PM PDT 24
Finished Mar 24 02:20:00 PM PDT 24
Peak memory 264772 kb
Host smart-7e004dab-81cf-4c72-b63a-7db8085166a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3491157911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.3491157911
Directory /workspace/3.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.120965073
Short name T347
Test name
Test status
Simulation time 16243400 ps
CPU time 13.67 seconds
Started Mar 24 12:39:05 PM PDT 24
Finished Mar 24 12:39:20 PM PDT 24
Peak memory 262748 kb
Host smart-bbe08031-729b-4f72-bdf0-ffb60c0b3d0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120965073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.120965073
Directory /workspace/14.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.4220467294
Short name T361
Test name
Test status
Simulation time 2009387800 ps
CPU time 384.47 seconds
Started Mar 24 12:38:47 PM PDT 24
Finished Mar 24 12:45:11 PM PDT 24
Peak memory 263692 kb
Host smart-3ee48d56-ac85-443a-aab9-13202f83cd6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220467294 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctr
l_tl_intg_err.4220467294
Directory /workspace/17.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_disable.1530998396
Short name T57
Test name
Test status
Simulation time 15654300 ps
CPU time 20.42 seconds
Started Mar 24 02:14:53 PM PDT 24
Finished Mar 24 02:15:15 PM PDT 24
Peak memory 273592 kb
Host smart-e6915f9d-57fb-42af-9623-e104a87a1919
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530998396 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_disable.1530998396
Directory /workspace/0.flash_ctrl_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_disable.1379488124
Short name T662
Test name
Test status
Simulation time 15398900 ps
CPU time 20.5 seconds
Started Mar 24 02:16:33 PM PDT 24
Finished Mar 24 02:16:53 PM PDT 24
Peak memory 273172 kb
Host smart-8bdc7e10-b05b-4e9f-8edf-fb62fa348c9b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379488124 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_disable.1379488124
Directory /workspace/1.flash_ctrl_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_info_access.4102025926
Short name T401
Test name
Test status
Simulation time 6219097200 ps
CPU time 76.2 seconds
Started Mar 24 02:16:38 PM PDT 24
Finished Mar 24 02:17:54 PM PDT 24
Peak memory 262696 kb
Host smart-bed648be-4afe-4161-96bb-4c77ec6564b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102025926 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.4102025926
Directory /workspace/1.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict_all_en.1245126239
Short name T335
Test name
Test status
Simulation time 29140300 ps
CPU time 29.12 seconds
Started Mar 24 02:25:06 PM PDT 24
Finished Mar 24 02:25:35 PM PDT 24
Peak memory 273608 kb
Host smart-e6c6b94a-ea66-4ada-8e4e-3ee8fce69038
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245126239 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict_all_en.1245126239
Directory /workspace/12.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/17.flash_ctrl_disable.2924663259
Short name T996
Test name
Test status
Simulation time 10986200 ps
CPU time 22.56 seconds
Started Mar 24 02:26:51 PM PDT 24
Finished Mar 24 02:27:14 PM PDT 24
Peak memory 273168 kb
Host smart-72247a44-ae0c-4fa3-a4ff-ac2595a58d83
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924663259 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_disable.2924663259
Directory /workspace/17.flash_ctrl_disable/latest

Test location /workspace/coverage/default/19.flash_ctrl_disable.3172080189
Short name T788
Test name
Test status
Simulation time 32345000 ps
CPU time 21.86 seconds
Started Mar 24 02:27:36 PM PDT 24
Finished Mar 24 02:27:58 PM PDT 24
Peak memory 264980 kb
Host smart-b2d8029b-33ba-4654-bff7-3742ce4e31b5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172080189 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.flash_ctrl_disable.3172080189
Directory /workspace/19.flash_ctrl_disable/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd_slow_flash.1478332700
Short name T328
Test name
Test status
Simulation time 131923026400 ps
CPU time 226.78 seconds
Started Mar 24 02:27:42 PM PDT 24
Finished Mar 24 02:31:29 PM PDT 24
Peak memory 284696 kb
Host smart-f0ac6e7f-dd05-48f3-b519-1ee26dd79b9a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478332700 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd_slow_flash.1478332700
Directory /workspace/20.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict.23561426
Short name T334
Test name
Test status
Simulation time 31576600 ps
CPU time 30.33 seconds
Started Mar 24 02:28:46 PM PDT 24
Finished Mar 24 02:29:17 PM PDT 24
Peak memory 267256 kb
Host smart-821354ba-da9e-41d0-8052-1cab9c88a318
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23561426 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flas
h_ctrl_rw_evict.23561426
Directory /workspace/27.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/42.flash_ctrl_sec_info_access.2848163575
Short name T27
Test name
Test status
Simulation time 4581492300 ps
CPU time 66.69 seconds
Started Mar 24 02:30:20 PM PDT 24
Finished Mar 24 02:31:29 PM PDT 24
Peak memory 264232 kb
Host smart-29aa624a-589e-497e-9185-cf1ecc0ad010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848163575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.2848163575
Directory /workspace/42.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/47.flash_ctrl_disable.2815495034
Short name T88
Test name
Test status
Simulation time 33876200 ps
CPU time 22.03 seconds
Started Mar 24 02:30:39 PM PDT 24
Finished Mar 24 02:31:02 PM PDT 24
Peak memory 273908 kb
Host smart-193607fc-3f69-49aa-8628-8d4681f196fd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815495034 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.flash_ctrl_disable.2815495034
Directory /workspace/47.flash_ctrl_disable/latest

Test location /workspace/coverage/default/10.flash_ctrl_rand_ops.1651552954
Short name T109
Test name
Test status
Simulation time 1367774500 ps
CPU time 378.64 seconds
Started Mar 24 02:24:07 PM PDT 24
Finished Mar 24 02:30:26 PM PDT 24
Peak memory 281204 kb
Host smart-445c60ff-fdcd-474c-8360-3d376c61ed74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651552954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.1651552954
Directory /workspace/10.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.1734138577
Short name T1144
Test name
Test status
Simulation time 40285600 ps
CPU time 16.87 seconds
Started Mar 24 12:38:46 PM PDT 24
Finished Mar 24 12:39:03 PM PDT 24
Peak memory 263636 kb
Host smart-7388ad98-1fe7-41a8-b583-2a9fed6c8f1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734138577 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.1
734138577
Directory /workspace/0.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr_slow_flash.2418862041
Short name T453
Test name
Test status
Simulation time 36149386300 ps
CPU time 299.25 seconds
Started Mar 24 02:14:49 PM PDT 24
Finished Mar 24 02:19:48 PM PDT 24
Peak memory 261456 kb
Host smart-5448dd2a-d24a-4b7e-9cda-46bdb1680b80
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241
8862041 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.2418862041
Directory /workspace/0.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_rma_reset.2022663851
Short name T136
Test name
Test status
Simulation time 80151306300 ps
CPU time 942.35 seconds
Started Mar 24 02:25:39 PM PDT 24
Finished Mar 24 02:41:21 PM PDT 24
Peak memory 263128 kb
Host smart-37658aa0-10d1-489e-9783-fb1b7234de77
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022663851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.flash_ctrl_hw_rma_reset.2022663851
Directory /workspace/14.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.694803514
Short name T312
Test name
Test status
Simulation time 291353500 ps
CPU time 17.79 seconds
Started Mar 24 12:38:52 PM PDT 24
Finished Mar 24 12:39:10 PM PDT 24
Peak memory 271868 kb
Host smart-df0e4ba0-48bc-4237-a61b-7ac09458c391
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694803514 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.694803514
Directory /workspace/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_mp.4145510393
Short name T183
Test name
Test status
Simulation time 3326348200 ps
CPU time 2164.17 seconds
Started Mar 24 02:13:58 PM PDT 24
Finished Mar 24 02:50:02 PM PDT 24
Peak memory 264164 kb
Host smart-379c52b5-93b4-46c9-9da2-1487c031f25d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145510393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_err
or_mp.4145510393
Directory /workspace/0.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_win.3414789311
Short name T749
Test name
Test status
Simulation time 394336200 ps
CPU time 973.48 seconds
Started Mar 24 02:13:58 PM PDT 24
Finished Mar 24 02:30:12 PM PDT 24
Peak memory 273108 kb
Host smart-cfad35e6-5baa-4d71-b19a-618ddf33edc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414789311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.3414789311
Directory /workspace/0.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_buff_evict.1452190222
Short name T56
Test name
Test status
Simulation time 310713600 ps
CPU time 101.94 seconds
Started Mar 24 02:13:31 PM PDT 24
Finished Mar 24 02:15:13 PM PDT 24
Peak memory 264816 kb
Host smart-2f5ec191-84bd-4693-a172-63c9220ade47
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1452190222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.1452190222
Directory /workspace/0.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_wr_intg.88685814
Short name T8
Test name
Test status
Simulation time 50888700 ps
CPU time 14.58 seconds
Started Mar 24 02:15:12 PM PDT 24
Finished Mar 24 02:15:26 PM PDT 24
Peak memory 264992 kb
Host smart-6b1154ad-fa8a-4f59-96d1-7a4a346278c9
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88685814 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wr_intg.88685814
Directory /workspace/0.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_access_after_disable.3611857349
Short name T44
Test name
Test status
Simulation time 21876500 ps
CPU time 13.61 seconds
Started Mar 24 02:16:44 PM PDT 24
Finished Mar 24 02:16:57 PM PDT 24
Peak memory 265048 kb
Host smart-a68500df-d8d8-4c4a-9572-28544e7d3c5b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611857349 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.3611857349
Directory /workspace/1.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_ctrl_arb.1204633884
Short name T176
Test name
Test status
Simulation time 312323956600 ps
CPU time 2128.95 seconds
Started Mar 24 02:15:55 PM PDT 24
Finished Mar 24 02:51:25 PM PDT 24
Peak memory 264652 kb
Host smart-d9f0961f-ec70-41bd-9fa6-13b16687d991
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204633884 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.flash_ctrl_host_ctrl_arb.1204633884
Directory /workspace/1.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.2417950888
Short name T304
Test name
Test status
Simulation time 2551890300 ps
CPU time 35.29 seconds
Started Mar 24 12:38:25 PM PDT 24
Finished Mar 24 12:39:00 PM PDT 24
Peak memory 259916 kb
Host smart-e71d05d8-d005-4ac0-8303-9d97fcb68a53
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417950888 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_aliasing.2417950888
Directory /workspace/0.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.620726252
Short name T1143
Test name
Test status
Simulation time 2190042100 ps
CPU time 67.35 seconds
Started Mar 24 12:38:42 PM PDT 24
Finished Mar 24 12:39:54 PM PDT 24
Peak memory 259976 kb
Host smart-486ab884-5ab4-4f42-a101-3817e56bfb86
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620726252 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.flash_ctrl_csr_bit_bash.620726252
Directory /workspace/0.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1176349590
Short name T175
Test name
Test status
Simulation time 597324900 ps
CPU time 46.18 seconds
Started Mar 24 12:38:35 PM PDT 24
Finished Mar 24 12:39:22 PM PDT 24
Peak memory 259964 kb
Host smart-eeb7367a-ee93-408a-967f-ca982f802c9a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176349590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_hw_reset.1176349590
Directory /workspace/0.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.4091421422
Short name T1099
Test name
Test status
Simulation time 180070500 ps
CPU time 14.93 seconds
Started Mar 24 12:38:37 PM PDT 24
Finished Mar 24 12:38:52 PM PDT 24
Peak memory 262780 kb
Host smart-25ed43b6-6369-4502-872c-4e90c95d1fa9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091421422 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.4091421422
Directory /workspace/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.2993835081
Short name T1178
Test name
Test status
Simulation time 962672100 ps
CPU time 17.71 seconds
Started Mar 24 12:38:39 PM PDT 24
Finished Mar 24 12:38:56 PM PDT 24
Peak memory 259984 kb
Host smart-a8d9b902-0933-44d7-a1bd-a3ecc4266b81
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993835081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_csr_rw.2993835081
Directory /workspace/0.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.3825008833
Short name T1189
Test name
Test status
Simulation time 56452800 ps
CPU time 13.32 seconds
Started Mar 24 12:38:35 PM PDT 24
Finished Mar 24 12:38:48 PM PDT 24
Peak memory 261936 kb
Host smart-d9939f02-54df-43a5-aeca-74d9a5e15f9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825008833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.3
825008833
Directory /workspace/0.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.3681866032
Short name T250
Test name
Test status
Simulation time 45189200 ps
CPU time 13.35 seconds
Started Mar 24 12:38:34 PM PDT 24
Finished Mar 24 12:38:47 PM PDT 24
Peak memory 263180 kb
Host smart-e406c388-af91-4fee-a035-9e8859efa85c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681866032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_mem_partial_access.3681866032
Directory /workspace/0.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2476144138
Short name T1067
Test name
Test status
Simulation time 41927000 ps
CPU time 13.28 seconds
Started Mar 24 12:38:36 PM PDT 24
Finished Mar 24 12:38:50 PM PDT 24
Peak memory 262180 kb
Host smart-6f9f5365-79ee-4c80-ae4e-695fce250e1c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476144138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_me
m_walk.2476144138
Directory /workspace/0.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.1154259727
Short name T1059
Test name
Test status
Simulation time 13274700 ps
CPU time 15.68 seconds
Started Mar 24 12:38:30 PM PDT 24
Finished Mar 24 12:38:46 PM PDT 24
Peak memory 259852 kb
Host smart-6c8bca7b-7003-405b-b444-7b1a6ccdf898
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154259727 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors.1154259727
Directory /workspace/0.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.3501694758
Short name T1173
Test name
Test status
Simulation time 25965400 ps
CPU time 15.71 seconds
Started Mar 24 12:38:56 PM PDT 24
Finished Mar 24 12:39:12 PM PDT 24
Peak memory 259948 kb
Host smart-e64a292a-42c9-42e9-aead-c0fac2494010
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501694758 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors_with_csr_rw.3501694758
Directory /workspace/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.265283267
Short name T302
Test name
Test status
Simulation time 11607017600 ps
CPU time 70.39 seconds
Started Mar 24 12:38:33 PM PDT 24
Finished Mar 24 12:39:44 PM PDT 24
Peak memory 259928 kb
Host smart-521fc9a6-4b06-4395-8fbd-3a216fa52d78
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265283267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.flash_ctrl_csr_aliasing.265283267
Directory /workspace/1.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.2405836130
Short name T1151
Test name
Test status
Simulation time 10514592000 ps
CPU time 64.68 seconds
Started Mar 24 12:38:45 PM PDT 24
Finished Mar 24 12:39:50 PM PDT 24
Peak memory 262304 kb
Host smart-50113ceb-79ba-4107-ab0c-022d2db451d6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405836130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_bit_bash.2405836130
Directory /workspace/1.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.3721344945
Short name T227
Test name
Test status
Simulation time 76105500 ps
CPU time 38.83 seconds
Started Mar 24 12:38:42 PM PDT 24
Finished Mar 24 12:39:21 PM PDT 24
Peak memory 259964 kb
Host smart-8241bc91-65d3-46e1-b60f-f33e84a79c71
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721344945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_hw_reset.3721344945
Directory /workspace/1.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.231697402
Short name T1194
Test name
Test status
Simulation time 185049600 ps
CPU time 17.4 seconds
Started Mar 24 12:38:37 PM PDT 24
Finished Mar 24 12:38:54 PM PDT 24
Peak memory 263732 kb
Host smart-665a5609-0846-406c-abde-721e110e4467
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231697402 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.231697402
Directory /workspace/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.388544475
Short name T261
Test name
Test status
Simulation time 59617700 ps
CPU time 17.41 seconds
Started Mar 24 12:38:41 PM PDT 24
Finished Mar 24 12:38:59 PM PDT 24
Peak memory 259960 kb
Host smart-2b783577-e5fd-4d28-a556-b363ac41d625
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388544475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 1.flash_ctrl_csr_rw.388544475
Directory /workspace/1.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.1123149361
Short name T1104
Test name
Test status
Simulation time 15841600 ps
CPU time 13.52 seconds
Started Mar 24 12:38:36 PM PDT 24
Finished Mar 24 12:38:50 PM PDT 24
Peak memory 262144 kb
Host smart-f9a379e2-4626-4864-9a39-565f3d36e397
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123149361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.1
123149361
Directory /workspace/1.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.3849943221
Short name T1069
Test name
Test status
Simulation time 19403800 ps
CPU time 13.31 seconds
Started Mar 24 12:38:41 PM PDT 24
Finished Mar 24 12:38:54 PM PDT 24
Peak memory 262232 kb
Host smart-cb440c28-cacd-4652-ae31-2306ff9b491a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849943221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_me
m_walk.3849943221
Directory /workspace/1.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2204313397
Short name T313
Test name
Test status
Simulation time 214258700 ps
CPU time 35.1 seconds
Started Mar 24 12:38:35 PM PDT 24
Finished Mar 24 12:39:10 PM PDT 24
Peak memory 263604 kb
Host smart-f20b4352-b85f-4962-8510-03b07304eaa0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204313397 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.flash_ctrl_same_csr_outstanding.2204313397
Directory /workspace/1.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.3888061795
Short name T1174
Test name
Test status
Simulation time 14726100 ps
CPU time 13.17 seconds
Started Mar 24 12:38:44 PM PDT 24
Finished Mar 24 12:38:58 PM PDT 24
Peak memory 259884 kb
Host smart-33cb9959-25e9-4776-b8d7-0f58c84edae6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888061795 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors.3888061795
Directory /workspace/1.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.2101122053
Short name T1183
Test name
Test status
Simulation time 36318500 ps
CPU time 13.12 seconds
Started Mar 24 12:38:57 PM PDT 24
Finished Mar 24 12:39:10 PM PDT 24
Peak memory 259768 kb
Host smart-6f9a07fa-93b2-45e0-b55b-432ca8f6b8bf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101122053 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors_with_csr_rw.2101122053
Directory /workspace/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.147298432
Short name T1167
Test name
Test status
Simulation time 898015800 ps
CPU time 458.65 seconds
Started Mar 24 12:38:37 PM PDT 24
Finished Mar 24 12:46:21 PM PDT 24
Peak memory 261116 kb
Host smart-a23a98ae-9891-4553-89d2-03bca8a7108d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147298432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_
tl_intg_err.147298432
Directory /workspace/1.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3407174785
Short name T1166
Test name
Test status
Simulation time 25258400 ps
CPU time 15.03 seconds
Started Mar 24 12:38:40 PM PDT 24
Finished Mar 24 12:38:55 PM PDT 24
Peak memory 271948 kb
Host smart-41d72d5a-9137-444f-a46a-ec91fc318bdc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407174785 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.3407174785
Directory /workspace/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.263062465
Short name T1176
Test name
Test status
Simulation time 116343400 ps
CPU time 17.36 seconds
Started Mar 24 12:38:30 PM PDT 24
Finished Mar 24 12:38:47 PM PDT 24
Peak memory 259932 kb
Host smart-6511ef4f-b35c-45e7-8065-317b10e15de3
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263062465 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 10.flash_ctrl_csr_rw.263062465
Directory /workspace/10.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.1083557208
Short name T1093
Test name
Test status
Simulation time 55739800 ps
CPU time 13.3 seconds
Started Mar 24 12:38:41 PM PDT 24
Finished Mar 24 12:38:55 PM PDT 24
Peak memory 262324 kb
Host smart-e2f3466e-dfea-475e-b52f-3dcb1cb13b36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083557208 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.
1083557208
Directory /workspace/10.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.2111055469
Short name T1118
Test name
Test status
Simulation time 578438600 ps
CPU time 34.25 seconds
Started Mar 24 12:38:44 PM PDT 24
Finished Mar 24 12:39:18 PM PDT 24
Peak memory 260016 kb
Host smart-c7b3bb2c-81af-4caf-b236-fd875e9e25dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111055469 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.flash_ctrl_same_csr_outstanding.2111055469
Directory /workspace/10.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.4150308768
Short name T1066
Test name
Test status
Simulation time 27458200 ps
CPU time 13.22 seconds
Started Mar 24 12:38:48 PM PDT 24
Finished Mar 24 12:39:02 PM PDT 24
Peak memory 259856 kb
Host smart-9d359fc9-96fc-41a2-8937-f9b3fd63b6eb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150308768 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors.4150308768
Directory /workspace/10.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1856500301
Short name T1064
Test name
Test status
Simulation time 42406600 ps
CPU time 13.02 seconds
Started Mar 24 12:38:47 PM PDT 24
Finished Mar 24 12:39:00 PM PDT 24
Peak memory 259864 kb
Host smart-e246b750-5570-4ad5-8bb8-c329b5a524f0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856500301 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors_with_csr_rw.1856500301
Directory /workspace/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.809863742
Short name T273
Test name
Test status
Simulation time 36899500 ps
CPU time 16.65 seconds
Started Mar 24 12:38:41 PM PDT 24
Finished Mar 24 12:38:58 PM PDT 24
Peak memory 263644 kb
Host smart-9415bece-684f-4812-9f91-a679d3cd854a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809863742 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.809863742
Directory /workspace/10.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.3583994988
Short name T362
Test name
Test status
Simulation time 670070000 ps
CPU time 891.76 seconds
Started Mar 24 12:38:45 PM PDT 24
Finished Mar 24 12:53:42 PM PDT 24
Peak memory 261560 kb
Host smart-c9f2e827-45b8-4e7a-b567-4245be85b683
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583994988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctr
l_tl_intg_err.3583994988
Directory /workspace/10.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.935285231
Short name T307
Test name
Test status
Simulation time 41571500 ps
CPU time 16.67 seconds
Started Mar 24 12:38:50 PM PDT 24
Finished Mar 24 12:39:07 PM PDT 24
Peak memory 263572 kb
Host smart-c901c4e7-af60-4ffc-ade6-75e951cbca5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935285231 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.flash_ctrl_csr_rw.935285231
Directory /workspace/11.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.302744944
Short name T1071
Test name
Test status
Simulation time 123257400 ps
CPU time 13.4 seconds
Started Mar 24 12:39:13 PM PDT 24
Finished Mar 24 12:39:26 PM PDT 24
Peak memory 262176 kb
Host smart-16916427-9b1e-49e0-8107-d57fb9dff693
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302744944 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.302744944
Directory /workspace/11.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.311734524
Short name T303
Test name
Test status
Simulation time 245927600 ps
CPU time 17.93 seconds
Started Mar 24 12:38:54 PM PDT 24
Finished Mar 24 12:39:12 PM PDT 24
Peak memory 261948 kb
Host smart-f79d913f-42d6-4d15-b53f-71e2c9f7b285
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311734524 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.flash_ctrl_same_csr_outstanding.311734524
Directory /workspace/11.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3566964485
Short name T1134
Test name
Test status
Simulation time 28320000 ps
CPU time 13.66 seconds
Started Mar 24 12:38:47 PM PDT 24
Finished Mar 24 12:39:01 PM PDT 24
Peak memory 259916 kb
Host smart-bdbe8045-258b-4935-ae69-52b363d5e5df
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566964485 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors.3566964485
Directory /workspace/11.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.4046967523
Short name T1063
Test name
Test status
Simulation time 14616500 ps
CPU time 15.78 seconds
Started Mar 24 12:38:52 PM PDT 24
Finished Mar 24 12:39:09 PM PDT 24
Peak memory 260012 kb
Host smart-4aac589d-74ef-4683-bf56-c166d94184dc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046967523 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors_with_csr_rw.4046967523
Directory /workspace/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.880720221
Short name T267
Test name
Test status
Simulation time 107356800 ps
CPU time 19.41 seconds
Started Mar 24 12:38:41 PM PDT 24
Finished Mar 24 12:39:00 PM PDT 24
Peak memory 263644 kb
Host smart-da9b9df0-c89b-430f-b5f6-524e3c895b23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880720221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.880720221
Directory /workspace/11.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.1812070173
Short name T306
Test name
Test status
Simulation time 456608100 ps
CPU time 453.58 seconds
Started Mar 24 12:38:41 PM PDT 24
Finished Mar 24 12:46:14 PM PDT 24
Peak memory 263684 kb
Host smart-52a1df29-6a36-46d1-be4f-86675ac0bb75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812070173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctr
l_tl_intg_err.1812070173
Directory /workspace/11.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.1445004942
Short name T1182
Test name
Test status
Simulation time 311698000 ps
CPU time 18.79 seconds
Started Mar 24 12:39:06 PM PDT 24
Finished Mar 24 12:39:25 PM PDT 24
Peak memory 271560 kb
Host smart-385ce822-4b74-4ba1-9545-ea7c0581f3b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445004942 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.1445004942
Directory /workspace/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.4283007
Short name T259
Test name
Test status
Simulation time 52973500 ps
CPU time 16.78 seconds
Started Mar 24 12:38:58 PM PDT 24
Finished Mar 24 12:39:15 PM PDT 24
Peak memory 259912 kb
Host smart-791aadcb-3092-4102-878a-570d04bb09a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.flash_ctrl_csr_rw.4283007
Directory /workspace/12.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.3360679156
Short name T1161
Test name
Test status
Simulation time 29401700 ps
CPU time 13.47 seconds
Started Mar 24 12:38:50 PM PDT 24
Finished Mar 24 12:39:04 PM PDT 24
Peak memory 261220 kb
Host smart-df3190b5-c684-46cb-a7ac-a962d0c430b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360679156 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.
3360679156
Directory /workspace/12.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.124379466
Short name T59
Test name
Test status
Simulation time 250100800 ps
CPU time 32.97 seconds
Started Mar 24 12:39:01 PM PDT 24
Finished Mar 24 12:39:39 PM PDT 24
Peak memory 261528 kb
Host smart-deb4a5a8-7fa2-4793-80cb-7265dc6546ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124379466 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.flash_ctrl_same_csr_outstanding.124379466
Directory /workspace/12.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.1874116260
Short name T1062
Test name
Test status
Simulation time 42881500 ps
CPU time 15.27 seconds
Started Mar 24 12:38:51 PM PDT 24
Finished Mar 24 12:39:06 PM PDT 24
Peak memory 259936 kb
Host smart-3431a81b-b595-43b4-ad21-c4380b9b8ad3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874116260 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors.1874116260
Directory /workspace/12.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.635506994
Short name T1154
Test name
Test status
Simulation time 57530200 ps
CPU time 15.41 seconds
Started Mar 24 12:39:26 PM PDT 24
Finished Mar 24 12:39:41 PM PDT 24
Peak memory 259852 kb
Host smart-8098cf35-05f8-4e14-9699-94666e945116
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635506994 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors_with_csr_rw.635506994
Directory /workspace/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.1224320352
Short name T272
Test name
Test status
Simulation time 59858500 ps
CPU time 19.51 seconds
Started Mar 24 12:38:48 PM PDT 24
Finished Mar 24 12:39:07 PM PDT 24
Peak memory 263732 kb
Host smart-e836c587-efe2-405a-a932-7c1de99e5fee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224320352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.
1224320352
Directory /workspace/12.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2652674280
Short name T363
Test name
Test status
Simulation time 241240700 ps
CPU time 453.23 seconds
Started Mar 24 12:38:47 PM PDT 24
Finished Mar 24 12:46:20 PM PDT 24
Peak memory 263768 kb
Host smart-3ef1a67f-d15e-404a-b6f6-2afa111c75f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652674280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctr
l_tl_intg_err.2652674280
Directory /workspace/12.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.3343159606
Short name T310
Test name
Test status
Simulation time 74486100 ps
CPU time 16.43 seconds
Started Mar 24 12:39:00 PM PDT 24
Finished Mar 24 12:39:17 PM PDT 24
Peak memory 259912 kb
Host smart-2c300b7c-dd9c-415a-9548-a2026acaa584
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343159606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.flash_ctrl_csr_rw.3343159606
Directory /workspace/13.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.2905959461
Short name T1108
Test name
Test status
Simulation time 45077100 ps
CPU time 13.42 seconds
Started Mar 24 12:39:06 PM PDT 24
Finished Mar 24 12:39:19 PM PDT 24
Peak memory 260500 kb
Host smart-e5691e6d-a4a5-4950-ba5c-02c9f88acfe3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905959461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.
2905959461
Directory /workspace/13.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.314161031
Short name T1096
Test name
Test status
Simulation time 220062300 ps
CPU time 18.04 seconds
Started Mar 24 12:39:03 PM PDT 24
Finished Mar 24 12:39:22 PM PDT 24
Peak memory 260084 kb
Host smart-5ff62f16-8b05-41ce-b613-189fe9dc6a99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314161031 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.flash_ctrl_same_csr_outstanding.314161031
Directory /workspace/13.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.1185759025
Short name T1148
Test name
Test status
Simulation time 19575500 ps
CPU time 15.57 seconds
Started Mar 24 12:38:47 PM PDT 24
Finished Mar 24 12:39:02 PM PDT 24
Peak memory 259672 kb
Host smart-59537b71-eb6a-4554-b151-911599609a44
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185759025 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors.1185759025
Directory /workspace/13.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.2774990235
Short name T1185
Test name
Test status
Simulation time 20928000 ps
CPU time 13.16 seconds
Started Mar 24 12:38:48 PM PDT 24
Finished Mar 24 12:39:01 PM PDT 24
Peak memory 259940 kb
Host smart-7fb64a94-ae7f-47d4-b729-6ad79658c89c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774990235 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors_with_csr_rw.2774990235
Directory /workspace/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.2464196854
Short name T1101
Test name
Test status
Simulation time 143110700 ps
CPU time 15.98 seconds
Started Mar 24 12:38:53 PM PDT 24
Finished Mar 24 12:39:10 PM PDT 24
Peak memory 263620 kb
Host smart-edcbd416-5f6c-4198-bfb3-d2dd48a3b85c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464196854 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.
2464196854
Directory /workspace/13.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.340897838
Short name T238
Test name
Test status
Simulation time 27173300 ps
CPU time 17.89 seconds
Started Mar 24 12:38:55 PM PDT 24
Finished Mar 24 12:39:14 PM PDT 24
Peak memory 277824 kb
Host smart-52d47a86-1a37-4bf0-94d0-ef2b6d806620
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340897838 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.340897838
Directory /workspace/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1236621803
Short name T1196
Test name
Test status
Simulation time 128882800 ps
CPU time 15.02 seconds
Started Mar 24 12:38:51 PM PDT 24
Finished Mar 24 12:39:06 PM PDT 24
Peak memory 260000 kb
Host smart-e6cfbd0b-88da-476d-9fb3-1de2b0f9e306
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236621803 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.flash_ctrl_csr_rw.1236621803
Directory /workspace/14.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.4194140343
Short name T1081
Test name
Test status
Simulation time 37613900 ps
CPU time 14.69 seconds
Started Mar 24 12:38:53 PM PDT 24
Finished Mar 24 12:39:08 PM PDT 24
Peak memory 261472 kb
Host smart-c8d72570-1b3b-46e5-bf31-8e9081347151
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194140343 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.flash_ctrl_same_csr_outstanding.4194140343
Directory /workspace/14.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.1810787068
Short name T1060
Test name
Test status
Simulation time 46819400 ps
CPU time 13.16 seconds
Started Mar 24 12:38:45 PM PDT 24
Finished Mar 24 12:38:58 PM PDT 24
Peak memory 259892 kb
Host smart-975631e7-52fa-42cd-8db1-23e2d343e4b9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810787068 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors.1810787068
Directory /workspace/14.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.2413376800
Short name T1057
Test name
Test status
Simulation time 36726400 ps
CPU time 12.88 seconds
Started Mar 24 12:39:07 PM PDT 24
Finished Mar 24 12:39:19 PM PDT 24
Peak memory 259824 kb
Host smart-0ebc44a7-f457-4e2c-99d0-413193dcf244
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413376800 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors_with_csr_rw.2413376800
Directory /workspace/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.677099585
Short name T245
Test name
Test status
Simulation time 295455300 ps
CPU time 17.65 seconds
Started Mar 24 12:38:49 PM PDT 24
Finished Mar 24 12:39:07 PM PDT 24
Peak memory 263624 kb
Host smart-c482bed3-836b-4be1-83fb-4df4a0096d6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677099585 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.677099585
Directory /workspace/14.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.1840854255
Short name T239
Test name
Test status
Simulation time 873903600 ps
CPU time 889.74 seconds
Started Mar 24 12:38:57 PM PDT 24
Finished Mar 24 12:53:47 PM PDT 24
Peak memory 263596 kb
Host smart-2cd207bd-ff9b-4c1a-bc6b-0eeb6478f236
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840854255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctr
l_tl_intg_err.1840854255
Directory /workspace/14.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.500682889
Short name T1152
Test name
Test status
Simulation time 78254400 ps
CPU time 18.62 seconds
Started Mar 24 12:38:45 PM PDT 24
Finished Mar 24 12:39:04 PM PDT 24
Peak memory 271924 kb
Host smart-1a64bfcb-98fa-4034-a305-deb2a2451267
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500682889 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.500682889
Directory /workspace/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.1360341862
Short name T257
Test name
Test status
Simulation time 71417900 ps
CPU time 13.7 seconds
Started Mar 24 12:38:54 PM PDT 24
Finished Mar 24 12:39:07 PM PDT 24
Peak memory 259972 kb
Host smart-8c6d5cb7-ca68-4d84-b030-a976bdf6cacf
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360341862 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.flash_ctrl_csr_rw.1360341862
Directory /workspace/15.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2615978643
Short name T1078
Test name
Test status
Simulation time 73206400 ps
CPU time 17.38 seconds
Started Mar 24 12:38:50 PM PDT 24
Finished Mar 24 12:39:08 PM PDT 24
Peak memory 260028 kb
Host smart-7090abbc-cf34-4503-b86b-5c74c27ed46f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615978643 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.flash_ctrl_same_csr_outstanding.2615978643
Directory /workspace/15.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2008365573
Short name T1120
Test name
Test status
Simulation time 12622700 ps
CPU time 13.15 seconds
Started Mar 24 12:38:59 PM PDT 24
Finished Mar 24 12:39:12 PM PDT 24
Peak memory 259928 kb
Host smart-9af3062a-10ba-4829-b511-cbdcbac95925
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008365573 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors.2008365573
Directory /workspace/15.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.2034581040
Short name T1058
Test name
Test status
Simulation time 37438400 ps
CPU time 15.65 seconds
Started Mar 24 12:38:49 PM PDT 24
Finished Mar 24 12:39:05 PM PDT 24
Peak memory 259928 kb
Host smart-217437a0-5763-48e6-83c9-25e8a3626ddf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034581040 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors_with_csr_rw.2034581040
Directory /workspace/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.2187033524
Short name T1141
Test name
Test status
Simulation time 50151000 ps
CPU time 18.66 seconds
Started Mar 24 12:38:55 PM PDT 24
Finished Mar 24 12:39:13 PM PDT 24
Peak memory 263576 kb
Host smart-a713af3a-41dc-4590-b39e-526b78be4791
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187033524 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.
2187033524
Directory /workspace/15.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1695636456
Short name T243
Test name
Test status
Simulation time 178986800 ps
CPU time 448.55 seconds
Started Mar 24 12:38:58 PM PDT 24
Finished Mar 24 12:46:27 PM PDT 24
Peak memory 263700 kb
Host smart-2c70e237-6306-4fb1-a33d-bfff69984a8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695636456 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctr
l_tl_intg_err.1695636456
Directory /workspace/15.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.648049825
Short name T1111
Test name
Test status
Simulation time 44438300 ps
CPU time 14.89 seconds
Started Mar 24 12:39:03 PM PDT 24
Finished Mar 24 12:39:18 PM PDT 24
Peak memory 277224 kb
Host smart-026e22dc-b259-4fbf-b2b2-b69bcc1e5d51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648049825 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.648049825
Directory /workspace/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.2600568054
Short name T258
Test name
Test status
Simulation time 27947700 ps
CPU time 14.63 seconds
Started Mar 24 12:39:02 PM PDT 24
Finished Mar 24 12:39:17 PM PDT 24
Peak memory 260148 kb
Host smart-1dba5625-8aba-4078-88dc-405a2eba4d0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600568054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.flash_ctrl_csr_rw.2600568054
Directory /workspace/16.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.38908367
Short name T1103
Test name
Test status
Simulation time 57477100 ps
CPU time 13.48 seconds
Started Mar 24 12:38:57 PM PDT 24
Finished Mar 24 12:39:11 PM PDT 24
Peak memory 262408 kb
Host smart-646ebaca-b8bc-44e0-80bd-a198b3fb3f79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38908367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test.38908367
Directory /workspace/16.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2218726154
Short name T301
Test name
Test status
Simulation time 453479900 ps
CPU time 18.25 seconds
Started Mar 24 12:38:48 PM PDT 24
Finished Mar 24 12:39:07 PM PDT 24
Peak memory 261504 kb
Host smart-68bc29ee-fca0-4fb7-b4e0-03a8a544009a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218726154 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.flash_ctrl_same_csr_outstanding.2218726154
Directory /workspace/16.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.807072692
Short name T1083
Test name
Test status
Simulation time 36574500 ps
CPU time 16.05 seconds
Started Mar 24 12:38:46 PM PDT 24
Finished Mar 24 12:39:03 PM PDT 24
Peak memory 259912 kb
Host smart-25beff23-1a04-4fb0-82ec-f0678e259b05
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807072692 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.flash_ctrl_shadow_reg_errors.807072692
Directory /workspace/16.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1555423533
Short name T1123
Test name
Test status
Simulation time 41878600 ps
CPU time 13.09 seconds
Started Mar 24 12:38:56 PM PDT 24
Finished Mar 24 12:39:10 PM PDT 24
Peak memory 259916 kb
Host smart-dd1a8ebb-2400-4ab8-baa1-9ca8d8a27b32
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555423533 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors_with_csr_rw.1555423533
Directory /workspace/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.477570661
Short name T275
Test name
Test status
Simulation time 49706800 ps
CPU time 15.65 seconds
Started Mar 24 12:38:49 PM PDT 24
Finished Mar 24 12:39:05 PM PDT 24
Peak memory 263644 kb
Host smart-a5b63521-af1b-43e1-a0f9-09295f2bdf86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477570661 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.477570661
Directory /workspace/16.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3968767186
Short name T1089
Test name
Test status
Simulation time 39216700 ps
CPU time 19.39 seconds
Started Mar 24 12:39:09 PM PDT 24
Finished Mar 24 12:39:28 PM PDT 24
Peak memory 278352 kb
Host smart-6e99e991-b17b-4ad2-899c-65bed9a6725b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968767186 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.3968767186
Directory /workspace/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.878119069
Short name T1122
Test name
Test status
Simulation time 128073300 ps
CPU time 17.4 seconds
Started Mar 24 12:38:56 PM PDT 24
Finished Mar 24 12:39:13 PM PDT 24
Peak memory 259956 kb
Host smart-a23afa09-ebe5-4fac-8254-024e770ef2e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878119069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.flash_ctrl_csr_rw.878119069
Directory /workspace/17.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.2685389109
Short name T1165
Test name
Test status
Simulation time 49240300 ps
CPU time 13.52 seconds
Started Mar 24 12:38:52 PM PDT 24
Finished Mar 24 12:39:06 PM PDT 24
Peak memory 262284 kb
Host smart-9ed6a9fe-c8ed-4982-ae19-20ab4856b2dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685389109 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.
2685389109
Directory /workspace/17.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.2228097641
Short name T255
Test name
Test status
Simulation time 39680700 ps
CPU time 17.44 seconds
Started Mar 24 12:38:52 PM PDT 24
Finished Mar 24 12:39:10 PM PDT 24
Peak memory 260076 kb
Host smart-c6ba7cc5-1656-4555-97b6-fee7bab7860e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228097641 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.flash_ctrl_same_csr_outstanding.2228097641
Directory /workspace/17.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.3313284614
Short name T1073
Test name
Test status
Simulation time 25627900 ps
CPU time 15.53 seconds
Started Mar 24 12:38:55 PM PDT 24
Finished Mar 24 12:39:10 PM PDT 24
Peak memory 260020 kb
Host smart-b4af5481-90a5-48e4-8211-a10b1bb0ea50
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313284614 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors.3313284614
Directory /workspace/17.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.321537353
Short name T1097
Test name
Test status
Simulation time 19802400 ps
CPU time 13.1 seconds
Started Mar 24 12:38:41 PM PDT 24
Finished Mar 24 12:38:54 PM PDT 24
Peak memory 259932 kb
Host smart-38475882-f919-45a7-8b7c-a96b321b8867
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321537353 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors_with_csr_rw.321537353
Directory /workspace/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1443947416
Short name T225
Test name
Test status
Simulation time 29244400 ps
CPU time 15.84 seconds
Started Mar 24 12:38:55 PM PDT 24
Finished Mar 24 12:39:12 PM PDT 24
Peak memory 263588 kb
Host smart-c86a2a59-a36b-4b05-8e5c-8f14327eba34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443947416 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.
1443947416
Directory /workspace/17.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.13724697
Short name T242
Test name
Test status
Simulation time 25554800 ps
CPU time 14.55 seconds
Started Mar 24 12:38:47 PM PDT 24
Finished Mar 24 12:39:07 PM PDT 24
Peak memory 271840 kb
Host smart-f5080a2e-af0a-4d88-9011-a9da9ee488a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13724697 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.13724697
Directory /workspace/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.4193193038
Short name T1088
Test name
Test status
Simulation time 19944700 ps
CPU time 16.25 seconds
Started Mar 24 12:39:08 PM PDT 24
Finished Mar 24 12:39:24 PM PDT 24
Peak memory 259988 kb
Host smart-957a701d-8f16-48d5-9b2e-35d559a72540
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193193038 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.flash_ctrl_csr_rw.4193193038
Directory /workspace/18.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3545550376
Short name T1086
Test name
Test status
Simulation time 66901300 ps
CPU time 13.43 seconds
Started Mar 24 12:39:02 PM PDT 24
Finished Mar 24 12:39:15 PM PDT 24
Peak memory 262348 kb
Host smart-1513216d-c620-43a0-99c1-e579f66a183a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545550376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.
3545550376
Directory /workspace/18.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.3647445891
Short name T1070
Test name
Test status
Simulation time 162193200 ps
CPU time 18.21 seconds
Started Mar 24 12:38:57 PM PDT 24
Finished Mar 24 12:39:15 PM PDT 24
Peak memory 260012 kb
Host smart-3a27ef89-065c-401c-983d-a8c9d477eb34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647445891 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.flash_ctrl_same_csr_outstanding.3647445891
Directory /workspace/18.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1488102052
Short name T1126
Test name
Test status
Simulation time 14352300 ps
CPU time 13.24 seconds
Started Mar 24 12:38:53 PM PDT 24
Finished Mar 24 12:39:06 PM PDT 24
Peak memory 259952 kb
Host smart-f794ba45-c520-48cc-a086-e728f29a43eb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488102052 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors.1488102052
Directory /workspace/18.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3502404120
Short name T1140
Test name
Test status
Simulation time 12568800 ps
CPU time 13.25 seconds
Started Mar 24 12:38:58 PM PDT 24
Finished Mar 24 12:39:11 PM PDT 24
Peak memory 259936 kb
Host smart-e8f97bda-a1ee-4f8e-acf1-f2861ad829eb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502404120 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors_with_csr_rw.3502404120
Directory /workspace/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3105236437
Short name T1160
Test name
Test status
Simulation time 28117900 ps
CPU time 15.68 seconds
Started Mar 24 12:38:40 PM PDT 24
Finished Mar 24 12:38:56 PM PDT 24
Peak memory 263616 kb
Host smart-e03a16e0-99d1-4bf6-b600-7b82d96d2ea1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105236437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.
3105236437
Directory /workspace/18.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2287272326
Short name T309
Test name
Test status
Simulation time 1736092700 ps
CPU time 473.03 seconds
Started Mar 24 12:38:54 PM PDT 24
Finished Mar 24 12:46:47 PM PDT 24
Peak memory 261172 kb
Host smart-5a64bcbc-80a0-4c4e-8d15-1abf1f086f61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287272326 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctr
l_tl_intg_err.2287272326
Directory /workspace/18.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.633892184
Short name T58
Test name
Test status
Simulation time 346368600 ps
CPU time 17.37 seconds
Started Mar 24 12:38:59 PM PDT 24
Finished Mar 24 12:39:17 PM PDT 24
Peak memory 270112 kb
Host smart-7ec3e4c1-7e0b-4ef0-998f-e9f584c41850
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633892184 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.633892184
Directory /workspace/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.3092799027
Short name T1145
Test name
Test status
Simulation time 133709900 ps
CPU time 16.11 seconds
Started Mar 24 12:38:58 PM PDT 24
Finished Mar 24 12:39:14 PM PDT 24
Peak memory 259964 kb
Host smart-3079026a-bfb9-4fea-a4bf-a9047388922e
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092799027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.flash_ctrl_csr_rw.3092799027
Directory /workspace/19.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.2490255888
Short name T1131
Test name
Test status
Simulation time 52500500 ps
CPU time 13.24 seconds
Started Mar 24 12:38:52 PM PDT 24
Finished Mar 24 12:39:06 PM PDT 24
Peak memory 262308 kb
Host smart-84e441cc-667f-4373-a3ae-6176a3417175
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490255888 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.
2490255888
Directory /workspace/19.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.3629629204
Short name T254
Test name
Test status
Simulation time 306274200 ps
CPU time 19.47 seconds
Started Mar 24 12:38:51 PM PDT 24
Finished Mar 24 12:39:11 PM PDT 24
Peak memory 260052 kb
Host smart-04390d4b-ee95-40b6-93c7-1933c894c7dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629629204 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.flash_ctrl_same_csr_outstanding.3629629204
Directory /workspace/19.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.2047264438
Short name T1139
Test name
Test status
Simulation time 37685400 ps
CPU time 15.7 seconds
Started Mar 24 12:39:15 PM PDT 24
Finished Mar 24 12:39:31 PM PDT 24
Peak memory 259900 kb
Host smart-279fedb0-c2a2-4bd4-bef2-3c3df4a64e92
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047264438 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors.2047264438
Directory /workspace/19.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.798429768
Short name T1079
Test name
Test status
Simulation time 148134300 ps
CPU time 15.48 seconds
Started Mar 24 12:39:08 PM PDT 24
Finished Mar 24 12:39:24 PM PDT 24
Peak memory 259940 kb
Host smart-01a58c4f-fcd7-48df-85e9-af3307c01581
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798429768 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors_with_csr_rw.798429768
Directory /workspace/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1222627500
Short name T359
Test name
Test status
Simulation time 866516400 ps
CPU time 750.04 seconds
Started Mar 24 12:38:41 PM PDT 24
Finished Mar 24 12:51:12 PM PDT 24
Peak memory 263644 kb
Host smart-6f9f9c34-6690-4ec9-9175-555ab0a9f327
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222627500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctr
l_tl_intg_err.1222627500
Directory /workspace/19.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2987017424
Short name T1061
Test name
Test status
Simulation time 1270163300 ps
CPU time 58.37 seconds
Started Mar 24 12:38:38 PM PDT 24
Finished Mar 24 12:39:37 PM PDT 24
Peak memory 260012 kb
Host smart-5ffa53bb-dcc6-4a9e-81b5-293a4b43067c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987017424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_aliasing.2987017424
Directory /workspace/2.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.269294217
Short name T1181
Test name
Test status
Simulation time 5949536900 ps
CPU time 45.72 seconds
Started Mar 24 12:38:36 PM PDT 24
Finished Mar 24 12:39:22 PM PDT 24
Peak memory 259948 kb
Host smart-b2005436-8724-40cc-b8b8-fd5a3408de96
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269294217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.flash_ctrl_csr_bit_bash.269294217
Directory /workspace/2.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.2314254261
Short name T1113
Test name
Test status
Simulation time 52440100 ps
CPU time 30.58 seconds
Started Mar 24 12:38:40 PM PDT 24
Finished Mar 24 12:39:10 PM PDT 24
Peak memory 260012 kb
Host smart-7a8d6e1a-2f9f-466c-883b-459a0e33e0d1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314254261 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_hw_reset.2314254261
Directory /workspace/2.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1837452422
Short name T1119
Test name
Test status
Simulation time 128143300 ps
CPU time 18.1 seconds
Started Mar 24 12:38:41 PM PDT 24
Finished Mar 24 12:38:59 PM PDT 24
Peak memory 277864 kb
Host smart-54260f33-5698-4d13-a107-2ef7ed392844
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837452422 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.1837452422
Directory /workspace/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1290309252
Short name T1107
Test name
Test status
Simulation time 319420300 ps
CPU time 15.11 seconds
Started Mar 24 12:38:50 PM PDT 24
Finished Mar 24 12:39:05 PM PDT 24
Peak memory 259852 kb
Host smart-657ef75e-fb20-434d-978a-79497841b605
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290309252 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.flash_ctrl_csr_rw.1290309252
Directory /workspace/2.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.2056277215
Short name T1130
Test name
Test status
Simulation time 16337000 ps
CPU time 13.36 seconds
Started Mar 24 12:38:44 PM PDT 24
Finished Mar 24 12:38:58 PM PDT 24
Peak memory 262132 kb
Host smart-43ef9422-c91b-4ff7-b387-ae590bdf0da6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056277215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.2
056277215
Directory /workspace/2.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.2290760095
Short name T249
Test name
Test status
Simulation time 33816400 ps
CPU time 13.75 seconds
Started Mar 24 12:38:34 PM PDT 24
Finished Mar 24 12:38:48 PM PDT 24
Peak memory 262776 kb
Host smart-ccc85669-899e-401e-b6df-01f2334a0395
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290760095 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_mem_partial_access.2290760095
Directory /workspace/2.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.455196086
Short name T1114
Test name
Test status
Simulation time 47161300 ps
CPU time 13.37 seconds
Started Mar 24 12:38:35 PM PDT 24
Finished Mar 24 12:38:48 PM PDT 24
Peak memory 262284 kb
Host smart-5251a3da-d76e-4922-8b0d-db22ad936734
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455196086 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mem
_walk.455196086
Directory /workspace/2.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3682321619
Short name T305
Test name
Test status
Simulation time 645420500 ps
CPU time 18 seconds
Started Mar 24 12:38:31 PM PDT 24
Finished Mar 24 12:38:49 PM PDT 24
Peak memory 260048 kb
Host smart-6dcb7190-46c3-4b64-bf11-e9c3704793b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682321619 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.flash_ctrl_same_csr_outstanding.3682321619
Directory /workspace/2.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.705299212
Short name T1074
Test name
Test status
Simulation time 14174200 ps
CPU time 15.98 seconds
Started Mar 24 12:38:53 PM PDT 24
Finished Mar 24 12:39:09 PM PDT 24
Peak memory 259856 kb
Host smart-8cf21c58-2c78-46dd-8a28-ed42366bb5ce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705299212 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.flash_ctrl_shadow_reg_errors.705299212
Directory /workspace/2.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1284108390
Short name T1162
Test name
Test status
Simulation time 12617600 ps
CPU time 15.55 seconds
Started Mar 24 12:38:55 PM PDT 24
Finished Mar 24 12:39:11 PM PDT 24
Peak memory 259928 kb
Host smart-48bb0aaf-c190-49d0-99b4-109775721867
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284108390 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors_with_csr_rw.1284108390
Directory /workspace/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3778006003
Short name T1106
Test name
Test status
Simulation time 32952300 ps
CPU time 15.83 seconds
Started Mar 24 12:38:45 PM PDT 24
Finished Mar 24 12:39:00 PM PDT 24
Peak memory 263668 kb
Host smart-7e571af8-54e2-490f-9c85-83fcb7aaaea5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778006003 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.3
778006003
Directory /workspace/2.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.1772111639
Short name T356
Test name
Test status
Simulation time 351805000 ps
CPU time 387.24 seconds
Started Mar 24 12:38:48 PM PDT 24
Finished Mar 24 12:45:15 PM PDT 24
Peak memory 261768 kb
Host smart-84152033-b868-4d3b-ae88-47cf343f4770
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772111639 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl
_tl_intg_err.1772111639
Directory /workspace/2.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.2319515909
Short name T1128
Test name
Test status
Simulation time 14648200 ps
CPU time 13.19 seconds
Started Mar 24 12:39:00 PM PDT 24
Finished Mar 24 12:39:13 PM PDT 24
Peak memory 261452 kb
Host smart-4a77ac69-9142-48d8-98d2-c12718573478
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319515909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.
2319515909
Directory /workspace/20.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.1471550196
Short name T1158
Test name
Test status
Simulation time 45306200 ps
CPU time 13.44 seconds
Started Mar 24 12:38:54 PM PDT 24
Finished Mar 24 12:39:08 PM PDT 24
Peak memory 262012 kb
Host smart-da68e33b-5841-4d66-b30f-ada654ee65eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471550196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.
1471550196
Directory /workspace/21.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.44255753
Short name T1184
Test name
Test status
Simulation time 16592700 ps
CPU time 13.31 seconds
Started Mar 24 12:38:49 PM PDT 24
Finished Mar 24 12:39:03 PM PDT 24
Peak memory 262420 kb
Host smart-da87074c-e74e-40f5-90f4-a86f9eefe4e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44255753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.44255753
Directory /workspace/22.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.1281786270
Short name T355
Test name
Test status
Simulation time 60175400 ps
CPU time 13.57 seconds
Started Mar 24 12:39:10 PM PDT 24
Finished Mar 24 12:39:29 PM PDT 24
Peak memory 260388 kb
Host smart-e6d36fca-a1bf-4892-85e1-a73c1a0a34be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281786270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.
1281786270
Directory /workspace/23.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.2235315417
Short name T348
Test name
Test status
Simulation time 26244600 ps
CPU time 13.39 seconds
Started Mar 24 12:38:56 PM PDT 24
Finished Mar 24 12:39:10 PM PDT 24
Peak memory 260516 kb
Host smart-70a324b4-8ff7-4f7e-85b5-d217d34f2d0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235315417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.
2235315417
Directory /workspace/24.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.375986105
Short name T1192
Test name
Test status
Simulation time 25332100 ps
CPU time 13.21 seconds
Started Mar 24 12:39:19 PM PDT 24
Finished Mar 24 12:39:32 PM PDT 24
Peak memory 262024 kb
Host smart-4852c2f5-a2e4-4451-8296-4116bd590dce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375986105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.375986105
Directory /workspace/25.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.3555812027
Short name T1187
Test name
Test status
Simulation time 70610400 ps
CPU time 13.39 seconds
Started Mar 24 12:39:11 PM PDT 24
Finished Mar 24 12:39:25 PM PDT 24
Peak memory 262312 kb
Host smart-1433814b-bf60-4204-b8c3-2a6262397832
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555812027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.
3555812027
Directory /workspace/26.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3088878268
Short name T1124
Test name
Test status
Simulation time 25838200 ps
CPU time 13.35 seconds
Started Mar 24 12:39:14 PM PDT 24
Finished Mar 24 12:39:28 PM PDT 24
Peak memory 262068 kb
Host smart-da40354e-3156-4029-9f54-25e25690e432
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088878268 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.
3088878268
Directory /workspace/27.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.402326140
Short name T1102
Test name
Test status
Simulation time 44194300 ps
CPU time 13.74 seconds
Started Mar 24 12:39:04 PM PDT 24
Finished Mar 24 12:39:18 PM PDT 24
Peak memory 262076 kb
Host smart-06cd85f4-5201-4f0a-9273-67f4172cf954
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402326140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.402326140
Directory /workspace/28.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.448251895
Short name T1110
Test name
Test status
Simulation time 15124700 ps
CPU time 13.57 seconds
Started Mar 24 12:38:57 PM PDT 24
Finished Mar 24 12:39:10 PM PDT 24
Peak memory 262056 kb
Host smart-8e133f8c-9561-46b0-b0da-1aa05e3b579d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448251895 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.448251895
Directory /workspace/29.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.1154941947
Short name T1136
Test name
Test status
Simulation time 3923029900 ps
CPU time 61.6 seconds
Started Mar 24 12:38:29 PM PDT 24
Finished Mar 24 12:39:31 PM PDT 24
Peak memory 259944 kb
Host smart-c194c97d-3c22-4f87-8331-7a7e56974b02
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154941947 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_aliasing.1154941947
Directory /workspace/3.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.790826498
Short name T1068
Test name
Test status
Simulation time 1293006200 ps
CPU time 62.06 seconds
Started Mar 24 12:38:32 PM PDT 24
Finished Mar 24 12:39:39 PM PDT 24
Peak memory 259924 kb
Host smart-52dc9345-34ff-41cb-a63b-6a6c395ea282
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790826498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.flash_ctrl_csr_bit_bash.790826498
Directory /workspace/3.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.296224544
Short name T308
Test name
Test status
Simulation time 150532700 ps
CPU time 29.82 seconds
Started Mar 24 12:38:30 PM PDT 24
Finished Mar 24 12:39:00 PM PDT 24
Peak memory 259888 kb
Host smart-d876b107-91db-4522-9889-ac7860957500
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296224544 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.flash_ctrl_csr_hw_reset.296224544
Directory /workspace/3.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1757100751
Short name T1153
Test name
Test status
Simulation time 60335200 ps
CPU time 14.52 seconds
Started Mar 24 12:38:56 PM PDT 24
Finished Mar 24 12:39:10 PM PDT 24
Peak memory 270184 kb
Host smart-1ecb4f5c-2d61-4438-82f1-812e5b38da0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757100751 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.1757100751
Directory /workspace/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1160185103
Short name T1115
Test name
Test status
Simulation time 63663500 ps
CPU time 13.87 seconds
Started Mar 24 12:38:34 PM PDT 24
Finished Mar 24 12:38:47 PM PDT 24
Peak memory 260020 kb
Host smart-3c9cd2db-6327-40c6-840b-95b441899d29
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160185103 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.flash_ctrl_csr_rw.1160185103
Directory /workspace/3.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3110175334
Short name T252
Test name
Test status
Simulation time 31387100 ps
CPU time 13.55 seconds
Started Mar 24 12:38:34 PM PDT 24
Finished Mar 24 12:38:48 PM PDT 24
Peak memory 263556 kb
Host smart-6d31f8bb-72b8-4110-a53b-e86359f9ae75
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110175334 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_mem_partial_access.3110175334
Directory /workspace/3.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1846048499
Short name T1087
Test name
Test status
Simulation time 50241800 ps
CPU time 13.39 seconds
Started Mar 24 12:38:46 PM PDT 24
Finished Mar 24 12:38:59 PM PDT 24
Peak memory 262152 kb
Host smart-9f20c417-3e3b-4550-9184-8a87ea332683
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846048499 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_me
m_walk.1846048499
Directory /workspace/3.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3814400077
Short name T1085
Test name
Test status
Simulation time 38433100 ps
CPU time 17.31 seconds
Started Mar 24 12:39:00 PM PDT 24
Finished Mar 24 12:39:17 PM PDT 24
Peak memory 261700 kb
Host smart-da68ac98-4ac9-4cac-83b0-a39240b392ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814400077 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.flash_ctrl_same_csr_outstanding.3814400077
Directory /workspace/3.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.944800298
Short name T1168
Test name
Test status
Simulation time 28264300 ps
CPU time 15.53 seconds
Started Mar 24 12:38:46 PM PDT 24
Finished Mar 24 12:39:07 PM PDT 24
Peak memory 259808 kb
Host smart-2070130d-e108-4880-805c-16a2c3f9be35
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944800298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.flash_ctrl_shadow_reg_errors.944800298
Directory /workspace/3.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.2809097641
Short name T1098
Test name
Test status
Simulation time 20555600 ps
CPU time 15.57 seconds
Started Mar 24 12:38:37 PM PDT 24
Finished Mar 24 12:38:52 PM PDT 24
Peak memory 259864 kb
Host smart-4a3a0ad2-2e56-4008-ad5e-678365c3aeaf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809097641 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors_with_csr_rw.2809097641
Directory /workspace/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1186845055
Short name T277
Test name
Test status
Simulation time 60803100 ps
CPU time 19.23 seconds
Started Mar 24 12:38:43 PM PDT 24
Finished Mar 24 12:39:03 PM PDT 24
Peak memory 263640 kb
Host smart-eaa76752-8ee3-49db-9d29-9fd0677f5019
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186845055 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.1
186845055
Directory /workspace/3.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.3278147744
Short name T1117
Test name
Test status
Simulation time 17740600 ps
CPU time 13.47 seconds
Started Mar 24 12:38:53 PM PDT 24
Finished Mar 24 12:39:06 PM PDT 24
Peak memory 262292 kb
Host smart-55eb01a9-59c6-4ff7-abfa-9ee3a9be22ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278147744 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.
3278147744
Directory /workspace/30.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.36427229
Short name T269
Test name
Test status
Simulation time 52530700 ps
CPU time 13.31 seconds
Started Mar 24 12:38:59 PM PDT 24
Finished Mar 24 12:39:12 PM PDT 24
Peak memory 262368 kb
Host smart-dbcf4f47-c186-4ed6-8dca-7e1a403629a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36427229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.36427229
Directory /workspace/31.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.1218505975
Short name T1169
Test name
Test status
Simulation time 70369100 ps
CPU time 13.26 seconds
Started Mar 24 12:39:08 PM PDT 24
Finished Mar 24 12:39:21 PM PDT 24
Peak memory 260532 kb
Host smart-1fd09103-eb9d-415e-bd58-d2b614c0a46a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218505975 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.
1218505975
Directory /workspace/32.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1879350985
Short name T1129
Test name
Test status
Simulation time 14636500 ps
CPU time 13.34 seconds
Started Mar 24 12:39:07 PM PDT 24
Finished Mar 24 12:39:21 PM PDT 24
Peak memory 262436 kb
Host smart-f2b135a9-a0c8-465d-a554-84f116b9820f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879350985 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.
1879350985
Directory /workspace/33.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.4171305857
Short name T342
Test name
Test status
Simulation time 18515000 ps
CPU time 13.31 seconds
Started Mar 24 12:38:54 PM PDT 24
Finished Mar 24 12:39:07 PM PDT 24
Peak memory 261968 kb
Host smart-b6f8d22a-3bb3-41f8-bcb2-45d6b29ce31b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171305857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.
4171305857
Directory /workspace/34.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.50409615
Short name T1127
Test name
Test status
Simulation time 20516100 ps
CPU time 13.42 seconds
Started Mar 24 12:38:46 PM PDT 24
Finished Mar 24 12:38:59 PM PDT 24
Peak memory 262532 kb
Host smart-0cb61804-f356-4e20-85d1-417adf97d906
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50409615 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test.50409615
Directory /workspace/35.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3383165247
Short name T1075
Test name
Test status
Simulation time 16154500 ps
CPU time 13.2 seconds
Started Mar 24 12:38:51 PM PDT 24
Finished Mar 24 12:39:04 PM PDT 24
Peak memory 262420 kb
Host smart-23e69da6-8b3e-47cc-9fbb-5781a14d8784
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383165247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.
3383165247
Directory /workspace/36.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.186416714
Short name T1116
Test name
Test status
Simulation time 52227800 ps
CPU time 13.4 seconds
Started Mar 24 12:39:01 PM PDT 24
Finished Mar 24 12:39:15 PM PDT 24
Peak memory 262136 kb
Host smart-41497f55-378e-4d35-9d83-5d98db5d89d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186416714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test.186416714
Directory /workspace/37.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.2016267101
Short name T1147
Test name
Test status
Simulation time 17401100 ps
CPU time 13.48 seconds
Started Mar 24 12:38:59 PM PDT 24
Finished Mar 24 12:39:12 PM PDT 24
Peak memory 262344 kb
Host smart-3218dc40-0aec-4304-a626-24f8dfaa5f16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016267101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.
2016267101
Directory /workspace/38.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.3501425
Short name T270
Test name
Test status
Simulation time 38044800 ps
CPU time 13.13 seconds
Started Mar 24 12:39:03 PM PDT 24
Finished Mar 24 12:39:16 PM PDT 24
Peak memory 262044 kb
Host smart-b15f3db8-f781-41ef-9776-c6bae178e6a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.3501425
Directory /workspace/39.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.3051649938
Short name T256
Test name
Test status
Simulation time 255204900 ps
CPU time 29.84 seconds
Started Mar 24 12:38:41 PM PDT 24
Finished Mar 24 12:39:11 PM PDT 24
Peak memory 259988 kb
Host smart-fab6149e-abdd-4ec0-8f15-2fd7669a0329
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051649938 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_aliasing.3051649938
Directory /workspace/4.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3380228870
Short name T1186
Test name
Test status
Simulation time 5968768900 ps
CPU time 69.83 seconds
Started Mar 24 12:38:43 PM PDT 24
Finished Mar 24 12:39:52 PM PDT 24
Peak memory 263108 kb
Host smart-bf90f591-fb7e-4a1f-b6dd-3ae6485beec4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380228870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_bit_bash.3380228870
Directory /workspace/4.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.4166270963
Short name T1172
Test name
Test status
Simulation time 339141400 ps
CPU time 31.18 seconds
Started Mar 24 12:38:47 PM PDT 24
Finished Mar 24 12:39:19 PM PDT 24
Peak memory 259964 kb
Host smart-413fdde6-c1a8-4932-91c2-9678707026d6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166270963 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_hw_reset.4166270963
Directory /workspace/4.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.2026000720
Short name T311
Test name
Test status
Simulation time 212487300 ps
CPU time 17.32 seconds
Started Mar 24 12:38:35 PM PDT 24
Finished Mar 24 12:38:53 PM PDT 24
Peak memory 270984 kb
Host smart-bcff478e-2665-4b1f-98f6-574eb3ed576b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026000720 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.2026000720
Directory /workspace/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.2599537022
Short name T1155
Test name
Test status
Simulation time 189107800 ps
CPU time 16.27 seconds
Started Mar 24 12:38:48 PM PDT 24
Finished Mar 24 12:39:04 PM PDT 24
Peak memory 260108 kb
Host smart-3614ad79-f4a8-4569-af76-1567f8b34b6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599537022 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.flash_ctrl_csr_rw.2599537022
Directory /workspace/4.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2409284958
Short name T1094
Test name
Test status
Simulation time 33796300 ps
CPU time 13.45 seconds
Started Mar 24 12:38:46 PM PDT 24
Finished Mar 24 12:38:59 PM PDT 24
Peak memory 262248 kb
Host smart-ca172d0e-a53b-47c3-bab8-3e77ef342137
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409284958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.2
409284958
Directory /workspace/4.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.3737312185
Short name T251
Test name
Test status
Simulation time 17939100 ps
CPU time 13.64 seconds
Started Mar 24 12:38:35 PM PDT 24
Finished Mar 24 12:38:54 PM PDT 24
Peak memory 263624 kb
Host smart-5179cf23-f68b-455f-b841-8746cf0a622d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737312185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_mem_partial_access.3737312185
Directory /workspace/4.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.137769605
Short name T1077
Test name
Test status
Simulation time 34458700 ps
CPU time 13.58 seconds
Started Mar 24 12:39:04 PM PDT 24
Finished Mar 24 12:39:18 PM PDT 24
Peak memory 262364 kb
Host smart-7cdf9338-1f07-493b-b4cd-eb698fa3f719
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137769605 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mem
_walk.137769605
Directory /workspace/4.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.2693255549
Short name T1095
Test name
Test status
Simulation time 294164400 ps
CPU time 17.51 seconds
Started Mar 24 12:38:53 PM PDT 24
Finished Mar 24 12:39:11 PM PDT 24
Peak memory 261900 kb
Host smart-a7b3fa23-1ccf-48e2-8d2a-29ad2bcc52e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693255549 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.flash_ctrl_same_csr_outstanding.2693255549
Directory /workspace/4.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.2322283524
Short name T1084
Test name
Test status
Simulation time 20624400 ps
CPU time 13.19 seconds
Started Mar 24 12:38:36 PM PDT 24
Finished Mar 24 12:38:49 PM PDT 24
Peak memory 259876 kb
Host smart-4b18fab2-4e31-491b-a9b3-6d2e41606d75
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322283524 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors.2322283524
Directory /workspace/4.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.4076773187
Short name T1072
Test name
Test status
Simulation time 17919900 ps
CPU time 13.07 seconds
Started Mar 24 12:38:54 PM PDT 24
Finished Mar 24 12:39:07 PM PDT 24
Peak memory 259896 kb
Host smart-fd4a244b-a9ab-410c-adf1-64ec5dd0f817
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076773187 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors_with_csr_rw.4076773187
Directory /workspace/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.332328038
Short name T1193
Test name
Test status
Simulation time 152636600 ps
CPU time 18.7 seconds
Started Mar 24 12:39:00 PM PDT 24
Finished Mar 24 12:39:19 PM PDT 24
Peak memory 260912 kb
Host smart-7dfb0abf-3283-4bf6-ab67-e30c9a5934cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332328038 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.332328038
Directory /workspace/4.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2376314128
Short name T1090
Test name
Test status
Simulation time 44551900 ps
CPU time 13.3 seconds
Started Mar 24 12:39:17 PM PDT 24
Finished Mar 24 12:39:30 PM PDT 24
Peak memory 262200 kb
Host smart-163f442c-140b-4e13-b8f4-a5657cf84fe3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376314128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.
2376314128
Directory /workspace/40.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3992010353
Short name T1177
Test name
Test status
Simulation time 31473700 ps
CPU time 13.42 seconds
Started Mar 24 12:38:50 PM PDT 24
Finished Mar 24 12:39:04 PM PDT 24
Peak memory 262004 kb
Host smart-84281825-340b-4f7c-a9be-de3a67d8b3bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992010353 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.
3992010353
Directory /workspace/41.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.54168305
Short name T346
Test name
Test status
Simulation time 30868300 ps
CPU time 13.58 seconds
Started Mar 24 12:38:55 PM PDT 24
Finished Mar 24 12:39:08 PM PDT 24
Peak memory 262144 kb
Host smart-5d281c26-429f-487f-ab98-05f776e383a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54168305 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.54168305
Directory /workspace/42.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.4237416233
Short name T345
Test name
Test status
Simulation time 16245300 ps
CPU time 13.25 seconds
Started Mar 24 12:38:57 PM PDT 24
Finished Mar 24 12:39:10 PM PDT 24
Peak memory 262408 kb
Host smart-743eb62e-b638-4d39-9aaf-41c38c4d88e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237416233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.
4237416233
Directory /workspace/43.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.3114585818
Short name T1170
Test name
Test status
Simulation time 15963700 ps
CPU time 13.6 seconds
Started Mar 24 12:38:59 PM PDT 24
Finished Mar 24 12:39:12 PM PDT 24
Peak memory 262348 kb
Host smart-34c4e49b-1daf-463f-96bf-112781153201
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114585818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.
3114585818
Directory /workspace/44.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.192682163
Short name T1076
Test name
Test status
Simulation time 16651800 ps
CPU time 13.2 seconds
Started Mar 24 12:39:00 PM PDT 24
Finished Mar 24 12:39:13 PM PDT 24
Peak memory 262320 kb
Host smart-af69fcb6-d14f-420d-bdae-63dac82cf1b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192682163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.192682163
Directory /workspace/45.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.1990056308
Short name T1133
Test name
Test status
Simulation time 105786000 ps
CPU time 13.46 seconds
Started Mar 24 12:39:00 PM PDT 24
Finished Mar 24 12:39:14 PM PDT 24
Peak memory 262348 kb
Host smart-ac0c40cc-ce0c-4a9f-a106-2ac63c8abe6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990056308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.
1990056308
Directory /workspace/46.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.1062606211
Short name T344
Test name
Test status
Simulation time 53401600 ps
CPU time 13.41 seconds
Started Mar 24 12:39:10 PM PDT 24
Finished Mar 24 12:39:23 PM PDT 24
Peak memory 262404 kb
Host smart-0707d428-3804-429e-b338-b1721b3073fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062606211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.
1062606211
Directory /workspace/47.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.139883332
Short name T1080
Test name
Test status
Simulation time 25339500 ps
CPU time 13.36 seconds
Started Mar 24 12:38:56 PM PDT 24
Finished Mar 24 12:39:10 PM PDT 24
Peak memory 262432 kb
Host smart-5153abab-a12c-46f6-a3b4-1a9139c66842
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139883332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.139883332
Directory /workspace/48.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3265648955
Short name T1191
Test name
Test status
Simulation time 52255600 ps
CPU time 13.19 seconds
Started Mar 24 12:38:59 PM PDT 24
Finished Mar 24 12:39:13 PM PDT 24
Peak memory 262356 kb
Host smart-60ec2429-8f3a-4280-a6b2-16dd2faa3314
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265648955 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.
3265648955
Directory /workspace/49.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.4152528930
Short name T314
Test name
Test status
Simulation time 115335300 ps
CPU time 18.69 seconds
Started Mar 24 12:38:48 PM PDT 24
Finished Mar 24 12:39:07 PM PDT 24
Peak memory 271844 kb
Host smart-4c507b8a-aa7c-4b6a-bdaa-9b404aa6c8b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152528930 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.4152528930
Directory /workspace/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3146349789
Short name T1132
Test name
Test status
Simulation time 184327500 ps
CPU time 16.28 seconds
Started Mar 24 12:38:33 PM PDT 24
Finished Mar 24 12:38:49 PM PDT 24
Peak memory 259924 kb
Host smart-92931f53-d37a-4306-bc89-73ae825b38d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146349789 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.flash_ctrl_csr_rw.3146349789
Directory /workspace/5.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.833453558
Short name T1157
Test name
Test status
Simulation time 17719600 ps
CPU time 13.35 seconds
Started Mar 24 12:38:42 PM PDT 24
Finished Mar 24 12:38:55 PM PDT 24
Peak memory 262336 kb
Host smart-55080a39-c32c-4d2b-897f-4a4baa503c27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833453558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.833453558
Directory /workspace/5.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1566882995
Short name T1150
Test name
Test status
Simulation time 76008700 ps
CPU time 18.03 seconds
Started Mar 24 12:38:46 PM PDT 24
Finished Mar 24 12:39:04 PM PDT 24
Peak memory 260020 kb
Host smart-3f4202bf-4c4f-4f46-ad20-7bed2773fc54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566882995 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.flash_ctrl_same_csr_outstanding.1566882995
Directory /workspace/5.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.1861276007
Short name T1188
Test name
Test status
Simulation time 88021100 ps
CPU time 13.28 seconds
Started Mar 24 12:38:49 PM PDT 24
Finished Mar 24 12:39:03 PM PDT 24
Peak memory 259872 kb
Host smart-618e4784-eacb-41ae-83e1-c5c60ab35fb7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861276007 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors.1861276007
Directory /workspace/5.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.1837478494
Short name T1082
Test name
Test status
Simulation time 41642500 ps
CPU time 15.43 seconds
Started Mar 24 12:38:40 PM PDT 24
Finished Mar 24 12:38:56 PM PDT 24
Peak memory 259768 kb
Host smart-868b8139-2b15-4d5a-80ef-8667300ba6d8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837478494 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors_with_csr_rw.1837478494
Directory /workspace/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.4012743055
Short name T1180
Test name
Test status
Simulation time 189369800 ps
CPU time 17.53 seconds
Started Mar 24 12:38:45 PM PDT 24
Finished Mar 24 12:39:02 PM PDT 24
Peak memory 263588 kb
Host smart-06736d48-f6e0-4ddc-a15b-8292b82229b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012743055 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.4
012743055
Directory /workspace/5.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.3321070213
Short name T357
Test name
Test status
Simulation time 3879800900 ps
CPU time 889.57 seconds
Started Mar 24 12:38:50 PM PDT 24
Finished Mar 24 12:53:40 PM PDT 24
Peak memory 260004 kb
Host smart-cab166f0-c8c7-4341-9e58-7610c98a3a15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321070213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl
_tl_intg_err.3321070213
Directory /workspace/5.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.2839442510
Short name T240
Test name
Test status
Simulation time 320042100 ps
CPU time 16.33 seconds
Started Mar 24 12:38:48 PM PDT 24
Finished Mar 24 12:39:04 PM PDT 24
Peak memory 270140 kb
Host smart-e680253f-df45-4126-9cc2-3477c1547da5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839442510 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.2839442510
Directory /workspace/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.3860900037
Short name T1146
Test name
Test status
Simulation time 228006500 ps
CPU time 17.08 seconds
Started Mar 24 12:38:54 PM PDT 24
Finished Mar 24 12:39:11 PM PDT 24
Peak memory 259984 kb
Host smart-e31c9bbb-3df7-40e4-ab65-8d1d3be9cc0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860900037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.flash_ctrl_csr_rw.3860900037
Directory /workspace/6.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.1987534843
Short name T1190
Test name
Test status
Simulation time 210895000 ps
CPU time 13.33 seconds
Started Mar 24 12:39:03 PM PDT 24
Finished Mar 24 12:39:16 PM PDT 24
Peak memory 260452 kb
Host smart-9435fc3e-da21-4606-aa17-e14d0429d0f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987534843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.1
987534843
Directory /workspace/6.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1975215068
Short name T1125
Test name
Test status
Simulation time 473790000 ps
CPU time 17.89 seconds
Started Mar 24 12:38:46 PM PDT 24
Finished Mar 24 12:39:04 PM PDT 24
Peak memory 260036 kb
Host smart-6ed84c61-d3e5-40bb-be2e-9cfbf858b489
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975215068 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.flash_ctrl_same_csr_outstanding.1975215068
Directory /workspace/6.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2399755494
Short name T1175
Test name
Test status
Simulation time 58220000 ps
CPU time 15.49 seconds
Started Mar 24 12:38:54 PM PDT 24
Finished Mar 24 12:39:10 PM PDT 24
Peak memory 259940 kb
Host smart-2cc7564b-c6a1-4196-a121-ce66cc780f7d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399755494 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors.2399755494
Directory /workspace/6.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.4114006590
Short name T1112
Test name
Test status
Simulation time 23556600 ps
CPU time 15.8 seconds
Started Mar 24 12:39:02 PM PDT 24
Finished Mar 24 12:39:18 PM PDT 24
Peak memory 259916 kb
Host smart-21fa0ed8-92b5-474b-8c5a-b4fcad21c1dd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114006590 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors_with_csr_rw.4114006590
Directory /workspace/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1252510886
Short name T1159
Test name
Test status
Simulation time 570483700 ps
CPU time 16.49 seconds
Started Mar 24 12:38:50 PM PDT 24
Finished Mar 24 12:39:06 PM PDT 24
Peak memory 263588 kb
Host smart-8d57e90c-b6b9-47eb-980f-27d724e75c23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252510886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.1
252510886
Directory /workspace/6.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.439136267
Short name T360
Test name
Test status
Simulation time 5305826000 ps
CPU time 897.04 seconds
Started Mar 24 12:38:54 PM PDT 24
Finished Mar 24 12:53:51 PM PDT 24
Peak memory 263656 kb
Host smart-2960e4b0-b27b-4d55-bc07-b0029fae9b87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439136267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_
tl_intg_err.439136267
Directory /workspace/6.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.3216336823
Short name T1091
Test name
Test status
Simulation time 69895200 ps
CPU time 15.81 seconds
Started Mar 24 12:38:31 PM PDT 24
Finished Mar 24 12:38:47 PM PDT 24
Peak memory 277188 kb
Host smart-568bc0b2-ac58-457d-8c84-e924da4fa582
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216336823 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.3216336823
Directory /workspace/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.4088631831
Short name T1149
Test name
Test status
Simulation time 88115800 ps
CPU time 16.92 seconds
Started Mar 24 12:38:54 PM PDT 24
Finished Mar 24 12:39:11 PM PDT 24
Peak memory 259960 kb
Host smart-292e3e93-c9ef-4cec-a549-83d3d98d2fd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088631831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.flash_ctrl_csr_rw.4088631831
Directory /workspace/7.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.3153630971
Short name T1195
Test name
Test status
Simulation time 16846500 ps
CPU time 13.37 seconds
Started Mar 24 12:39:06 PM PDT 24
Finished Mar 24 12:39:19 PM PDT 24
Peak memory 262248 kb
Host smart-41ab07d2-206a-43a0-b1a8-d5d4050fa4a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153630971 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.3
153630971
Directory /workspace/7.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.626880007
Short name T1142
Test name
Test status
Simulation time 72362100 ps
CPU time 15.49 seconds
Started Mar 24 12:39:03 PM PDT 24
Finished Mar 24 12:39:19 PM PDT 24
Peak memory 260076 kb
Host smart-c40a7de2-d8ea-4bea-b791-a9818292b62f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626880007 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.flash_ctrl_same_csr_outstanding.626880007
Directory /workspace/7.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.3601886312
Short name T1156
Test name
Test status
Simulation time 51228600 ps
CPU time 12.99 seconds
Started Mar 24 12:38:51 PM PDT 24
Finished Mar 24 12:39:04 PM PDT 24
Peak memory 260004 kb
Host smart-f3ab9f13-5420-46fe-a22c-b8b967c52320
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601886312 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors.3601886312
Directory /workspace/7.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.594444012
Short name T1138
Test name
Test status
Simulation time 18824300 ps
CPU time 15.82 seconds
Started Mar 24 12:38:49 PM PDT 24
Finished Mar 24 12:39:05 PM PDT 24
Peak memory 259788 kb
Host smart-6ad87208-a152-45f1-993a-61a6abcfe724
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594444012 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors_with_csr_rw.594444012
Directory /workspace/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2530775401
Short name T241
Test name
Test status
Simulation time 26578600 ps
CPU time 15.45 seconds
Started Mar 24 12:38:59 PM PDT 24
Finished Mar 24 12:39:16 PM PDT 24
Peak memory 263616 kb
Host smart-2faf0bfa-bbd7-47e4-a0c1-661d147a2d1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530775401 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.2
530775401
Directory /workspace/7.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.3536635093
Short name T358
Test name
Test status
Simulation time 1631748200 ps
CPU time 459.2 seconds
Started Mar 24 12:38:58 PM PDT 24
Finished Mar 24 12:46:37 PM PDT 24
Peak memory 264012 kb
Host smart-54da91fc-9b8e-4705-94a0-2f79f1aaf342
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536635093 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl
_tl_intg_err.3536635093
Directory /workspace/7.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2439246259
Short name T1121
Test name
Test status
Simulation time 205316500 ps
CPU time 16.6 seconds
Started Mar 24 12:38:41 PM PDT 24
Finished Mar 24 12:39:02 PM PDT 24
Peak memory 271884 kb
Host smart-9e3d001e-e4ec-425a-b63e-feabdfbf6461
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439246259 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.2439246259
Directory /workspace/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.737778374
Short name T1137
Test name
Test status
Simulation time 28043900 ps
CPU time 16.35 seconds
Started Mar 24 12:39:13 PM PDT 24
Finished Mar 24 12:39:29 PM PDT 24
Peak memory 260096 kb
Host smart-2f0b6b6e-8c65-476e-9200-983b7bbfc835
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737778374 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 8.flash_ctrl_csr_rw.737778374
Directory /workspace/8.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.718159647
Short name T349
Test name
Test status
Simulation time 47884400 ps
CPU time 14.11 seconds
Started Mar 24 12:38:40 PM PDT 24
Finished Mar 24 12:38:54 PM PDT 24
Peak memory 262464 kb
Host smart-80071fc6-0836-4e2b-b31e-e236de500afc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718159647 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.718159647
Directory /workspace/8.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3761322023
Short name T1105
Test name
Test status
Simulation time 135592100 ps
CPU time 17.42 seconds
Started Mar 24 12:38:38 PM PDT 24
Finished Mar 24 12:38:56 PM PDT 24
Peak memory 261688 kb
Host smart-25c250d2-72cc-49ec-820a-c5b445ea15bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761322023 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.flash_ctrl_same_csr_outstanding.3761322023
Directory /workspace/8.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.3822586642
Short name T1065
Test name
Test status
Simulation time 33070800 ps
CPU time 15.91 seconds
Started Mar 24 12:38:49 PM PDT 24
Finished Mar 24 12:39:05 PM PDT 24
Peak memory 259908 kb
Host smart-2b777153-59b8-4fc4-a87f-749265ff13eb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822586642 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors.3822586642
Directory /workspace/8.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.4106826823
Short name T1171
Test name
Test status
Simulation time 18842100 ps
CPU time 15.35 seconds
Started Mar 24 12:38:44 PM PDT 24
Finished Mar 24 12:39:00 PM PDT 24
Peak memory 259840 kb
Host smart-c3412d8f-3754-42c9-8e0c-c6f16af86aec
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106826823 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors_with_csr_rw.4106826823
Directory /workspace/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.260219197
Short name T276
Test name
Test status
Simulation time 116773900 ps
CPU time 16.02 seconds
Started Mar 24 12:38:49 PM PDT 24
Finished Mar 24 12:39:06 PM PDT 24
Peak memory 260764 kb
Host smart-66f6f324-fcbb-48c9-9ef7-f40af3bdc505
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260219197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.260219197
Directory /workspace/8.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.372577322
Short name T1179
Test name
Test status
Simulation time 777020000 ps
CPU time 454.64 seconds
Started Mar 24 12:38:50 PM PDT 24
Finished Mar 24 12:46:25 PM PDT 24
Peak memory 260140 kb
Host smart-15036feb-b507-4676-97c0-a57abcb58b97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372577322 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_
tl_intg_err.372577322
Directory /workspace/8.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.3510663574
Short name T1100
Test name
Test status
Simulation time 163439800 ps
CPU time 18.68 seconds
Started Mar 24 12:38:54 PM PDT 24
Finished Mar 24 12:39:13 PM PDT 24
Peak memory 270944 kb
Host smart-ae4ddbca-b29e-435b-8a0e-8cb833b2e489
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510663574 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.3510663574
Directory /workspace/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.3444947998
Short name T1092
Test name
Test status
Simulation time 183096800 ps
CPU time 17.06 seconds
Started Mar 24 12:38:44 PM PDT 24
Finished Mar 24 12:39:01 PM PDT 24
Peak memory 259924 kb
Host smart-e90ec255-f905-407e-912e-132333eb0bcb
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444947998 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.flash_ctrl_csr_rw.3444947998
Directory /workspace/9.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.2579300975
Short name T1164
Test name
Test status
Simulation time 25011400 ps
CPU time 13.37 seconds
Started Mar 24 12:38:39 PM PDT 24
Finished Mar 24 12:38:53 PM PDT 24
Peak memory 262380 kb
Host smart-755ec4e9-2724-4ac0-9132-8f4dd0a93c59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579300975 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.2
579300975
Directory /workspace/9.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2940999004
Short name T1163
Test name
Test status
Simulation time 1518462300 ps
CPU time 19.21 seconds
Started Mar 24 12:38:38 PM PDT 24
Finished Mar 24 12:38:58 PM PDT 24
Peak memory 261420 kb
Host smart-4680c0c1-bc4a-40a1-b7ff-d1a6601ad9fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940999004 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.flash_ctrl_same_csr_outstanding.2940999004
Directory /workspace/9.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.659523588
Short name T1109
Test name
Test status
Simulation time 15447500 ps
CPU time 13.05 seconds
Started Mar 24 12:38:57 PM PDT 24
Finished Mar 24 12:39:10 PM PDT 24
Peak memory 259936 kb
Host smart-b8f8b0d0-9cf5-4dc9-811d-2baac5e96395
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659523588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.flash_ctrl_shadow_reg_errors.659523588
Directory /workspace/9.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2230489555
Short name T1135
Test name
Test status
Simulation time 26775800 ps
CPU time 13.27 seconds
Started Mar 24 12:39:08 PM PDT 24
Finished Mar 24 12:39:21 PM PDT 24
Peak memory 260300 kb
Host smart-c7c3dc0b-bd4f-49b7-8cbf-a78be301e23b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230489555 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors_with_csr_rw.2230489555
Directory /workspace/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.1605774288
Short name T246
Test name
Test status
Simulation time 168065900 ps
CPU time 18.05 seconds
Started Mar 24 12:38:45 PM PDT 24
Finished Mar 24 12:39:03 PM PDT 24
Peak memory 263644 kb
Host smart-52548dd9-256b-4a38-b08a-46fbc80399a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605774288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.1
605774288
Directory /workspace/9.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1623290498
Short name T274
Test name
Test status
Simulation time 335242000 ps
CPU time 455.76 seconds
Started Mar 24 12:39:01 PM PDT 24
Finished Mar 24 12:46:37 PM PDT 24
Peak memory 260124 kb
Host smart-a07d06bf-6d45-47e4-9f22-baf8b5842b06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623290498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl
_tl_intg_err.1623290498
Directory /workspace/9.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_alert_test.1872233394
Short name T577
Test name
Test status
Simulation time 100347800 ps
CPU time 13.64 seconds
Started Mar 24 02:15:30 PM PDT 24
Finished Mar 24 02:15:43 PM PDT 24
Peak memory 257992 kb
Host smart-2455c578-4885-47b9-9678-99a4232416c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872233394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.1
872233394
Directory /workspace/0.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.flash_ctrl_config_regwen.259510249
Short name T937
Test name
Test status
Simulation time 32540300 ps
CPU time 13.66 seconds
Started Mar 24 02:15:25 PM PDT 24
Finished Mar 24 02:15:39 PM PDT 24
Peak memory 264904 kb
Host smart-db128f15-ae18-468d-8348-adc94bbbff3f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259510249 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
flash_ctrl_config_regwen.259510249
Directory /workspace/0.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/0.flash_ctrl_connect.834824764
Short name T872
Test name
Test status
Simulation time 14978200 ps
CPU time 15.74 seconds
Started Mar 24 02:15:07 PM PDT 24
Finished Mar 24 02:15:23 PM PDT 24
Peak memory 274496 kb
Host smart-f593bb61-8b8f-47cf-9211-0c0b5b713574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834824764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.834824764
Directory /workspace/0.flash_ctrl_connect/latest

Test location /workspace/coverage/default/0.flash_ctrl_derr_detect.3653674416
Short name T264
Test name
Test status
Simulation time 333056600 ps
CPU time 103.41 seconds
Started Mar 24 02:14:34 PM PDT 24
Finished Mar 24 02:16:17 PM PDT 24
Peak memory 280544 kb
Host smart-d4899e9e-f31a-42c5-b6d8-825a63492e19
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653674416 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_derr_detect.3653674416
Directory /workspace/0.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/0.flash_ctrl_erase_suspend.3755356346
Short name T984
Test name
Test status
Simulation time 8854162500 ps
CPU time 501.4 seconds
Started Mar 24 02:13:44 PM PDT 24
Finished Mar 24 02:22:05 PM PDT 24
Peak memory 261124 kb
Host smart-03c2f49e-77d6-4515-8cc3-d328099f6ae6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3755356346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.3755356346
Directory /workspace/0.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/0.flash_ctrl_fetch_code.2584052900
Short name T53
Test name
Test status
Simulation time 754291300 ps
CPU time 21.79 seconds
Started Mar 24 02:13:49 PM PDT 24
Finished Mar 24 02:14:11 PM PDT 24
Peak memory 264808 kb
Host smart-b03c2ece-88cb-4ffa-bece-fde7a1537d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584052900 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetch_code.2584052900
Directory /workspace/0.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/0.flash_ctrl_fs_sup.1193252586
Short name T286
Test name
Test status
Simulation time 1060011700 ps
CPU time 37.1 seconds
Started Mar 24 02:15:18 PM PDT 24
Finished Mar 24 02:15:55 PM PDT 24
Peak memory 273120 kb
Host smart-c97b9977-b14c-4be0-9b58-443f3ecf8ceb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193252586 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.flash_ctrl_fs_sup.1193252586
Directory /workspace/0.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/0.flash_ctrl_full_mem_access.965731673
Short name T942
Test name
Test status
Simulation time 352889381200 ps
CPU time 2652.94 seconds
Started Mar 24 02:13:54 PM PDT 24
Finished Mar 24 02:58:08 PM PDT 24
Peak memory 261660 kb
Host smart-52096974-d139-469b-a217-e11c7ce346ac
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965731673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ct
rl_full_mem_access.965731673
Directory /workspace/0.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_ctrl_arb.1910737290
Short name T865
Test name
Test status
Simulation time 294882171600 ps
CPU time 2978.57 seconds
Started Mar 24 02:13:50 PM PDT 24
Finished Mar 24 03:03:29 PM PDT 24
Peak memory 264944 kb
Host smart-34bcf19e-54d8-453e-b0c2-7125810d74fa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910737290 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.flash_ctrl_host_ctrl_arb.1910737290
Directory /workspace/0.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_dir_rd.2537600076
Short name T770
Test name
Test status
Simulation time 87890400 ps
CPU time 37.53 seconds
Started Mar 24 02:13:28 PM PDT 24
Finished Mar 24 02:14:06 PM PDT 24
Peak memory 262328 kb
Host smart-edaec022-90d1-4a32-9a25-f8b9362347af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2537600076 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.2537600076
Directory /workspace/0.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_read_seed_err.3642166077
Short name T741
Test name
Test status
Simulation time 17145000 ps
CPU time 13.27 seconds
Started Mar 24 02:15:26 PM PDT 24
Finished Mar 24 02:15:39 PM PDT 24
Peak memory 264888 kb
Host smart-62ce82f9-5b00-4bb1-bec4-a772d282e489
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642166077 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.3642166077
Directory /workspace/0.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma.1407490362
Short name T1004
Test name
Test status
Simulation time 501961457800 ps
CPU time 2261.01 seconds
Started Mar 24 02:13:44 PM PDT 24
Finished Mar 24 02:51:25 PM PDT 24
Peak memory 263532 kb
Host smart-70dd1603-6cfc-4253-b8a2-f00c1fea47b0
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407490362 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.flash_ctrl_hw_rma.1407490362
Directory /workspace/0.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma_reset.174906807
Short name T790
Test name
Test status
Simulation time 160185465000 ps
CPU time 1017.79 seconds
Started Mar 24 02:13:44 PM PDT 24
Finished Mar 24 02:30:42 PM PDT 24
Peak memory 263000 kb
Host smart-d40dcf94-d5b0-41d2-b583-0b2377207396
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174906807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_hw_rma_reset.174906807
Directory /workspace/0.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_sec_otp.674123789
Short name T419
Test name
Test status
Simulation time 2450722200 ps
CPU time 178.38 seconds
Started Mar 24 02:13:42 PM PDT 24
Finished Mar 24 02:16:41 PM PDT 24
Peak memory 262372 kb
Host smart-0ef05489-ec11-4cfe-a210-19ef1c5c441e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674123789 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw
_sec_otp.674123789
Directory /workspace/0.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd_slow_flash.4033134727
Short name T792
Test name
Test status
Simulation time 9404858600 ps
CPU time 238.87 seconds
Started Mar 24 02:14:43 PM PDT 24
Finished Mar 24 02:18:42 PM PDT 24
Peak memory 284652 kb
Host smart-2977f649-822c-45b5-8086-901af9cbbf36
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033134727 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd_slow_flash.4033134727
Directory /workspace/0.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr.3671194213
Short name T590
Test name
Test status
Simulation time 6979939700 ps
CPU time 92.4 seconds
Started Mar 24 02:14:45 PM PDT 24
Finished Mar 24 02:16:17 PM PDT 24
Peak memory 261108 kb
Host smart-3c440631-4f84-473d-a133-678b78397ddb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671194213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.flash_ctrl_intr_wr.3671194213
Directory /workspace/0.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/0.flash_ctrl_invalid_op.1406791435
Short name T702
Test name
Test status
Simulation time 8566550500 ps
CPU time 69.78 seconds
Started Mar 24 02:14:15 PM PDT 24
Finished Mar 24 02:15:25 PM PDT 24
Peak memory 262488 kb
Host smart-61189e17-b334-47d1-8c43-e97dceb62f54
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406791435 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.1406791435
Directory /workspace/0.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_lcmgr_intg.2326538599
Short name T946
Test name
Test status
Simulation time 25641200 ps
CPU time 13.4 seconds
Started Mar 24 02:15:25 PM PDT 24
Finished Mar 24 02:15:39 PM PDT 24
Peak memory 264876 kb
Host smart-3e89387d-0c6b-42c4-b631-29f833ded5d3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326538599 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_lcmgr_intg.2326538599
Directory /workspace/0.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_mid_op_rst.2158311761
Short name T126
Test name
Test status
Simulation time 1741029800 ps
CPU time 70.71 seconds
Started Mar 24 02:14:20 PM PDT 24
Finished Mar 24 02:15:31 PM PDT 24
Peak memory 264732 kb
Host smart-d253eb42-b129-40e4-8c9c-b6c1ab199ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158311761 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.2158311761
Directory /workspace/0.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/0.flash_ctrl_mp_regions.3488382474
Short name T237
Test name
Test status
Simulation time 17023366800 ps
CPU time 295.49 seconds
Started Mar 24 02:13:48 PM PDT 24
Finished Mar 24 02:18:43 PM PDT 24
Peak memory 274020 kb
Host smart-17248434-fd71-46e5-a446-c2375b357bac
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488382474 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_mp_regions.3488382474
Directory /workspace/0.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/0.flash_ctrl_otp_reset.2982295915
Short name T524
Test name
Test status
Simulation time 78076500 ps
CPU time 130.17 seconds
Started Mar 24 02:13:48 PM PDT 24
Finished Mar 24 02:15:59 PM PDT 24
Peak memory 259452 kb
Host smart-ed2ad8e7-5b6e-4135-a798-da2d9b3fe62e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982295915 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ot
p_reset.2982295915
Directory /workspace/0.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb.572488092
Short name T868
Test name
Test status
Simulation time 41933600 ps
CPU time 111.25 seconds
Started Mar 24 02:13:34 PM PDT 24
Finished Mar 24 02:15:25 PM PDT 24
Peak memory 262304 kb
Host smart-dbefc9e2-46e6-4736-b530-4b02b1e5c978
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=572488092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.572488092
Directory /workspace/0.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_prog_reset.3211865267
Short name T125
Test name
Test status
Simulation time 34843900 ps
CPU time 13.53 seconds
Started Mar 24 02:14:49 PM PDT 24
Finished Mar 24 02:15:03 PM PDT 24
Peak memory 260036 kb
Host smart-89c7932c-b199-4afd-a731-fffcb98b599f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211865267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_prog_res
et.3211865267
Directory /workspace/0.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_rand_ops.663117855
Short name T866
Test name
Test status
Simulation time 31881300 ps
CPU time 100.16 seconds
Started Mar 24 02:13:27 PM PDT 24
Finished Mar 24 02:15:08 PM PDT 24
Peak memory 275064 kb
Host smart-9037bafc-fcf3-48be-9c2a-0e5441578f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663117855 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.663117855
Directory /workspace/0.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_intg.3281168407
Short name T837
Test name
Test status
Simulation time 270198700 ps
CPU time 32.31 seconds
Started Mar 24 02:15:07 PM PDT 24
Finished Mar 24 02:15:40 PM PDT 24
Peak memory 274200 kb
Host smart-640872c1-f2ec-44ba-9740-627d02600ffb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281168407 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_rd_intg.3281168407
Directory /workspace/0.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_ooo.1188933022
Short name T616
Test name
Test status
Simulation time 93555400 ps
CPU time 43.68 seconds
Started Mar 24 02:15:29 PM PDT 24
Finished Mar 24 02:16:13 PM PDT 24
Peak memory 275292 kb
Host smart-73e1ddf6-585b-490d-b1f0-8d40b6ba1087
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188933022 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_rd_ooo.1188933022
Directory /workspace/0.flash_ctrl_rd_ooo/latest

Test location /workspace/coverage/default/0.flash_ctrl_re_evict.2704512290
Short name T406
Test name
Test status
Simulation time 569395400 ps
CPU time 39.63 seconds
Started Mar 24 02:14:49 PM PDT 24
Finished Mar 24 02:15:29 PM PDT 24
Peak memory 274324 kb
Host smart-a52596a1-86db-4f52-b80d-07eb625682ae
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704512290 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_re_evict.2704512290
Directory /workspace/0.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep.1559242887
Short name T414
Test name
Test status
Simulation time 41261100 ps
CPU time 14.22 seconds
Started Mar 24 02:14:20 PM PDT 24
Finished Mar 24 02:14:35 PM PDT 24
Peak memory 257796 kb
Host smart-0f6998f8-25f0-4847-a123-6102d3b2d73e
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1559242887 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep
.1559242887
Directory /workspace/0.flash_ctrl_read_word_sweep/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_derr.3060874714
Short name T755
Test name
Test status
Simulation time 136539900 ps
CPU time 22.55 seconds
Started Mar 24 02:14:28 PM PDT 24
Finished Mar 24 02:14:51 PM PDT 24
Peak memory 264932 kb
Host smart-58f6944c-914a-4af4-91a5-0ccb72d5fe89
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060874714 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_derr.3060874714
Directory /workspace/0.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_serr.573271321
Short name T185
Test name
Test status
Simulation time 202723400 ps
CPU time 22.05 seconds
Started Mar 24 02:14:22 PM PDT 24
Finished Mar 24 02:14:45 PM PDT 24
Peak memory 264224 kb
Host smart-5176c227-7f2f-4ee8-b9c0-0424d8e6390d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573271321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_read_word_sweep_serr.573271321
Directory /workspace/0.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rma_err.402112663
Short name T150
Test name
Test status
Simulation time 497821797800 ps
CPU time 1302.71 seconds
Started Mar 24 02:15:26 PM PDT 24
Finished Mar 24 02:37:09 PM PDT 24
Peak memory 259116 kb
Host smart-9da0c086-70f4-49c1-91f2-c5bc571f5648
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402112663 -assert nopostproc +UVM_TEST
NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rma_err.402112663
Directory /workspace/0.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_serr.3948999058
Short name T170
Test name
Test status
Simulation time 531906600 ps
CPU time 136.48 seconds
Started Mar 24 02:14:23 PM PDT 24
Finished Mar 24 02:16:41 PM PDT 24
Peak memory 281452 kb
Host smart-3ea3463e-3d33-4126-bace-4b1d9da711ea
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948999058 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.flash_ctrl_ro_serr.3948999058
Directory /workspace/0.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw.4203677343
Short name T961
Test name
Test status
Simulation time 3386133200 ps
CPU time 467.09 seconds
Started Mar 24 02:14:23 PM PDT 24
Finished Mar 24 02:22:12 PM PDT 24
Peak memory 314068 kb
Host smart-b53eb271-ef3e-4330-8d30-ef624ebb9cf3
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203677343 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ct
rl_rw.4203677343
Directory /workspace/0.flash_ctrl_rw/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict.3997596501
Short name T871
Test name
Test status
Simulation time 32429200 ps
CPU time 31.18 seconds
Started Mar 24 02:14:51 PM PDT 24
Finished Mar 24 02:15:22 PM PDT 24
Peak memory 267204 kb
Host smart-e27dfc50-f84c-42cc-b659-cea36cecf72f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997596501 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_rw_evict.3997596501
Directory /workspace/0.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict_all_en.1061784373
Short name T940
Test name
Test status
Simulation time 36108400 ps
CPU time 31.31 seconds
Started Mar 24 02:14:52 PM PDT 24
Finished Mar 24 02:15:24 PM PDT 24
Peak memory 274316 kb
Host smart-e8b38486-92b5-4ea3-9659-c67957794e84
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061784373 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict_all_en.1061784373
Directory /workspace/0.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_address.1513061757
Short name T995
Test name
Test status
Simulation time 3461158300 ps
CPU time 89.6 seconds
Started Mar 24 02:14:27 PM PDT 24
Finished Mar 24 02:15:57 PM PDT 24
Peak memory 273340 kb
Host smart-444ee86d-31a8-4a17-aede-eeb2c627c81b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513061757 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_serr_address.1513061757
Directory /workspace/0.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_counter.1598802103
Short name T193
Test name
Test status
Simulation time 1428601300 ps
CPU time 80.71 seconds
Started Mar 24 02:14:29 PM PDT 24
Finished Mar 24 02:15:50 PM PDT 24
Peak memory 273280 kb
Host smart-40650719-91d7-4a6a-b57a-f67289edd1a4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598802103 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_serr_counter.1598802103
Directory /workspace/0.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke.4176645044
Short name T1026
Test name
Test status
Simulation time 29462400 ps
CPU time 145.04 seconds
Started Mar 24 02:13:20 PM PDT 24
Finished Mar 24 02:15:46 PM PDT 24
Peak memory 277108 kb
Host smart-14107106-c294-453b-bc5a-86a2083b24c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176645044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.4176645044
Directory /workspace/0.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke_hw.3702027377
Short name T1025
Test name
Test status
Simulation time 29221400 ps
CPU time 23.33 seconds
Started Mar 24 02:13:23 PM PDT 24
Finished Mar 24 02:13:46 PM PDT 24
Peak memory 258620 kb
Host smart-13dec3c6-9712-4f4a-8a7e-6706a99c43a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702027377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.3702027377
Directory /workspace/0.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/0.flash_ctrl_stress_all.2898779293
Short name T748
Test name
Test status
Simulation time 1697016200 ps
CPU time 1084.68 seconds
Started Mar 24 02:15:07 PM PDT 24
Finished Mar 24 02:33:12 PM PDT 24
Peak memory 285472 kb
Host smart-8d22c94c-d64c-488a-8894-17256c45fb36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898779293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stres
s_all.2898779293
Directory /workspace/0.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.flash_ctrl_sw_op.1998865532
Short name T765
Test name
Test status
Simulation time 77154100 ps
CPU time 26.65 seconds
Started Mar 24 02:13:27 PM PDT 24
Finished Mar 24 02:13:55 PM PDT 24
Peak memory 261448 kb
Host smart-5865921a-3ce0-4da0-8257-51db2a9cfa6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998865532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.1998865532
Directory /workspace/0.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_wo.55089568
Short name T498
Test name
Test status
Simulation time 2160525800 ps
CPU time 157.74 seconds
Started Mar 24 02:14:19 PM PDT 24
Finished Mar 24 02:16:57 PM PDT 24
Peak memory 259404 kb
Host smart-6ef69fff-e8ce-46f8-9c2d-6aeffdafdad6
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55089568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.flash_ctrl_wo.55089568
Directory /workspace/0.flash_ctrl_wo/latest

Test location /workspace/coverage/default/0.flash_ctrl_write_word_sweep.3892852107
Short name T860
Test name
Test status
Simulation time 63296900 ps
CPU time 17.33 seconds
Started Mar 24 02:14:20 PM PDT 24
Finished Mar 24 02:14:37 PM PDT 24
Peak memory 264740 kb
Host smart-30812d1a-c737-412e-8ca0-ab0f4fab4bcb
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3892852107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_swe
ep.3892852107
Directory /workspace/0.flash_ctrl_write_word_sweep/latest

Test location /workspace/coverage/default/1.flash_ctrl_alert_test.1619489663
Short name T412
Test name
Test status
Simulation time 91747100 ps
CPU time 13.53 seconds
Started Mar 24 02:16:58 PM PDT 24
Finished Mar 24 02:17:12 PM PDT 24
Peak memory 264944 kb
Host smart-7da693db-0c5a-435a-87ce-4bc68aaecbd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619489663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.1
619489663
Directory /workspace/1.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.flash_ctrl_config_regwen.889823286
Short name T266
Test name
Test status
Simulation time 70686800 ps
CPU time 13.67 seconds
Started Mar 24 02:16:51 PM PDT 24
Finished Mar 24 02:17:04 PM PDT 24
Peak memory 261812 kb
Host smart-13867e71-19d4-4bed-ae1c-58ac26eeb226
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889823286 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
flash_ctrl_config_regwen.889823286
Directory /workspace/1.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/1.flash_ctrl_connect.2516761375
Short name T773
Test name
Test status
Simulation time 72658500 ps
CPU time 13.2 seconds
Started Mar 24 02:16:41 PM PDT 24
Finished Mar 24 02:16:54 PM PDT 24
Peak memory 275560 kb
Host smart-3bbf173e-80e7-4743-9d96-0c6a190bdd9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516761375 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.2516761375
Directory /workspace/1.flash_ctrl_connect/latest

Test location /workspace/coverage/default/1.flash_ctrl_derr_detect.690502355
Short name T1010
Test name
Test status
Simulation time 322281200 ps
CPU time 106.26 seconds
Started Mar 24 02:16:13 PM PDT 24
Finished Mar 24 02:17:59 PM PDT 24
Peak memory 273324 kb
Host smart-ed56e0ec-2383-4843-99ed-9e32135cc356
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690502355 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.flash_ctrl_derr_detect.690502355
Directory /workspace/1.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_mp.2701612982
Short name T588
Test name
Test status
Simulation time 30532577800 ps
CPU time 2297.86 seconds
Started Mar 24 02:15:58 PM PDT 24
Finished Mar 24 02:54:16 PM PDT 24
Peak memory 264828 kb
Host smart-057e6180-7907-4564-9178-18072a9375dc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701612982 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_err
or_mp.2701612982
Directory /workspace/1.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_type.3053664246
Short name T160
Test name
Test status
Simulation time 2569971000 ps
CPU time 2918.82 seconds
Started Mar 24 02:15:57 PM PDT 24
Finished Mar 24 03:04:37 PM PDT 24
Peak memory 264048 kb
Host smart-b2b96a97-0ae3-4160-b72f-523c46a9199b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053664246 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_type.3053664246
Directory /workspace/1.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_win.3937560450
Short name T299
Test name
Test status
Simulation time 655525600 ps
CPU time 766.73 seconds
Started Mar 24 02:15:58 PM PDT 24
Finished Mar 24 02:28:45 PM PDT 24
Peak memory 264864 kb
Host smart-5d005674-f1d0-4b21-bd06-277af74b7b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937560450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.3937560450
Directory /workspace/1.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/1.flash_ctrl_fetch_code.1229391431
Short name T1028
Test name
Test status
Simulation time 151118800 ps
CPU time 25.98 seconds
Started Mar 24 02:16:00 PM PDT 24
Finished Mar 24 02:16:26 PM PDT 24
Peak memory 264780 kb
Host smart-3183ef1a-9bab-426c-ba83-8d5fcdacdffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229391431 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetch_code.1229391431
Directory /workspace/1.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/1.flash_ctrl_fs_sup.141615394
Short name T289
Test name
Test status
Simulation time 665089300 ps
CPU time 40.01 seconds
Started Mar 24 02:16:43 PM PDT 24
Finished Mar 24 02:17:23 PM PDT 24
Peak memory 273140 kb
Host smart-e004d1f9-0145-4d84-b95e-b7ef09b6b985
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141615394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_fs_sup.141615394
Directory /workspace/1.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/1.flash_ctrl_full_mem_access.2059950437
Short name T93
Test name
Test status
Simulation time 49892943900 ps
CPU time 4328.84 seconds
Started Mar 24 02:15:58 PM PDT 24
Finished Mar 24 03:28:08 PM PDT 24
Peak memory 264840 kb
Host smart-73bb0c8f-10d5-457c-99c8-4d05ddebe3a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059950437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_c
trl_full_mem_access.2059950437
Directory /workspace/1.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_dir_rd.2759074776
Short name T769
Test name
Test status
Simulation time 187262800 ps
CPU time 59.65 seconds
Started Mar 24 02:15:43 PM PDT 24
Finished Mar 24 02:16:44 PM PDT 24
Peak memory 264784 kb
Host smart-8b8ae132-29cf-4f56-9e9b-f54b98e93cee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2759074776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.2759074776
Directory /workspace/1.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.1526530809
Short name T899
Test name
Test status
Simulation time 10012508700 ps
CPU time 130.14 seconds
Started Mar 24 02:16:52 PM PDT 24
Finished Mar 24 02:19:02 PM PDT 24
Peak memory 328536 kb
Host smart-8214173f-3a7a-44e9-b6a7-4698daf5c84a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526530809 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.1526530809
Directory /workspace/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_read_seed_err.1769408478
Short name T291
Test name
Test status
Simulation time 64303500 ps
CPU time 13.76 seconds
Started Mar 24 02:16:52 PM PDT 24
Finished Mar 24 02:17:05 PM PDT 24
Peak memory 265016 kb
Host smart-661c88cd-49b7-480e-b3a5-981f1970187b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769408478 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_read_seed_err.1769408478
Directory /workspace/1.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma.1181974929
Short name T672
Test name
Test status
Simulation time 277579139300 ps
CPU time 2014.91 seconds
Started Mar 24 02:15:49 PM PDT 24
Finished Mar 24 02:49:24 PM PDT 24
Peak memory 263556 kb
Host smart-f6047c57-5a56-4f27-95ba-334feae3d97e
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181974929 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.flash_ctrl_hw_rma.1181974929
Directory /workspace/1.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma_reset.1161256658
Short name T76
Test name
Test status
Simulation time 170173952200 ps
CPU time 825.2 seconds
Started Mar 24 02:15:48 PM PDT 24
Finished Mar 24 02:29:34 PM PDT 24
Peak memory 264260 kb
Host smart-32ee9e47-d09e-429e-91ee-8dc3a0370df7
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161256658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.flash_ctrl_hw_rma_reset.1161256658
Directory /workspace/1.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_sec_otp.3276086813
Short name T319
Test name
Test status
Simulation time 4296245700 ps
CPU time 139.24 seconds
Started Mar 24 02:15:51 PM PDT 24
Finished Mar 24 02:18:10 PM PDT 24
Peak memory 262468 kb
Host smart-9bc8c6c5-181c-4bf8-a714-405bf0a49a4c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276086813 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_h
w_sec_otp.3276086813
Directory /workspace/1.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.3750048510
Short name T195
Test name
Test status
Simulation time 11190394000 ps
CPU time 227.81 seconds
Started Mar 24 02:16:16 PM PDT 24
Finished Mar 24 02:20:04 PM PDT 24
Peak memory 284628 kb
Host smart-5edae9c6-4949-4913-9147-ef4f18f33468
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750048510 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd_slow_flash.3750048510
Directory /workspace/1.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr.176027848
Short name T436
Test name
Test status
Simulation time 3910468200 ps
CPU time 85.43 seconds
Started Mar 24 02:16:12 PM PDT 24
Finished Mar 24 02:17:38 PM PDT 24
Peak memory 265012 kb
Host smart-14e4a647-589c-4f2a-82a7-aee4381d7fc3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176027848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.flash_ctrl_intr_wr.176027848
Directory /workspace/1.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr_slow_flash.1028942210
Short name T887
Test name
Test status
Simulation time 52710758700 ps
CPU time 366.81 seconds
Started Mar 24 02:16:21 PM PDT 24
Finished Mar 24 02:22:28 PM PDT 24
Peak memory 264564 kb
Host smart-4e913df6-4beb-4f9f-88a6-11f62e245226
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102
8942210 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.1028942210
Directory /workspace/1.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_invalid_op.1683830610
Short name T847
Test name
Test status
Simulation time 4204672600 ps
CPU time 73.4 seconds
Started Mar 24 02:15:57 PM PDT 24
Finished Mar 24 02:17:10 PM PDT 24
Peak memory 259736 kb
Host smart-5031cbfb-0495-49f0-903f-a6e5826a4d5a
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683830610 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.1683830610
Directory /workspace/1.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_lcmgr_intg.1063784439
Short name T945
Test name
Test status
Simulation time 25837600 ps
CPU time 13.56 seconds
Started Mar 24 02:16:53 PM PDT 24
Finished Mar 24 02:17:07 PM PDT 24
Peak memory 259740 kb
Host smart-f088ef93-f161-432a-9f06-845a6d9db1c3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063784439 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_lcmgr_intg.1063784439
Directory /workspace/1.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_mp_regions.2464857844
Short name T113
Test name
Test status
Simulation time 17322716500 ps
CPU time 424.13 seconds
Started Mar 24 02:15:53 PM PDT 24
Finished Mar 24 02:22:57 PM PDT 24
Peak memory 273684 kb
Host smart-6dafde32-b280-41e7-a718-37cb30048064
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464857844 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_mp_regions.2464857844
Directory /workspace/1.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/1.flash_ctrl_otp_reset.1732979037
Short name T139
Test name
Test status
Simulation time 77333800 ps
CPU time 130.81 seconds
Started Mar 24 02:15:54 PM PDT 24
Finished Mar 24 02:18:04 PM PDT 24
Peak memory 259888 kb
Host smart-808509b7-dfd6-4cfe-a19e-3096b0f715b6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732979037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ot
p_reset.1732979037
Directory /workspace/1.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_oversize_error.3203936313
Short name T726
Test name
Test status
Simulation time 6253374200 ps
CPU time 231.97 seconds
Started Mar 24 02:16:13 PM PDT 24
Finished Mar 24 02:20:05 PM PDT 24
Peak memory 281504 kb
Host smart-f00d52a5-1c37-4f75-845d-9435e286054e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203936313 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_oversize_error.3203936313
Directory /workspace/1.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb.1145150333
Short name T688
Test name
Test status
Simulation time 101113400 ps
CPU time 65.6 seconds
Started Mar 24 02:15:48 PM PDT 24
Finished Mar 24 02:16:55 PM PDT 24
Peak memory 264720 kb
Host smart-8c4955cb-02e6-41a7-bdcf-4c77a943aa04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1145150333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.1145150333
Directory /workspace/1.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb_redun.1188703450
Short name T79
Test name
Test status
Simulation time 926734200 ps
CPU time 28.45 seconds
Started Mar 24 02:16:43 PM PDT 24
Finished Mar 24 02:17:12 PM PDT 24
Peak memory 265056 kb
Host smart-b4d64b59-737c-4e98-950f-ee1cf0ff7180
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188703450 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.1188703450
Directory /workspace/1.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_host_grant_err.3247426856
Short name T205
Test name
Test status
Simulation time 19042100 ps
CPU time 13.87 seconds
Started Mar 24 02:16:49 PM PDT 24
Finished Mar 24 02:17:03 PM PDT 24
Peak memory 265056 kb
Host smart-30cebd09-e44a-4f8c-903d-8e5f4523748a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247426856 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.3247426856
Directory /workspace/1.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_prog_reset.1432637917
Short name T1043
Test name
Test status
Simulation time 22990195300 ps
CPU time 325.7 seconds
Started Mar 24 02:16:27 PM PDT 24
Finished Mar 24 02:21:54 PM PDT 24
Peak memory 264912 kb
Host smart-34e7966a-991d-42ba-95d5-eacce98e5eab
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432637917 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_prog_res
et.1432637917
Directory /workspace/1.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_rand_ops.3495849629
Short name T526
Test name
Test status
Simulation time 542231200 ps
CPU time 761.54 seconds
Started Mar 24 02:15:39 PM PDT 24
Finished Mar 24 02:28:21 PM PDT 24
Peak memory 282216 kb
Host smart-c5e7f496-f277-41b4-8afb-3931da959297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495849629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.3495849629
Directory /workspace/1.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_buff_evict.402466082
Short name T284
Test name
Test status
Simulation time 296720200 ps
CPU time 99.41 seconds
Started Mar 24 02:15:43 PM PDT 24
Finished Mar 24 02:17:23 PM PDT 24
Peak memory 265040 kb
Host smart-d0cba012-6294-41d7-b940-15fcd795527c
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=402466082 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.402466082
Directory /workspace/1.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_intg.2154196598
Short name T836
Test name
Test status
Simulation time 296801700 ps
CPU time 31.68 seconds
Started Mar 24 02:16:38 PM PDT 24
Finished Mar 24 02:17:10 PM PDT 24
Peak memory 273444 kb
Host smart-66b32d4a-efb2-4e8f-8ab9-e6f6715bfca8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154196598 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_rd_intg.2154196598
Directory /workspace/1.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_re_evict.4126744582
Short name T1022
Test name
Test status
Simulation time 227554400 ps
CPU time 39.07 seconds
Started Mar 24 02:16:34 PM PDT 24
Finished Mar 24 02:17:13 PM PDT 24
Peak memory 273264 kb
Host smart-ebb94a67-0e26-4787-b609-3e58d8bd6a49
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126744582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_re_evict.4126744582
Directory /workspace/1.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_derr.1792192830
Short name T204
Test name
Test status
Simulation time 59744600 ps
CPU time 22.49 seconds
Started Mar 24 02:16:06 PM PDT 24
Finished Mar 24 02:16:29 PM PDT 24
Peak memory 265084 kb
Host smart-b5beb6e7-359a-4068-8d8d-b971da6fa6e7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792192830 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_derr.1792192830
Directory /workspace/1.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_serr.1984508041
Short name T538
Test name
Test status
Simulation time 128009800 ps
CPU time 21.15 seconds
Started Mar 24 02:16:03 PM PDT 24
Finished Mar 24 02:16:24 PM PDT 24
Peak memory 265028 kb
Host smart-e964e145-7e99-4060-a98d-6b9bec173756
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984508041 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fl
ash_ctrl_read_word_sweep_serr.1984508041
Directory /workspace/1.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rma_err.2312087731
Short name T151
Test name
Test status
Simulation time 113033596300 ps
CPU time 902.51 seconds
Started Mar 24 02:16:53 PM PDT 24
Finished Mar 24 02:31:56 PM PDT 24
Peak memory 259008 kb
Host smart-7ee0947c-6623-47d3-9cfb-acb0f204c0cb
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312087731 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rma_err.2312087731
Directory /workspace/1.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro.2286752437
Short name T247
Test name
Test status
Simulation time 8441765100 ps
CPU time 147.49 seconds
Started Mar 24 02:16:00 PM PDT 24
Finished Mar 24 02:18:27 PM PDT 24
Peak memory 280804 kb
Host smart-c21a977d-b3c8-4786-968b-38ee3c99d860
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286752437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.flash_ctrl_ro.2286752437
Directory /workspace/1.flash_ctrl_ro/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw.1661548426
Short name T101
Test name
Test status
Simulation time 14670095900 ps
CPU time 536.43 seconds
Started Mar 24 02:16:00 PM PDT 24
Finished Mar 24 02:24:56 PM PDT 24
Peak memory 314188 kb
Host smart-fec17611-b9ad-42c1-91a9-22e391fcd684
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661548426 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ct
rl_rw.1661548426
Directory /workspace/1.flash_ctrl_rw/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict.1773912081
Short name T891
Test name
Test status
Simulation time 82983800 ps
CPU time 32.89 seconds
Started Mar 24 02:16:27 PM PDT 24
Finished Mar 24 02:17:01 PM PDT 24
Peak memory 273308 kb
Host smart-82dcc1cd-f9a9-4327-9f56-f04d1f5805db
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773912081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_rw_evict.1773912081
Directory /workspace/1.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict_all_en.2691334920
Short name T762
Test name
Test status
Simulation time 131154100 ps
CPU time 37.07 seconds
Started Mar 24 02:16:27 PM PDT 24
Finished Mar 24 02:17:05 PM PDT 24
Peak memory 266048 kb
Host smart-0b7b8429-17eb-4d94-b4f8-8ddf7a7ab053
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691334920 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict_all_en.2691334920
Directory /workspace/1.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_address.2588743621
Short name T883
Test name
Test status
Simulation time 1271817100 ps
CPU time 68 seconds
Started Mar 24 02:16:06 PM PDT 24
Finished Mar 24 02:17:15 PM PDT 24
Peak memory 265104 kb
Host smart-e7deff6b-183d-4ba3-8c26-4afaa13fc8ed
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588743621 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_serr_address.2588743621
Directory /workspace/1.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_counter.1273433126
Short name T190
Test name
Test status
Simulation time 1830269600 ps
CPU time 92.55 seconds
Started Mar 24 02:16:09 PM PDT 24
Finished Mar 24 02:17:42 PM PDT 24
Peak memory 273404 kb
Host smart-fdd59009-8070-416f-affc-7c8d7705432f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273433126 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_serr_counter.1273433126
Directory /workspace/1.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke.3690113500
Short name T737
Test name
Test status
Simulation time 104690800 ps
CPU time 118.87 seconds
Started Mar 24 02:15:34 PM PDT 24
Finished Mar 24 02:17:32 PM PDT 24
Peak memory 275500 kb
Host smart-305bf81b-406a-422b-94cb-1a65610bca20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690113500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.3690113500
Directory /workspace/1.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke_hw.1872613181
Short name T510
Test name
Test status
Simulation time 15877100 ps
CPU time 25.95 seconds
Started Mar 24 02:15:34 PM PDT 24
Finished Mar 24 02:16:01 PM PDT 24
Peak memory 258700 kb
Host smart-ddc5b8d8-ae35-429b-8056-ed850d95fcb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872613181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.1872613181
Directory /workspace/1.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/1.flash_ctrl_stress_all.3246529000
Short name T830
Test name
Test status
Simulation time 277883900 ps
CPU time 628.94 seconds
Started Mar 24 02:16:39 PM PDT 24
Finished Mar 24 02:27:08 PM PDT 24
Peak memory 281004 kb
Host smart-3a92926e-6868-4e77-bb97-e11c2a914328
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246529000 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stres
s_all.3246529000
Directory /workspace/1.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.flash_ctrl_sw_op.2726712704
Short name T480
Test name
Test status
Simulation time 85194100 ps
CPU time 26.83 seconds
Started Mar 24 02:15:39 PM PDT 24
Finished Mar 24 02:16:06 PM PDT 24
Peak memory 261320 kb
Host smart-c64430cf-7181-4665-b3be-d832ab04dfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726712704 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.2726712704
Directory /workspace/1.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_wo.3778370394
Short name T507
Test name
Test status
Simulation time 2294831400 ps
CPU time 167.27 seconds
Started Mar 24 02:15:57 PM PDT 24
Finished Mar 24 02:18:45 PM PDT 24
Peak memory 259492 kb
Host smart-b6bc4e5b-1ee0-4658-8ff4-99fcbdad15ce
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778370394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.flash_ctrl_wo.3778370394
Directory /workspace/1.flash_ctrl_wo/latest

Test location /workspace/coverage/default/10.flash_ctrl_alert_test.2311459373
Short name T435
Test name
Test status
Simulation time 51691900 ps
CPU time 13.45 seconds
Started Mar 24 02:24:23 PM PDT 24
Finished Mar 24 02:24:37 PM PDT 24
Peak memory 258640 kb
Host smart-2aee55ae-635f-482e-9207-24c84d59e56a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311459373 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.
2311459373
Directory /workspace/10.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.flash_ctrl_connect.667216845
Short name T831
Test name
Test status
Simulation time 42460100 ps
CPU time 13.25 seconds
Started Mar 24 02:24:19 PM PDT 24
Finished Mar 24 02:24:33 PM PDT 24
Peak memory 275092 kb
Host smart-b8f3f08c-b278-4515-a666-77c2dc01c48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667216845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.667216845
Directory /workspace/10.flash_ctrl_connect/latest

Test location /workspace/coverage/default/10.flash_ctrl_disable.2906185412
Short name T917
Test name
Test status
Simulation time 11391800 ps
CPU time 21.68 seconds
Started Mar 24 02:24:19 PM PDT 24
Finished Mar 24 02:24:41 PM PDT 24
Peak memory 273192 kb
Host smart-d188f94b-98ab-4d2e-8c54-0787d5d42682
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906185412 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_disable.2906185412
Directory /workspace/10.flash_ctrl_disable/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.2287654273
Short name T888
Test name
Test status
Simulation time 10019608100 ps
CPU time 90.16 seconds
Started Mar 24 02:24:24 PM PDT 24
Finished Mar 24 02:25:54 PM PDT 24
Peak memory 329956 kb
Host smart-8307ffed-0f4c-47fb-a7c2-89ed3a556b88
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287654273 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.2287654273
Directory /workspace/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_read_seed_err.998562511
Short name T579
Test name
Test status
Simulation time 52793600 ps
CPU time 13.35 seconds
Started Mar 24 02:24:23 PM PDT 24
Finished Mar 24 02:24:36 PM PDT 24
Peak memory 259968 kb
Host smart-23766d8f-2735-4545-bf7b-7190d1a989b9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998562511 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_seed_err.998562511
Directory /workspace/10.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_rma_reset.4196225127
Short name T154
Test name
Test status
Simulation time 80135860200 ps
CPU time 806.34 seconds
Started Mar 24 02:24:05 PM PDT 24
Finished Mar 24 02:37:32 PM PDT 24
Peak memory 263132 kb
Host smart-ecdbd1ec-c16a-4ec1-aec3-77c18810a133
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196225127 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.flash_ctrl_hw_rma_reset.4196225127
Directory /workspace/10.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_sec_otp.966428490
Short name T780
Test name
Test status
Simulation time 4164473300 ps
CPU time 117.52 seconds
Started Mar 24 02:24:06 PM PDT 24
Finished Mar 24 02:26:04 PM PDT 24
Peak memory 262220 kb
Host smart-24b28491-dbd4-4b75-a0a5-3ac581b15050
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966428490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_h
w_sec_otp.966428490
Directory /workspace/10.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd_slow_flash.3525224978
Short name T333
Test name
Test status
Simulation time 33367011200 ps
CPU time 217.8 seconds
Started Mar 24 02:24:10 PM PDT 24
Finished Mar 24 02:27:48 PM PDT 24
Peak memory 289464 kb
Host smart-57e38ea8-0a1e-4f87-af22-f3af2ac2d4ef
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525224978 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd_slow_flash.3525224978
Directory /workspace/10.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/10.flash_ctrl_invalid_op.4258050277
Short name T703
Test name
Test status
Simulation time 2093623100 ps
CPU time 71.96 seconds
Started Mar 24 02:24:11 PM PDT 24
Finished Mar 24 02:25:24 PM PDT 24
Peak memory 262556 kb
Host smart-6c7a4024-5e1e-4778-92d0-54ab84528396
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258050277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.4
258050277
Directory /workspace/10.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/10.flash_ctrl_lcmgr_intg.3865164554
Short name T603
Test name
Test status
Simulation time 34265800 ps
CPU time 13.31 seconds
Started Mar 24 02:24:19 PM PDT 24
Finished Mar 24 02:24:33 PM PDT 24
Peak memory 264940 kb
Host smart-78fc63f7-7218-444c-a02c-ca2eb6e84ed4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865164554 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.flash_ctrl_lcmgr_intg.3865164554
Directory /workspace/10.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/10.flash_ctrl_mp_regions.1396497915
Short name T668
Test name
Test status
Simulation time 8784700700 ps
CPU time 167.53 seconds
Started Mar 24 02:24:05 PM PDT 24
Finished Mar 24 02:26:53 PM PDT 24
Peak memory 264904 kb
Host smart-cd023a99-8366-4d76-bc1d-f52ca5d7b111
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396497915 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.flash_ctrl_mp_regions.1396497915
Directory /workspace/10.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/10.flash_ctrl_otp_reset.3974638526
Short name T613
Test name
Test status
Simulation time 139086600 ps
CPU time 133.3 seconds
Started Mar 24 02:24:05 PM PDT 24
Finished Mar 24 02:26:19 PM PDT 24
Peak memory 264536 kb
Host smart-3bb7c1ce-2bab-49ed-ae93-945e240dadf3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974638526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_o
tp_reset.3974638526
Directory /workspace/10.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_phy_arb.3729658230
Short name T775
Test name
Test status
Simulation time 74450900 ps
CPU time 69.42 seconds
Started Mar 24 02:24:04 PM PDT 24
Finished Mar 24 02:25:14 PM PDT 24
Peak memory 262280 kb
Host smart-62d2c86a-e120-41c7-a27b-942cddac1add
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3729658230 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.3729658230
Directory /workspace/10.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/10.flash_ctrl_prog_reset.3274484376
Short name T1012
Test name
Test status
Simulation time 33468300 ps
CPU time 13.44 seconds
Started Mar 24 02:24:12 PM PDT 24
Finished Mar 24 02:24:25 PM PDT 24
Peak memory 259964 kb
Host smart-307ca82d-19f8-4df4-a393-5d35138e0260
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274484376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_prog_re
set.3274484376
Directory /workspace/10.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_re_evict.1588538179
Short name T963
Test name
Test status
Simulation time 123796800 ps
CPU time 33.82 seconds
Started Mar 24 02:24:20 PM PDT 24
Finished Mar 24 02:24:54 PM PDT 24
Peak memory 266112 kb
Host smart-f0dcd1d5-9177-4882-be9f-170a85581a64
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588538179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl
ash_ctrl_re_evict.1588538179
Directory /workspace/10.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_ro.1222755765
Short name T525
Test name
Test status
Simulation time 627079800 ps
CPU time 118.27 seconds
Started Mar 24 02:24:10 PM PDT 24
Finished Mar 24 02:26:08 PM PDT 24
Peak memory 280816 kb
Host smart-bbf01e25-2a18-4df1-b4b3-be1a82596e7d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222755765 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.flash_ctrl_ro.1222755765
Directory /workspace/10.flash_ctrl_ro/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw.1776013966
Short name T19
Test name
Test status
Simulation time 6841457000 ps
CPU time 462.89 seconds
Started Mar 24 02:24:11 PM PDT 24
Finished Mar 24 02:31:54 PM PDT 24
Peak memory 314476 kb
Host smart-c23dcb8e-2fa0-44eb-a83d-7655abcf4f47
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776013966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_c
trl_rw.1776013966
Directory /workspace/10.flash_ctrl_rw/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict.346120487
Short name T753
Test name
Test status
Simulation time 53405600 ps
CPU time 33.68 seconds
Started Mar 24 02:24:18 PM PDT 24
Finished Mar 24 02:24:53 PM PDT 24
Peak memory 267380 kb
Host smart-d9eda779-55f6-4429-bb12-b1c5ec32b761
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346120487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla
sh_ctrl_rw_evict.346120487
Directory /workspace/10.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict_all_en.2838404925
Short name T467
Test name
Test status
Simulation time 36644200 ps
CPU time 31.89 seconds
Started Mar 24 02:24:20 PM PDT 24
Finished Mar 24 02:24:52 PM PDT 24
Peak memory 273268 kb
Host smart-9b2b6df7-a65f-4079-a173-fdd5bf5983a7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838404925 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict_all_en.2838404925
Directory /workspace/10.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/10.flash_ctrl_smoke.4285148858
Short name T492
Test name
Test status
Simulation time 117112200 ps
CPU time 192.83 seconds
Started Mar 24 02:24:06 PM PDT 24
Finished Mar 24 02:27:19 PM PDT 24
Peak memory 277488 kb
Host smart-b1c4a15d-f062-4b02-af21-85cf759318fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285148858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.4285148858
Directory /workspace/10.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/10.flash_ctrl_wo.1885993299
Short name T472
Test name
Test status
Simulation time 10045765700 ps
CPU time 153.59 seconds
Started Mar 24 02:24:09 PM PDT 24
Finished Mar 24 02:26:43 PM PDT 24
Peak memory 265004 kb
Host smart-e7abf662-423c-425d-88f9-dcd3673159e0
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885993299 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.flash_ctrl_wo.1885993299
Directory /workspace/10.flash_ctrl_wo/latest

Test location /workspace/coverage/default/11.flash_ctrl_connect.1958399376
Short name T262
Test name
Test status
Simulation time 15095100 ps
CPU time 13.18 seconds
Started Mar 24 02:24:46 PM PDT 24
Finished Mar 24 02:24:59 PM PDT 24
Peak memory 274992 kb
Host smart-e46dfa02-5870-4b2c-a682-6cf4cacd3321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958399376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.1958399376
Directory /workspace/11.flash_ctrl_connect/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.3151779665
Short name T141
Test name
Test status
Simulation time 10032490400 ps
CPU time 59.91 seconds
Started Mar 24 02:24:48 PM PDT 24
Finished Mar 24 02:25:48 PM PDT 24
Peak memory 292968 kb
Host smart-2c6cb1e6-ce04-4ffe-9f9a-1d3916f873d8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151779665 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.3151779665
Directory /workspace/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.3668724858
Short name T789
Test name
Test status
Simulation time 46869500 ps
CPU time 13.3 seconds
Started Mar 24 02:24:53 PM PDT 24
Finished Mar 24 02:25:07 PM PDT 24
Peak memory 264772 kb
Host smart-b4396924-28b4-48c5-a68a-4c74211fead5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668724858 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.3668724858
Directory /workspace/11.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_rma_reset.2464823775
Short name T486
Test name
Test status
Simulation time 50127910600 ps
CPU time 867.7 seconds
Started Mar 24 02:24:32 PM PDT 24
Finished Mar 24 02:39:00 PM PDT 24
Peak memory 263092 kb
Host smart-3fe380c8-1df3-4e90-9a13-206306398489
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464823775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.flash_ctrl_hw_rma_reset.2464823775
Directory /workspace/11.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_sec_otp.1965985179
Short name T188
Test name
Test status
Simulation time 12862075400 ps
CPU time 115.15 seconds
Started Mar 24 02:24:26 PM PDT 24
Finished Mar 24 02:26:21 PM PDT 24
Peak memory 262448 kb
Host smart-20c183c8-1371-4340-b11e-eb61817637af
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965985179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_
hw_sec_otp.1965985179
Directory /workspace/11.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd_slow_flash.3558354014
Short name T327
Test name
Test status
Simulation time 8659230700 ps
CPU time 211.91 seconds
Started Mar 24 02:24:40 PM PDT 24
Finished Mar 24 02:28:12 PM PDT 24
Peak memory 284584 kb
Host smart-82c95a91-9d5b-478e-a4e4-0867efa1e301
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558354014 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd_slow_flash.3558354014
Directory /workspace/11.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/11.flash_ctrl_invalid_op.2215494252
Short name T843
Test name
Test status
Simulation time 6554795300 ps
CPU time 72.19 seconds
Started Mar 24 02:24:32 PM PDT 24
Finished Mar 24 02:25:45 PM PDT 24
Peak memory 260548 kb
Host smart-d9edab18-f636-4502-bf8f-008242d4d21d
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215494252 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.2
215494252
Directory /workspace/11.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/11.flash_ctrl_mp_regions.3990030064
Short name T94
Test name
Test status
Simulation time 11151309600 ps
CPU time 161.15 seconds
Started Mar 24 02:24:35 PM PDT 24
Finished Mar 24 02:27:16 PM PDT 24
Peak memory 264904 kb
Host smart-19aba5ed-0fde-40fa-b0c9-6369321195bf
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990030064 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.flash_ctrl_mp_regions.3990030064
Directory /workspace/11.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/11.flash_ctrl_phy_arb.2416775219
Short name T1032
Test name
Test status
Simulation time 2931846100 ps
CPU time 456.41 seconds
Started Mar 24 02:24:26 PM PDT 24
Finished Mar 24 02:32:03 PM PDT 24
Peak memory 262180 kb
Host smart-866fccab-d4d0-4033-858c-f1ccee9e783e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2416775219 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.2416775219
Directory /workspace/11.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/11.flash_ctrl_prog_reset.8936739
Short name T1048
Test name
Test status
Simulation time 50365900 ps
CPU time 13.29 seconds
Started Mar 24 02:24:40 PM PDT 24
Finished Mar 24 02:24:53 PM PDT 24
Peak memory 260108 kb
Host smart-ba3670e8-2136-4be5-ae28-6b8f5d83db7f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8936739 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_prog_reset.8936739
Directory /workspace/11.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_rand_ops.1303661629
Short name T110
Test name
Test status
Simulation time 991509200 ps
CPU time 1163.3 seconds
Started Mar 24 02:24:27 PM PDT 24
Finished Mar 24 02:43:50 PM PDT 24
Peak memory 286140 kb
Host smart-48269681-8b24-4922-8908-088387e8acb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303661629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.1303661629
Directory /workspace/11.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/11.flash_ctrl_re_evict.1691693862
Short name T722
Test name
Test status
Simulation time 126634900 ps
CPU time 32.07 seconds
Started Mar 24 02:24:45 PM PDT 24
Finished Mar 24 02:25:18 PM PDT 24
Peak memory 273148 kb
Host smart-00c7b497-3702-4531-8e09-f56d43e5875b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691693862 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl
ash_ctrl_re_evict.1691693862
Directory /workspace/11.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/11.flash_ctrl_ro.355808241
Short name T517
Test name
Test status
Simulation time 1545342500 ps
CPU time 81.67 seconds
Started Mar 24 02:24:37 PM PDT 24
Finished Mar 24 02:25:59 PM PDT 24
Peak memory 280848 kb
Host smart-81bd4a3a-3671-4f16-9a55-cc3352525359
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355808241 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.flash_ctrl_ro.355808241
Directory /workspace/11.flash_ctrl_ro/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw.717824868
Short name T845
Test name
Test status
Simulation time 23899616200 ps
CPU time 524.4 seconds
Started Mar 24 02:24:36 PM PDT 24
Finished Mar 24 02:33:21 PM PDT 24
Peak memory 314120 kb
Host smart-57e26988-95c1-445a-88e0-2b23e49c0623
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717824868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ct
rl_rw.717824868
Directory /workspace/11.flash_ctrl_rw/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.876429808
Short name T280
Test name
Test status
Simulation time 46917600 ps
CPU time 31.05 seconds
Started Mar 24 02:24:43 PM PDT 24
Finished Mar 24 02:25:14 PM PDT 24
Peak memory 273336 kb
Host smart-37e742b2-eb1e-4810-9b1e-b0e9c78558a6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876429808 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict_all_en.876429808
Directory /workspace/11.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/11.flash_ctrl_sec_info_access.2610058398
Short name T392
Test name
Test status
Simulation time 903545400 ps
CPU time 58.8 seconds
Started Mar 24 02:24:43 PM PDT 24
Finished Mar 24 02:25:42 PM PDT 24
Peak memory 262948 kb
Host smart-ca271e1b-761a-4923-b140-499c5c6dfb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610058398 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.2610058398
Directory /workspace/11.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/11.flash_ctrl_smoke.2792873609
Short name T631
Test name
Test status
Simulation time 35602500 ps
CPU time 97.81 seconds
Started Mar 24 02:24:24 PM PDT 24
Finished Mar 24 02:26:02 PM PDT 24
Peak memory 274960 kb
Host smart-50458512-c058-4cb9-9771-01354492d302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792873609 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.2792873609
Directory /workspace/11.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/11.flash_ctrl_wo.1071633823
Short name T715
Test name
Test status
Simulation time 1731886700 ps
CPU time 144.68 seconds
Started Mar 24 02:24:38 PM PDT 24
Finished Mar 24 02:27:03 PM PDT 24
Peak memory 259456 kb
Host smart-3a9c22a8-8421-4f7f-acac-4b9db3e7540e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071633823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.flash_ctrl_wo.1071633823
Directory /workspace/11.flash_ctrl_wo/latest

Test location /workspace/coverage/default/12.flash_ctrl_alert_test.3545721697
Short name T651
Test name
Test status
Simulation time 69307700 ps
CPU time 13.81 seconds
Started Mar 24 02:25:14 PM PDT 24
Finished Mar 24 02:25:27 PM PDT 24
Peak memory 264892 kb
Host smart-7427e3e5-9627-4e9f-a4c9-eace2c5452cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545721697 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.
3545721697
Directory /workspace/12.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.flash_ctrl_connect.1961150926
Short name T820
Test name
Test status
Simulation time 31554600 ps
CPU time 15.38 seconds
Started Mar 24 02:25:11 PM PDT 24
Finished Mar 24 02:25:27 PM PDT 24
Peak memory 275200 kb
Host smart-1903f30a-331a-4c12-a9f8-44b9d0590f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961150926 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.1961150926
Directory /workspace/12.flash_ctrl_connect/latest

Test location /workspace/coverage/default/12.flash_ctrl_disable.1837553786
Short name T228
Test name
Test status
Simulation time 37061700 ps
CPU time 21.83 seconds
Started Mar 24 02:25:13 PM PDT 24
Finished Mar 24 02:25:35 PM PDT 24
Peak memory 264876 kb
Host smart-f3aa61e3-5c6e-49ae-9313-559cfb1563d8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837553786 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_disable.1837553786
Directory /workspace/12.flash_ctrl_disable/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.2526693021
Short name T292
Test name
Test status
Simulation time 10019953900 ps
CPU time 86.67 seconds
Started Mar 24 02:25:13 PM PDT 24
Finished Mar 24 02:26:40 PM PDT 24
Peak memory 312840 kb
Host smart-2b2d0e18-db08-48a2-8420-f9e1a7c963c5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526693021 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.2526693021
Directory /workspace/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_read_seed_err.2150020949
Short name T878
Test name
Test status
Simulation time 48039600 ps
CPU time 13.41 seconds
Started Mar 24 02:25:13 PM PDT 24
Finished Mar 24 02:25:27 PM PDT 24
Peak memory 264924 kb
Host smart-227a4fd5-166c-49c4-80b7-9370be4f6879
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150020949 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_seed_err.2150020949
Directory /workspace/12.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_rma_reset.3801975686
Short name T1007
Test name
Test status
Simulation time 160181097600 ps
CPU time 905.72 seconds
Started Mar 24 02:24:53 PM PDT 24
Finished Mar 24 02:40:00 PM PDT 24
Peak memory 262532 kb
Host smart-e239bbc8-043e-4540-af9c-863a3729328a
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801975686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.flash_ctrl_hw_rma_reset.3801975686
Directory /workspace/12.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_sec_otp.181870388
Short name T570
Test name
Test status
Simulation time 2812052500 ps
CPU time 85.49 seconds
Started Mar 24 02:24:48 PM PDT 24
Finished Mar 24 02:26:14 PM PDT 24
Peak memory 262284 kb
Host smart-6c99f3d1-c952-42c6-8e76-61f5c82aed81
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181870388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_h
w_sec_otp.181870388
Directory /workspace/12.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/12.flash_ctrl_invalid_op.3216034568
Short name T677
Test name
Test status
Simulation time 1010691300 ps
CPU time 75.43 seconds
Started Mar 24 02:24:54 PM PDT 24
Finished Mar 24 02:26:10 PM PDT 24
Peak memory 259620 kb
Host smart-2ddee9cf-6b84-4544-899f-c4baf240b3c5
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216034568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.3
216034568
Directory /workspace/12.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/12.flash_ctrl_lcmgr_intg.1631985107
Short name T550
Test name
Test status
Simulation time 15522200 ps
CPU time 13.5 seconds
Started Mar 24 02:25:13 PM PDT 24
Finished Mar 24 02:25:26 PM PDT 24
Peak memory 264932 kb
Host smart-c44908a4-f831-434a-9413-66ff518287e4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631985107 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.flash_ctrl_lcmgr_intg.1631985107
Directory /workspace/12.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/12.flash_ctrl_mp_regions.1904372113
Short name T853
Test name
Test status
Simulation time 18106013600 ps
CPU time 206.94 seconds
Started Mar 24 02:24:53 PM PDT 24
Finished Mar 24 02:28:21 PM PDT 24
Peak memory 262576 kb
Host smart-09152f48-8812-4ba5-aba2-10f42af19537
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904372113 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 12.flash_ctrl_mp_regions.1904372113
Directory /workspace/12.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/12.flash_ctrl_otp_reset.494352208
Short name T923
Test name
Test status
Simulation time 111962300 ps
CPU time 133.84 seconds
Started Mar 24 02:24:49 PM PDT 24
Finished Mar 24 02:27:03 PM PDT 24
Peak memory 264092 kb
Host smart-4399a2da-e91c-4666-9a02-e9988bcdaf0f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494352208 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_ot
p_reset.494352208
Directory /workspace/12.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_phy_arb.640360879
Short name T936
Test name
Test status
Simulation time 131010700 ps
CPU time 269.93 seconds
Started Mar 24 02:24:48 PM PDT 24
Finished Mar 24 02:29:19 PM PDT 24
Peak memory 264808 kb
Host smart-4f38f8e8-39da-46ad-a692-c4cabb3aa3a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=640360879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.640360879
Directory /workspace/12.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/12.flash_ctrl_prog_reset.1419756187
Short name T730
Test name
Test status
Simulation time 70308500 ps
CPU time 13.83 seconds
Started Mar 24 02:25:00 PM PDT 24
Finished Mar 24 02:25:14 PM PDT 24
Peak memory 259992 kb
Host smart-1f2117bd-9299-4ca6-8af9-08448a232174
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419756187 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_prog_re
set.1419756187
Directory /workspace/12.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_rand_ops.863671862
Short name T842
Test name
Test status
Simulation time 409164600 ps
CPU time 451.48 seconds
Started Mar 24 02:24:49 PM PDT 24
Finished Mar 24 02:32:21 PM PDT 24
Peak memory 282504 kb
Host smart-c2f70861-1a3d-4a4b-b1cd-5eb40d2fd2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863671862 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.863671862
Directory /workspace/12.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/12.flash_ctrl_re_evict.921593906
Short name T371
Test name
Test status
Simulation time 681258700 ps
CPU time 33.81 seconds
Started Mar 24 02:25:06 PM PDT 24
Finished Mar 24 02:25:40 PM PDT 24
Peak memory 273232 kb
Host smart-afa044b3-9841-4766-95fb-1bb44fb9b296
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921593906 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla
sh_ctrl_re_evict.921593906
Directory /workspace/12.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_ro.2078430469
Short name T248
Test name
Test status
Simulation time 972372300 ps
CPU time 126.45 seconds
Started Mar 24 02:24:54 PM PDT 24
Finished Mar 24 02:27:00 PM PDT 24
Peak memory 281024 kb
Host smart-a680d034-7288-4804-b974-1bad32f7bce7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078430469 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.flash_ctrl_ro.2078430469
Directory /workspace/12.flash_ctrl_ro/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw.3677829503
Short name T192
Test name
Test status
Simulation time 3295489800 ps
CPU time 464.74 seconds
Started Mar 24 02:25:00 PM PDT 24
Finished Mar 24 02:32:45 PM PDT 24
Peak memory 313668 kb
Host smart-03425cc8-1367-493b-a61f-f54c6cb87996
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677829503 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_c
trl_rw.3677829503
Directory /workspace/12.flash_ctrl_rw/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict.1338759729
Short name T787
Test name
Test status
Simulation time 36877400 ps
CPU time 30.78 seconds
Started Mar 24 02:25:06 PM PDT 24
Finished Mar 24 02:25:37 PM PDT 24
Peak memory 273276 kb
Host smart-fa18e39c-d3e5-4c1d-a357-76a3114ca022
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338759729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl
ash_ctrl_rw_evict.1338759729
Directory /workspace/12.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_smoke.2520413145
Short name T462
Test name
Test status
Simulation time 28737000 ps
CPU time 121.96 seconds
Started Mar 24 02:24:50 PM PDT 24
Finished Mar 24 02:26:53 PM PDT 24
Peak memory 275396 kb
Host smart-2329a626-d8b8-4d34-9121-ce45a54ae471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520413145 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.2520413145
Directory /workspace/12.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/12.flash_ctrl_wo.3513822132
Short name T666
Test name
Test status
Simulation time 2482131000 ps
CPU time 115.32 seconds
Started Mar 24 02:24:53 PM PDT 24
Finished Mar 24 02:26:50 PM PDT 24
Peak memory 258612 kb
Host smart-61e40fd9-1aae-441a-8b55-15c11ff4bf8f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513822132 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.flash_ctrl_wo.3513822132
Directory /workspace/12.flash_ctrl_wo/latest

Test location /workspace/coverage/default/13.flash_ctrl_alert_test.701696340
Short name T578
Test name
Test status
Simulation time 53138600 ps
CPU time 13.88 seconds
Started Mar 24 02:25:33 PM PDT 24
Finished Mar 24 02:25:47 PM PDT 24
Peak memory 258728 kb
Host smart-f23659b4-61bf-4092-a535-9c9929a9a6e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701696340 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test.701696340
Directory /workspace/13.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.flash_ctrl_connect.3813758531
Short name T746
Test name
Test status
Simulation time 20151400 ps
CPU time 13.43 seconds
Started Mar 24 02:25:29 PM PDT 24
Finished Mar 24 02:25:42 PM PDT 24
Peak memory 274688 kb
Host smart-308f88fa-4349-4370-91b6-88e27b92934c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813758531 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.3813758531
Directory /workspace/13.flash_ctrl_connect/latest

Test location /workspace/coverage/default/13.flash_ctrl_disable.21405917
Short name T42
Test name
Test status
Simulation time 110601900 ps
CPU time 21.77 seconds
Started Mar 24 02:25:29 PM PDT 24
Finished Mar 24 02:25:51 PM PDT 24
Peak memory 264996 kb
Host smart-307d346e-e667-4a25-819f-6f7d51447a37
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21405917 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 13.flash_ctrl_disable.21405917
Directory /workspace/13.flash_ctrl_disable/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_read_seed_err.1856506444
Short name T597
Test name
Test status
Simulation time 14722000 ps
CPU time 13.28 seconds
Started Mar 24 02:25:35 PM PDT 24
Finished Mar 24 02:25:48 PM PDT 24
Peak memory 264896 kb
Host smart-26843a66-9175-4bb3-bd6f-251e8ac161e4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856506444 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.1856506444
Directory /workspace/13.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_rma_reset.2015030152
Short name T74
Test name
Test status
Simulation time 160188801200 ps
CPU time 963.68 seconds
Started Mar 24 02:25:18 PM PDT 24
Finished Mar 24 02:41:22 PM PDT 24
Peak memory 263028 kb
Host smart-9f22507f-9107-4967-8b38-404c705bcdb5
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015030152 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.flash_ctrl_hw_rma_reset.2015030152
Directory /workspace/13.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_sec_otp.1100678003
Short name T432
Test name
Test status
Simulation time 66694883300 ps
CPU time 208.9 seconds
Started Mar 24 02:25:17 PM PDT 24
Finished Mar 24 02:28:46 PM PDT 24
Peak memory 262300 kb
Host smart-42a8f6d6-8059-436a-a26f-e2cfbac6b8b7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100678003 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_
hw_sec_otp.1100678003
Directory /workspace/13.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd_slow_flash.258278798
Short name T825
Test name
Test status
Simulation time 22163491000 ps
CPU time 235.55 seconds
Started Mar 24 02:25:22 PM PDT 24
Finished Mar 24 02:29:17 PM PDT 24
Peak memory 284500 kb
Host smart-b6f79d18-9c4e-47a0-82ab-d6e596dbc422
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258278798 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd_slow_flash.258278798
Directory /workspace/13.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/13.flash_ctrl_invalid_op.4062567124
Short name T678
Test name
Test status
Simulation time 3445299100 ps
CPU time 76.84 seconds
Started Mar 24 02:25:16 PM PDT 24
Finished Mar 24 02:26:33 PM PDT 24
Peak memory 260400 kb
Host smart-9e638a42-b08e-44cd-8ebe-8b8f718cb549
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062567124 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.4
062567124
Directory /workspace/13.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/13.flash_ctrl_lcmgr_intg.1619598867
Short name T611
Test name
Test status
Simulation time 44235100 ps
CPU time 13.31 seconds
Started Mar 24 02:25:27 PM PDT 24
Finished Mar 24 02:25:41 PM PDT 24
Peak memory 264788 kb
Host smart-1ea45c0e-6f6b-45de-98cd-0848a9fa1834
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619598867 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.flash_ctrl_lcmgr_intg.1619598867
Directory /workspace/13.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/13.flash_ctrl_otp_reset.2750064853
Short name T427
Test name
Test status
Simulation time 148446000 ps
CPU time 130.77 seconds
Started Mar 24 02:25:18 PM PDT 24
Finished Mar 24 02:27:29 PM PDT 24
Peak memory 259656 kb
Host smart-bf244386-82da-44d5-b651-d9333517ef1d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750064853 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_o
tp_reset.2750064853
Directory /workspace/13.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_phy_arb.2181655947
Short name T944
Test name
Test status
Simulation time 65381200 ps
CPU time 317.57 seconds
Started Mar 24 02:25:19 PM PDT 24
Finished Mar 24 02:30:37 PM PDT 24
Peak memory 261472 kb
Host smart-c9db3acd-0d7e-4df3-9e5b-98d725ef39a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2181655947 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.2181655947
Directory /workspace/13.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/13.flash_ctrl_prog_reset.4280833686
Short name T1038
Test name
Test status
Simulation time 19637800 ps
CPU time 13.67 seconds
Started Mar 24 02:25:22 PM PDT 24
Finished Mar 24 02:25:36 PM PDT 24
Peak memory 259936 kb
Host smart-237d4e86-9a85-431a-9f51-f7bbab0e35fb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280833686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_prog_re
set.4280833686
Directory /workspace/13.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_rand_ops.3323992241
Short name T739
Test name
Test status
Simulation time 65750000 ps
CPU time 50.98 seconds
Started Mar 24 02:25:19 PM PDT 24
Finished Mar 24 02:26:10 PM PDT 24
Peak memory 262300 kb
Host smart-ba992090-eadd-4761-bfe1-53eaa0ad7b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323992241 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.3323992241
Directory /workspace/13.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/13.flash_ctrl_re_evict.2050771993
Short name T841
Test name
Test status
Simulation time 234362500 ps
CPU time 39.21 seconds
Started Mar 24 02:25:22 PM PDT 24
Finished Mar 24 02:26:02 PM PDT 24
Peak memory 266088 kb
Host smart-08d42be5-7979-4ca8-ab7b-6f135b516232
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050771993 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl
ash_ctrl_re_evict.2050771993
Directory /workspace/13.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_ro.3572447216
Short name T202
Test name
Test status
Simulation time 538327300 ps
CPU time 104.89 seconds
Started Mar 24 02:25:17 PM PDT 24
Finished Mar 24 02:27:02 PM PDT 24
Peak memory 280940 kb
Host smart-fdb3abea-514c-4f60-98f9-88fd458a8faa
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572447216 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.flash_ctrl_ro.3572447216
Directory /workspace/13.flash_ctrl_ro/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw.3063928388
Short name T537
Test name
Test status
Simulation time 3496310900 ps
CPU time 590.72 seconds
Started Mar 24 02:25:22 PM PDT 24
Finished Mar 24 02:35:13 PM PDT 24
Peak memory 314176 kb
Host smart-93671191-90da-4de8-8cae-2b4299beb015
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063928388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_c
trl_rw.3063928388
Directory /workspace/13.flash_ctrl_rw/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict.720789720
Short name T279
Test name
Test status
Simulation time 77268400 ps
CPU time 31.16 seconds
Started Mar 24 02:25:23 PM PDT 24
Finished Mar 24 02:25:54 PM PDT 24
Peak memory 267172 kb
Host smart-95411479-bb1e-4891-a7cf-1fb2ae5d3812
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720789720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla
sh_ctrl_rw_evict.720789720
Directory /workspace/13.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict_all_en.2043359538
Short name T784
Test name
Test status
Simulation time 32039200 ps
CPU time 31.66 seconds
Started Mar 24 02:25:22 PM PDT 24
Finished Mar 24 02:25:54 PM PDT 24
Peak memory 273324 kb
Host smart-8eda6f8f-93cf-4397-96b1-c7293d699311
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043359538 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict_all_en.2043359538
Directory /workspace/13.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/13.flash_ctrl_sec_info_access.283683880
Short name T390
Test name
Test status
Simulation time 4313913600 ps
CPU time 59 seconds
Started Mar 24 02:25:27 PM PDT 24
Finished Mar 24 02:26:26 PM PDT 24
Peak memory 263112 kb
Host smart-cab4b05f-8036-4c3d-a8c4-22e73a28b685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283683880 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.283683880
Directory /workspace/13.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/13.flash_ctrl_smoke.3931483037
Short name T902
Test name
Test status
Simulation time 302396100 ps
CPU time 149.91 seconds
Started Mar 24 02:25:18 PM PDT 24
Finished Mar 24 02:27:48 PM PDT 24
Peak memory 276096 kb
Host smart-3d11d672-909d-4115-a63f-7f3a92f663ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931483037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.3931483037
Directory /workspace/13.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/13.flash_ctrl_wo.3557102007
Short name T999
Test name
Test status
Simulation time 5531971700 ps
CPU time 155.87 seconds
Started Mar 24 02:25:17 PM PDT 24
Finished Mar 24 02:27:53 PM PDT 24
Peak memory 258740 kb
Host smart-57bf1425-6744-4d3c-bb3e-af53ddc33888
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557102007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.flash_ctrl_wo.3557102007
Directory /workspace/13.flash_ctrl_wo/latest

Test location /workspace/coverage/default/14.flash_ctrl_alert_test.315102019
Short name T859
Test name
Test status
Simulation time 71283900 ps
CPU time 13.9 seconds
Started Mar 24 02:26:02 PM PDT 24
Finished Mar 24 02:26:16 PM PDT 24
Peak memory 257980 kb
Host smart-71df6844-e17d-41ea-bc6d-d24f130b3689
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315102019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test.315102019
Directory /workspace/14.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.flash_ctrl_connect.3220347291
Short name T1013
Test name
Test status
Simulation time 14561400 ps
CPU time 15.48 seconds
Started Mar 24 02:25:52 PM PDT 24
Finished Mar 24 02:26:07 PM PDT 24
Peak memory 275196 kb
Host smart-9e6337ac-060c-4f73-ad7b-d0ead6fc7807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220347291 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.3220347291
Directory /workspace/14.flash_ctrl_connect/latest

Test location /workspace/coverage/default/14.flash_ctrl_disable.4260663160
Short name T915
Test name
Test status
Simulation time 42566200 ps
CPU time 22.15 seconds
Started Mar 24 02:25:50 PM PDT 24
Finished Mar 24 02:26:13 PM PDT 24
Peak memory 264900 kb
Host smart-ba7b8f6f-a58e-4021-995b-c0ea7e96a3da
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260663160 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.flash_ctrl_disable.4260663160
Directory /workspace/14.flash_ctrl_disable/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.1063866115
Short name T496
Test name
Test status
Simulation time 10036984900 ps
CPU time 61.67 seconds
Started Mar 24 02:25:57 PM PDT 24
Finished Mar 24 02:26:59 PM PDT 24
Peak memory 292920 kb
Host smart-bf7a52ae-5793-439b-816d-562678f2ea1c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063866115 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.1063866115
Directory /workspace/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_sec_otp.452306244
Short name T810
Test name
Test status
Simulation time 16339610700 ps
CPU time 152.2 seconds
Started Mar 24 02:25:38 PM PDT 24
Finished Mar 24 02:28:11 PM PDT 24
Peak memory 262544 kb
Host smart-a1e54edd-10d8-42e9-aab3-473b648947d1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452306244 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_h
w_sec_otp.452306244
Directory /workspace/14.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.4073539933
Short name T324
Test name
Test status
Simulation time 17379030200 ps
CPU time 275.21 seconds
Started Mar 24 02:25:46 PM PDT 24
Finished Mar 24 02:30:22 PM PDT 24
Peak memory 284512 kb
Host smart-7810d6d2-b99d-4a64-959c-c64c2ca0aad4
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073539933 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd_slow_flash.4073539933
Directory /workspace/14.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/14.flash_ctrl_invalid_op.1167801529
Short name T926
Test name
Test status
Simulation time 2181177800 ps
CPU time 68.87 seconds
Started Mar 24 02:25:43 PM PDT 24
Finished Mar 24 02:26:52 PM PDT 24
Peak memory 261988 kb
Host smart-68c41871-59f2-4bcc-8e33-31d595455381
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167801529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.1
167801529
Directory /workspace/14.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/14.flash_ctrl_lcmgr_intg.2047460282
Short name T296
Test name
Test status
Simulation time 15537600 ps
CPU time 13.77 seconds
Started Mar 24 02:25:57 PM PDT 24
Finished Mar 24 02:26:11 PM PDT 24
Peak memory 264868 kb
Host smart-076d875b-5c77-426f-8b14-dee73b9309b7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047460282 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.flash_ctrl_lcmgr_intg.2047460282
Directory /workspace/14.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/14.flash_ctrl_mp_regions.3730510195
Short name T98
Test name
Test status
Simulation time 60162998500 ps
CPU time 329.27 seconds
Started Mar 24 02:25:41 PM PDT 24
Finished Mar 24 02:31:11 PM PDT 24
Peak memory 273372 kb
Host smart-97a8e451-503c-4d1f-867a-1307bf32bc8c
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730510195 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.flash_ctrl_mp_regions.3730510195
Directory /workspace/14.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/14.flash_ctrl_otp_reset.3408926039
Short name T973
Test name
Test status
Simulation time 69303300 ps
CPU time 109.64 seconds
Started Mar 24 02:25:39 PM PDT 24
Finished Mar 24 02:27:29 PM PDT 24
Peak memory 259604 kb
Host smart-8c246f10-2e45-4960-9040-2fe14dcf9fde
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408926039 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_o
tp_reset.3408926039
Directory /workspace/14.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_phy_arb.65506667
Short name T234
Test name
Test status
Simulation time 692440900 ps
CPU time 122.51 seconds
Started Mar 24 02:25:38 PM PDT 24
Finished Mar 24 02:27:41 PM PDT 24
Peak memory 261432 kb
Host smart-698f7798-b993-4448-a825-3f71ec0a9030
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=65506667 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.65506667
Directory /workspace/14.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/14.flash_ctrl_prog_reset.1072416878
Short name T375
Test name
Test status
Simulation time 39384300 ps
CPU time 13.81 seconds
Started Mar 24 02:25:50 PM PDT 24
Finished Mar 24 02:26:04 PM PDT 24
Peak memory 260244 kb
Host smart-5b11a1a8-a83c-45a7-bf68-18ced68bd790
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072416878 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_prog_re
set.1072416878
Directory /workspace/14.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_rand_ops.1961305504
Short name T104
Test name
Test status
Simulation time 133955000 ps
CPU time 670.08 seconds
Started Mar 24 02:25:39 PM PDT 24
Finished Mar 24 02:36:49 PM PDT 24
Peak memory 282448 kb
Host smart-d5e3812b-64c4-4bf2-b302-c88454ccd0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961305504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.1961305504
Directory /workspace/14.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/14.flash_ctrl_ro.3428852959
Short name T1002
Test name
Test status
Simulation time 8649513500 ps
CPU time 129.57 seconds
Started Mar 24 02:25:43 PM PDT 24
Finished Mar 24 02:27:53 PM PDT 24
Peak memory 280820 kb
Host smart-92480f1c-f98e-4706-bfee-551c47502d59
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428852959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.flash_ctrl_ro.3428852959
Directory /workspace/14.flash_ctrl_ro/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw.416885076
Short name T599
Test name
Test status
Simulation time 10480398900 ps
CPU time 423.35 seconds
Started Mar 24 02:25:47 PM PDT 24
Finished Mar 24 02:32:51 PM PDT 24
Peak memory 319024 kb
Host smart-f703c270-c746-4b85-9613-ee4f71306fc5
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416885076 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ct
rl_rw.416885076
Directory /workspace/14.flash_ctrl_rw/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict.1642029544
Short name T458
Test name
Test status
Simulation time 35360600 ps
CPU time 31.4 seconds
Started Mar 24 02:25:52 PM PDT 24
Finished Mar 24 02:26:24 PM PDT 24
Peak memory 275244 kb
Host smart-190c69d9-a1d0-4898-a0d9-2f6ea12d264e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642029544 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_rw_evict.1642029544
Directory /workspace/14.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_sec_info_access.207666942
Short name T1020
Test name
Test status
Simulation time 2034320600 ps
CPU time 66.18 seconds
Started Mar 24 02:25:50 PM PDT 24
Finished Mar 24 02:26:57 PM PDT 24
Peak memory 262804 kb
Host smart-5cc63e5d-d9ce-480d-8527-66616887c833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207666942 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.207666942
Directory /workspace/14.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/14.flash_ctrl_smoke.3398748126
Short name T704
Test name
Test status
Simulation time 17407000 ps
CPU time 53.86 seconds
Started Mar 24 02:25:38 PM PDT 24
Finished Mar 24 02:26:32 PM PDT 24
Peak memory 270428 kb
Host smart-7ba18fce-2b86-432c-b4a6-80d6ad6d1f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398748126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.3398748126
Directory /workspace/14.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/14.flash_ctrl_wo.478111733
Short name T477
Test name
Test status
Simulation time 9342624800 ps
CPU time 194.71 seconds
Started Mar 24 02:25:42 PM PDT 24
Finished Mar 24 02:28:58 PM PDT 24
Peak memory 259128 kb
Host smart-883d485b-b1df-445e-8415-d910c637c9d1
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478111733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.flash_ctrl_wo.478111733
Directory /workspace/14.flash_ctrl_wo/latest

Test location /workspace/coverage/default/15.flash_ctrl_alert_test.558079789
Short name T99
Test name
Test status
Simulation time 103136000 ps
CPU time 14.33 seconds
Started Mar 24 02:26:22 PM PDT 24
Finished Mar 24 02:26:36 PM PDT 24
Peak memory 264816 kb
Host smart-b618cb04-e212-4bc2-be18-16bcc5ea06ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558079789 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test.558079789
Directory /workspace/15.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.flash_ctrl_connect.1728217902
Short name T574
Test name
Test status
Simulation time 64296800 ps
CPU time 15.73 seconds
Started Mar 24 02:26:24 PM PDT 24
Finished Mar 24 02:26:39 PM PDT 24
Peak memory 275152 kb
Host smart-8aa5c5ff-d577-4e4e-a148-afd2bdf509a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728217902 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.1728217902
Directory /workspace/15.flash_ctrl_connect/latest

Test location /workspace/coverage/default/15.flash_ctrl_disable.920570299
Short name T365
Test name
Test status
Simulation time 13154000 ps
CPU time 21.88 seconds
Started Mar 24 02:26:31 PM PDT 24
Finished Mar 24 02:26:53 PM PDT 24
Peak memory 264976 kb
Host smart-f478a5b6-844d-4579-a4e1-dd6f61156c1f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920570299 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.flash_ctrl_disable.920570299
Directory /workspace/15.flash_ctrl_disable/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.760158514
Short name T294
Test name
Test status
Simulation time 10024569900 ps
CPU time 152.65 seconds
Started Mar 24 02:26:23 PM PDT 24
Finished Mar 24 02:28:56 PM PDT 24
Peak memory 285404 kb
Host smart-4c28f95d-25fe-40e0-ad23-020129285ab4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760158514 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.760158514
Directory /workspace/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.2505105196
Short name T796
Test name
Test status
Simulation time 18872300 ps
CPU time 13.36 seconds
Started Mar 24 02:26:22 PM PDT 24
Finished Mar 24 02:26:36 PM PDT 24
Peak memory 264868 kb
Host smart-eb908485-a1ee-4c36-8891-67b2f4d54a98
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505105196 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_read_seed_err.2505105196
Directory /workspace/15.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_sec_otp.2147010283
Short name T423
Test name
Test status
Simulation time 6383798100 ps
CPU time 131.99 seconds
Started Mar 24 02:26:01 PM PDT 24
Finished Mar 24 02:28:14 PM PDT 24
Peak memory 262504 kb
Host smart-29f284bb-a623-4652-b350-202f8a6701cf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147010283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_
hw_sec_otp.2147010283
Directory /workspace/15.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd_slow_flash.4020600423
Short name T615
Test name
Test status
Simulation time 8692435900 ps
CPU time 191.52 seconds
Started Mar 24 02:26:10 PM PDT 24
Finished Mar 24 02:29:22 PM PDT 24
Peak memory 289560 kb
Host smart-971445d7-365c-4aed-b485-4ae71d6d7815
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020600423 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd_slow_flash.4020600423
Directory /workspace/15.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/15.flash_ctrl_invalid_op.3008537120
Short name T405
Test name
Test status
Simulation time 19044000100 ps
CPU time 78.05 seconds
Started Mar 24 02:26:01 PM PDT 24
Finished Mar 24 02:27:20 PM PDT 24
Peak memory 260340 kb
Host smart-dedb58c0-ae84-4c05-886f-d6b6f49bc242
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008537120 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.3
008537120
Directory /workspace/15.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/15.flash_ctrl_lcmgr_intg.3360197646
Short name T465
Test name
Test status
Simulation time 45172400 ps
CPU time 13.77 seconds
Started Mar 24 02:26:23 PM PDT 24
Finished Mar 24 02:26:37 PM PDT 24
Peak memory 264956 kb
Host smart-d425efd0-402a-467e-b97f-ab3cd94018e8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360197646 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.flash_ctrl_lcmgr_intg.3360197646
Directory /workspace/15.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/15.flash_ctrl_mp_regions.2248292650
Short name T826
Test name
Test status
Simulation time 20856784300 ps
CPU time 151.29 seconds
Started Mar 24 02:26:03 PM PDT 24
Finished Mar 24 02:28:35 PM PDT 24
Peak memory 262536 kb
Host smart-2cb9b4ae-8858-4b9c-9719-5b7be7be65bb
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248292650 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.flash_ctrl_mp_regions.2248292650
Directory /workspace/15.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/15.flash_ctrl_otp_reset.2841434948
Short name T939
Test name
Test status
Simulation time 133147600 ps
CPU time 131.89 seconds
Started Mar 24 02:26:06 PM PDT 24
Finished Mar 24 02:28:19 PM PDT 24
Peak memory 259380 kb
Host smart-80276edc-4353-4967-9ff0-96cea1c5dcd9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841434948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_o
tp_reset.2841434948
Directory /workspace/15.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_phy_arb.739412798
Short name T485
Test name
Test status
Simulation time 60227500 ps
CPU time 108.36 seconds
Started Mar 24 02:26:01 PM PDT 24
Finished Mar 24 02:27:50 PM PDT 24
Peak memory 264728 kb
Host smart-78a28ebf-eb38-4113-8600-f9db8428a41d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=739412798 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.739412798
Directory /workspace/15.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/15.flash_ctrl_prog_reset.3992535896
Short name T894
Test name
Test status
Simulation time 60502900 ps
CPU time 13.83 seconds
Started Mar 24 02:26:11 PM PDT 24
Finished Mar 24 02:26:25 PM PDT 24
Peak memory 264504 kb
Host smart-f8dfee64-b6d1-4277-a195-d5ab76138765
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992535896 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_prog_re
set.3992535896
Directory /workspace/15.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_rand_ops.1479735434
Short name T705
Test name
Test status
Simulation time 71379800 ps
CPU time 242.82 seconds
Started Mar 24 02:26:03 PM PDT 24
Finished Mar 24 02:30:06 PM PDT 24
Peak memory 281236 kb
Host smart-07a53657-aa23-460b-8bac-6fa228c35eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479735434 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.1479735434
Directory /workspace/15.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/15.flash_ctrl_re_evict.1040558431
Short name T862
Test name
Test status
Simulation time 122134700 ps
CPU time 37.6 seconds
Started Mar 24 02:26:15 PM PDT 24
Finished Mar 24 02:26:55 PM PDT 24
Peak memory 273220 kb
Host smart-6709f4eb-8185-447a-a21d-f2ae66c1239a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040558431 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl
ash_ctrl_re_evict.1040558431
Directory /workspace/15.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_ro.3483568835
Short name T1052
Test name
Test status
Simulation time 1949135600 ps
CPU time 97.04 seconds
Started Mar 24 02:26:05 PM PDT 24
Finished Mar 24 02:27:42 PM PDT 24
Peak memory 280728 kb
Host smart-87aeb777-ee96-428a-b21b-519c53416b90
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483568835 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.flash_ctrl_ro.3483568835
Directory /workspace/15.flash_ctrl_ro/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw.499482249
Short name T191
Test name
Test status
Simulation time 3376931900 ps
CPU time 509.23 seconds
Started Mar 24 02:26:07 PM PDT 24
Finished Mar 24 02:34:37 PM PDT 24
Peak memory 314052 kb
Host smart-424ec7d1-decf-4257-8eff-de6de2230be5
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499482249 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ct
rl_rw.499482249
Directory /workspace/15.flash_ctrl_rw/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict.3951334045
Short name T601
Test name
Test status
Simulation time 155102200 ps
CPU time 33.21 seconds
Started Mar 24 02:26:12 PM PDT 24
Finished Mar 24 02:26:45 PM PDT 24
Peak memory 273276 kb
Host smart-caa9ff99-16e2-419b-83dd-f37c1e6663ba
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951334045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl
ash_ctrl_rw_evict.3951334045
Directory /workspace/15.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_sec_info_access.1309425184
Short name T805
Test name
Test status
Simulation time 1326579000 ps
CPU time 60.42 seconds
Started Mar 24 02:26:30 PM PDT 24
Finished Mar 24 02:27:31 PM PDT 24
Peak memory 264716 kb
Host smart-63804534-e268-4cc8-866d-c78ed8f13a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309425184 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.1309425184
Directory /workspace/15.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/15.flash_ctrl_smoke.1349813329
Short name T832
Test name
Test status
Simulation time 70012200 ps
CPU time 76.16 seconds
Started Mar 24 02:26:01 PM PDT 24
Finished Mar 24 02:27:18 PM PDT 24
Peak memory 275620 kb
Host smart-57136f62-b2bf-417a-ad3f-7e92758ab56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349813329 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.1349813329
Directory /workspace/15.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/15.flash_ctrl_wo.431466601
Short name T471
Test name
Test status
Simulation time 6908144700 ps
CPU time 147.78 seconds
Started Mar 24 02:26:07 PM PDT 24
Finished Mar 24 02:28:35 PM PDT 24
Peak memory 264976 kb
Host smart-14872928-f9c0-4555-8975-7f6d4e5119ce
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431466601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.flash_ctrl_wo.431466601
Directory /workspace/15.flash_ctrl_wo/latest

Test location /workspace/coverage/default/16.flash_ctrl_alert_test.2270406705
Short name T882
Test name
Test status
Simulation time 107222200 ps
CPU time 13.3 seconds
Started Mar 24 02:26:37 PM PDT 24
Finished Mar 24 02:26:51 PM PDT 24
Peak memory 264880 kb
Host smart-7b892979-0b82-4e4e-a920-784cd021f16f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270406705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.
2270406705
Directory /workspace/16.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.flash_ctrl_connect.2709141897
Short name T823
Test name
Test status
Simulation time 25096600 ps
CPU time 15.43 seconds
Started Mar 24 02:26:28 PM PDT 24
Finished Mar 24 02:26:44 PM PDT 24
Peak memory 275376 kb
Host smart-26c421e1-0446-4a4e-bde9-c0c5ec52423a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709141897 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.2709141897
Directory /workspace/16.flash_ctrl_connect/latest

Test location /workspace/coverage/default/16.flash_ctrl_disable.2573955922
Short name T1042
Test name
Test status
Simulation time 26198700 ps
CPU time 20.44 seconds
Started Mar 24 02:26:28 PM PDT 24
Finished Mar 24 02:26:48 PM PDT 24
Peak memory 264984 kb
Host smart-0fc20b86-a4e0-46ff-bd31-99c92a5b2810
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573955922 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_disable.2573955922
Directory /workspace/16.flash_ctrl_disable/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.1453142170
Short name T295
Test name
Test status
Simulation time 10037869100 ps
CPU time 103.49 seconds
Started Mar 24 02:26:32 PM PDT 24
Finished Mar 24 02:28:16 PM PDT 24
Peak memory 270792 kb
Host smart-0e72e58c-82b1-4aa2-a0dc-ef7e0ade61e9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453142170 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.1453142170
Directory /workspace/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.3864021874
Short name T922
Test name
Test status
Simulation time 33438400 ps
CPU time 13.52 seconds
Started Mar 24 02:26:32 PM PDT 24
Finished Mar 24 02:26:45 PM PDT 24
Peak memory 265096 kb
Host smart-f5346671-3bad-442b-95e2-f6608e2c2094
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864021874 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.3864021874
Directory /workspace/16.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_rma_reset.541220135
Short name T479
Test name
Test status
Simulation time 40124592500 ps
CPU time 862.03 seconds
Started Mar 24 02:26:22 PM PDT 24
Finished Mar 24 02:40:44 PM PDT 24
Peak memory 263492 kb
Host smart-c2755022-7612-4313-8821-4e3108dfe448
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541220135 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.flash_ctrl_hw_rma_reset.541220135
Directory /workspace/16.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_sec_otp.4122449425
Short name T628
Test name
Test status
Simulation time 5303699400 ps
CPU time 111.51 seconds
Started Mar 24 02:26:31 PM PDT 24
Finished Mar 24 02:28:22 PM PDT 24
Peak memory 262328 kb
Host smart-a3f7940a-7e1f-42dd-b67c-1353354516c8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122449425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_
hw_sec_otp.4122449425
Directory /workspace/16.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.2084376740
Short name T29
Test name
Test status
Simulation time 9474193900 ps
CPU time 225.52 seconds
Started Mar 24 02:26:27 PM PDT 24
Finished Mar 24 02:30:13 PM PDT 24
Peak memory 292896 kb
Host smart-ddc969a6-a1b2-40f2-8ba5-f95225bc16e6
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084376740 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd_slow_flash.2084376740
Directory /workspace/16.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/16.flash_ctrl_invalid_op.4208258945
Short name T877
Test name
Test status
Simulation time 3674925500 ps
CPU time 68.36 seconds
Started Mar 24 02:26:30 PM PDT 24
Finished Mar 24 02:27:38 PM PDT 24
Peak memory 260376 kb
Host smart-09677743-6cb0-4acb-af38-87e33d74d4f8
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208258945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.4
208258945
Directory /workspace/16.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/16.flash_ctrl_lcmgr_intg.2490052656
Short name T130
Test name
Test status
Simulation time 15558700 ps
CPU time 13.54 seconds
Started Mar 24 02:26:32 PM PDT 24
Finished Mar 24 02:26:45 PM PDT 24
Peak memory 264932 kb
Host smart-7246f79d-a482-4575-9f60-49fe07be4be5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490052656 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.flash_ctrl_lcmgr_intg.2490052656
Directory /workspace/16.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/16.flash_ctrl_mp_regions.809584362
Short name T96
Test name
Test status
Simulation time 26448773700 ps
CPU time 1085.61 seconds
Started Mar 24 02:26:23 PM PDT 24
Finished Mar 24 02:44:29 PM PDT 24
Peak memory 273488 kb
Host smart-6ff4045b-e61e-4ed1-96e7-a2f1b8cd2cb3
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809584362 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 16.flash_ctrl_mp_regions.809584362
Directory /workspace/16.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/16.flash_ctrl_otp_reset.100507033
Short name T991
Test name
Test status
Simulation time 83529700 ps
CPU time 131.97 seconds
Started Mar 24 02:26:30 PM PDT 24
Finished Mar 24 02:28:42 PM PDT 24
Peak memory 259688 kb
Host smart-334fdb61-d827-4696-815f-3d90ec5c30bc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100507033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_ot
p_reset.100507033
Directory /workspace/16.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_phy_arb.975210495
Short name T725
Test name
Test status
Simulation time 187635500 ps
CPU time 179.6 seconds
Started Mar 24 02:26:21 PM PDT 24
Finished Mar 24 02:29:21 PM PDT 24
Peak memory 264716 kb
Host smart-034aef4a-e0aa-4e7c-86bc-e9ded0269925
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=975210495 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.975210495
Directory /workspace/16.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/16.flash_ctrl_prog_reset.4050701418
Short name T680
Test name
Test status
Simulation time 18465700 ps
CPU time 13.34 seconds
Started Mar 24 02:26:27 PM PDT 24
Finished Mar 24 02:26:40 PM PDT 24
Peak memory 264944 kb
Host smart-003a3960-28f0-44ce-bef0-5516d29f62bf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050701418 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_prog_re
set.4050701418
Directory /workspace/16.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_rand_ops.2989309562
Short name T931
Test name
Test status
Simulation time 5246979500 ps
CPU time 582.41 seconds
Started Mar 24 02:26:22 PM PDT 24
Finished Mar 24 02:36:05 PM PDT 24
Peak memory 282616 kb
Host smart-e35000be-32d2-4871-a258-5a153ac73d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989309562 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.2989309562
Directory /workspace/16.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/16.flash_ctrl_re_evict.375556432
Short name T285
Test name
Test status
Simulation time 394435700 ps
CPU time 35.01 seconds
Started Mar 24 02:26:28 PM PDT 24
Finished Mar 24 02:27:03 PM PDT 24
Peak memory 274304 kb
Host smart-3ef487e8-5b31-47f0-9bc1-9fe8be3d6cb4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375556432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla
sh_ctrl_re_evict.375556432
Directory /workspace/16.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_ro.973233782
Short name T70
Test name
Test status
Simulation time 1184326200 ps
CPU time 99.26 seconds
Started Mar 24 02:26:31 PM PDT 24
Finished Mar 24 02:28:10 PM PDT 24
Peak memory 280756 kb
Host smart-a81c5e57-8974-4804-997e-76299ec4d05c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973233782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.flash_ctrl_ro.973233782
Directory /workspace/16.flash_ctrl_ro/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw.2584338548
Short name T103
Test name
Test status
Simulation time 6574201800 ps
CPU time 481.81 seconds
Started Mar 24 02:26:28 PM PDT 24
Finished Mar 24 02:34:30 PM PDT 24
Peak memory 314208 kb
Host smart-466d55d0-7cba-4c7c-9fcc-f83043c522e9
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584338548 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_c
trl_rw.2584338548
Directory /workspace/16.flash_ctrl_rw/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict.1084015797
Short name T341
Test name
Test status
Simulation time 58802200 ps
CPU time 32.07 seconds
Started Mar 24 02:26:28 PM PDT 24
Finished Mar 24 02:27:00 PM PDT 24
Peak memory 272028 kb
Host smart-6cc19911-2337-453b-805f-17e677c3ff27
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084015797 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl
ash_ctrl_rw_evict.1084015797
Directory /workspace/16.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict_all_en.1610832434
Short name T758
Test name
Test status
Simulation time 463483000 ps
CPU time 37.83 seconds
Started Mar 24 02:26:27 PM PDT 24
Finished Mar 24 02:27:06 PM PDT 24
Peak memory 273288 kb
Host smart-34457cbc-575b-47f3-87ff-d20b25eb1518
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610832434 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict_all_en.1610832434
Directory /workspace/16.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/16.flash_ctrl_smoke.2941823420
Short name T743
Test name
Test status
Simulation time 25457900 ps
CPU time 125.39 seconds
Started Mar 24 02:26:20 PM PDT 24
Finished Mar 24 02:28:26 PM PDT 24
Peak memory 276616 kb
Host smart-731a8cbd-0af6-4cfb-b6f9-9a3003d62fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941823420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.2941823420
Directory /workspace/16.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/16.flash_ctrl_wo.4033169006
Short name T475
Test name
Test status
Simulation time 2338452700 ps
CPU time 151.91 seconds
Started Mar 24 02:26:23 PM PDT 24
Finished Mar 24 02:28:55 PM PDT 24
Peak memory 258880 kb
Host smart-5001d300-c1aa-4013-9b58-7c4c4c9c327c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033169006 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.flash_ctrl_wo.4033169006
Directory /workspace/16.flash_ctrl_wo/latest

Test location /workspace/coverage/default/17.flash_ctrl_alert_test.583382514
Short name T418
Test name
Test status
Simulation time 74517800 ps
CPU time 13.78 seconds
Started Mar 24 02:26:56 PM PDT 24
Finished Mar 24 02:27:10 PM PDT 24
Peak memory 264872 kb
Host smart-8c784b6c-0b0b-4562-a9cb-98110b7cdf72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583382514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test.583382514
Directory /workspace/17.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.flash_ctrl_connect.2940350075
Short name T629
Test name
Test status
Simulation time 38256700 ps
CPU time 15.61 seconds
Started Mar 24 02:26:56 PM PDT 24
Finished Mar 24 02:27:11 PM PDT 24
Peak memory 275520 kb
Host smart-eb4ae250-a79f-4605-8c72-0c3bbd83faa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940350075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.2940350075
Directory /workspace/17.flash_ctrl_connect/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.877021947
Short name T683
Test name
Test status
Simulation time 10012301400 ps
CPU time 125.45 seconds
Started Mar 24 02:26:56 PM PDT 24
Finished Mar 24 02:29:02 PM PDT 24
Peak memory 339680 kb
Host smart-a644d310-0445-4c33-919f-e194b040f20e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877021947 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.877021947
Directory /workspace/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.865664137
Short name T756
Test name
Test status
Simulation time 65301200 ps
CPU time 13.79 seconds
Started Mar 24 02:26:54 PM PDT 24
Finished Mar 24 02:27:08 PM PDT 24
Peak memory 264864 kb
Host smart-3d403ed2-b67a-40f9-8c61-98b6abc173e4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865664137 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_read_seed_err.865664137
Directory /workspace/17.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_rma_reset.1388187530
Short name T156
Test name
Test status
Simulation time 80130435100 ps
CPU time 861.89 seconds
Started Mar 24 02:26:38 PM PDT 24
Finished Mar 24 02:41:00 PM PDT 24
Peak memory 263592 kb
Host smart-ecebeeae-da0a-40a5-9db8-90f5070cc16c
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388187530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.flash_ctrl_hw_rma_reset.1388187530
Directory /workspace/17.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_sec_otp.1795986126
Short name T707
Test name
Test status
Simulation time 5982590000 ps
CPU time 122.15 seconds
Started Mar 24 02:26:37 PM PDT 24
Finished Mar 24 02:28:39 PM PDT 24
Peak memory 262228 kb
Host smart-e6fe1c8e-b49f-4166-9aea-32e4277bf458
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795986126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_
hw_sec_otp.1795986126
Directory /workspace/17.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.4227923161
Short name T881
Test name
Test status
Simulation time 37152412000 ps
CPU time 272.99 seconds
Started Mar 24 02:26:46 PM PDT 24
Finished Mar 24 02:31:19 PM PDT 24
Peak memory 289508 kb
Host smart-63a65bc3-fe33-4865-b0e4-1f5fa1a6d2e5
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227923161 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd_slow_flash.4227923161
Directory /workspace/17.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/17.flash_ctrl_lcmgr_intg.2590985358
Short name T998
Test name
Test status
Simulation time 25598600 ps
CPU time 13.59 seconds
Started Mar 24 02:26:55 PM PDT 24
Finished Mar 24 02:27:08 PM PDT 24
Peak memory 264956 kb
Host smart-58ee296c-3150-400a-b41d-8326b3c9188f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590985358 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.flash_ctrl_lcmgr_intg.2590985358
Directory /workspace/17.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/17.flash_ctrl_mp_regions.2265747224
Short name T232
Test name
Test status
Simulation time 9269660500 ps
CPU time 194.03 seconds
Started Mar 24 02:26:36 PM PDT 24
Finished Mar 24 02:29:50 PM PDT 24
Peak memory 264928 kb
Host smart-4486069a-b6bd-4ce9-8128-46404ca16818
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265747224 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 17.flash_ctrl_mp_regions.2265747224
Directory /workspace/17.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/17.flash_ctrl_otp_reset.2635647419
Short name T440
Test name
Test status
Simulation time 68586000 ps
CPU time 113.13 seconds
Started Mar 24 02:26:36 PM PDT 24
Finished Mar 24 02:28:30 PM PDT 24
Peak memory 263868 kb
Host smart-47e60bf5-c9c4-4c23-96ff-7170353ca0d3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635647419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_o
tp_reset.2635647419
Directory /workspace/17.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_phy_arb.1085806063
Short name T194
Test name
Test status
Simulation time 72234400 ps
CPU time 401.01 seconds
Started Mar 24 02:26:36 PM PDT 24
Finished Mar 24 02:33:18 PM PDT 24
Peak memory 262364 kb
Host smart-a4f8961e-7638-448a-ae5c-8df548e49329
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1085806063 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.1085806063
Directory /workspace/17.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/17.flash_ctrl_prog_reset.4249016906
Short name T503
Test name
Test status
Simulation time 82002200 ps
CPU time 15.57 seconds
Started Mar 24 02:26:50 PM PDT 24
Finished Mar 24 02:27:05 PM PDT 24
Peak memory 264924 kb
Host smart-c710077f-46c9-4b48-aee0-2209ba45ffb1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249016906 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_prog_re
set.4249016906
Directory /workspace/17.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_rand_ops.1578472489
Short name T903
Test name
Test status
Simulation time 49212300 ps
CPU time 423.62 seconds
Started Mar 24 02:26:36 PM PDT 24
Finished Mar 24 02:33:39 PM PDT 24
Peak memory 281204 kb
Host smart-0848dcf8-949f-4213-a648-498d8e7c5ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578472489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.1578472489
Directory /workspace/17.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/17.flash_ctrl_re_evict.846996649
Short name T339
Test name
Test status
Simulation time 223190300 ps
CPU time 35.77 seconds
Started Mar 24 02:26:51 PM PDT 24
Finished Mar 24 02:27:27 PM PDT 24
Peak memory 273204 kb
Host smart-3186ec65-22a8-49a2-87ed-d708870763b6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846996649 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla
sh_ctrl_re_evict.846996649
Directory /workspace/17.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_ro.2524142614
Short name T700
Test name
Test status
Simulation time 528461000 ps
CPU time 94.43 seconds
Started Mar 24 02:26:42 PM PDT 24
Finished Mar 24 02:28:16 PM PDT 24
Peak memory 280704 kb
Host smart-bee9cb5e-d3d3-4298-a1e5-07b156d05b42
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524142614 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.flash_ctrl_ro.2524142614
Directory /workspace/17.flash_ctrl_ro/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw.2027644797
Short name T316
Test name
Test status
Simulation time 3947811700 ps
CPU time 569.87 seconds
Started Mar 24 02:26:48 PM PDT 24
Finished Mar 24 02:36:18 PM PDT 24
Peak memory 314068 kb
Host smart-6719fb74-9f6a-47d9-b01b-db770eff6a75
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027644797 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_c
trl_rw.2027644797
Directory /workspace/17.flash_ctrl_rw/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict.4141570385
Short name T759
Test name
Test status
Simulation time 52183500 ps
CPU time 31.41 seconds
Started Mar 24 02:26:47 PM PDT 24
Finished Mar 24 02:27:18 PM PDT 24
Peak memory 273280 kb
Host smart-0b95f2dc-fc45-4765-a2b7-8b1d36260cfd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141570385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl
ash_ctrl_rw_evict.4141570385
Directory /workspace/17.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict_all_en.341133956
Short name T287
Test name
Test status
Simulation time 46788200 ps
CPU time 31.76 seconds
Started Mar 24 02:26:45 PM PDT 24
Finished Mar 24 02:27:17 PM PDT 24
Peak memory 273312 kb
Host smart-2401d77e-c3d8-4906-b7bc-8d0c8b465efb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341133956 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict_all_en.341133956
Directory /workspace/17.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/17.flash_ctrl_sec_info_access.4025534672
Short name T742
Test name
Test status
Simulation time 1934278700 ps
CPU time 63.84 seconds
Started Mar 24 02:26:52 PM PDT 24
Finished Mar 24 02:27:56 PM PDT 24
Peak memory 263288 kb
Host smart-14b14282-123c-4796-8f6e-ef934f2e7e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025534672 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.4025534672
Directory /workspace/17.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/17.flash_ctrl_smoke.2472907260
Short name T874
Test name
Test status
Simulation time 57040000 ps
CPU time 195.35 seconds
Started Mar 24 02:26:37 PM PDT 24
Finished Mar 24 02:29:52 PM PDT 24
Peak memory 276612 kb
Host smart-5339deb2-7e67-4c70-bf43-ce2f06231e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472907260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.2472907260
Directory /workspace/17.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/17.flash_ctrl_wo.1892109577
Short name T476
Test name
Test status
Simulation time 7645529500 ps
CPU time 154.01 seconds
Started Mar 24 02:26:44 PM PDT 24
Finished Mar 24 02:29:18 PM PDT 24
Peak memory 259412 kb
Host smart-eb6e8a05-b729-4fa8-aaeb-6ee7e5e38c1d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892109577 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.flash_ctrl_wo.1892109577
Directory /workspace/17.flash_ctrl_wo/latest

Test location /workspace/coverage/default/18.flash_ctrl_alert_test.3437913204
Short name T740
Test name
Test status
Simulation time 62043300 ps
CPU time 13.7 seconds
Started Mar 24 02:27:21 PM PDT 24
Finished Mar 24 02:27:35 PM PDT 24
Peak memory 264900 kb
Host smart-4ec0ca31-0816-4398-bc35-17c5dab26b55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437913204 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test.
3437913204
Directory /workspace/18.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.flash_ctrl_connect.3757035872
Short name T512
Test name
Test status
Simulation time 38822600 ps
CPU time 13.23 seconds
Started Mar 24 02:27:21 PM PDT 24
Finished Mar 24 02:27:35 PM PDT 24
Peak memory 274520 kb
Host smart-a67a057e-95e4-4d3c-8a0f-801d08ba6123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757035872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.3757035872
Directory /workspace/18.flash_ctrl_connect/latest

Test location /workspace/coverage/default/18.flash_ctrl_disable.3838920048
Short name T379
Test name
Test status
Simulation time 18494000 ps
CPU time 22.41 seconds
Started Mar 24 02:27:15 PM PDT 24
Finished Mar 24 02:27:38 PM PDT 24
Peak memory 264916 kb
Host smart-ad299dd5-18fd-4391-ac19-1a746ddaf774
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838920048 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_disable.3838920048
Directory /workspace/18.flash_ctrl_disable/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.2360035707
Short name T875
Test name
Test status
Simulation time 10039031700 ps
CPU time 48.61 seconds
Started Mar 24 02:27:21 PM PDT 24
Finished Mar 24 02:28:09 PM PDT 24
Peak memory 277240 kb
Host smart-8e2c3253-00c3-4335-bba7-213e938b13d2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360035707 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.2360035707
Directory /workspace/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.2272475548
Short name T163
Test name
Test status
Simulation time 26556200 ps
CPU time 13.47 seconds
Started Mar 24 02:27:22 PM PDT 24
Finished Mar 24 02:27:36 PM PDT 24
Peak memory 265040 kb
Host smart-15b4e77d-5833-41b6-acf8-4ba3b14574fd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272475548 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_read_seed_err.2272475548
Directory /workspace/18.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_rma_reset.1788939831
Short name T614
Test name
Test status
Simulation time 40125479600 ps
CPU time 815.49 seconds
Started Mar 24 02:27:00 PM PDT 24
Finished Mar 24 02:40:36 PM PDT 24
Peak memory 264112 kb
Host smart-e06e019a-48c6-4bea-bcf4-3fb778d0a3f9
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788939831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 18.flash_ctrl_hw_rma_reset.1788939831
Directory /workspace/18.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd_slow_flash.3241448187
Short name T650
Test name
Test status
Simulation time 15667717400 ps
CPU time 256.93 seconds
Started Mar 24 02:27:11 PM PDT 24
Finished Mar 24 02:31:29 PM PDT 24
Peak memory 289424 kb
Host smart-0fbb129b-f6dc-4a94-af49-9d74103dc03a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241448187 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd_slow_flash.3241448187
Directory /workspace/18.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/18.flash_ctrl_invalid_op.498109967
Short name T217
Test name
Test status
Simulation time 1952261400 ps
CPU time 63.3 seconds
Started Mar 24 02:27:06 PM PDT 24
Finished Mar 24 02:28:09 PM PDT 24
Peak memory 260556 kb
Host smart-93c631cc-963e-404b-b5f0-0fcee1bc84a3
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498109967 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.498109967
Directory /workspace/18.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/18.flash_ctrl_lcmgr_intg.1469521077
Short name T927
Test name
Test status
Simulation time 26064100 ps
CPU time 13.56 seconds
Started Mar 24 02:27:21 PM PDT 24
Finished Mar 24 02:27:35 PM PDT 24
Peak memory 264904 kb
Host smart-e537e5bd-f191-4a70-b45a-3b4ff7f34b94
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469521077 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.flash_ctrl_lcmgr_intg.1469521077
Directory /workspace/18.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/18.flash_ctrl_mp_regions.3916413253
Short name T112
Test name
Test status
Simulation time 29013104200 ps
CPU time 527.63 seconds
Started Mar 24 02:27:06 PM PDT 24
Finished Mar 24 02:35:54 PM PDT 24
Peak memory 273872 kb
Host smart-832f0296-8027-4eb9-b30e-6c610f6582ea
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916413253 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 18.flash_ctrl_mp_regions.3916413253
Directory /workspace/18.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/18.flash_ctrl_otp_reset.2552771119
Short name T861
Test name
Test status
Simulation time 227799700 ps
CPU time 109.77 seconds
Started Mar 24 02:27:05 PM PDT 24
Finished Mar 24 02:28:55 PM PDT 24
Peak memory 264372 kb
Host smart-908b0dcb-d0e5-43df-bcc7-01e49f10ea62
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552771119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_o
tp_reset.2552771119
Directory /workspace/18.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_phy_arb.2932669351
Short name T495
Test name
Test status
Simulation time 155264300 ps
CPU time 156.09 seconds
Started Mar 24 02:27:01 PM PDT 24
Finished Mar 24 02:29:37 PM PDT 24
Peak memory 264760 kb
Host smart-55519155-868d-4156-96c8-755daeb0f97f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2932669351 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.2932669351
Directory /workspace/18.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/18.flash_ctrl_prog_reset.2860352219
Short name T592
Test name
Test status
Simulation time 71078800 ps
CPU time 13.65 seconds
Started Mar 24 02:27:15 PM PDT 24
Finished Mar 24 02:27:29 PM PDT 24
Peak memory 260144 kb
Host smart-3f42b6bf-7c0a-4078-a24a-e0cfb893e755
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860352219 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_prog_re
set.2860352219
Directory /workspace/18.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_rand_ops.4020427739
Short name T547
Test name
Test status
Simulation time 21434300 ps
CPU time 72.96 seconds
Started Mar 24 02:27:00 PM PDT 24
Finished Mar 24 02:28:14 PM PDT 24
Peak memory 274548 kb
Host smart-6bdbf6a3-fc59-49bc-b503-71647e353f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020427739 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.4020427739
Directory /workspace/18.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/18.flash_ctrl_re_evict.4133630512
Short name T580
Test name
Test status
Simulation time 73596300 ps
CPU time 31.11 seconds
Started Mar 24 02:27:15 PM PDT 24
Finished Mar 24 02:27:47 PM PDT 24
Peak memory 273296 kb
Host smart-a7055b22-afd7-4a39-962f-9e2888c8634d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133630512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl
ash_ctrl_re_evict.4133630512
Directory /workspace/18.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_ro.168655627
Short name T1051
Test name
Test status
Simulation time 531378700 ps
CPU time 116.85 seconds
Started Mar 24 02:27:10 PM PDT 24
Finished Mar 24 02:29:07 PM PDT 24
Peak memory 280840 kb
Host smart-07a133c0-aea8-49a5-b834-30f7a8143804
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168655627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.flash_ctrl_ro.168655627
Directory /workspace/18.flash_ctrl_ro/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw.1291260126
Short name T729
Test name
Test status
Simulation time 13141224400 ps
CPU time 594.95 seconds
Started Mar 24 02:27:10 PM PDT 24
Finished Mar 24 02:37:06 PM PDT 24
Peak memory 309240 kb
Host smart-016f9aa5-8fcc-447f-b8b5-512e3b1ee5a7
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291260126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_c
trl_rw.1291260126
Directory /workspace/18.flash_ctrl_rw/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict.4168961610
Short name T925
Test name
Test status
Simulation time 176620300 ps
CPU time 36.45 seconds
Started Mar 24 02:27:15 PM PDT 24
Finished Mar 24 02:27:52 PM PDT 24
Peak memory 267108 kb
Host smart-5e66ff7f-10aa-494f-8080-bdf74dffd2cf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168961610 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl
ash_ctrl_rw_evict.4168961610
Directory /workspace/18.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict_all_en.3561026814
Short name T224
Test name
Test status
Simulation time 85406000 ps
CPU time 30.96 seconds
Started Mar 24 02:27:16 PM PDT 24
Finished Mar 24 02:27:47 PM PDT 24
Peak memory 273256 kb
Host smart-174d5b91-4794-430b-b3f5-304430663372
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561026814 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict_all_en.3561026814
Directory /workspace/18.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/18.flash_ctrl_sec_info_access.3779835913
Short name T919
Test name
Test status
Simulation time 1577246500 ps
CPU time 64.15 seconds
Started Mar 24 02:27:22 PM PDT 24
Finished Mar 24 02:28:26 PM PDT 24
Peak memory 264420 kb
Host smart-763904d8-7bed-4f7c-a28f-e68303b3e08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779835913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.3779835913
Directory /workspace/18.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/18.flash_ctrl_smoke.1317555723
Short name T596
Test name
Test status
Simulation time 160905500 ps
CPU time 125.94 seconds
Started Mar 24 02:26:54 PM PDT 24
Finished Mar 24 02:29:01 PM PDT 24
Peak memory 276396 kb
Host smart-f1fb8f32-652f-44e3-85b4-ab1b41c7fe73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317555723 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.1317555723
Directory /workspace/18.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/18.flash_ctrl_wo.273301709
Short name T913
Test name
Test status
Simulation time 27355907600 ps
CPU time 168.19 seconds
Started Mar 24 02:27:06 PM PDT 24
Finished Mar 24 02:29:54 PM PDT 24
Peak memory 258992 kb
Host smart-c63b32b5-b920-443c-9e47-012a525e688c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273301709 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.flash_ctrl_wo.273301709
Directory /workspace/18.flash_ctrl_wo/latest

Test location /workspace/coverage/default/19.flash_ctrl_alert_test.3184943695
Short name T166
Test name
Test status
Simulation time 31042200 ps
CPU time 13.4 seconds
Started Mar 24 02:27:40 PM PDT 24
Finished Mar 24 02:27:54 PM PDT 24
Peak memory 258236 kb
Host smart-4a801a5e-e9ad-4755-8cdd-1b5b0c9c480a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184943695 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test.
3184943695
Directory /workspace/19.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.flash_ctrl_connect.2979218402
Short name T484
Test name
Test status
Simulation time 54105000 ps
CPU time 13.28 seconds
Started Mar 24 02:27:37 PM PDT 24
Finished Mar 24 02:27:52 PM PDT 24
Peak memory 275608 kb
Host smart-7ec67d24-d2b9-476c-93e8-5ac2c56d353a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979218402 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.2979218402
Directory /workspace/19.flash_ctrl_connect/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.198135550
Short name T951
Test name
Test status
Simulation time 10030972400 ps
CPU time 106.3 seconds
Started Mar 24 02:27:43 PM PDT 24
Finished Mar 24 02:29:29 PM PDT 24
Peak memory 275104 kb
Host smart-e184a6dc-6d03-4e65-afc6-387f1a112199
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198135550 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.198135550
Directory /workspace/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_read_seed_err.240975401
Short name T351
Test name
Test status
Simulation time 17294200 ps
CPU time 13.33 seconds
Started Mar 24 02:27:34 PM PDT 24
Finished Mar 24 02:27:48 PM PDT 24
Peak memory 258728 kb
Host smart-ba0371af-4b39-4beb-a92b-eba1042f5472
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240975401 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.240975401
Directory /workspace/19.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_rma_reset.2970414441
Short name T969
Test name
Test status
Simulation time 40126202700 ps
CPU time 812.57 seconds
Started Mar 24 02:27:26 PM PDT 24
Finished Mar 24 02:40:59 PM PDT 24
Peak memory 262648 kb
Host smart-789268e9-4d4a-4c01-84f3-9b5cb56802a1
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970414441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.flash_ctrl_hw_rma_reset.2970414441
Directory /workspace/19.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_sec_otp.424278634
Short name T976
Test name
Test status
Simulation time 12347686600 ps
CPU time 117.57 seconds
Started Mar 24 02:27:26 PM PDT 24
Finished Mar 24 02:29:24 PM PDT 24
Peak memory 262456 kb
Host smart-03526c30-d77b-4875-b591-6857de906d92
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424278634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_h
w_sec_otp.424278634
Directory /workspace/19.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd_slow_flash.3811542426
Short name T325
Test name
Test status
Simulation time 34938948600 ps
CPU time 236.38 seconds
Started Mar 24 02:27:30 PM PDT 24
Finished Mar 24 02:31:27 PM PDT 24
Peak memory 289476 kb
Host smart-5cb1494e-8fd8-4066-965d-a59ac0545857
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811542426 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd_slow_flash.3811542426
Directory /workspace/19.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/19.flash_ctrl_invalid_op.2840211924
Short name T934
Test name
Test status
Simulation time 1237520300 ps
CPU time 95.12 seconds
Started Mar 24 02:27:27 PM PDT 24
Finished Mar 24 02:29:02 PM PDT 24
Peak memory 262480 kb
Host smart-2fb37942-27c0-4ea3-9d57-84788f158c70
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840211924 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.2
840211924
Directory /workspace/19.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/19.flash_ctrl_lcmgr_intg.2411141147
Short name T461
Test name
Test status
Simulation time 15446200 ps
CPU time 13.71 seconds
Started Mar 24 02:27:36 PM PDT 24
Finished Mar 24 02:27:51 PM PDT 24
Peak memory 264976 kb
Host smart-b2f1195d-b691-4888-8d7f-17170b1c8869
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411141147 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.flash_ctrl_lcmgr_intg.2411141147
Directory /workspace/19.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/19.flash_ctrl_mp_regions.2798086674
Short name T114
Test name
Test status
Simulation time 24924182600 ps
CPU time 765.1 seconds
Started Mar 24 02:27:26 PM PDT 24
Finished Mar 24 02:40:12 PM PDT 24
Peak memory 273944 kb
Host smart-1de9efbe-bebf-4198-92b9-dfaee6b2dae7
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798086674 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 19.flash_ctrl_mp_regions.2798086674
Directory /workspace/19.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/19.flash_ctrl_otp_reset.4238036690
Short name T676
Test name
Test status
Simulation time 73596300 ps
CPU time 111.74 seconds
Started Mar 24 02:27:25 PM PDT 24
Finished Mar 24 02:29:17 PM PDT 24
Peak memory 260832 kb
Host smart-d846aec2-2795-41a6-a16c-9a58ba39bfa0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238036690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_o
tp_reset.4238036690
Directory /workspace/19.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_phy_arb.2244933433
Short name T838
Test name
Test status
Simulation time 93950700 ps
CPU time 68.74 seconds
Started Mar 24 02:27:28 PM PDT 24
Finished Mar 24 02:28:37 PM PDT 24
Peak memory 262212 kb
Host smart-cfec01b0-565b-4913-9525-819574bada0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2244933433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.2244933433
Directory /workspace/19.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/19.flash_ctrl_prog_reset.4110896938
Short name T816
Test name
Test status
Simulation time 67419000 ps
CPU time 13.89 seconds
Started Mar 24 02:27:37 PM PDT 24
Finished Mar 24 02:27:52 PM PDT 24
Peak memory 260032 kb
Host smart-d3506868-fe9d-49e6-888a-7523aa099d78
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110896938 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_prog_re
set.4110896938
Directory /workspace/19.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_rand_ops.1566748948
Short name T106
Test name
Test status
Simulation time 189087000 ps
CPU time 616.71 seconds
Started Mar 24 02:27:20 PM PDT 24
Finished Mar 24 02:37:37 PM PDT 24
Peak memory 282212 kb
Host smart-4f86b7bc-ed95-4be7-ba1a-ab9e05b9477d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566748948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.1566748948
Directory /workspace/19.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/19.flash_ctrl_re_evict.1505192184
Short name T207
Test name
Test status
Simulation time 723798500 ps
CPU time 35.43 seconds
Started Mar 24 02:27:33 PM PDT 24
Finished Mar 24 02:28:09 PM PDT 24
Peak memory 273276 kb
Host smart-f8f2ab7b-60e1-42d4-a118-ba43e6c9e43a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505192184 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl
ash_ctrl_re_evict.1505192184
Directory /workspace/19.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_ro.325861311
Short name T695
Test name
Test status
Simulation time 739903500 ps
CPU time 104.86 seconds
Started Mar 24 02:27:29 PM PDT 24
Finished Mar 24 02:29:14 PM PDT 24
Peak memory 280748 kb
Host smart-da68a1c2-aa5f-445e-9d13-10c86b529e1a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325861311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.flash_ctrl_ro.325861311
Directory /workspace/19.flash_ctrl_ro/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw.3208755960
Short name T627
Test name
Test status
Simulation time 7741363600 ps
CPU time 472.75 seconds
Started Mar 24 02:27:28 PM PDT 24
Finished Mar 24 02:35:21 PM PDT 24
Peak memory 314224 kb
Host smart-4fb1d2b8-51ed-4a5b-a430-678f14ab42cc
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208755960 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_c
trl_rw.3208755960
Directory /workspace/19.flash_ctrl_rw/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict.3153451017
Short name T713
Test name
Test status
Simulation time 113186200 ps
CPU time 33.06 seconds
Started Mar 24 02:27:37 PM PDT 24
Finished Mar 24 02:28:11 PM PDT 24
Peak memory 273352 kb
Host smart-8b7177f2-6f6d-45e0-8c99-c4585648940d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153451017 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl
ash_ctrl_rw_evict.3153451017
Directory /workspace/19.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict_all_en.2053207819
Short name T196
Test name
Test status
Simulation time 44205900 ps
CPU time 31 seconds
Started Mar 24 02:27:37 PM PDT 24
Finished Mar 24 02:28:09 PM PDT 24
Peak memory 273268 kb
Host smart-ce2e2910-a35b-4018-8ceb-0714d47067d7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053207819 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict_all_en.2053207819
Directory /workspace/19.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/19.flash_ctrl_sec_info_access.1990262994
Short name T584
Test name
Test status
Simulation time 1822125200 ps
CPU time 76.84 seconds
Started Mar 24 02:27:34 PM PDT 24
Finished Mar 24 02:28:52 PM PDT 24
Peak memory 262140 kb
Host smart-b6e154a2-f639-4955-925d-ad4082218532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990262994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.1990262994
Directory /workspace/19.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/19.flash_ctrl_smoke.1859450798
Short name T502
Test name
Test status
Simulation time 29340100 ps
CPU time 125.49 seconds
Started Mar 24 02:27:23 PM PDT 24
Finished Mar 24 02:29:28 PM PDT 24
Peak memory 277432 kb
Host smart-e059c0c0-cb6f-4629-b945-554886c2a1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859450798 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.1859450798
Directory /workspace/19.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/19.flash_ctrl_wo.3076256893
Short name T898
Test name
Test status
Simulation time 8644381600 ps
CPU time 183.91 seconds
Started Mar 24 02:27:25 PM PDT 24
Finished Mar 24 02:30:29 PM PDT 24
Peak memory 258980 kb
Host smart-9250fade-d87b-4e53-b71a-063eb5e1691b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076256893 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.flash_ctrl_wo.3076256893
Directory /workspace/19.flash_ctrl_wo/latest

Test location /workspace/coverage/default/2.flash_ctrl_access_after_disable.3134297090
Short name T46
Test name
Test status
Simulation time 33157900 ps
CPU time 13.71 seconds
Started Mar 24 02:18:03 PM PDT 24
Finished Mar 24 02:18:16 PM PDT 24
Peak memory 264972 kb
Host smart-fbe441fa-c2a0-4484-aead-56c0799a9685
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134297090 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.3134297090
Directory /workspace/2.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_alert_test.1207535126
Short name T943
Test name
Test status
Simulation time 48524900 ps
CPU time 13.97 seconds
Started Mar 24 02:18:16 PM PDT 24
Finished Mar 24 02:18:30 PM PDT 24
Peak memory 257960 kb
Host smart-dd8286a1-1b4b-423c-8269-f9faca540dc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207535126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.1
207535126
Directory /workspace/2.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.flash_ctrl_connect.3567776664
Short name T1044
Test name
Test status
Simulation time 13330400 ps
CPU time 15.76 seconds
Started Mar 24 02:17:55 PM PDT 24
Finished Mar 24 02:18:11 PM PDT 24
Peak memory 275612 kb
Host smart-9bde8bb5-0a59-4f5c-bfe4-4063b67eedbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567776664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.3567776664
Directory /workspace/2.flash_ctrl_connect/latest

Test location /workspace/coverage/default/2.flash_ctrl_derr_detect.2946300108
Short name T604
Test name
Test status
Simulation time 180235500 ps
CPU time 104.56 seconds
Started Mar 24 02:17:38 PM PDT 24
Finished Mar 24 02:19:24 PM PDT 24
Peak memory 272204 kb
Host smart-df9235c9-a254-4dfd-81ea-f859265f9d12
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946300108 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_derr_detect.2946300108
Directory /workspace/2.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/2.flash_ctrl_disable.16156859
Short name T229
Test name
Test status
Simulation time 20386300 ps
CPU time 22.2 seconds
Started Mar 24 02:17:52 PM PDT 24
Finished Mar 24 02:18:14 PM PDT 24
Peak memory 265000 kb
Host smart-d94e791d-a53e-402f-884b-110f363486d8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16156859 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.flash_ctrl_disable.16156859
Directory /workspace/2.flash_ctrl_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_erase_suspend.1371239231
Short name T776
Test name
Test status
Simulation time 4252074800 ps
CPU time 444.5 seconds
Started Mar 24 02:17:15 PM PDT 24
Finished Mar 24 02:24:39 PM PDT 24
Peak memory 261068 kb
Host smart-5baa9f26-bf16-4a36-9986-d6c75648e5b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1371239231 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.1371239231
Directory /workspace/2.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_mp.121832295
Short name T658
Test name
Test status
Simulation time 6781720700 ps
CPU time 2303.12 seconds
Started Mar 24 02:17:29 PM PDT 24
Finished Mar 24 02:55:53 PM PDT 24
Peak memory 264620 kb
Host smart-76c3efbf-8b97-4fea-839d-387ad6d57c73
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121832295 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erro
r_mp.121832295
Directory /workspace/2.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_type.3832528496
Short name T781
Test name
Test status
Simulation time 809474600 ps
CPU time 2051.14 seconds
Started Mar 24 02:17:18 PM PDT 24
Finished Mar 24 02:51:30 PM PDT 24
Peak memory 264592 kb
Host smart-d92dce3e-30db-4c3f-b272-a235c918245a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832528496 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_type.3832528496
Directory /workspace/2.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_win.787417111
Short name T901
Test name
Test status
Simulation time 4169503200 ps
CPU time 822.97 seconds
Started Mar 24 02:17:22 PM PDT 24
Finished Mar 24 02:31:05 PM PDT 24
Peak memory 273092 kb
Host smart-7e1649b2-a206-4668-9e0b-ae4b04011045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787417111 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.787417111
Directory /workspace/2.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/2.flash_ctrl_fetch_code.3805690524
Short name T47
Test name
Test status
Simulation time 308479400 ps
CPU time 22.36 seconds
Started Mar 24 02:17:17 PM PDT 24
Finished Mar 24 02:17:40 PM PDT 24
Peak memory 264796 kb
Host smart-9998e10b-870f-45ab-9d3c-725e6d1fb574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805690524 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetch_code.3805690524
Directory /workspace/2.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/2.flash_ctrl_fs_sup.3204170165
Short name T1034
Test name
Test status
Simulation time 300485600 ps
CPU time 41.56 seconds
Started Mar 24 02:18:01 PM PDT 24
Finished Mar 24 02:18:43 PM PDT 24
Peak memory 273144 kb
Host smart-8de61ea5-49e5-47df-8411-71ce1690bac8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204170165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.flash_ctrl_fs_sup.3204170165
Directory /workspace/2.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/2.flash_ctrl_full_mem_access.1781547693
Short name T68
Test name
Test status
Simulation time 122695681100 ps
CPU time 2720.26 seconds
Started Mar 24 02:17:18 PM PDT 24
Finished Mar 24 03:02:39 PM PDT 24
Peak memory 264780 kb
Host smart-43a5fc11-a82b-42fb-beb6-7dc2a9c785ba
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781547693 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_c
trl_full_mem_access.1781547693
Directory /workspace/2.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_dir_rd.3135472727
Short name T994
Test name
Test status
Simulation time 89892900 ps
CPU time 81.84 seconds
Started Mar 24 02:17:03 PM PDT 24
Finished Mar 24 02:18:24 PM PDT 24
Peak memory 262220 kb
Host smart-0fbfacae-d4d7-46ca-a2b4-0cd102d05eba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3135472727 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.3135472727
Directory /workspace/2.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.193720906
Short name T697
Test name
Test status
Simulation time 10067879400 ps
CPU time 46.12 seconds
Started Mar 24 02:18:17 PM PDT 24
Finished Mar 24 02:19:04 PM PDT 24
Peak memory 265100 kb
Host smart-d748c182-40b1-445f-adfc-595ab905cb47
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193720906 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.193720906
Directory /workspace/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_read_seed_err.448331321
Short name T290
Test name
Test status
Simulation time 36322900 ps
CPU time 13.32 seconds
Started Mar 24 02:18:17 PM PDT 24
Finished Mar 24 02:18:31 PM PDT 24
Peak memory 258164 kb
Host smart-515a8e83-0b62-4d05-906c-d76f44358d77
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448331321 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_read_seed_err.448331321
Directory /workspace/2.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma.2732720629
Short name T870
Test name
Test status
Simulation time 83679118900 ps
CPU time 1933.42 seconds
Started Mar 24 02:17:17 PM PDT 24
Finished Mar 24 02:49:31 PM PDT 24
Peak memory 262476 kb
Host smart-3f941007-2228-49fe-8c7f-8f16e737d16c
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732720629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.flash_ctrl_hw_rma.2732720629
Directory /workspace/2.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma_reset.230895490
Short name T661
Test name
Test status
Simulation time 160152927400 ps
CPU time 817.36 seconds
Started Mar 24 02:17:19 PM PDT 24
Finished Mar 24 02:30:57 PM PDT 24
Peak memory 263272 kb
Host smart-ce9af2e3-1639-4c89-9b4f-40d4b145c1f4
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230895490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_hw_rma_reset.230895490
Directory /workspace/2.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_sec_otp.1351280634
Short name T858
Test name
Test status
Simulation time 1801474200 ps
CPU time 68.86 seconds
Started Mar 24 02:17:07 PM PDT 24
Finished Mar 24 02:18:16 PM PDT 24
Peak memory 262280 kb
Host smart-0b32cb86-6085-4712-b4b9-d23a658a1ed4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351280634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_h
w_sec_otp.1351280634
Directory /workspace/2.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd_slow_flash.2668014136
Short name T606
Test name
Test status
Simulation time 139177495000 ps
CPU time 248.48 seconds
Started Mar 24 02:17:49 PM PDT 24
Finished Mar 24 02:21:58 PM PDT 24
Peak memory 289408 kb
Host smart-bed9b28c-bd5e-4273-b466-6b64cc43912f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668014136 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd_slow_flash.2668014136
Directory /workspace/2.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr.277276777
Short name T446
Test name
Test status
Simulation time 8175617400 ps
CPU time 92.13 seconds
Started Mar 24 02:17:42 PM PDT 24
Finished Mar 24 02:19:15 PM PDT 24
Peak memory 265004 kb
Host smart-6d7e6acb-0848-42c1-945f-21a5f0cb63f1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277276777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.flash_ctrl_intr_wr.277276777
Directory /workspace/2.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr_slow_flash.2168140827
Short name T1050
Test name
Test status
Simulation time 43685056500 ps
CPU time 360.82 seconds
Started Mar 24 02:17:47 PM PDT 24
Finished Mar 24 02:23:50 PM PDT 24
Peak memory 260912 kb
Host smart-133f3fd4-368f-4929-a23c-04502c4c8d50
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216
8140827 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.2168140827
Directory /workspace/2.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_invalid_op.2330271633
Short name T864
Test name
Test status
Simulation time 4185293200 ps
CPU time 69.37 seconds
Started Mar 24 02:17:29 PM PDT 24
Finished Mar 24 02:18:38 PM PDT 24
Peak memory 260372 kb
Host smart-2763637c-2b1a-49e1-8840-0fd068ca1908
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330271633 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.2330271633
Directory /workspace/2.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_lcmgr_intg.75297612
Short name T131
Test name
Test status
Simulation time 80401300 ps
CPU time 13.37 seconds
Started Mar 24 02:18:12 PM PDT 24
Finished Mar 24 02:18:26 PM PDT 24
Peak memory 264944 kb
Host smart-908e05e0-5027-48e6-9902-b141f7a24663
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75297612 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 2.flash_ctrl_lcmgr_intg.75297612
Directory /workspace/2.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_mid_op_rst.289507441
Short name T116
Test name
Test status
Simulation time 677563900 ps
CPU time 77.81 seconds
Started Mar 24 02:17:30 PM PDT 24
Finished Mar 24 02:18:48 PM PDT 24
Peak memory 264696 kb
Host smart-6ac3a617-eb4d-4453-859b-6eda73792b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289507441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.289507441
Directory /workspace/2.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/2.flash_ctrl_mp_regions.1080319330
Short name T236
Test name
Test status
Simulation time 14825457700 ps
CPU time 265.94 seconds
Started Mar 24 02:17:21 PM PDT 24
Finished Mar 24 02:21:47 PM PDT 24
Peak memory 273276 kb
Host smart-d57a8027-845a-4bb4-927f-d21347e6e1d3
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080319330 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_mp_regions.1080319330
Directory /workspace/2.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/2.flash_ctrl_otp_reset.2091406418
Short name T985
Test name
Test status
Simulation time 43496400 ps
CPU time 110 seconds
Started Mar 24 02:17:16 PM PDT 24
Finished Mar 24 02:19:06 PM PDT 24
Peak memory 260784 kb
Host smart-080ed74f-bbcd-4b65-b6a0-5dbb463e818e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091406418 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ot
p_reset.2091406418
Directory /workspace/2.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_oversize_error.2863510595
Short name T208
Test name
Test status
Simulation time 812043400 ps
CPU time 159.3 seconds
Started Mar 24 02:17:38 PM PDT 24
Finished Mar 24 02:20:17 PM PDT 24
Peak memory 281492 kb
Host smart-f2f4e6ab-1ea7-42f8-a431-e66a3c2fdf07
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863510595 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_oversize_error.2863510595
Directory /workspace/2.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_ack_consistency.1718652955
Short name T65
Test name
Test status
Simulation time 26786100 ps
CPU time 13.76 seconds
Started Mar 24 02:18:09 PM PDT 24
Finished Mar 24 02:18:23 PM PDT 24
Peak memory 276364 kb
Host smart-1fd2d5ab-baff-4142-a109-3e3d4b13521f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1718652955 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.1718652955
Directory /workspace/2.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb.387815148
Short name T6
Test name
Test status
Simulation time 59712500 ps
CPU time 275.18 seconds
Started Mar 24 02:17:08 PM PDT 24
Finished Mar 24 02:21:44 PM PDT 24
Peak memory 262376 kb
Host smart-dc14e9af-6f41-4911-a2aa-243519e326ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=387815148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.387815148
Directory /workspace/2.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb_redun.1737663488
Short name T61
Test name
Test status
Simulation time 624950000 ps
CPU time 39.19 seconds
Started Mar 24 02:18:07 PM PDT 24
Finished Mar 24 02:18:47 PM PDT 24
Peak memory 264872 kb
Host smart-4b67fb77-3090-4ce1-9924-d2d67419826f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737663488 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.1737663488
Directory /workspace/2.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_host_grant_err.4273578299
Short name T123
Test name
Test status
Simulation time 15450700 ps
CPU time 13.59 seconds
Started Mar 24 02:18:09 PM PDT 24
Finished Mar 24 02:18:23 PM PDT 24
Peak memory 265124 kb
Host smart-ece95e6a-ec9f-41e6-8b49-694dfbfa225e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273578299 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.4273578299
Directory /workspace/2.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_prog_reset.1450946770
Short name T429
Test name
Test status
Simulation time 79433100 ps
CPU time 13.77 seconds
Started Mar 24 02:17:48 PM PDT 24
Finished Mar 24 02:18:04 PM PDT 24
Peak memory 260152 kb
Host smart-e2c8ff09-00cf-44e4-9e85-fb2c320a41c3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450946770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_prog_res
et.1450946770
Directory /workspace/2.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_rand_ops.2240822589
Short name T441
Test name
Test status
Simulation time 77372500 ps
CPU time 109.67 seconds
Started Mar 24 02:17:02 PM PDT 24
Finished Mar 24 02:18:52 PM PDT 24
Peak memory 268640 kb
Host smart-7305ec81-cf99-4b9d-bc2d-a101ddcb7ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240822589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.2240822589
Directory /workspace/2.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_buff_evict.49752515
Short name T929
Test name
Test status
Simulation time 52060400 ps
CPU time 104.02 seconds
Started Mar 24 02:17:07 PM PDT 24
Finished Mar 24 02:18:52 PM PDT 24
Peak memory 264672 kb
Host smart-67b6cd64-772c-4f00-9a33-07b7a36258ce
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=49752515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.49752515
Directory /workspace/2.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_re_evict.1709550224
Short name T439
Test name
Test status
Simulation time 797277700 ps
CPU time 36.41 seconds
Started Mar 24 02:17:48 PM PDT 24
Finished Mar 24 02:18:26 PM PDT 24
Peak memory 276932 kb
Host smart-dabcdcf2-1c26-455f-8475-4449f47ea846
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709550224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_re_evict.1709550224
Directory /workspace/2.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_derr.4248503998
Short name T203
Test name
Test status
Simulation time 20662000 ps
CPU time 22.34 seconds
Started Mar 24 02:17:37 PM PDT 24
Finished Mar 24 02:18:00 PM PDT 24
Peak memory 264940 kb
Host smart-84c9ba6c-0463-43f4-9cbc-257473666ec9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248503998 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_derr.4248503998
Directory /workspace/2.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_serr.2706547334
Short name T33
Test name
Test status
Simulation time 38621700 ps
CPU time 22.69 seconds
Started Mar 24 02:17:28 PM PDT 24
Finished Mar 24 02:17:51 PM PDT 24
Peak memory 265056 kb
Host smart-dd812c67-d27a-4ee0-beba-49ee81d447a1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706547334 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fl
ash_ctrl_read_word_sweep_serr.2706547334
Directory /workspace/2.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro.3009691742
Short name T220
Test name
Test status
Simulation time 4107584000 ps
CPU time 126.19 seconds
Started Mar 24 02:17:30 PM PDT 24
Finished Mar 24 02:19:37 PM PDT 24
Peak memory 280744 kb
Host smart-15f99de0-b2b3-4a76-9583-130a0ca0a545
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009691742 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.flash_ctrl_ro.3009691742
Directory /workspace/2.flash_ctrl_ro/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw.174093071
Short name T69
Test name
Test status
Simulation time 14507278900 ps
CPU time 627.97 seconds
Started Mar 24 02:17:28 PM PDT 24
Finished Mar 24 02:27:56 PM PDT 24
Peak memory 314132 kb
Host smart-cdcb96c7-5d16-472b-9f55-1d54e8a165ee
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174093071 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctr
l_rw.174093071
Directory /workspace/2.flash_ctrl_rw/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict.991191173
Short name T288
Test name
Test status
Simulation time 69717500 ps
CPU time 33.63 seconds
Started Mar 24 02:17:47 PM PDT 24
Finished Mar 24 02:18:22 PM PDT 24
Peak memory 266076 kb
Host smart-191797ca-bba8-4674-87a3-e159e3a2593f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991191173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_rw_evict.991191173
Directory /workspace/2.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict_all_en.2771153943
Short name T665
Test name
Test status
Simulation time 70408400 ps
CPU time 31.3 seconds
Started Mar 24 02:17:49 PM PDT 24
Finished Mar 24 02:18:22 PM PDT 24
Peak memory 272404 kb
Host smart-83fe862f-8d62-425c-8bcb-68f2d9c88943
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771153943 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict_all_en.2771153943
Directory /workspace/2.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_cm.2354565808
Short name T14
Test name
Test status
Simulation time 13480534300 ps
CPU time 4765.92 seconds
Started Mar 24 02:17:52 PM PDT 24
Finished Mar 24 03:37:18 PM PDT 24
Peak memory 282280 kb
Host smart-9a3ffbe8-f10b-485f-9048-35cd32cba4fc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354565808 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.2354565808
Directory /workspace/2.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_info_access.3742823319
Short name T846
Test name
Test status
Simulation time 527498100 ps
CPU time 59.43 seconds
Started Mar 24 02:17:52 PM PDT 24
Finished Mar 24 02:18:51 PM PDT 24
Peak memory 261852 kb
Host smart-91952be3-3c7f-4dbc-9599-a2946a7c590c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742823319 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.3742823319
Directory /workspace/2.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_address.773697889
Short name T481
Test name
Test status
Simulation time 2674512400 ps
CPU time 57.01 seconds
Started Mar 24 02:17:40 PM PDT 24
Finished Mar 24 02:18:38 PM PDT 24
Peak memory 265116 kb
Host smart-1227c0c2-5d2d-4fea-8468-ae217578f57f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773697889 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.flash_ctrl_serr_address.773697889
Directory /workspace/2.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_counter.4138944366
Short name T543
Test name
Test status
Simulation time 635433400 ps
CPU time 73.47 seconds
Started Mar 24 02:17:32 PM PDT 24
Finished Mar 24 02:18:46 PM PDT 24
Peak memory 273304 kb
Host smart-a948cb7f-5e5f-47ba-9469-83b261aa25ca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138944366 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_serr_counter.4138944366
Directory /workspace/2.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke.3809014391
Short name T880
Test name
Test status
Simulation time 75540100 ps
CPU time 72.56 seconds
Started Mar 24 02:17:02 PM PDT 24
Finished Mar 24 02:18:15 PM PDT 24
Peak memory 274700 kb
Host smart-b41a0222-2a9b-44b7-82b1-feeec4ac0f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809014391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.3809014391
Directory /workspace/2.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke_hw.2300127920
Short name T533
Test name
Test status
Simulation time 15791000 ps
CPU time 25.49 seconds
Started Mar 24 02:17:03 PM PDT 24
Finished Mar 24 02:17:28 PM PDT 24
Peak memory 258588 kb
Host smart-d3c67c01-2f39-49db-9786-4b237b6474b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300127920 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.2300127920
Directory /workspace/2.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/2.flash_ctrl_stress_all.833742674
Short name T935
Test name
Test status
Simulation time 116968400 ps
CPU time 453.5 seconds
Started Mar 24 02:17:57 PM PDT 24
Finished Mar 24 02:25:30 PM PDT 24
Peak memory 279248 kb
Host smart-22045e87-2150-440e-adbd-4a2e99a8dc3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833742674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stress
_all.833742674
Directory /workspace/2.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.flash_ctrl_sw_op.1624888821
Short name T686
Test name
Test status
Simulation time 51230500 ps
CPU time 26.88 seconds
Started Mar 24 02:17:05 PM PDT 24
Finished Mar 24 02:17:32 PM PDT 24
Peak memory 261156 kb
Host smart-f77a82d0-5806-44a1-8a73-9eb2df1855ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624888821 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.1624888821
Directory /workspace/2.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_wo.2719671043
Short name T469
Test name
Test status
Simulation time 5683461300 ps
CPU time 199.1 seconds
Started Mar 24 02:17:29 PM PDT 24
Finished Mar 24 02:20:48 PM PDT 24
Peak memory 259588 kb
Host smart-a465d1ec-4088-4094-8aae-f1cfcabef64b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719671043 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.flash_ctrl_wo.2719671043
Directory /workspace/2.flash_ctrl_wo/latest

Test location /workspace/coverage/default/2.flash_ctrl_wr_intg.876181326
Short name T298
Test name
Test status
Simulation time 347737700 ps
CPU time 15.16 seconds
Started Mar 24 02:18:01 PM PDT 24
Finished Mar 24 02:18:17 PM PDT 24
Peak memory 260340 kb
Host smart-dcc08dfd-b829-44ff-84f0-b495b831eb6b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876181326 -assert nopostproc +UVM
_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wr_intg.876181326
Directory /workspace/2.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/20.flash_ctrl_alert_test.970828846
Short name T448
Test name
Test status
Simulation time 34040700 ps
CPU time 13.63 seconds
Started Mar 24 02:27:44 PM PDT 24
Finished Mar 24 02:27:59 PM PDT 24
Peak memory 258028 kb
Host smart-be4f4eea-bd6b-42c9-8a8a-561a15b80c84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970828846 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.970828846
Directory /workspace/20.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.flash_ctrl_connect.3816165714
Short name T178
Test name
Test status
Simulation time 33732400 ps
CPU time 15.63 seconds
Started Mar 24 02:27:47 PM PDT 24
Finished Mar 24 02:28:03 PM PDT 24
Peak memory 275220 kb
Host smart-2b77772d-61e1-498d-9fcf-e5402b08056c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816165714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.3816165714
Directory /workspace/20.flash_ctrl_connect/latest

Test location /workspace/coverage/default/20.flash_ctrl_disable.357070093
Short name T974
Test name
Test status
Simulation time 13459500 ps
CPU time 21.68 seconds
Started Mar 24 02:27:39 PM PDT 24
Finished Mar 24 02:28:02 PM PDT 24
Peak memory 265016 kb
Host smart-11e93177-68e5-4c5a-9220-623ef9fa1200
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357070093 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_disable.357070093
Directory /workspace/20.flash_ctrl_disable/latest

Test location /workspace/coverage/default/20.flash_ctrl_hw_sec_otp.3632226495
Short name T172
Test name
Test status
Simulation time 15848706300 ps
CPU time 115.4 seconds
Started Mar 24 02:27:46 PM PDT 24
Finished Mar 24 02:29:41 PM PDT 24
Peak memory 262272 kb
Host smart-6d6620c9-a3a2-42af-8b82-913413cf6727
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632226495 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_
hw_sec_otp.3632226495
Directory /workspace/20.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/20.flash_ctrl_otp_reset.3961854122
Short name T82
Test name
Test status
Simulation time 37937700 ps
CPU time 131.12 seconds
Started Mar 24 02:27:40 PM PDT 24
Finished Mar 24 02:29:52 PM PDT 24
Peak memory 260888 kb
Host smart-ffd14a51-ebfa-48cf-bcb2-98e7c40fe027
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961854122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_o
tp_reset.3961854122
Directory /workspace/20.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_prog_reset.537138699
Short name T505
Test name
Test status
Simulation time 571575100 ps
CPU time 21.49 seconds
Started Mar 24 02:27:40 PM PDT 24
Finished Mar 24 02:28:02 PM PDT 24
Peak memory 264968 kb
Host smart-17c11054-5a78-4f93-82e2-340305182712
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537138699 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_prog_res
et.537138699
Directory /workspace/20.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict.813009398
Short name T336
Test name
Test status
Simulation time 403003200 ps
CPU time 35.12 seconds
Started Mar 24 02:27:38 PM PDT 24
Finished Mar 24 02:28:14 PM PDT 24
Peak memory 273312 kb
Host smart-acc510a6-0ff5-4555-8e4a-70205ff16c01
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813009398 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fla
sh_ctrl_rw_evict.813009398
Directory /workspace/20.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict_all_en.2397741538
Short name T447
Test name
Test status
Simulation time 94894600 ps
CPU time 28.46 seconds
Started Mar 24 02:27:41 PM PDT 24
Finished Mar 24 02:28:10 PM PDT 24
Peak memory 275368 kb
Host smart-4683e2b2-f373-4493-9701-1905942cbc0f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397741538 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict_all_en.2397741538
Directory /workspace/20.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/20.flash_ctrl_sec_info_access.493065349
Short name T821
Test name
Test status
Simulation time 2143292100 ps
CPU time 69.7 seconds
Started Mar 24 02:27:44 PM PDT 24
Finished Mar 24 02:28:55 PM PDT 24
Peak memory 262720 kb
Host smart-1957255f-8061-4bf4-b7dd-0dece4e55612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493065349 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.493065349
Directory /workspace/20.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/20.flash_ctrl_smoke.1279944024
Short name T819
Test name
Test status
Simulation time 26455800 ps
CPU time 171.56 seconds
Started Mar 24 02:27:40 PM PDT 24
Finished Mar 24 02:30:32 PM PDT 24
Peak memory 279024 kb
Host smart-4a88cae5-7c4f-403f-a579-3c46a405241d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279944024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.1279944024
Directory /workspace/20.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/21.flash_ctrl_alert_test.4215873236
Short name T1023
Test name
Test status
Simulation time 59538900 ps
CPU time 13.6 seconds
Started Mar 24 02:27:53 PM PDT 24
Finished Mar 24 02:28:07 PM PDT 24
Peak memory 264904 kb
Host smart-33a61257-9322-472f-be55-ac31cb0ae10f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215873236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test.
4215873236
Directory /workspace/21.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.flash_ctrl_connect.1512851563
Short name T530
Test name
Test status
Simulation time 50705100 ps
CPU time 13.74 seconds
Started Mar 24 02:27:55 PM PDT 24
Finished Mar 24 02:28:09 PM PDT 24
Peak memory 275448 kb
Host smart-eab1ff4b-b009-423c-8f3d-415f6e26ef7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512851563 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.1512851563
Directory /workspace/21.flash_ctrl_connect/latest

Test location /workspace/coverage/default/21.flash_ctrl_disable.2050516031
Short name T620
Test name
Test status
Simulation time 10755100 ps
CPU time 21.87 seconds
Started Mar 24 02:27:54 PM PDT 24
Finished Mar 24 02:28:16 PM PDT 24
Peak memory 264852 kb
Host smart-263147eb-de96-44bc-8631-e37f65cedcdc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050516031 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.flash_ctrl_disable.2050516031
Directory /workspace/21.flash_ctrl_disable/latest

Test location /workspace/coverage/default/21.flash_ctrl_hw_sec_otp.2800170976
Short name T422
Test name
Test status
Simulation time 7076991200 ps
CPU time 44.48 seconds
Started Mar 24 02:27:50 PM PDT 24
Finished Mar 24 02:28:35 PM PDT 24
Peak memory 261836 kb
Host smart-27d38caa-a644-4185-bcb7-647ae0a33011
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800170976 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_
hw_sec_otp.2800170976
Directory /workspace/21.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd.395313384
Short name T30
Test name
Test status
Simulation time 1133595400 ps
CPU time 170.33 seconds
Started Mar 24 02:27:49 PM PDT 24
Finished Mar 24 02:30:39 PM PDT 24
Peak memory 285004 kb
Host smart-438d209a-c298-4b03-b29b-2060b3576c9e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395313384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flas
h_ctrl_intr_rd.395313384
Directory /workspace/21.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd_slow_flash.2318734794
Short name T960
Test name
Test status
Simulation time 83194717000 ps
CPU time 241.92 seconds
Started Mar 24 02:27:50 PM PDT 24
Finished Mar 24 02:31:52 PM PDT 24
Peak memory 284676 kb
Host smart-4c5b5e75-1a8d-4b7f-87d9-736cb37cde8d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318734794 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd_slow_flash.2318734794
Directory /workspace/21.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/21.flash_ctrl_prog_reset.730292596
Short name T516
Test name
Test status
Simulation time 70602000 ps
CPU time 13.65 seconds
Started Mar 24 02:27:48 PM PDT 24
Finished Mar 24 02:28:02 PM PDT 24
Peak memory 260028 kb
Host smart-1dc8dacb-2e35-4f53-85db-fd605d3fc2df
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730292596 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_prog_res
et.730292596
Directory /workspace/21.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict.1687645618
Short name T829
Test name
Test status
Simulation time 187973300 ps
CPU time 33.09 seconds
Started Mar 24 02:27:51 PM PDT 24
Finished Mar 24 02:28:24 PM PDT 24
Peak memory 273272 kb
Host smart-25931f46-e365-428d-874d-acf5e44e572e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687645618 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fl
ash_ctrl_rw_evict.1687645618
Directory /workspace/21.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict_all_en.1974266333
Short name T214
Test name
Test status
Simulation time 64964800 ps
CPU time 31.02 seconds
Started Mar 24 02:27:55 PM PDT 24
Finished Mar 24 02:28:26 PM PDT 24
Peak memory 273280 kb
Host smart-6f73dc24-4230-4188-8d06-620d11a0c9d7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974266333 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict_all_en.1974266333
Directory /workspace/21.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/21.flash_ctrl_sec_info_access.2532177119
Short name T385
Test name
Test status
Simulation time 665664900 ps
CPU time 55.28 seconds
Started Mar 24 02:27:54 PM PDT 24
Finished Mar 24 02:28:49 PM PDT 24
Peak memory 262700 kb
Host smart-e391af29-424d-401c-878b-f8f6f507ed51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532177119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.2532177119
Directory /workspace/21.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/21.flash_ctrl_smoke.944585250
Short name T930
Test name
Test status
Simulation time 45699100 ps
CPU time 96.8 seconds
Started Mar 24 02:27:44 PM PDT 24
Finished Mar 24 02:29:21 PM PDT 24
Peak memory 275400 kb
Host smart-75adff82-f3d2-48cf-a702-2eedd7c41286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944585250 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.944585250
Directory /workspace/21.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/22.flash_ctrl_alert_test.4160132345
Short name T536
Test name
Test status
Simulation time 49422100 ps
CPU time 13.62 seconds
Started Mar 24 02:28:03 PM PDT 24
Finished Mar 24 02:28:16 PM PDT 24
Peak memory 258096 kb
Host smart-7a79e76e-edba-4d46-b8a9-eeb1119e4945
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160132345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.
4160132345
Directory /workspace/22.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.flash_ctrl_connect.2437284251
Short name T415
Test name
Test status
Simulation time 26671200 ps
CPU time 15.63 seconds
Started Mar 24 02:28:04 PM PDT 24
Finished Mar 24 02:28:19 PM PDT 24
Peak memory 275516 kb
Host smart-077cbc29-dfb6-4ef9-839a-86f8b34bbef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437284251 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.2437284251
Directory /workspace/22.flash_ctrl_connect/latest

Test location /workspace/coverage/default/22.flash_ctrl_disable.2341339276
Short name T744
Test name
Test status
Simulation time 18919600 ps
CPU time 21.24 seconds
Started Mar 24 02:28:03 PM PDT 24
Finished Mar 24 02:28:24 PM PDT 24
Peak memory 273176 kb
Host smart-31fa5591-0394-46ba-9e77-d692573d6fec
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341339276 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.flash_ctrl_disable.2341339276
Directory /workspace/22.flash_ctrl_disable/latest

Test location /workspace/coverage/default/22.flash_ctrl_hw_sec_otp.2595708881
Short name T785
Test name
Test status
Simulation time 2631279300 ps
CPU time 62.33 seconds
Started Mar 24 02:27:55 PM PDT 24
Finished Mar 24 02:28:57 PM PDT 24
Peak memory 262384 kb
Host smart-15b57cfe-1beb-4d00-80f9-4cb72564e7db
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595708881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_
hw_sec_otp.2595708881
Directory /workspace/22.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd_slow_flash.1287031039
Short name T31
Test name
Test status
Simulation time 38796952700 ps
CPU time 226.76 seconds
Started Mar 24 02:27:57 PM PDT 24
Finished Mar 24 02:31:44 PM PDT 24
Peak memory 289520 kb
Host smart-9f67f5a6-32ea-409d-8e54-7109cd104327
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287031039 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd_slow_flash.1287031039
Directory /workspace/22.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/22.flash_ctrl_otp_reset.536048344
Short name T147
Test name
Test status
Simulation time 195788000 ps
CPU time 135.78 seconds
Started Mar 24 02:27:55 PM PDT 24
Finished Mar 24 02:30:11 PM PDT 24
Peak memory 264412 kb
Host smart-65e68b35-31de-4938-8910-7aa20600f8cf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536048344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_ot
p_reset.536048344
Directory /workspace/22.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_prog_reset.2159925105
Short name T993
Test name
Test status
Simulation time 76541300 ps
CPU time 13.42 seconds
Started Mar 24 02:28:05 PM PDT 24
Finished Mar 24 02:28:18 PM PDT 24
Peak memory 260280 kb
Host smart-c9ee35fd-c411-42fb-aa43-254e5e183f6b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159925105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_prog_re
set.2159925105
Directory /workspace/22.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict.2784448055
Short name T518
Test name
Test status
Simulation time 307217100 ps
CPU time 30.66 seconds
Started Mar 24 02:28:03 PM PDT 24
Finished Mar 24 02:28:34 PM PDT 24
Peak memory 273348 kb
Host smart-594fd6de-282c-44d1-827b-96dbffdf404e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784448055 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fl
ash_ctrl_rw_evict.2784448055
Directory /workspace/22.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/22.flash_ctrl_sec_info_access.99359224
Short name T396
Test name
Test status
Simulation time 719093800 ps
CPU time 73.56 seconds
Started Mar 24 02:28:04 PM PDT 24
Finished Mar 24 02:29:17 PM PDT 24
Peak memory 263032 kb
Host smart-020bdf49-ec6c-42ee-9724-269e4187c1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99359224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.99359224
Directory /workspace/22.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/22.flash_ctrl_smoke.1121564210
Short name T751
Test name
Test status
Simulation time 91754600 ps
CPU time 100.32 seconds
Started Mar 24 02:27:54 PM PDT 24
Finished Mar 24 02:29:34 PM PDT 24
Peak memory 274792 kb
Host smart-2916819f-5fcf-4859-ad91-f9da7e031d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121564210 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.1121564210
Directory /workspace/22.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/23.flash_ctrl_alert_test.1531107396
Short name T591
Test name
Test status
Simulation time 24871700 ps
CPU time 13.35 seconds
Started Mar 24 02:28:15 PM PDT 24
Finished Mar 24 02:28:29 PM PDT 24
Peak memory 264900 kb
Host smart-5d8581f5-adf3-4136-abf1-d36a4dac28bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531107396 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.
1531107396
Directory /workspace/23.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.flash_ctrl_connect.1312026837
Short name T1033
Test name
Test status
Simulation time 16285200 ps
CPU time 13.5 seconds
Started Mar 24 02:28:14 PM PDT 24
Finished Mar 24 02:28:27 PM PDT 24
Peak memory 275616 kb
Host smart-10f78675-ad6a-4382-ba13-ce01880c62f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312026837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.1312026837
Directory /workspace/23.flash_ctrl_connect/latest

Test location /workspace/coverage/default/23.flash_ctrl_disable.4084087078
Short name T75
Test name
Test status
Simulation time 35439600 ps
CPU time 22.12 seconds
Started Mar 24 02:28:16 PM PDT 24
Finished Mar 24 02:28:38 PM PDT 24
Peak memory 273252 kb
Host smart-c893a7d3-6a6d-4184-9a5d-dab67d658330
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084087078 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.flash_ctrl_disable.4084087078
Directory /workspace/23.flash_ctrl_disable/latest

Test location /workspace/coverage/default/23.flash_ctrl_hw_sec_otp.1676831948
Short name T750
Test name
Test status
Simulation time 3492919200 ps
CPU time 43.04 seconds
Started Mar 24 02:28:09 PM PDT 24
Finished Mar 24 02:28:52 PM PDT 24
Peak memory 262256 kb
Host smart-b3ba6553-68f1-4938-8cf0-ae0006216433
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676831948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_
hw_sec_otp.1676831948
Directory /workspace/23.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.149812040
Short name T332
Test name
Test status
Simulation time 33900945900 ps
CPU time 225.12 seconds
Started Mar 24 02:28:08 PM PDT 24
Finished Mar 24 02:31:53 PM PDT 24
Peak memory 289496 kb
Host smart-86c0369b-9a70-4e2f-b4ab-1409eba4e276
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149812040 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd_slow_flash.149812040
Directory /workspace/23.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/23.flash_ctrl_otp_reset.555067560
Short name T714
Test name
Test status
Simulation time 244273500 ps
CPU time 133.13 seconds
Started Mar 24 02:28:08 PM PDT 24
Finished Mar 24 02:30:21 PM PDT 24
Peak memory 263964 kb
Host smart-c75c7d62-d9e8-40b9-b6ec-1171af92c466
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555067560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_ot
p_reset.555067560
Directory /workspace/23.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_prog_reset.992798739
Short name T632
Test name
Test status
Simulation time 298721900 ps
CPU time 16.37 seconds
Started Mar 24 02:28:10 PM PDT 24
Finished Mar 24 02:28:27 PM PDT 24
Peak memory 264924 kb
Host smart-1866bd72-2137-4d04-885c-a6c6d7c74c3e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992798739 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_prog_res
et.992798739
Directory /workspace/23.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_rw_evict.3770525507
Short name T21
Test name
Test status
Simulation time 264980600 ps
CPU time 28.85 seconds
Started Mar 24 02:28:16 PM PDT 24
Finished Mar 24 02:28:44 PM PDT 24
Peak memory 267244 kb
Host smart-f5b1d409-e072-46bc-b2be-8d113ad818f7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770525507 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fl
ash_ctrl_rw_evict.3770525507
Directory /workspace/23.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/23.flash_ctrl_rw_evict_all_en.66016018
Short name T585
Test name
Test status
Simulation time 32823400 ps
CPU time 31.51 seconds
Started Mar 24 02:28:14 PM PDT 24
Finished Mar 24 02:28:46 PM PDT 24
Peak memory 273272 kb
Host smart-37204aa7-8acc-40bd-b1af-3b1823c51c1f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66016018 -assert nopostproc +UVM_TESTNAME=fl
ash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 23.flash_ctrl_rw_evict_all_en.66016018
Directory /workspace/23.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/23.flash_ctrl_sec_info_access.3834918837
Short name T388
Test name
Test status
Simulation time 2048841400 ps
CPU time 70.6 seconds
Started Mar 24 02:28:14 PM PDT 24
Finished Mar 24 02:29:25 PM PDT 24
Peak memory 262292 kb
Host smart-2cf874cb-e415-4eff-9c6c-ebb30e7455cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834918837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.3834918837
Directory /workspace/23.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/23.flash_ctrl_smoke.230385773
Short name T684
Test name
Test status
Simulation time 32151500 ps
CPU time 52.18 seconds
Started Mar 24 02:28:04 PM PDT 24
Finished Mar 24 02:28:57 PM PDT 24
Peak memory 270444 kb
Host smart-6c1c7c56-28a3-4f3e-a58e-dcc83412d416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230385773 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.230385773
Directory /workspace/23.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/24.flash_ctrl_alert_test.2418543323
Short name T456
Test name
Test status
Simulation time 121309300 ps
CPU time 13.66 seconds
Started Mar 24 02:28:29 PM PDT 24
Finished Mar 24 02:28:44 PM PDT 24
Peak memory 258756 kb
Host smart-331336d8-6c6c-4b3e-9184-c30233db892e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418543323 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.
2418543323
Directory /workspace/24.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.flash_ctrl_connect.1839271983
Short name T409
Test name
Test status
Simulation time 14733400 ps
CPU time 15.67 seconds
Started Mar 24 02:28:28 PM PDT 24
Finished Mar 24 02:28:44 PM PDT 24
Peak memory 275544 kb
Host smart-d8217f55-261b-4e73-8543-20b48c48fd3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839271983 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.1839271983
Directory /workspace/24.flash_ctrl_connect/latest

Test location /workspace/coverage/default/24.flash_ctrl_disable.3201555950
Short name T41
Test name
Test status
Simulation time 24678600 ps
CPU time 21.41 seconds
Started Mar 24 02:28:28 PM PDT 24
Finished Mar 24 02:28:50 PM PDT 24
Peak memory 273304 kb
Host smart-008fa57f-baa1-4ed9-b78e-865cd70ad552
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201555950 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_disable.3201555950
Directory /workspace/24.flash_ctrl_disable/latest

Test location /workspace/coverage/default/24.flash_ctrl_hw_sec_otp.2898074935
Short name T890
Test name
Test status
Simulation time 27574926400 ps
CPU time 122.73 seconds
Started Mar 24 02:28:23 PM PDT 24
Finished Mar 24 02:30:26 PM PDT 24
Peak memory 262424 kb
Host smart-97a50eaf-3696-49fa-a77a-42b35d2cadf4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898074935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_
hw_sec_otp.2898074935
Directory /workspace/24.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd_slow_flash.3438359796
Short name T320
Test name
Test status
Simulation time 8373655100 ps
CPU time 239.64 seconds
Started Mar 24 02:28:22 PM PDT 24
Finished Mar 24 02:32:22 PM PDT 24
Peak memory 284512 kb
Host smart-6bc86027-2520-49ee-a69a-c869415a0f94
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438359796 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd_slow_flash.3438359796
Directory /workspace/24.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/24.flash_ctrl_otp_reset.3544369440
Short name T129
Test name
Test status
Simulation time 42027700 ps
CPU time 133.53 seconds
Started Mar 24 02:28:22 PM PDT 24
Finished Mar 24 02:30:36 PM PDT 24
Peak memory 260876 kb
Host smart-6f0315d2-f20b-4d32-bf0c-8008c8f0d070
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544369440 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_o
tp_reset.3544369440
Directory /workspace/24.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_prog_reset.604448731
Short name T719
Test name
Test status
Simulation time 22080400 ps
CPU time 13.36 seconds
Started Mar 24 02:28:23 PM PDT 24
Finished Mar 24 02:28:36 PM PDT 24
Peak memory 259864 kb
Host smart-18c62c71-198f-4fe4-b0ef-dbfd03bfe031
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604448731 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_prog_res
et.604448731
Directory /workspace/24.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict.3908901135
Short name T803
Test name
Test status
Simulation time 46519600 ps
CPU time 32.2 seconds
Started Mar 24 02:28:24 PM PDT 24
Finished Mar 24 02:28:57 PM PDT 24
Peak memory 274360 kb
Host smart-29878748-49c0-4ba8-888f-9fa819486007
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908901135 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fl
ash_ctrl_rw_evict.3908901135
Directory /workspace/24.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict_all_en.3518817867
Short name T340
Test name
Test status
Simulation time 1092104400 ps
CPU time 35.17 seconds
Started Mar 24 02:28:22 PM PDT 24
Finished Mar 24 02:28:58 PM PDT 24
Peak memory 266040 kb
Host smart-bf5486b0-8716-4fe2-b0dc-cf502b40c1d9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518817867 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict_all_en.3518817867
Directory /workspace/24.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/24.flash_ctrl_sec_info_access.2898339954
Short name T391
Test name
Test status
Simulation time 1173471200 ps
CPU time 62.25 seconds
Started Mar 24 02:28:29 PM PDT 24
Finished Mar 24 02:29:33 PM PDT 24
Peak memory 262040 kb
Host smart-e1a56615-33a8-4e80-8c44-e487cd64b24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898339954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.2898339954
Directory /workspace/24.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/24.flash_ctrl_smoke.4115171872
Short name T593
Test name
Test status
Simulation time 24703900 ps
CPU time 123.06 seconds
Started Mar 24 02:28:19 PM PDT 24
Finished Mar 24 02:30:22 PM PDT 24
Peak memory 275528 kb
Host smart-83381daa-47db-4340-91af-6f25ce516a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115171872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.4115171872
Directory /workspace/24.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/25.flash_ctrl_alert_test.2873838790
Short name T778
Test name
Test status
Simulation time 58531700 ps
CPU time 13.82 seconds
Started Mar 24 02:28:37 PM PDT 24
Finished Mar 24 02:28:51 PM PDT 24
Peak memory 258052 kb
Host smart-11688450-66df-4941-a4fd-0099c3560fde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873838790 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test.
2873838790
Directory /workspace/25.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.flash_ctrl_connect.2253180809
Short name T493
Test name
Test status
Simulation time 17602000 ps
CPU time 15.51 seconds
Started Mar 24 02:28:33 PM PDT 24
Finished Mar 24 02:28:49 PM PDT 24
Peak memory 275172 kb
Host smart-83194bc5-1485-4be8-866d-b5656c145f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253180809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.2253180809
Directory /workspace/25.flash_ctrl_connect/latest

Test location /workspace/coverage/default/25.flash_ctrl_disable.2634067720
Short name T474
Test name
Test status
Simulation time 19318200 ps
CPU time 21.78 seconds
Started Mar 24 02:28:31 PM PDT 24
Finished Mar 24 02:28:53 PM PDT 24
Peak memory 265004 kb
Host smart-e8a1f388-2add-409b-bafc-451a04a48138
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634067720 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.flash_ctrl_disable.2634067720
Directory /workspace/25.flash_ctrl_disable/latest

Test location /workspace/coverage/default/25.flash_ctrl_hw_sec_otp.2234934160
Short name T315
Test name
Test status
Simulation time 9416532000 ps
CPU time 222.7 seconds
Started Mar 24 02:28:28 PM PDT 24
Finished Mar 24 02:32:13 PM PDT 24
Peak memory 262468 kb
Host smart-252f2448-23ff-4b22-aac4-808d6f1be3be
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234934160 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_
hw_sec_otp.2234934160
Directory /workspace/25.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd_slow_flash.3111791700
Short name T352
Test name
Test status
Simulation time 9107006300 ps
CPU time 199.89 seconds
Started Mar 24 02:28:27 PM PDT 24
Finished Mar 24 02:31:48 PM PDT 24
Peak memory 293824 kb
Host smart-aeccb2a9-494e-4f6a-85d4-bc344164bac6
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111791700 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd_slow_flash.3111791700
Directory /workspace/25.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/25.flash_ctrl_prog_reset.2182424151
Short name T809
Test name
Test status
Simulation time 202923600 ps
CPU time 13.55 seconds
Started Mar 24 02:28:32 PM PDT 24
Finished Mar 24 02:28:46 PM PDT 24
Peak memory 264840 kb
Host smart-9fc12aa3-f4a3-4e4a-97c8-d76e3ea9abd7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182424151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_prog_re
set.2182424151
Directory /workspace/25.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_rw_evict.3863331578
Short name T849
Test name
Test status
Simulation time 164368400 ps
CPU time 36.95 seconds
Started Mar 24 02:28:37 PM PDT 24
Finished Mar 24 02:29:14 PM PDT 24
Peak memory 273376 kb
Host smart-9984b24d-76b6-45ed-be6f-1a8ece971bd9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863331578 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fl
ash_ctrl_rw_evict.3863331578
Directory /workspace/25.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/25.flash_ctrl_rw_evict_all_en.2950988320
Short name T793
Test name
Test status
Simulation time 28648800 ps
CPU time 29.71 seconds
Started Mar 24 02:28:31 PM PDT 24
Finished Mar 24 02:29:01 PM PDT 24
Peak memory 274332 kb
Host smart-037e7cf1-350a-4bd3-af02-cdb6d2d66abc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950988320 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict_all_en.2950988320
Directory /workspace/25.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/25.flash_ctrl_sec_info_access.2324805173
Short name T932
Test name
Test status
Simulation time 2595364200 ps
CPU time 78.64 seconds
Started Mar 24 02:28:32 PM PDT 24
Finished Mar 24 02:29:51 PM PDT 24
Peak memory 262192 kb
Host smart-d9c6ef44-6978-4735-8e1b-e0fd376ead57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324805173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.2324805173
Directory /workspace/25.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/25.flash_ctrl_smoke.3320735363
Short name T895
Test name
Test status
Simulation time 25983000 ps
CPU time 53.53 seconds
Started Mar 24 02:28:27 PM PDT 24
Finished Mar 24 02:29:22 PM PDT 24
Peak memory 270388 kb
Host smart-0342bb5e-38ad-411d-9015-162bfd20ba44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320735363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.3320735363
Directory /workspace/25.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/26.flash_ctrl_alert_test.4229497280
Short name T445
Test name
Test status
Simulation time 132928000 ps
CPU time 13.7 seconds
Started Mar 24 02:28:41 PM PDT 24
Finished Mar 24 02:28:55 PM PDT 24
Peak memory 258776 kb
Host smart-515572be-d4f1-48f5-b6f0-5e207b344e3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229497280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.
4229497280
Directory /workspace/26.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.flash_ctrl_connect.1853584767
Short name T948
Test name
Test status
Simulation time 22134700 ps
CPU time 15.56 seconds
Started Mar 24 02:28:43 PM PDT 24
Finished Mar 24 02:28:59 PM PDT 24
Peak memory 275224 kb
Host smart-89b860ed-d483-41bf-830d-8b46e10024d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853584767 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.1853584767
Directory /workspace/26.flash_ctrl_connect/latest

Test location /workspace/coverage/default/26.flash_ctrl_disable.266078820
Short name T377
Test name
Test status
Simulation time 12349300 ps
CPU time 21.9 seconds
Started Mar 24 02:28:42 PM PDT 24
Finished Mar 24 02:29:04 PM PDT 24
Peak memory 280172 kb
Host smart-bf51f293-e2e3-4d03-8f14-fd941ed8e240
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266078820 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_disable.266078820
Directory /workspace/26.flash_ctrl_disable/latest

Test location /workspace/coverage/default/26.flash_ctrl_hw_sec_otp.406591312
Short name T624
Test name
Test status
Simulation time 2866172700 ps
CPU time 113.54 seconds
Started Mar 24 02:28:42 PM PDT 24
Finished Mar 24 02:30:36 PM PDT 24
Peak memory 261764 kb
Host smart-e53f55ed-6043-4b0b-93a6-8787044a0455
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406591312 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_h
w_sec_otp.406591312
Directory /workspace/26.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd_slow_flash.1282858799
Short name T330
Test name
Test status
Simulation time 32580301700 ps
CPU time 203.92 seconds
Started Mar 24 02:28:43 PM PDT 24
Finished Mar 24 02:32:07 PM PDT 24
Peak memory 289524 kb
Host smart-fd455dc0-0caf-4785-9a80-8c73e3e137ac
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282858799 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd_slow_flash.1282858799
Directory /workspace/26.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/26.flash_ctrl_otp_reset.510757445
Short name T559
Test name
Test status
Simulation time 93723600 ps
CPU time 131.32 seconds
Started Mar 24 02:28:42 PM PDT 24
Finished Mar 24 02:30:53 PM PDT 24
Peak memory 260876 kb
Host smart-2f96e111-f07b-4372-a4d9-9d5e44f762d1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510757445 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_ot
p_reset.510757445
Directory /workspace/26.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_prog_reset.3907760618
Short name T968
Test name
Test status
Simulation time 18379100 ps
CPU time 13.41 seconds
Started Mar 24 02:28:41 PM PDT 24
Finished Mar 24 02:28:54 PM PDT 24
Peak memory 259884 kb
Host smart-3cbfd391-1a24-425a-9b47-21c2ef7da5fb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907760618 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_prog_re
set.3907760618
Directory /workspace/26.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict.3512455931
Short name T693
Test name
Test status
Simulation time 91448700 ps
CPU time 32.91 seconds
Started Mar 24 02:28:44 PM PDT 24
Finished Mar 24 02:29:17 PM PDT 24
Peak memory 273528 kb
Host smart-37649618-20a6-44da-8f54-f3ba4a872fbb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512455931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fl
ash_ctrl_rw_evict.3512455931
Directory /workspace/26.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict_all_en.711365637
Short name T209
Test name
Test status
Simulation time 205373100 ps
CPU time 30.9 seconds
Started Mar 24 02:28:43 PM PDT 24
Finished Mar 24 02:29:14 PM PDT 24
Peak memory 273296 kb
Host smart-77eb74a7-b6c8-4b4b-9766-09a8d97f71be
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711365637 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict_all_en.711365637
Directory /workspace/26.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/26.flash_ctrl_sec_info_access.3653487688
Short name T382
Test name
Test status
Simulation time 2089430200 ps
CPU time 69.26 seconds
Started Mar 24 02:28:44 PM PDT 24
Finished Mar 24 02:29:53 PM PDT 24
Peak memory 262064 kb
Host smart-e3a604ef-c13a-4d41-9873-eac73ff53b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653487688 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.3653487688
Directory /workspace/26.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/26.flash_ctrl_smoke.4093369122
Short name T434
Test name
Test status
Simulation time 34397800 ps
CPU time 176.48 seconds
Started Mar 24 02:28:38 PM PDT 24
Finished Mar 24 02:31:34 PM PDT 24
Peak memory 276652 kb
Host smart-edec4615-ab35-4cb0-b981-1ca72adbd629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093369122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.4093369122
Directory /workspace/26.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/27.flash_ctrl_alert_test.797264861
Short name T571
Test name
Test status
Simulation time 167506600 ps
CPU time 14.11 seconds
Started Mar 24 02:28:50 PM PDT 24
Finished Mar 24 02:29:05 PM PDT 24
Peak memory 257960 kb
Host smart-09274078-aaa3-44e6-8454-bb742d2c66a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797264861 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.797264861
Directory /workspace/27.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.flash_ctrl_connect.3306302003
Short name T828
Test name
Test status
Simulation time 45137600 ps
CPU time 15.62 seconds
Started Mar 24 02:28:44 PM PDT 24
Finished Mar 24 02:29:00 PM PDT 24
Peak memory 275452 kb
Host smart-d865515f-56a2-435a-bc33-ac3e05016e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306302003 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.3306302003
Directory /workspace/27.flash_ctrl_connect/latest

Test location /workspace/coverage/default/27.flash_ctrl_disable.404363590
Short name T754
Test name
Test status
Simulation time 15940300 ps
CPU time 21.37 seconds
Started Mar 24 02:28:45 PM PDT 24
Finished Mar 24 02:29:06 PM PDT 24
Peak memory 264880 kb
Host smart-f1264d2e-ca83-41d7-a33b-89538b889e92
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404363590 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_disable.404363590
Directory /workspace/27.flash_ctrl_disable/latest

Test location /workspace/coverage/default/27.flash_ctrl_hw_sec_otp.1153564872
Short name T424
Test name
Test status
Simulation time 1291839200 ps
CPU time 89.54 seconds
Started Mar 24 02:28:47 PM PDT 24
Finished Mar 24 02:30:17 PM PDT 24
Peak memory 262472 kb
Host smart-1cc09f87-89d2-415d-9c3c-64e1fe8c99cd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153564872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_
hw_sec_otp.1153564872
Directory /workspace/27.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.2401584429
Short name T952
Test name
Test status
Simulation time 17818612400 ps
CPU time 211.9 seconds
Started Mar 24 02:28:47 PM PDT 24
Finished Mar 24 02:32:19 PM PDT 24
Peak memory 284592 kb
Host smart-9dcb2c2d-8be8-4fa9-8c1c-acb24208cd8c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401584429 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd_slow_flash.2401584429
Directory /workspace/27.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/27.flash_ctrl_otp_reset.48320863
Short name T80
Test name
Test status
Simulation time 131875700 ps
CPU time 131.22 seconds
Started Mar 24 02:28:46 PM PDT 24
Finished Mar 24 02:30:58 PM PDT 24
Peak memory 260092 kb
Host smart-3257c7b1-2d65-48b5-86c9-d8a6b708bf1c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48320863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_otp
_reset.48320863
Directory /workspace/27.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_prog_reset.3027712002
Short name T407
Test name
Test status
Simulation time 31322800 ps
CPU time 13.37 seconds
Started Mar 24 02:28:45 PM PDT 24
Finished Mar 24 02:28:59 PM PDT 24
Peak memory 259872 kb
Host smart-ef7ebc31-dd95-4ddf-adc1-f5f965d271a2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027712002 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_prog_re
set.3027712002
Directory /workspace/27.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict_all_en.427134684
Short name T947
Test name
Test status
Simulation time 71008300 ps
CPU time 28.37 seconds
Started Mar 24 02:28:46 PM PDT 24
Finished Mar 24 02:29:14 PM PDT 24
Peak memory 273304 kb
Host smart-6fa08f2b-5bb3-41b0-ab07-187c5c6a27c6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427134684 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict_all_en.427134684
Directory /workspace/27.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/27.flash_ctrl_sec_info_access.3100287061
Short name T454
Test name
Test status
Simulation time 4770631000 ps
CPU time 90.24 seconds
Started Mar 24 02:28:44 PM PDT 24
Finished Mar 24 02:30:14 PM PDT 24
Peak memory 264752 kb
Host smart-0cfdb3af-63e5-419d-9e1f-0c8346880cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100287061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.3100287061
Directory /workspace/27.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/27.flash_ctrl_smoke.1191193830
Short name T374
Test name
Test status
Simulation time 65322000 ps
CPU time 75.03 seconds
Started Mar 24 02:28:42 PM PDT 24
Finished Mar 24 02:29:57 PM PDT 24
Peak memory 274712 kb
Host smart-9ff84085-919a-4852-a1e2-5f35681bade9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191193830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.1191193830
Directory /workspace/27.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/28.flash_ctrl_alert_test.2218877878
Short name T1041
Test name
Test status
Simulation time 74479100 ps
CPU time 14.09 seconds
Started Mar 24 02:28:57 PM PDT 24
Finished Mar 24 02:29:11 PM PDT 24
Peak memory 258816 kb
Host smart-2c17d85b-43e1-4678-b565-36e18a2e88b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218877878 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.
2218877878
Directory /workspace/28.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.flash_ctrl_connect.2234229485
Short name T801
Test name
Test status
Simulation time 14436000 ps
CPU time 15.62 seconds
Started Mar 24 02:28:56 PM PDT 24
Finished Mar 24 02:29:12 PM PDT 24
Peak memory 275108 kb
Host smart-40cb5c0c-625e-4c5a-b663-ff1c7bdac3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234229485 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.2234229485
Directory /workspace/28.flash_ctrl_connect/latest

Test location /workspace/coverage/default/28.flash_ctrl_disable.2943721306
Short name T378
Test name
Test status
Simulation time 45887500 ps
CPU time 21.75 seconds
Started Mar 24 02:28:58 PM PDT 24
Finished Mar 24 02:29:20 PM PDT 24
Peak memory 264896 kb
Host smart-e4732ddc-1c97-48bd-b33a-86a04e241a7f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943721306 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_disable.2943721306
Directory /workspace/28.flash_ctrl_disable/latest

Test location /workspace/coverage/default/28.flash_ctrl_hw_sec_otp.163918151
Short name T318
Test name
Test status
Simulation time 6589330000 ps
CPU time 251.92 seconds
Started Mar 24 02:28:51 PM PDT 24
Finished Mar 24 02:33:03 PM PDT 24
Peak memory 262372 kb
Host smart-b058b693-d751-45d8-b7b8-3fa27c856d20
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163918151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_h
w_sec_otp.163918151
Directory /workspace/28.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd_slow_flash.2005525349
Short name T329
Test name
Test status
Simulation time 16447026000 ps
CPU time 200.75 seconds
Started Mar 24 02:28:51 PM PDT 24
Finished Mar 24 02:32:11 PM PDT 24
Peak memory 284540 kb
Host smart-134889d5-d16d-442d-ab73-61e562016352
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005525349 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd_slow_flash.2005525349
Directory /workspace/28.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/28.flash_ctrl_otp_reset.446302973
Short name T636
Test name
Test status
Simulation time 39354900 ps
CPU time 110.59 seconds
Started Mar 24 02:28:51 PM PDT 24
Finished Mar 24 02:30:42 PM PDT 24
Peak memory 259756 kb
Host smart-4d929964-edb3-4660-8e71-786056abba7e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446302973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_ot
p_reset.446302973
Directory /workspace/28.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_prog_reset.2001068588
Short name T184
Test name
Test status
Simulation time 69725900 ps
CPU time 13.5 seconds
Started Mar 24 02:28:55 PM PDT 24
Finished Mar 24 02:29:09 PM PDT 24
Peak memory 259828 kb
Host smart-3db2036f-e796-4a94-8f09-f6bca18bfdd9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001068588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_prog_re
set.2001068588
Directory /workspace/28.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict.1198479687
Short name T711
Test name
Test status
Simulation time 65892200 ps
CPU time 31.19 seconds
Started Mar 24 02:28:57 PM PDT 24
Finished Mar 24 02:29:28 PM PDT 24
Peak memory 273260 kb
Host smart-a1a1b046-17d7-424d-81ae-2947e5d6a9f6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198479687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fl
ash_ctrl_rw_evict.1198479687
Directory /workspace/28.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.1054507398
Short name T20
Test name
Test status
Simulation time 167192200 ps
CPU time 33.28 seconds
Started Mar 24 02:28:54 PM PDT 24
Finished Mar 24 02:29:29 PM PDT 24
Peak memory 267156 kb
Host smart-4688c62a-b571-4e1b-94b4-c262b99b06f5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054507398 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict_all_en.1054507398
Directory /workspace/28.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/28.flash_ctrl_sec_info_access.1987450248
Short name T398
Test name
Test status
Simulation time 689367300 ps
CPU time 54.43 seconds
Started Mar 24 02:28:56 PM PDT 24
Finished Mar 24 02:29:51 PM PDT 24
Peak memory 262944 kb
Host smart-d77b3f43-06c9-401a-a57d-3d901b40b658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987450248 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.1987450248
Directory /workspace/28.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/28.flash_ctrl_smoke.376503763
Short name T757
Test name
Test status
Simulation time 40111400 ps
CPU time 122.51 seconds
Started Mar 24 02:28:50 PM PDT 24
Finished Mar 24 02:30:53 PM PDT 24
Peak memory 276800 kb
Host smart-d4250524-6d1a-45f5-9603-b687013091ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376503763 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.376503763
Directory /workspace/28.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/29.flash_ctrl_alert_test.1962525664
Short name T980
Test name
Test status
Simulation time 365784200 ps
CPU time 14.27 seconds
Started Mar 24 02:29:04 PM PDT 24
Finished Mar 24 02:29:18 PM PDT 24
Peak memory 258980 kb
Host smart-6b948ee7-fc92-4ee3-b73e-5f58febe30e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962525664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test.
1962525664
Directory /workspace/29.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.flash_ctrl_connect.314630105
Short name T814
Test name
Test status
Simulation time 43419600 ps
CPU time 15.86 seconds
Started Mar 24 02:29:01 PM PDT 24
Finished Mar 24 02:29:17 PM PDT 24
Peak memory 275508 kb
Host smart-b7eeb444-9b27-4a62-813e-37fc9ebd6d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314630105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.314630105
Directory /workspace/29.flash_ctrl_connect/latest

Test location /workspace/coverage/default/29.flash_ctrl_disable.3250572894
Short name T873
Test name
Test status
Simulation time 35683700 ps
CPU time 22.43 seconds
Started Mar 24 02:29:00 PM PDT 24
Finished Mar 24 02:29:23 PM PDT 24
Peak memory 273324 kb
Host smart-9e40eb95-ad66-4ed8-971a-0d0ad66578fb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250572894 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_disable.3250572894
Directory /workspace/29.flash_ctrl_disable/latest

Test location /workspace/coverage/default/29.flash_ctrl_hw_sec_otp.445183857
Short name T478
Test name
Test status
Simulation time 6707751000 ps
CPU time 141.06 seconds
Started Mar 24 02:28:55 PM PDT 24
Finished Mar 24 02:31:17 PM PDT 24
Peak memory 262636 kb
Host smart-3f50cc59-7813-4d3d-9e97-57b8647c6544
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445183857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_h
w_sec_otp.445183857
Directory /workspace/29.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.4254358973
Short name T657
Test name
Test status
Simulation time 114452825200 ps
CPU time 210.12 seconds
Started Mar 24 02:28:59 PM PDT 24
Finished Mar 24 02:32:30 PM PDT 24
Peak memory 290660 kb
Host smart-cf292c0a-0bce-460c-9276-2866b32c2bf6
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254358973 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd_slow_flash.4254358973
Directory /workspace/29.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/29.flash_ctrl_otp_reset.2591872857
Short name T1030
Test name
Test status
Simulation time 150837700 ps
CPU time 131.26 seconds
Started Mar 24 02:29:00 PM PDT 24
Finished Mar 24 02:31:11 PM PDT 24
Peak memory 261016 kb
Host smart-da22299c-f2a9-4c8d-ad6e-0e52760e6b5b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591872857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_o
tp_reset.2591872857
Directory /workspace/29.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_prog_reset.3180325264
Short name T15
Test name
Test status
Simulation time 22800200 ps
CPU time 13.76 seconds
Started Mar 24 02:29:00 PM PDT 24
Finished Mar 24 02:29:14 PM PDT 24
Peak memory 260224 kb
Host smart-dab2f05d-d218-45af-bc30-7a107bde5eb6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180325264 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_prog_re
set.3180325264
Directory /workspace/29.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict.548913508
Short name T652
Test name
Test status
Simulation time 43602500 ps
CPU time 31.53 seconds
Started Mar 24 02:29:00 PM PDT 24
Finished Mar 24 02:29:32 PM PDT 24
Peak memory 273288 kb
Host smart-b15bb968-810d-4cfd-952f-a63589aa61da
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548913508 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fla
sh_ctrl_rw_evict.548913508
Directory /workspace/29.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict_all_en.3458067104
Short name T38
Test name
Test status
Simulation time 29628100 ps
CPU time 30.7 seconds
Started Mar 24 02:28:59 PM PDT 24
Finished Mar 24 02:29:30 PM PDT 24
Peak memory 273248 kb
Host smart-16a63f39-18b6-4653-ae5e-906175c43a28
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458067104 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict_all_en.3458067104
Directory /workspace/29.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/29.flash_ctrl_sec_info_access.3498596519
Short name T1000
Test name
Test status
Simulation time 7191009400 ps
CPU time 71.72 seconds
Started Mar 24 02:29:00 PM PDT 24
Finished Mar 24 02:30:12 PM PDT 24
Peak memory 262748 kb
Host smart-91287344-0df8-4277-93c2-255d46271b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498596519 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.3498596519
Directory /workspace/29.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/29.flash_ctrl_smoke.1396353251
Short name T967
Test name
Test status
Simulation time 29273700 ps
CPU time 124.2 seconds
Started Mar 24 02:28:55 PM PDT 24
Finished Mar 24 02:31:00 PM PDT 24
Peak memory 275300 kb
Host smart-3e2e31e3-c679-4544-ad37-3c0226a7112a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396353251 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.1396353251
Directory /workspace/29.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_alert_test.1666001796
Short name T1049
Test name
Test status
Simulation time 91422400 ps
CPU time 13.85 seconds
Started Mar 24 02:19:29 PM PDT 24
Finished Mar 24 02:19:43 PM PDT 24
Peak memory 257908 kb
Host smart-00a8ef27-f7bd-4e7b-a8c3-8111d58b0d14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666001796 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.1
666001796
Directory /workspace/3.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.flash_ctrl_config_regwen.4016133629
Short name T265
Test name
Test status
Simulation time 23477500 ps
CPU time 13.99 seconds
Started Mar 24 02:19:26 PM PDT 24
Finished Mar 24 02:19:40 PM PDT 24
Peak memory 264556 kb
Host smart-5d2fe334-b058-4aa5-937f-397d5263a40d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016133629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.flash_ctrl_config_regwen.4016133629
Directory /workspace/3.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/3.flash_ctrl_connect.403467433
Short name T621
Test name
Test status
Simulation time 58510700 ps
CPU time 15.86 seconds
Started Mar 24 02:19:23 PM PDT 24
Finished Mar 24 02:19:39 PM PDT 24
Peak memory 274504 kb
Host smart-28dd50aa-25ed-4060-b486-f95966e270be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403467433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.403467433
Directory /workspace/3.flash_ctrl_connect/latest

Test location /workspace/coverage/default/3.flash_ctrl_derr_detect.3851399068
Short name T199
Test name
Test status
Simulation time 389612500 ps
CPU time 105.29 seconds
Started Mar 24 02:19:04 PM PDT 24
Finished Mar 24 02:20:50 PM PDT 24
Peak memory 273224 kb
Host smart-3fa09eb6-47db-41e2-9fa3-844b4cdcc462
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851399068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.flash_ctrl_derr_detect.3851399068
Directory /workspace/3.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/3.flash_ctrl_disable.1811721736
Short name T542
Test name
Test status
Simulation time 12956600 ps
CPU time 20.63 seconds
Started Mar 24 02:19:19 PM PDT 24
Finished Mar 24 02:19:39 PM PDT 24
Peak memory 273220 kb
Host smart-3aa0f104-ff5b-4c07-9967-24b0a5f66bc2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811721736 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_disable.1811721736
Directory /workspace/3.flash_ctrl_disable/latest

Test location /workspace/coverage/default/3.flash_ctrl_erase_suspend.412653980
Short name T118
Test name
Test status
Simulation time 4848764200 ps
CPU time 668.47 seconds
Started Mar 24 02:18:37 PM PDT 24
Finished Mar 24 02:29:46 PM PDT 24
Peak memory 262844 kb
Host smart-984e4c2c-307b-41ee-bf1e-08792a224053
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=412653980 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.412653980
Directory /workspace/3.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_mp.1750840892
Short name T1040
Test name
Test status
Simulation time 17984107100 ps
CPU time 2378.14 seconds
Started Mar 24 02:18:52 PM PDT 24
Finished Mar 24 02:58:31 PM PDT 24
Peak memory 264392 kb
Host smart-a2f38cfe-6b06-452a-8d95-794d690732ef
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750840892 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_err
or_mp.1750840892
Directory /workspace/3.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_type.2749434690
Short name T159
Test name
Test status
Simulation time 3289081600 ps
CPU time 2710.81 seconds
Started Mar 24 02:18:54 PM PDT 24
Finished Mar 24 03:04:05 PM PDT 24
Peak memory 264808 kb
Host smart-7d2f4669-8546-45c4-b188-9b0fa5ff6ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749434690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_type.2749434690
Directory /workspace/3.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_win.3353424876
Short name T916
Test name
Test status
Simulation time 972669200 ps
CPU time 999.36 seconds
Started Mar 24 02:18:53 PM PDT 24
Finished Mar 24 02:35:33 PM PDT 24
Peak memory 270956 kb
Host smart-ba54dcdd-3f68-4479-a0e8-c76ef421b8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353424876 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.3353424876
Directory /workspace/3.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/3.flash_ctrl_fetch_code.1322000785
Short name T642
Test name
Test status
Simulation time 344725100 ps
CPU time 25.13 seconds
Started Mar 24 02:18:46 PM PDT 24
Finished Mar 24 02:19:12 PM PDT 24
Peak memory 264812 kb
Host smart-64ec0054-eda1-4496-9ab4-150bf0e5cfd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322000785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetch_code.1322000785
Directory /workspace/3.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/3.flash_ctrl_full_mem_access.3521272232
Short name T115
Test name
Test status
Simulation time 101739657200 ps
CPU time 4433.1 seconds
Started Mar 24 02:18:49 PM PDT 24
Finished Mar 24 03:32:43 PM PDT 24
Peak memory 265024 kb
Host smart-fcf0b5c4-bce6-43f9-ae51-b34c0fc42398
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521272232 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_c
trl_full_mem_access.3521272232
Directory /workspace/3.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_ctrl_arb.3690361779
Short name T149
Test name
Test status
Simulation time 260642162400 ps
CPU time 2606.58 seconds
Started Mar 24 02:18:46 PM PDT 24
Finished Mar 24 03:02:13 PM PDT 24
Peak memory 264668 kb
Host smart-b87c0429-2fc8-4eb8-b3d8-7733036a6eff
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690361779 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.flash_ctrl_host_ctrl_arb.3690361779
Directory /workspace/3.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.3143789570
Short name T1009
Test name
Test status
Simulation time 10034351300 ps
CPU time 100.76 seconds
Started Mar 24 02:19:29 PM PDT 24
Finished Mar 24 02:21:09 PM PDT 24
Peak memory 264988 kb
Host smart-c2d9727c-ae3b-4209-9d33-a3221b9f9d5b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143789570 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.3143789570
Directory /workspace/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_read_seed_err.2718972728
Short name T121
Test name
Test status
Simulation time 15450800 ps
CPU time 13.31 seconds
Started Mar 24 02:19:29 PM PDT 24
Finished Mar 24 02:19:42 PM PDT 24
Peak memory 257980 kb
Host smart-b43a0ee1-bae0-4193-8deb-518c6cc6da1d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718972728 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_read_seed_err.2718972728
Directory /workspace/3.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_rma_reset.774738261
Short name T733
Test name
Test status
Simulation time 40126370000 ps
CPU time 887.34 seconds
Started Mar 24 02:18:40 PM PDT 24
Finished Mar 24 02:33:28 PM PDT 24
Peak memory 263060 kb
Host smart-999f6224-4b80-40d9-8ad5-053c06e0176d
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774738261 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_hw_rma_reset.774738261
Directory /workspace/3.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_sec_otp.1472501040
Short name T546
Test name
Test status
Simulation time 5547789400 ps
CPU time 61.7 seconds
Started Mar 24 02:18:37 PM PDT 24
Finished Mar 24 02:19:39 PM PDT 24
Peak memory 262640 kb
Host smart-07a17703-0d55-4d25-89e1-73c1e183c6be
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472501040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_h
w_sec_otp.1472501040
Directory /workspace/3.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.3297665045
Short name T607
Test name
Test status
Simulation time 15793437500 ps
CPU time 206.11 seconds
Started Mar 24 02:19:08 PM PDT 24
Finished Mar 24 02:22:34 PM PDT 24
Peak memory 291196 kb
Host smart-69e878df-ccd2-4590-b04e-7f26f634896a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297665045 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd_slow_flash.3297665045
Directory /workspace/3.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr.3755047820
Short name T187
Test name
Test status
Simulation time 4030555300 ps
CPU time 93.48 seconds
Started Mar 24 02:19:08 PM PDT 24
Finished Mar 24 02:20:42 PM PDT 24
Peak memory 265028 kb
Host smart-1f864bd1-0916-4d24-8602-adbd735d57dc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755047820 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.flash_ctrl_intr_wr.3755047820
Directory /workspace/3.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr_slow_flash.933735942
Short name T638
Test name
Test status
Simulation time 141174739400 ps
CPU time 398.88 seconds
Started Mar 24 02:19:07 PM PDT 24
Finished Mar 24 02:25:46 PM PDT 24
Peak memory 261244 kb
Host smart-4a93c9aa-f7e2-46ff-8e1d-f840364955f1
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933
735942 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.933735942
Directory /workspace/3.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_invalid_op.2147984215
Short name T111
Test name
Test status
Simulation time 2013329600 ps
CPU time 94.77 seconds
Started Mar 24 02:18:54 PM PDT 24
Finished Mar 24 02:20:28 PM PDT 24
Peak memory 262856 kb
Host smart-9a2e1f5e-33de-4544-bde7-faf24ca778e9
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147984215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.2147984215
Directory /workspace/3.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_lcmgr_intg.2351494582
Short name T564
Test name
Test status
Simulation time 132884800 ps
CPU time 13.55 seconds
Started Mar 24 02:19:24 PM PDT 24
Finished Mar 24 02:19:38 PM PDT 24
Peak memory 264920 kb
Host smart-3875d50b-cf30-4990-9018-04a3d87b4cf0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351494582 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_lcmgr_intg.2351494582
Directory /workspace/3.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/3.flash_ctrl_otp_reset.487885901
Short name T1037
Test name
Test status
Simulation time 59177900 ps
CPU time 133.93 seconds
Started Mar 24 02:18:42 PM PDT 24
Finished Mar 24 02:20:56 PM PDT 24
Peak memory 259736 kb
Host smart-09788d37-9923-4885-a76d-1b2771d9e03f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487885901 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_otp
_reset.487885901
Directory /workspace/3.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.1883413731
Short name T231
Test name
Test status
Simulation time 28946300 ps
CPU time 15.69 seconds
Started Mar 24 02:19:27 PM PDT 24
Finished Mar 24 02:19:43 PM PDT 24
Peak memory 265016 kb
Host smart-19612e01-cff9-4c78-b6b7-45ffeeed5042
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1883413731 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.1883413731
Directory /workspace/3.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb.1427944680
Short name T233
Test name
Test status
Simulation time 5380582600 ps
CPU time 291.58 seconds
Started Mar 24 02:18:36 PM PDT 24
Finished Mar 24 02:23:28 PM PDT 24
Peak memory 261464 kb
Host smart-04edf1ab-d3f1-4b2a-8fa9-dc2d272061c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1427944680 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.1427944680
Directory /workspace/3.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb_redun.777506955
Short name T73
Test name
Test status
Simulation time 894011100 ps
CPU time 49.05 seconds
Started Mar 24 02:19:19 PM PDT 24
Finished Mar 24 02:20:08 PM PDT 24
Peak memory 265104 kb
Host smart-7f98f8fd-f6db-4d9c-937c-e67c0ccd4bab
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777506955 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.777506955
Directory /workspace/3.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.1803005851
Short name T230
Test name
Test status
Simulation time 164737200 ps
CPU time 14.53 seconds
Started Mar 24 02:19:26 PM PDT 24
Finished Mar 24 02:19:40 PM PDT 24
Peak memory 264964 kb
Host smart-5b47ca7e-69d2-472d-a2e6-14131fd1808e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803005851 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.1803005851
Directory /workspace/3.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_prog_reset.2491141595
Short name T452
Test name
Test status
Simulation time 43204300 ps
CPU time 13.99 seconds
Started Mar 24 02:19:07 PM PDT 24
Finished Mar 24 02:19:21 PM PDT 24
Peak memory 260024 kb
Host smart-6fba7925-9a11-40c9-be37-7500d5cff1c3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491141595 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_prog_res
et.2491141595
Directory /workspace/3.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_rand_ops.1483598821
Short name T808
Test name
Test status
Simulation time 260148300 ps
CPU time 922.29 seconds
Started Mar 24 02:18:30 PM PDT 24
Finished Mar 24 02:33:53 PM PDT 24
Peak memory 284120 kb
Host smart-ccae5a6d-edd3-4dcf-9820-98e1622ae8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483598821 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.1483598821
Directory /workspace/3.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/3.flash_ctrl_rd_buff_evict.2604509182
Short name T521
Test name
Test status
Simulation time 732602700 ps
CPU time 154.47 seconds
Started Mar 24 02:18:32 PM PDT 24
Finished Mar 24 02:21:07 PM PDT 24
Peak memory 264804 kb
Host smart-29b41c04-1033-4be1-851c-d7f7f7a18859
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2604509182 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.2604509182
Directory /workspace/3.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_re_evict.95026825
Short name T734
Test name
Test status
Simulation time 234144800 ps
CPU time 31.47 seconds
Started Mar 24 02:19:13 PM PDT 24
Finished Mar 24 02:19:44 PM PDT 24
Peak memory 273296 kb
Host smart-65888614-7fbe-4970-a141-17830418bd7a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95026825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash
_ctrl_re_evict.95026825
Directory /workspace/3.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_derr.773589257
Short name T727
Test name
Test status
Simulation time 59606700 ps
CPU time 22.41 seconds
Started Mar 24 02:18:59 PM PDT 24
Finished Mar 24 02:19:23 PM PDT 24
Peak memory 265276 kb
Host smart-d5a98966-c6b8-4e2f-84fa-b1e1b4912df7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773589257 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_derr.773589257
Directory /workspace/3.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_serr.3770136717
Short name T282
Test name
Test status
Simulation time 29027700 ps
CPU time 22.51 seconds
Started Mar 24 02:19:02 PM PDT 24
Finished Mar 24 02:19:26 PM PDT 24
Peak memory 264916 kb
Host smart-7d733bde-25c9-4fee-993a-7cf1bbd86711
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770136717 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fl
ash_ctrl_read_word_sweep_serr.3770136717
Directory /workspace/3.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro.3733940495
Short name T798
Test name
Test status
Simulation time 478398100 ps
CPU time 103.05 seconds
Started Mar 24 02:18:53 PM PDT 24
Finished Mar 24 02:20:36 PM PDT 24
Peak memory 280828 kb
Host smart-56e5c508-1527-4f42-be81-2e9781d2fc13
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733940495 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.flash_ctrl_ro.3733940495
Directory /workspace/3.flash_ctrl_ro/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_derr.3849802253
Short name T169
Test name
Test status
Simulation time 520468100 ps
CPU time 117.44 seconds
Started Mar 24 02:18:56 PM PDT 24
Finished Mar 24 02:20:54 PM PDT 24
Peak memory 281396 kb
Host smart-1cf604b9-4a4f-44e8-b9e6-059b1908701e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3849802253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.3849802253
Directory /workspace/3.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw.382706715
Short name T488
Test name
Test status
Simulation time 14774720300 ps
CPU time 486.92 seconds
Started Mar 24 02:18:54 PM PDT 24
Finished Mar 24 02:27:01 PM PDT 24
Peak memory 309260 kb
Host smart-9970dc6d-da83-4134-996c-f28eb326c6d5
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382706715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctr
l_rw.382706715
Directory /workspace/3.flash_ctrl_rw/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict.990376447
Short name T768
Test name
Test status
Simulation time 51520500 ps
CPU time 33.16 seconds
Started Mar 24 02:19:13 PM PDT 24
Finished Mar 24 02:19:47 PM PDT 24
Peak memory 273280 kb
Host smart-04b0a648-a3dc-43c4-907d-4ec687e15499
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990376447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas
h_ctrl_rw_evict.990376447
Directory /workspace/3.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict_all_en.672214254
Short name T222
Test name
Test status
Simulation time 70605000 ps
CPU time 30.91 seconds
Started Mar 24 02:19:13 PM PDT 24
Finished Mar 24 02:19:44 PM PDT 24
Peak memory 274316 kb
Host smart-5e0aab87-0262-4162-9203-5ecb6a6636da
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672214254 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict_all_en.672214254
Directory /workspace/3.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_cm.2170894047
Short name T181
Test name
Test status
Simulation time 3219430100 ps
CPU time 4867.08 seconds
Started Mar 24 02:19:19 PM PDT 24
Finished Mar 24 03:40:26 PM PDT 24
Peak memory 284784 kb
Host smart-2bcec555-7ec8-4767-9ced-f10fe29a5033
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170894047 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.2170894047
Directory /workspace/3.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_info_access.1685581369
Short name T986
Test name
Test status
Simulation time 1019568000 ps
CPU time 60.94 seconds
Started Mar 24 02:19:18 PM PDT 24
Finished Mar 24 02:20:19 PM PDT 24
Peak memory 262988 kb
Host smart-8c1e5fbe-4f34-43c7-bfd5-735bb532cd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685581369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.1685581369
Directory /workspace/3.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_address.4215297626
Short name T35
Test name
Test status
Simulation time 2177787400 ps
CPU time 66.59 seconds
Started Mar 24 02:19:03 PM PDT 24
Finished Mar 24 02:20:10 PM PDT 24
Peak memory 265092 kb
Host smart-feb41f6d-ab18-45a4-8e03-1f4dd098dee5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215297626 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_serr_address.4215297626
Directory /workspace/3.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_counter.3357640638
Short name T221
Test name
Test status
Simulation time 1028078300 ps
CPU time 55.56 seconds
Started Mar 24 02:19:02 PM PDT 24
Finished Mar 24 02:19:59 PM PDT 24
Peak memory 273260 kb
Host smart-ba3c4783-c583-4816-b98a-c8ed5b0394e9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357640638 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_serr_counter.3357640638
Directory /workspace/3.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke.3385690456
Short name T854
Test name
Test status
Simulation time 182163200 ps
CPU time 51.97 seconds
Started Mar 24 02:18:16 PM PDT 24
Finished Mar 24 02:19:08 PM PDT 24
Peak memory 270148 kb
Host smart-f8764476-7e5b-476c-a7d2-3e6d7b71a618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385690456 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.3385690456
Directory /workspace/3.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke_hw.1440236122
Short name T912
Test name
Test status
Simulation time 23957900 ps
CPU time 25.89 seconds
Started Mar 24 02:18:21 PM PDT 24
Finished Mar 24 02:18:47 PM PDT 24
Peak memory 258712 kb
Host smart-6ffce57e-bb5d-4d1b-95c0-d3712f59c515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440236122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.1440236122
Directory /workspace/3.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/3.flash_ctrl_stress_all.3636634584
Short name T520
Test name
Test status
Simulation time 964683900 ps
CPU time 784.65 seconds
Started Mar 24 02:19:18 PM PDT 24
Finished Mar 24 02:32:23 PM PDT 24
Peak memory 283520 kb
Host smart-77e24df9-0f92-4a36-96ac-cc1d60123310
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636634584 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stres
s_all.3636634584
Directory /workspace/3.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.flash_ctrl_sw_op.3794887047
Short name T535
Test name
Test status
Simulation time 25603200 ps
CPU time 24.86 seconds
Started Mar 24 02:18:31 PM PDT 24
Finished Mar 24 02:18:56 PM PDT 24
Peak memory 261040 kb
Host smart-767c1eb9-780b-4b53-8427-bee6ecbaac1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794887047 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.3794887047
Directory /workspace/3.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_wo.2367605742
Short name T646
Test name
Test status
Simulation time 7280633100 ps
CPU time 152.03 seconds
Started Mar 24 02:18:52 PM PDT 24
Finished Mar 24 02:21:24 PM PDT 24
Peak memory 265044 kb
Host smart-25ceee6e-1e4b-47cb-8ebe-2571b031964c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367605742 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.flash_ctrl_wo.2367605742
Directory /workspace/3.flash_ctrl_wo/latest

Test location /workspace/coverage/default/30.flash_ctrl_alert_test.2813003846
Short name T914
Test name
Test status
Simulation time 44738900 ps
CPU time 14.15 seconds
Started Mar 24 02:29:09 PM PDT 24
Finished Mar 24 02:29:23 PM PDT 24
Peak memory 264912 kb
Host smart-aca1b1fb-dc8e-44a4-a586-156268563265
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813003846 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.
2813003846
Directory /workspace/30.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.flash_ctrl_connect.3238356857
Short name T728
Test name
Test status
Simulation time 51168000 ps
CPU time 16.33 seconds
Started Mar 24 02:29:10 PM PDT 24
Finished Mar 24 02:29:26 PM PDT 24
Peak memory 275176 kb
Host smart-ed523f87-0c69-4593-a3f1-8f21b5fae992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238356857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.3238356857
Directory /workspace/30.flash_ctrl_connect/latest

Test location /workspace/coverage/default/30.flash_ctrl_disable.2173797682
Short name T153
Test name
Test status
Simulation time 59786900 ps
CPU time 22.77 seconds
Started Mar 24 02:29:08 PM PDT 24
Finished Mar 24 02:29:31 PM PDT 24
Peak memory 273352 kb
Host smart-bb89f36f-794a-4578-8c76-aded0274960e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173797682 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_disable.2173797682
Directory /workspace/30.flash_ctrl_disable/latest

Test location /workspace/coverage/default/30.flash_ctrl_hw_sec_otp.1805082024
Short name T500
Test name
Test status
Simulation time 9482378900 ps
CPU time 171.6 seconds
Started Mar 24 02:29:03 PM PDT 24
Finished Mar 24 02:31:55 PM PDT 24
Peak memory 262516 kb
Host smart-a3623f7a-dd29-428d-b676-61e6e578ed44
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805082024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_
hw_sec_otp.1805082024
Directory /workspace/30.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd_slow_flash.1793615169
Short name T752
Test name
Test status
Simulation time 9702808500 ps
CPU time 213.5 seconds
Started Mar 24 02:29:10 PM PDT 24
Finished Mar 24 02:32:44 PM PDT 24
Peak memory 284328 kb
Host smart-a7ed3cb7-deda-426a-89db-564701102ec1
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793615169 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd_slow_flash.1793615169
Directory /workspace/30.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/30.flash_ctrl_otp_reset.1637730635
Short name T905
Test name
Test status
Simulation time 45158900 ps
CPU time 110.2 seconds
Started Mar 24 02:29:04 PM PDT 24
Finished Mar 24 02:30:54 PM PDT 24
Peak memory 259468 kb
Host smart-dcc5d31b-a36b-4bac-8c18-25fd1e91302e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637730635 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_o
tp_reset.1637730635
Directory /workspace/30.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict.3087787819
Short name T552
Test name
Test status
Simulation time 75038400 ps
CPU time 33.11 seconds
Started Mar 24 02:29:10 PM PDT 24
Finished Mar 24 02:29:43 PM PDT 24
Peak memory 273240 kb
Host smart-b9f08be8-3d65-41a7-a815-833f04cc1c2a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087787819 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fl
ash_ctrl_rw_evict.3087787819
Directory /workspace/30.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict_all_en.2046300239
Short name T656
Test name
Test status
Simulation time 31386300 ps
CPU time 32.02 seconds
Started Mar 24 02:29:10 PM PDT 24
Finished Mar 24 02:29:42 PM PDT 24
Peak memory 267108 kb
Host smart-19ed154c-f89f-484d-9573-a6d7e661d705
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046300239 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict_all_en.2046300239
Directory /workspace/30.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/30.flash_ctrl_sec_info_access.2986760160
Short name T370
Test name
Test status
Simulation time 383422600 ps
CPU time 56.36 seconds
Started Mar 24 02:29:10 PM PDT 24
Finished Mar 24 02:30:07 PM PDT 24
Peak memory 262996 kb
Host smart-cd8047f5-569f-4987-a137-805f373ebd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986760160 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.2986760160
Directory /workspace/30.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/30.flash_ctrl_smoke.2043988404
Short name T992
Test name
Test status
Simulation time 94075000 ps
CPU time 123.04 seconds
Started Mar 24 02:29:03 PM PDT 24
Finished Mar 24 02:31:07 PM PDT 24
Peak memory 275128 kb
Host smart-7c93be86-5194-49f3-97a4-3b68b6f945e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043988404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.2043988404
Directory /workspace/30.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/31.flash_ctrl_alert_test.2758816753
Short name T558
Test name
Test status
Simulation time 110034600 ps
CPU time 13.87 seconds
Started Mar 24 02:29:18 PM PDT 24
Finished Mar 24 02:29:32 PM PDT 24
Peak memory 264844 kb
Host smart-6f37289a-49c6-4ed9-b029-d65a2ef8fb71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758816753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test.
2758816753
Directory /workspace/31.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.flash_ctrl_connect.934010152
Short name T681
Test name
Test status
Simulation time 16310700 ps
CPU time 13.21 seconds
Started Mar 24 02:29:18 PM PDT 24
Finished Mar 24 02:29:32 PM PDT 24
Peak memory 274520 kb
Host smart-ebb5d66d-20c3-4139-afb1-206816c39b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934010152 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.934010152
Directory /workspace/31.flash_ctrl_connect/latest

Test location /workspace/coverage/default/31.flash_ctrl_disable.4214257773
Short name T589
Test name
Test status
Simulation time 21183200 ps
CPU time 22.16 seconds
Started Mar 24 02:29:19 PM PDT 24
Finished Mar 24 02:29:42 PM PDT 24
Peak memory 273268 kb
Host smart-2101e32d-cb73-4439-9cef-22e6de2f1ab5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214257773 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_disable.4214257773
Directory /workspace/31.flash_ctrl_disable/latest

Test location /workspace/coverage/default/31.flash_ctrl_hw_sec_otp.177363773
Short name T425
Test name
Test status
Simulation time 2123726200 ps
CPU time 72.68 seconds
Started Mar 24 02:29:16 PM PDT 24
Finished Mar 24 02:30:29 PM PDT 24
Peak memory 262432 kb
Host smart-555433aa-cc9c-4503-8cdf-0545c2ac719d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177363773 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_h
w_sec_otp.177363773
Directory /workspace/31.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd_slow_flash.2824610432
Short name T560
Test name
Test status
Simulation time 36554885600 ps
CPU time 247.05 seconds
Started Mar 24 02:29:15 PM PDT 24
Finished Mar 24 02:33:22 PM PDT 24
Peak memory 289512 kb
Host smart-fb7c49df-0c3a-432b-9e99-c5a8c6efa765
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824610432 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd_slow_flash.2824610432
Directory /workspace/31.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/31.flash_ctrl_otp_reset.3827925487
Short name T152
Test name
Test status
Simulation time 558045000 ps
CPU time 132.35 seconds
Started Mar 24 02:29:14 PM PDT 24
Finished Mar 24 02:31:27 PM PDT 24
Peak memory 263292 kb
Host smart-b4c4f090-c1ed-4ce3-9f43-b3bb9eccfe6c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827925487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_o
tp_reset.3827925487
Directory /workspace/31.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict.1514937964
Short name T970
Test name
Test status
Simulation time 54179200 ps
CPU time 31.01 seconds
Started Mar 24 02:29:14 PM PDT 24
Finished Mar 24 02:29:45 PM PDT 24
Peak memory 267164 kb
Host smart-571d3b6f-2f74-4a18-849b-6a4631f3fd6e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514937964 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fl
ash_ctrl_rw_evict.1514937964
Directory /workspace/31.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict_all_en.334214070
Short name T767
Test name
Test status
Simulation time 38465800 ps
CPU time 29.02 seconds
Started Mar 24 02:29:24 PM PDT 24
Finished Mar 24 02:29:53 PM PDT 24
Peak memory 273172 kb
Host smart-a25d5ccd-646a-49be-98c0-b5144ecfd3ae
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334214070 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict_all_en.334214070
Directory /workspace/31.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/31.flash_ctrl_sec_info_access.3973854404
Short name T956
Test name
Test status
Simulation time 4563939500 ps
CPU time 71.35 seconds
Started Mar 24 02:29:18 PM PDT 24
Finished Mar 24 02:30:30 PM PDT 24
Peak memory 262244 kb
Host smart-e1ec11db-2007-485b-b9ff-6aa30774a7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973854404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.3973854404
Directory /workspace/31.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/31.flash_ctrl_smoke.1439772447
Short name T548
Test name
Test status
Simulation time 63010400 ps
CPU time 100.29 seconds
Started Mar 24 02:29:13 PM PDT 24
Finished Mar 24 02:30:53 PM PDT 24
Peak memory 276244 kb
Host smart-c7562238-154f-4091-81aa-0606adeb7ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439772447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.1439772447
Directory /workspace/31.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/32.flash_ctrl_alert_test.1317605432
Short name T747
Test name
Test status
Simulation time 136094500 ps
CPU time 13.63 seconds
Started Mar 24 02:29:31 PM PDT 24
Finished Mar 24 02:29:44 PM PDT 24
Peak memory 258116 kb
Host smart-9bc144ba-d13f-4663-8fac-5319ef02c365
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317605432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.
1317605432
Directory /workspace/32.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.flash_ctrl_connect.3043518120
Short name T408
Test name
Test status
Simulation time 27077700 ps
CPU time 16.05 seconds
Started Mar 24 02:29:35 PM PDT 24
Finished Mar 24 02:29:51 PM PDT 24
Peak memory 275512 kb
Host smart-92ddd88e-fc90-49cc-94a3-1c51b90f49fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043518120 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.3043518120
Directory /workspace/32.flash_ctrl_connect/latest

Test location /workspace/coverage/default/32.flash_ctrl_disable.42187855
Short name T1035
Test name
Test status
Simulation time 40326800 ps
CPU time 22.22 seconds
Started Mar 24 02:29:29 PM PDT 24
Finished Mar 24 02:29:51 PM PDT 24
Peak memory 273184 kb
Host smart-d375f2c3-8267-43c6-8463-21c942e54790
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42187855 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.flash_ctrl_disable.42187855
Directory /workspace/32.flash_ctrl_disable/latest

Test location /workspace/coverage/default/32.flash_ctrl_hw_sec_otp.3661875178
Short name T735
Test name
Test status
Simulation time 11759328800 ps
CPU time 116.34 seconds
Started Mar 24 02:29:19 PM PDT 24
Finished Mar 24 02:31:16 PM PDT 24
Peak memory 261800 kb
Host smart-13b3a410-a506-4e49-894a-f826057ed080
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661875178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_
hw_sec_otp.3661875178
Directory /workspace/32.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd_slow_flash.329913067
Short name T326
Test name
Test status
Simulation time 15499462000 ps
CPU time 206.33 seconds
Started Mar 24 02:29:24 PM PDT 24
Finished Mar 24 02:32:50 PM PDT 24
Peak memory 289540 kb
Host smart-daddfe8d-9073-4c04-92b5-9ac121cfc8fe
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329913067 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd_slow_flash.329913067
Directory /workspace/32.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/32.flash_ctrl_otp_reset.1714787158
Short name T691
Test name
Test status
Simulation time 108388200 ps
CPU time 131.57 seconds
Started Mar 24 02:29:24 PM PDT 24
Finished Mar 24 02:31:35 PM PDT 24
Peak memory 264176 kb
Host smart-870f7b3a-ab6c-4c68-9de0-c32f34d7b10b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714787158 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_o
tp_reset.1714787158
Directory /workspace/32.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict.448714183
Short name T18
Test name
Test status
Simulation time 51919000 ps
CPU time 32.89 seconds
Started Mar 24 02:29:26 PM PDT 24
Finished Mar 24 02:29:59 PM PDT 24
Peak memory 273320 kb
Host smart-951b0c85-d64f-4d1c-8d0e-eeaf1418d9db
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448714183 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fla
sh_ctrl_rw_evict.448714183
Directory /workspace/32.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict_all_en.869305455
Short name T36
Test name
Test status
Simulation time 30713800 ps
CPU time 30.32 seconds
Started Mar 24 02:29:27 PM PDT 24
Finished Mar 24 02:29:58 PM PDT 24
Peak memory 273256 kb
Host smart-4ab2366f-af34-4cc7-9ffe-3d1b239b9af5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869305455 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict_all_en.869305455
Directory /workspace/32.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/32.flash_ctrl_sec_info_access.3496330788
Short name T988
Test name
Test status
Simulation time 3651244900 ps
CPU time 71.42 seconds
Started Mar 24 02:29:28 PM PDT 24
Finished Mar 24 02:30:40 PM PDT 24
Peak memory 262788 kb
Host smart-e510b977-03e7-4e3d-8190-2ddff522279c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496330788 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.3496330788
Directory /workspace/32.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/32.flash_ctrl_smoke.3953164800
Short name T1039
Test name
Test status
Simulation time 59392500 ps
CPU time 215.94 seconds
Started Mar 24 02:29:24 PM PDT 24
Finished Mar 24 02:33:00 PM PDT 24
Peak memory 276804 kb
Host smart-ad9ef776-fb64-4113-a3bf-1049bcacfc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953164800 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.3953164800
Directory /workspace/32.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/33.flash_ctrl_alert_test.2694632556
Short name T602
Test name
Test status
Simulation time 20041600 ps
CPU time 13.28 seconds
Started Mar 24 02:29:39 PM PDT 24
Finished Mar 24 02:29:52 PM PDT 24
Peak memory 264772 kb
Host smart-689d9d4b-88c2-4214-b13a-cb278f3e7fdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694632556 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test.
2694632556
Directory /workspace/33.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.flash_ctrl_connect.1219700205
Short name T834
Test name
Test status
Simulation time 14212400 ps
CPU time 13.39 seconds
Started Mar 24 02:29:28 PM PDT 24
Finished Mar 24 02:29:42 PM PDT 24
Peak memory 275204 kb
Host smart-c3a3152e-e2c5-4a7a-894a-2206a4f4775b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219700205 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.1219700205
Directory /workspace/33.flash_ctrl_connect/latest

Test location /workspace/coverage/default/33.flash_ctrl_disable.81471534
Short name T364
Test name
Test status
Simulation time 10581100 ps
CPU time 21.84 seconds
Started Mar 24 02:29:34 PM PDT 24
Finished Mar 24 02:29:56 PM PDT 24
Peak memory 273160 kb
Host smart-6e1981d3-1305-461b-a278-1d04f2860ad3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81471534 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.flash_ctrl_disable.81471534
Directory /workspace/33.flash_ctrl_disable/latest

Test location /workspace/coverage/default/33.flash_ctrl_hw_sec_otp.1493866151
Short name T513
Test name
Test status
Simulation time 5554177200 ps
CPU time 202.08 seconds
Started Mar 24 02:29:29 PM PDT 24
Finished Mar 24 02:32:51 PM PDT 24
Peak memory 262404 kb
Host smart-1695815d-0531-49a1-8eb7-a8a4b8769b77
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493866151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_
hw_sec_otp.1493866151
Directory /workspace/33.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd_slow_flash.2291622512
Short name T323
Test name
Test status
Simulation time 8369250500 ps
CPU time 219.74 seconds
Started Mar 24 02:29:28 PM PDT 24
Finished Mar 24 02:33:08 PM PDT 24
Peak memory 284548 kb
Host smart-f46a78a6-ed1e-4725-b5b3-ab02728b914f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291622512 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd_slow_flash.2291622512
Directory /workspace/33.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/33.flash_ctrl_otp_reset.166770177
Short name T848
Test name
Test status
Simulation time 43840200 ps
CPU time 129.01 seconds
Started Mar 24 02:29:34 PM PDT 24
Finished Mar 24 02:31:44 PM PDT 24
Peak memory 263120 kb
Host smart-4271fad3-b9d5-4c7e-8a65-512896f167d7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166770177 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_ot
p_reset.166770177
Directory /workspace/33.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict.2136744592
Short name T924
Test name
Test status
Simulation time 77305100 ps
CPU time 31.95 seconds
Started Mar 24 02:29:27 PM PDT 24
Finished Mar 24 02:30:00 PM PDT 24
Peak memory 273312 kb
Host smart-d86339a0-fe88-4aa2-9445-beaab9f9d223
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136744592 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fl
ash_ctrl_rw_evict.2136744592
Directory /workspace/33.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict_all_en.2034822576
Short name T655
Test name
Test status
Simulation time 299924600 ps
CPU time 31.21 seconds
Started Mar 24 02:29:28 PM PDT 24
Finished Mar 24 02:29:59 PM PDT 24
Peak memory 273300 kb
Host smart-f7f99241-ff1d-4210-843f-1c91685df147
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034822576 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict_all_en.2034822576
Directory /workspace/33.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/33.flash_ctrl_smoke.429520648
Short name T813
Test name
Test status
Simulation time 70575600 ps
CPU time 96.76 seconds
Started Mar 24 02:29:30 PM PDT 24
Finished Mar 24 02:31:07 PM PDT 24
Peak memory 276152 kb
Host smart-f4e13fe8-c44c-419f-a41c-999de2f83e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429520648 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.429520648
Directory /workspace/33.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/34.flash_ctrl_alert_test.2580149365
Short name T699
Test name
Test status
Simulation time 72605100 ps
CPU time 13.7 seconds
Started Mar 24 02:29:38 PM PDT 24
Finished Mar 24 02:29:52 PM PDT 24
Peak memory 264884 kb
Host smart-e16314d0-68ec-4774-ae31-e156905b95dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580149365 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.
2580149365
Directory /workspace/34.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.flash_ctrl_connect.1588910336
Short name T977
Test name
Test status
Simulation time 16474100 ps
CPU time 15.82 seconds
Started Mar 24 02:29:39 PM PDT 24
Finished Mar 24 02:29:55 PM PDT 24
Peak memory 275328 kb
Host smart-83d320f7-13f0-4540-807d-42fc62bbaa7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588910336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.1588910336
Directory /workspace/34.flash_ctrl_connect/latest

Test location /workspace/coverage/default/34.flash_ctrl_disable.716115542
Short name T380
Test name
Test status
Simulation time 29658300 ps
CPU time 20.28 seconds
Started Mar 24 02:29:39 PM PDT 24
Finished Mar 24 02:29:59 PM PDT 24
Peak memory 264880 kb
Host smart-82c92281-3bfb-4ec6-a65a-54a4f33ebd87
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716115542 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_disable.716115542
Directory /workspace/34.flash_ctrl_disable/latest

Test location /workspace/coverage/default/34.flash_ctrl_hw_sec_otp.1013961832
Short name T800
Test name
Test status
Simulation time 2598364400 ps
CPU time 93.16 seconds
Started Mar 24 02:29:33 PM PDT 24
Finished Mar 24 02:31:06 PM PDT 24
Peak memory 262288 kb
Host smart-647c0689-ea5d-4dcb-9bb4-801b6a6e12fa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013961832 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_
hw_sec_otp.1013961832
Directory /workspace/34.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd_slow_flash.959846616
Short name T331
Test name
Test status
Simulation time 63416062300 ps
CPU time 249.02 seconds
Started Mar 24 02:29:36 PM PDT 24
Finished Mar 24 02:33:45 PM PDT 24
Peak memory 292636 kb
Host smart-324e3197-5843-4cf7-a4ea-e6302fd42c53
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959846616 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd_slow_flash.959846616
Directory /workspace/34.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/34.flash_ctrl_otp_reset.1688780981
Short name T145
Test name
Test status
Simulation time 114052400 ps
CPU time 131.77 seconds
Started Mar 24 02:29:35 PM PDT 24
Finished Mar 24 02:31:47 PM PDT 24
Peak memory 259424 kb
Host smart-19823c59-d5f7-4791-be33-f532465c5822
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688780981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_o
tp_reset.1688780981
Directory /workspace/34.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict.242890562
Short name T198
Test name
Test status
Simulation time 161132100 ps
CPU time 32.32 seconds
Started Mar 24 02:29:33 PM PDT 24
Finished Mar 24 02:30:06 PM PDT 24
Peak memory 273304 kb
Host smart-cd2826ed-5d11-448b-b105-72052c3209b9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242890562 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fla
sh_ctrl_rw_evict.242890562
Directory /workspace/34.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict_all_en.2439351316
Short name T982
Test name
Test status
Simulation time 54239500 ps
CPU time 31.28 seconds
Started Mar 24 02:29:35 PM PDT 24
Finished Mar 24 02:30:06 PM PDT 24
Peak memory 270440 kb
Host smart-78db45eb-b7fc-48fe-ad81-585dc866399e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439351316 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict_all_en.2439351316
Directory /workspace/34.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/34.flash_ctrl_sec_info_access.3925810991
Short name T706
Test name
Test status
Simulation time 4082586900 ps
CPU time 60.88 seconds
Started Mar 24 02:29:39 PM PDT 24
Finished Mar 24 02:30:40 PM PDT 24
Peak memory 262592 kb
Host smart-84fe56a9-5515-4f58-9428-224f84cb6f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925810991 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.3925810991
Directory /workspace/34.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/34.flash_ctrl_smoke.4087202380
Short name T911
Test name
Test status
Simulation time 43484300 ps
CPU time 172.85 seconds
Started Mar 24 02:29:33 PM PDT 24
Finished Mar 24 02:32:26 PM PDT 24
Peak memory 279620 kb
Host smart-140c9b58-1b2a-47ea-9d93-7826619c404f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087202380 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.4087202380
Directory /workspace/34.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/35.flash_ctrl_alert_test.2508831747
Short name T555
Test name
Test status
Simulation time 116337800 ps
CPU time 13.72 seconds
Started Mar 24 02:29:43 PM PDT 24
Finished Mar 24 02:29:57 PM PDT 24
Peak memory 264860 kb
Host smart-c4a062d0-7539-4f7a-bc6e-6053aa4cae3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508831747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test.
2508831747
Directory /workspace/35.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.flash_ctrl_connect.1794061462
Short name T718
Test name
Test status
Simulation time 66426300 ps
CPU time 15.65 seconds
Started Mar 24 02:29:43 PM PDT 24
Finished Mar 24 02:29:59 PM PDT 24
Peak memory 275552 kb
Host smart-45141499-a044-4333-bd7d-4f2aeb2d6026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794061462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.1794061462
Directory /workspace/35.flash_ctrl_connect/latest

Test location /workspace/coverage/default/35.flash_ctrl_disable.2019804811
Short name T949
Test name
Test status
Simulation time 22748600 ps
CPU time 20.97 seconds
Started Mar 24 02:29:42 PM PDT 24
Finished Mar 24 02:30:03 PM PDT 24
Peak memory 264840 kb
Host smart-53d5c51d-5297-4c83-a0d8-9ca58ee88c82
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019804811 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.flash_ctrl_disable.2019804811
Directory /workspace/35.flash_ctrl_disable/latest

Test location /workspace/coverage/default/35.flash_ctrl_hw_sec_otp.2358319839
Short name T411
Test name
Test status
Simulation time 15760608200 ps
CPU time 141.48 seconds
Started Mar 24 02:29:38 PM PDT 24
Finished Mar 24 02:31:59 PM PDT 24
Peak memory 262424 kb
Host smart-d423a109-020e-40ef-9a94-3987b158c74f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358319839 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_
hw_sec_otp.2358319839
Directory /workspace/35.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd_slow_flash.3481105546
Short name T694
Test name
Test status
Simulation time 35727863800 ps
CPU time 280.22 seconds
Started Mar 24 02:29:43 PM PDT 24
Finished Mar 24 02:34:23 PM PDT 24
Peak memory 284540 kb
Host smart-4c737a6a-8e5b-4bc7-8a89-efd99277971a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481105546 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd_slow_flash.3481105546
Directory /workspace/35.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/35.flash_ctrl_otp_reset.2546058045
Short name T143
Test name
Test status
Simulation time 60418200 ps
CPU time 130.92 seconds
Started Mar 24 02:29:38 PM PDT 24
Finished Mar 24 02:31:49 PM PDT 24
Peak memory 263768 kb
Host smart-ab61a7c3-e88a-45e7-8d39-20c2b6213753
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546058045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_o
tp_reset.2546058045
Directory /workspace/35.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict.3130106344
Short name T827
Test name
Test status
Simulation time 105101000 ps
CPU time 31.84 seconds
Started Mar 24 02:29:44 PM PDT 24
Finished Mar 24 02:30:15 PM PDT 24
Peak memory 273252 kb
Host smart-2b54e193-c20c-4ad8-bd9e-c847aa1f5f04
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130106344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fl
ash_ctrl_rw_evict.3130106344
Directory /workspace/35.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict_all_en.759691134
Short name T669
Test name
Test status
Simulation time 29545700 ps
CPU time 31.2 seconds
Started Mar 24 02:29:44 PM PDT 24
Finished Mar 24 02:30:16 PM PDT 24
Peak memory 267056 kb
Host smart-54916e00-c3e9-458c-8c49-8148cd0e0f16
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759691134 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.flash_ctrl_rw_evict_all_en.759691134
Directory /workspace/35.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/35.flash_ctrl_sec_info_access.690259168
Short name T806
Test name
Test status
Simulation time 7047964300 ps
CPU time 65.41 seconds
Started Mar 24 02:29:46 PM PDT 24
Finished Mar 24 02:30:51 PM PDT 24
Peak memory 262096 kb
Host smart-995c3ac8-b221-4f6c-b057-0d681a739077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690259168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.690259168
Directory /workspace/35.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/35.flash_ctrl_smoke.3415839448
Short name T444
Test name
Test status
Simulation time 161135800 ps
CPU time 76.42 seconds
Started Mar 24 02:29:38 PM PDT 24
Finished Mar 24 02:30:54 PM PDT 24
Peak memory 275664 kb
Host smart-58194f7b-1fb9-47e6-b91c-0dd42e91b38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415839448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.3415839448
Directory /workspace/35.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/36.flash_ctrl_alert_test.4076587777
Short name T431
Test name
Test status
Simulation time 106832700 ps
CPU time 13.6 seconds
Started Mar 24 02:29:47 PM PDT 24
Finished Mar 24 02:30:01 PM PDT 24
Peak memory 258016 kb
Host smart-487bb7f2-1aea-4d05-bd9b-689103f7f834
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076587777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.
4076587777
Directory /workspace/36.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.flash_ctrl_connect.952570254
Short name T760
Test name
Test status
Simulation time 167913000 ps
CPU time 15.79 seconds
Started Mar 24 02:29:48 PM PDT 24
Finished Mar 24 02:30:04 PM PDT 24
Peak memory 275492 kb
Host smart-1154d6b8-8b4c-40e0-bc9b-ab12cb64c263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952570254 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.952570254
Directory /workspace/36.flash_ctrl_connect/latest

Test location /workspace/coverage/default/36.flash_ctrl_disable.1582532706
Short name T87
Test name
Test status
Simulation time 10167800 ps
CPU time 20.73 seconds
Started Mar 24 02:29:48 PM PDT 24
Finished Mar 24 02:30:08 PM PDT 24
Peak memory 273172 kb
Host smart-c200e0d4-0b0e-4bf2-95f9-65340299bb01
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582532706 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_disable.1582532706
Directory /workspace/36.flash_ctrl_disable/latest

Test location /workspace/coverage/default/36.flash_ctrl_hw_sec_otp.1067965312
Short name T40
Test name
Test status
Simulation time 2112648100 ps
CPU time 67.26 seconds
Started Mar 24 02:29:49 PM PDT 24
Finished Mar 24 02:30:57 PM PDT 24
Peak memory 262168 kb
Host smart-b229221c-a250-4a71-878b-c8888638a2c9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067965312 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_
hw_sec_otp.1067965312
Directory /workspace/36.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.127934790
Short name T1053
Test name
Test status
Simulation time 8462078900 ps
CPU time 222.74 seconds
Started Mar 24 02:29:47 PM PDT 24
Finished Mar 24 02:33:30 PM PDT 24
Peak memory 289780 kb
Host smart-6b6d9fc6-edea-444b-9f9a-03126478abdd
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127934790 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd_slow_flash.127934790
Directory /workspace/36.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/36.flash_ctrl_otp_reset.2988666089
Short name T717
Test name
Test status
Simulation time 156700200 ps
CPU time 109.92 seconds
Started Mar 24 02:29:48 PM PDT 24
Finished Mar 24 02:31:38 PM PDT 24
Peak memory 259596 kb
Host smart-e0badc39-4d81-4056-9594-81d9ac0fcb4c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988666089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_o
tp_reset.2988666089
Directory /workspace/36.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict.391534623
Short name T223
Test name
Test status
Simulation time 47013400 ps
CPU time 28.16 seconds
Started Mar 24 02:29:49 PM PDT 24
Finished Mar 24 02:30:17 PM PDT 24
Peak memory 273272 kb
Host smart-b01707c5-26fb-4018-8bd5-ec7690d056c1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391534623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fla
sh_ctrl_rw_evict.391534623
Directory /workspace/36.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict_all_en.1987798369
Short name T215
Test name
Test status
Simulation time 44113600 ps
CPU time 31.02 seconds
Started Mar 24 02:29:51 PM PDT 24
Finished Mar 24 02:30:22 PM PDT 24
Peak memory 267188 kb
Host smart-5dabc4c1-ff22-4f70-a539-3f4f0641460c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987798369 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict_all_en.1987798369
Directory /workspace/36.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/36.flash_ctrl_sec_info_access.1842897670
Short name T1005
Test name
Test status
Simulation time 1093386200 ps
CPU time 68.19 seconds
Started Mar 24 02:29:49 PM PDT 24
Finished Mar 24 02:30:57 PM PDT 24
Peak memory 263160 kb
Host smart-041c4c00-4c30-4ac0-9183-e5ab420d1f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842897670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.1842897670
Directory /workspace/36.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/36.flash_ctrl_smoke.2282028688
Short name T815
Test name
Test status
Simulation time 29242000 ps
CPU time 124.05 seconds
Started Mar 24 02:29:48 PM PDT 24
Finished Mar 24 02:31:53 PM PDT 24
Peak memory 277480 kb
Host smart-615da1b3-5f1f-45e8-85a7-57d733c7aaf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282028688 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.2282028688
Directory /workspace/36.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/37.flash_ctrl_alert_test.295827506
Short name T1047
Test name
Test status
Simulation time 230608800 ps
CPU time 13.67 seconds
Started Mar 24 02:29:51 PM PDT 24
Finished Mar 24 02:30:05 PM PDT 24
Peak memory 257988 kb
Host smart-da3abf3d-3618-4e3a-bb25-ec88ab8536ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295827506 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test.295827506
Directory /workspace/37.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.flash_ctrl_connect.2789199645
Short name T189
Test name
Test status
Simulation time 41864500 ps
CPU time 16.05 seconds
Started Mar 24 02:29:51 PM PDT 24
Finished Mar 24 02:30:07 PM PDT 24
Peak memory 274600 kb
Host smart-a7c90fcf-f6e7-4e6a-a5bb-bd1f380968c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789199645 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.2789199645
Directory /workspace/37.flash_ctrl_connect/latest

Test location /workspace/coverage/default/37.flash_ctrl_disable.980131148
Short name T595
Test name
Test status
Simulation time 12825800 ps
CPU time 21.67 seconds
Started Mar 24 02:29:53 PM PDT 24
Finished Mar 24 02:30:15 PM PDT 24
Peak memory 272896 kb
Host smart-ce6810b7-0d93-4447-ab6e-55814c97210a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980131148 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_disable.980131148
Directory /workspace/37.flash_ctrl_disable/latest

Test location /workspace/coverage/default/37.flash_ctrl_hw_sec_otp.1888068764
Short name T764
Test name
Test status
Simulation time 2312961300 ps
CPU time 50.41 seconds
Started Mar 24 02:29:51 PM PDT 24
Finished Mar 24 02:30:42 PM PDT 24
Peak memory 261708 kb
Host smart-cff3602c-1950-49d7-af48-c6b8908bc1f0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888068764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_
hw_sec_otp.1888068764
Directory /workspace/37.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd_slow_flash.2216380066
Short name T618
Test name
Test status
Simulation time 16582836100 ps
CPU time 220.82 seconds
Started Mar 24 02:29:51 PM PDT 24
Finished Mar 24 02:33:32 PM PDT 24
Peak memory 284628 kb
Host smart-e2448b3b-06fe-4012-877c-2a3c5893afa5
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216380066 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd_slow_flash.2216380066
Directory /workspace/37.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/37.flash_ctrl_otp_reset.1714338147
Short name T807
Test name
Test status
Simulation time 92912200 ps
CPU time 130.57 seconds
Started Mar 24 02:29:51 PM PDT 24
Finished Mar 24 02:32:02 PM PDT 24
Peak memory 264140 kb
Host smart-eab48728-80ec-4fb4-9187-fe5a5fa9c528
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714338147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_o
tp_reset.1714338147
Directory /workspace/37.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict.500108963
Short name T511
Test name
Test status
Simulation time 30058100 ps
CPU time 31.14 seconds
Started Mar 24 02:29:51 PM PDT 24
Finished Mar 24 02:30:23 PM PDT 24
Peak memory 273232 kb
Host smart-df710232-d1fd-4f21-bc59-17658618d245
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500108963 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fla
sh_ctrl_rw_evict.500108963
Directory /workspace/37.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict_all_en.2534149504
Short name T197
Test name
Test status
Simulation time 42658200 ps
CPU time 29.58 seconds
Started Mar 24 02:29:51 PM PDT 24
Finished Mar 24 02:30:21 PM PDT 24
Peak memory 273296 kb
Host smart-f1dc1cc1-0139-44ad-b13b-67dfa98e1cbf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534149504 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict_all_en.2534149504
Directory /workspace/37.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/37.flash_ctrl_sec_info_access.2894886995
Short name T928
Test name
Test status
Simulation time 1934161600 ps
CPU time 68.16 seconds
Started Mar 24 02:29:51 PM PDT 24
Finished Mar 24 02:31:00 PM PDT 24
Peak memory 262684 kb
Host smart-7d92ce40-94ce-4491-8aab-65ffb0ecb93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894886995 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.2894886995
Directory /workspace/37.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/37.flash_ctrl_smoke.57636905
Short name T619
Test name
Test status
Simulation time 68111900 ps
CPU time 194.96 seconds
Started Mar 24 02:29:48 PM PDT 24
Finished Mar 24 02:33:03 PM PDT 24
Peak memory 277692 kb
Host smart-ba76dc4c-f31e-485e-b500-c24a246f48ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57636905 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.57636905
Directory /workspace/37.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/38.flash_ctrl_alert_test.2410729054
Short name T997
Test name
Test status
Simulation time 26417800 ps
CPU time 14.05 seconds
Started Mar 24 02:30:02 PM PDT 24
Finished Mar 24 02:30:16 PM PDT 24
Peak memory 258068 kb
Host smart-ecb53424-fe8a-4298-a9c3-a658aa00c4b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410729054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test.
2410729054
Directory /workspace/38.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.flash_ctrl_connect.277866410
Short name T817
Test name
Test status
Simulation time 14938700 ps
CPU time 13.75 seconds
Started Mar 24 02:29:59 PM PDT 24
Finished Mar 24 02:30:13 PM PDT 24
Peak memory 274500 kb
Host smart-67d96f68-7551-4d58-ae32-832c52ade7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277866410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.277866410
Directory /workspace/38.flash_ctrl_connect/latest

Test location /workspace/coverage/default/38.flash_ctrl_disable.1156350760
Short name T366
Test name
Test status
Simulation time 16741600 ps
CPU time 21.85 seconds
Started Mar 24 02:29:57 PM PDT 24
Finished Mar 24 02:30:19 PM PDT 24
Peak memory 273148 kb
Host smart-8d401449-090d-4e98-bdab-f1c3b11040cd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156350760 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.flash_ctrl_disable.1156350760
Directory /workspace/38.flash_ctrl_disable/latest

Test location /workspace/coverage/default/38.flash_ctrl_hw_sec_otp.2855589422
Short name T908
Test name
Test status
Simulation time 1616517600 ps
CPU time 66.75 seconds
Started Mar 24 02:29:57 PM PDT 24
Finished Mar 24 02:31:04 PM PDT 24
Peak memory 261744 kb
Host smart-f81b721f-314d-48e1-8fc0-e70fce883545
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855589422 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_
hw_sec_otp.2855589422
Directory /workspace/38.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd_slow_flash.669800960
Short name T675
Test name
Test status
Simulation time 8739635600 ps
CPU time 199.11 seconds
Started Mar 24 02:29:57 PM PDT 24
Finished Mar 24 02:33:17 PM PDT 24
Peak memory 290596 kb
Host smart-0209d6cf-a0dc-458f-8b78-130eb10f9527
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669800960 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd_slow_flash.669800960
Directory /workspace/38.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/38.flash_ctrl_otp_reset.4187924626
Short name T506
Test name
Test status
Simulation time 41317600 ps
CPU time 131.6 seconds
Started Mar 24 02:29:57 PM PDT 24
Finished Mar 24 02:32:09 PM PDT 24
Peak memory 260928 kb
Host smart-e154dc62-9ae8-4b0a-a753-6cf334b3063c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187924626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_o
tp_reset.4187924626
Directory /workspace/38.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict.13932831
Short name T210
Test name
Test status
Simulation time 39997300 ps
CPU time 30.6 seconds
Started Mar 24 02:29:56 PM PDT 24
Finished Mar 24 02:30:27 PM PDT 24
Peak memory 266152 kb
Host smart-a72f355c-d9a2-4606-a5cd-5253ebab62a9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13932831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flas
h_ctrl_rw_evict.13932831
Directory /workspace/38.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict_all_en.3569768167
Short name T540
Test name
Test status
Simulation time 327419300 ps
CPU time 32.17 seconds
Started Mar 24 02:29:56 PM PDT 24
Finished Mar 24 02:30:29 PM PDT 24
Peak memory 273272 kb
Host smart-bca41a6a-b63e-4381-91e1-740e2c89edd0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569768167 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict_all_en.3569768167
Directory /workspace/38.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/38.flash_ctrl_sec_info_access.1261053793
Short name T386
Test name
Test status
Simulation time 711143300 ps
CPU time 82.5 seconds
Started Mar 24 02:29:58 PM PDT 24
Finished Mar 24 02:31:20 PM PDT 24
Peak memory 263164 kb
Host smart-673118c9-3a63-4a8d-800e-66bfdfd15dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261053793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.1261053793
Directory /workspace/38.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/38.flash_ctrl_smoke.3217333830
Short name T840
Test name
Test status
Simulation time 33345500 ps
CPU time 147.9 seconds
Started Mar 24 02:29:52 PM PDT 24
Finished Mar 24 02:32:20 PM PDT 24
Peak memory 275952 kb
Host smart-09358fde-d255-464e-b719-bbda84d352e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217333830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.3217333830
Directory /workspace/38.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/39.flash_ctrl_alert_test.2209109114
Short name T416
Test name
Test status
Simulation time 51662600 ps
CPU time 13.56 seconds
Started Mar 24 02:30:08 PM PDT 24
Finished Mar 24 02:30:22 PM PDT 24
Peak memory 257952 kb
Host smart-4b01a736-d2f8-41c7-ac1d-dcf476a2d4ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209109114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test.
2209109114
Directory /workspace/39.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.flash_ctrl_connect.3274303407
Short name T626
Test name
Test status
Simulation time 16489700 ps
CPU time 15.69 seconds
Started Mar 24 02:30:08 PM PDT 24
Finished Mar 24 02:30:23 PM PDT 24
Peak memory 275096 kb
Host smart-160d8a25-a54c-4ee1-a985-6dadd7e049ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274303407 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.3274303407
Directory /workspace/39.flash_ctrl_connect/latest

Test location /workspace/coverage/default/39.flash_ctrl_disable.2869087734
Short name T572
Test name
Test status
Simulation time 14124700 ps
CPU time 22.1 seconds
Started Mar 24 02:30:01 PM PDT 24
Finished Mar 24 02:30:23 PM PDT 24
Peak memory 273140 kb
Host smart-4a887293-6184-48ac-b282-b6d37c7e118b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869087734 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_disable.2869087734
Directory /workspace/39.flash_ctrl_disable/latest

Test location /workspace/coverage/default/39.flash_ctrl_hw_sec_otp.568263306
Short name T182
Test name
Test status
Simulation time 5741497400 ps
CPU time 203.44 seconds
Started Mar 24 02:30:01 PM PDT 24
Finished Mar 24 02:33:24 PM PDT 24
Peak memory 262324 kb
Host smart-2c0d41d5-edb5-408e-be87-a4e58af8e6df
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568263306 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_h
w_sec_otp.568263306
Directory /workspace/39.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd_slow_flash.1334284052
Short name T1016
Test name
Test status
Simulation time 33251169900 ps
CPU time 257.89 seconds
Started Mar 24 02:30:02 PM PDT 24
Finished Mar 24 02:34:20 PM PDT 24
Peak memory 284484 kb
Host smart-c7ed14ea-1207-4fef-a23b-d6c70e8584be
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334284052 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd_slow_flash.1334284052
Directory /workspace/39.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/39.flash_ctrl_otp_reset.1560913066
Short name T81
Test name
Test status
Simulation time 261142300 ps
CPU time 109.36 seconds
Started Mar 24 02:30:02 PM PDT 24
Finished Mar 24 02:31:51 PM PDT 24
Peak memory 259612 kb
Host smart-96f00e61-04e8-4191-9365-f607370f529f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560913066 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_o
tp_reset.1560913066
Directory /workspace/39.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict.2848403771
Short name T640
Test name
Test status
Simulation time 30445000 ps
CPU time 31.54 seconds
Started Mar 24 02:30:01 PM PDT 24
Finished Mar 24 02:30:33 PM PDT 24
Peak memory 273244 kb
Host smart-4ae19a25-6f6b-48b4-a8a8-ae692f80196e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848403771 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fl
ash_ctrl_rw_evict.2848403771
Directory /workspace/39.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict_all_en.3980716278
Short name T200
Test name
Test status
Simulation time 38856200 ps
CPU time 30.88 seconds
Started Mar 24 02:30:01 PM PDT 24
Finished Mar 24 02:30:31 PM PDT 24
Peak memory 266120 kb
Host smart-d20f120e-2317-48be-87cf-e5d3d69fb991
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980716278 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict_all_en.3980716278
Directory /workspace/39.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/39.flash_ctrl_sec_info_access.1472730436
Short name T389
Test name
Test status
Simulation time 1965987700 ps
CPU time 72.57 seconds
Started Mar 24 02:30:02 PM PDT 24
Finished Mar 24 02:31:15 PM PDT 24
Peak memory 263872 kb
Host smart-8290d9ac-2aab-4335-9425-3f0be7b6bc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472730436 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.1472730436
Directory /workspace/39.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/39.flash_ctrl_smoke.188812433
Short name T442
Test name
Test status
Simulation time 26438000 ps
CPU time 49.81 seconds
Started Mar 24 02:30:03 PM PDT 24
Finished Mar 24 02:30:53 PM PDT 24
Peak memory 270392 kb
Host smart-f418547d-18e7-4f61-8853-375d46c3b5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188812433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.188812433
Directory /workspace/39.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_alert_test.289631347
Short name T562
Test name
Test status
Simulation time 29833900 ps
CPU time 13.63 seconds
Started Mar 24 02:20:45 PM PDT 24
Finished Mar 24 02:21:00 PM PDT 24
Peak memory 264868 kb
Host smart-89e7976f-e534-47fe-aaab-d54915e8f5c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289631347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.289631347
Directory /workspace/4.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.flash_ctrl_config_regwen.3592159010
Short name T886
Test name
Test status
Simulation time 22877100 ps
CPU time 14.44 seconds
Started Mar 24 02:20:41 PM PDT 24
Finished Mar 24 02:20:55 PM PDT 24
Peak memory 261740 kb
Host smart-8dd328fb-284d-4498-af29-8558909a69e3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592159010 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.flash_ctrl_config_regwen.3592159010
Directory /workspace/4.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.flash_ctrl_connect.2967655802
Short name T483
Test name
Test status
Simulation time 123631700 ps
CPU time 15.72 seconds
Started Mar 24 02:20:39 PM PDT 24
Finished Mar 24 02:20:55 PM PDT 24
Peak memory 275248 kb
Host smart-bbcb4536-8ffa-4edb-9098-718e5754a079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967655802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.2967655802
Directory /workspace/4.flash_ctrl_connect/latest

Test location /workspace/coverage/default/4.flash_ctrl_derr_detect.4121982399
Short name T794
Test name
Test status
Simulation time 211160300 ps
CPU time 104.01 seconds
Started Mar 24 02:20:17 PM PDT 24
Finished Mar 24 02:22:01 PM PDT 24
Peak memory 273376 kb
Host smart-f46474d3-14e4-4455-8ac0-823e2d060605
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121982399 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.flash_ctrl_derr_detect.4121982399
Directory /workspace/4.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/4.flash_ctrl_disable.2376351250
Short name T86
Test name
Test status
Simulation time 10909000 ps
CPU time 22 seconds
Started Mar 24 02:20:26 PM PDT 24
Finished Mar 24 02:20:48 PM PDT 24
Peak memory 273184 kb
Host smart-c2b05dd3-6720-4b27-98f4-681894ba1c21
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376351250 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_disable.2376351250
Directory /workspace/4.flash_ctrl_disable/latest

Test location /workspace/coverage/default/4.flash_ctrl_erase_suspend.2933106272
Short name T120
Test name
Test status
Simulation time 5570745900 ps
CPU time 375.79 seconds
Started Mar 24 02:19:42 PM PDT 24
Finished Mar 24 02:25:58 PM PDT 24
Peak memory 261004 kb
Host smart-a99dba28-55d2-432b-9f14-bbb242671d47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2933106272 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.2933106272
Directory /workspace/4.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_mp.859320007
Short name T508
Test name
Test status
Simulation time 3713184300 ps
CPU time 2399.08 seconds
Started Mar 24 02:19:58 PM PDT 24
Finished Mar 24 02:59:58 PM PDT 24
Peak memory 264796 kb
Host smart-78bd4b78-54ab-476e-8d65-0bfae867bee6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859320007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erro
r_mp.859320007
Directory /workspace/4.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_type.2912478241
Short name T812
Test name
Test status
Simulation time 308802400 ps
CPU time 1834.99 seconds
Started Mar 24 02:19:57 PM PDT 24
Finished Mar 24 02:50:33 PM PDT 24
Peak memory 264840 kb
Host smart-3ce6853f-876b-4ca8-b782-a0ff4a1eb3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912478241 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_type.2912478241
Directory /workspace/4.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_win.573140283
Short name T162
Test name
Test status
Simulation time 1267337000 ps
CPU time 846.42 seconds
Started Mar 24 02:19:59 PM PDT 24
Finished Mar 24 02:34:06 PM PDT 24
Peak memory 273064 kb
Host smart-45043f9f-7f54-4cd8-98a3-d28e8a918621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573140283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.573140283
Directory /workspace/4.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/4.flash_ctrl_fetch_code.3490478054
Short name T48
Test name
Test status
Simulation time 221407800 ps
CPU time 21 seconds
Started Mar 24 02:19:52 PM PDT 24
Finished Mar 24 02:20:13 PM PDT 24
Peak memory 264788 kb
Host smart-0a31dbba-426f-40a7-8b55-47951011a9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490478054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetch_code.3490478054
Directory /workspace/4.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/4.flash_ctrl_full_mem_access.4215664188
Short name T97
Test name
Test status
Simulation time 575637444200 ps
CPU time 2606.98 seconds
Started Mar 24 02:19:52 PM PDT 24
Finished Mar 24 03:03:20 PM PDT 24
Peak memory 264688 kb
Host smart-36530d8d-3f96-45c5-98f5-95e560afc291
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215664188 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_c
trl_full_mem_access.4215664188
Directory /workspace/4.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_ctrl_arb.3310939793
Short name T157
Test name
Test status
Simulation time 229981059100 ps
CPU time 2692.19 seconds
Started Mar 24 02:19:47 PM PDT 24
Finished Mar 24 03:04:40 PM PDT 24
Peak memory 264864 kb
Host smart-671f8090-9520-4a57-a41c-835d959513e5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310939793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 4.flash_ctrl_host_ctrl_arb.3310939793
Directory /workspace/4.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_dir_rd.566040478
Short name T283
Test name
Test status
Simulation time 109486100 ps
CPU time 124.17 seconds
Started Mar 24 02:19:39 PM PDT 24
Finished Mar 24 02:21:43 PM PDT 24
Peak memory 262324 kb
Host smart-4b344bd8-cb11-41ee-9194-c2d8cee33069
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=566040478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.566040478
Directory /workspace/4.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.1497156723
Short name T625
Test name
Test status
Simulation time 10011826600 ps
CPU time 140.79 seconds
Started Mar 24 02:20:45 PM PDT 24
Finished Mar 24 02:23:07 PM PDT 24
Peak memory 372924 kb
Host smart-72179e7c-7d04-4b5f-a71e-b5b57685bca3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497156723 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.1497156723
Directory /workspace/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_read_seed_err.1668553456
Short name T654
Test name
Test status
Simulation time 15708600 ps
CPU time 13.28 seconds
Started Mar 24 02:20:41 PM PDT 24
Finished Mar 24 02:20:54 PM PDT 24
Peak memory 258132 kb
Host smart-6c1d9324-07d2-4e0b-ad59-47068a3d9f52
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668553456 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_seed_err.1668553456
Directory /workspace/4.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_rma_reset.1798855320
Short name T155
Test name
Test status
Simulation time 80146701200 ps
CPU time 848.82 seconds
Started Mar 24 02:19:42 PM PDT 24
Finished Mar 24 02:33:51 PM PDT 24
Peak memory 263000 kb
Host smart-b7d60bcd-d8dc-4349-b276-ea429141f6d6
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798855320 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.flash_ctrl_hw_rma_reset.1798855320
Directory /workspace/4.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_sec_otp.4286446194
Short name T501
Test name
Test status
Simulation time 1257832100 ps
CPU time 57.26 seconds
Started Mar 24 02:19:45 PM PDT 24
Finished Mar 24 02:20:42 PM PDT 24
Peak memory 262264 kb
Host smart-f43df78a-bb9a-45da-800c-bb9367fddfbe
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286446194 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_h
w_sec_otp.4286446194
Directory /workspace/4.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd_slow_flash.3764132865
Short name T321
Test name
Test status
Simulation time 18143117000 ps
CPU time 305.14 seconds
Started Mar 24 02:20:22 PM PDT 24
Finished Mar 24 02:25:28 PM PDT 24
Peak memory 284536 kb
Host smart-dc83a820-3c43-4013-8b88-cde39b541d4a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764132865 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd_slow_flash.3764132865
Directory /workspace/4.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr.4142005270
Short name T1011
Test name
Test status
Simulation time 11218475800 ps
CPU time 92.8 seconds
Started Mar 24 02:20:21 PM PDT 24
Finished Mar 24 02:21:54 PM PDT 24
Peak memory 260852 kb
Host smart-673c519d-cba1-4c8a-a5e2-5411405e2456
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142005270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.flash_ctrl_intr_wr.4142005270
Directory /workspace/4.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr_slow_flash.1661154444
Short name T941
Test name
Test status
Simulation time 80056619900 ps
CPU time 311.76 seconds
Started Mar 24 02:20:21 PM PDT 24
Finished Mar 24 02:25:34 PM PDT 24
Peak memory 264976 kb
Host smart-1618a3c9-00d0-4c48-9022-82da7326bd44
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166
1154444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.1661154444
Directory /workspace/4.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_invalid_op.162193037
Short name T404
Test name
Test status
Simulation time 12146934500 ps
CPU time 114.85 seconds
Started Mar 24 02:19:57 PM PDT 24
Finished Mar 24 02:21:52 PM PDT 24
Peak memory 260536 kb
Host smart-cfc75e16-0877-401c-95c5-b20eca9a5ccc
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162193037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.162193037
Directory /workspace/4.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_lcmgr_intg.1836573237
Short name T582
Test name
Test status
Simulation time 25105000 ps
CPU time 13.24 seconds
Started Mar 24 02:20:40 PM PDT 24
Finished Mar 24 02:20:54 PM PDT 24
Peak memory 264892 kb
Host smart-865bb99d-4e40-4c03-969f-e586ae702f9b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836573237 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.flash_ctrl_lcmgr_intg.1836573237
Directory /workspace/4.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/4.flash_ctrl_mid_op_rst.2305988899
Short name T117
Test name
Test status
Simulation time 1300405100 ps
CPU time 76.9 seconds
Started Mar 24 02:19:58 PM PDT 24
Finished Mar 24 02:21:15 PM PDT 24
Peak memory 264744 kb
Host smart-14c60c2b-f02d-4653-9f02-f65665d47813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305988899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.2305988899
Directory /workspace/4.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/4.flash_ctrl_mp_regions.20147506
Short name T811
Test name
Test status
Simulation time 5183664500 ps
CPU time 140.53 seconds
Started Mar 24 02:19:47 PM PDT 24
Finished Mar 24 02:22:08 PM PDT 24
Peak memory 264920 kb
Host smart-412bb391-9192-46cd-bfa0-a119bf3b01bd
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20147506 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.flash_ctrl_mp_regions.20147506
Directory /workspace/4.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/4.flash_ctrl_otp_reset.1325624702
Short name T975
Test name
Test status
Simulation time 140768700 ps
CPU time 111.83 seconds
Started Mar 24 02:19:47 PM PDT 24
Finished Mar 24 02:21:39 PM PDT 24
Peak memory 260748 kb
Host smart-066317fe-2930-4dd7-b831-06ad3e72fe5f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325624702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ot
p_reset.1325624702
Directory /workspace/4.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_ack_consistency.2036270200
Short name T62
Test name
Test status
Simulation time 36674400 ps
CPU time 14.28 seconds
Started Mar 24 02:20:37 PM PDT 24
Finished Mar 24 02:20:51 PM PDT 24
Peak memory 260528 kb
Host smart-4db54fbb-bf4a-4b01-b4b6-8d6a2b247ca1
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2036270200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.2036270200
Directory /workspace/4.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb.3866830629
Short name T679
Test name
Test status
Simulation time 1618064400 ps
CPU time 296.13 seconds
Started Mar 24 02:19:45 PM PDT 24
Finished Mar 24 02:24:41 PM PDT 24
Peak memory 261472 kb
Host smart-f1e1ebfb-5d9a-4d78-a694-bd230129312c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3866830629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.3866830629
Directory /workspace/4.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_prog_reset.1939744601
Short name T17
Test name
Test status
Simulation time 22714700 ps
CPU time 13.54 seconds
Started Mar 24 02:20:21 PM PDT 24
Finished Mar 24 02:20:35 PM PDT 24
Peak memory 264876 kb
Host smart-1b80cde0-59ec-4f80-a3dc-adac3b6a0293
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939744601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_prog_res
et.1939744601
Directory /workspace/4.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_rand_ops.2095739839
Short name T108
Test name
Test status
Simulation time 173899200 ps
CPU time 441.38 seconds
Started Mar 24 02:19:41 PM PDT 24
Finished Mar 24 02:27:02 PM PDT 24
Peak memory 281180 kb
Host smart-efa43183-f7fd-4f8b-95bb-41a0e5617e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095739839 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.2095739839
Directory /workspace/4.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/4.flash_ctrl_rd_buff_evict.876167693
Short name T1055
Test name
Test status
Simulation time 80412500 ps
CPU time 101.62 seconds
Started Mar 24 02:19:38 PM PDT 24
Finished Mar 24 02:21:20 PM PDT 24
Peak memory 264708 kb
Host smart-987d758b-c43c-4092-a12f-10563211a543
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=876167693 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.876167693
Directory /workspace/4.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_re_evict.4070450913
Short name T708
Test name
Test status
Simulation time 45497000 ps
CPU time 33.38 seconds
Started Mar 24 02:20:28 PM PDT 24
Finished Mar 24 02:21:01 PM PDT 24
Peak memory 273272 kb
Host smart-ffe84e61-ef56-4cc1-a954-6db26b67fe61
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070450913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_re_evict.4070450913
Directory /workspace/4.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.1213312798
Short name T167
Test name
Test status
Simulation time 33824200 ps
CPU time 20.91 seconds
Started Mar 24 02:20:12 PM PDT 24
Finished Mar 24 02:20:33 PM PDT 24
Peak memory 265056 kb
Host smart-c12881f5-cacb-41e7-b9f0-77da90bf255f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213312798 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_derr.1213312798
Directory /workspace/4.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_serr.3622976509
Short name T443
Test name
Test status
Simulation time 25748500 ps
CPU time 22.71 seconds
Started Mar 24 02:20:02 PM PDT 24
Finished Mar 24 02:20:25 PM PDT 24
Peak memory 264544 kb
Host smart-c8c58b28-ce68-487e-a695-d19fdf60861a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622976509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fl
ash_ctrl_read_word_sweep_serr.3622976509
Directory /workspace/4.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro.1497340741
Short name T856
Test name
Test status
Simulation time 2510435300 ps
CPU time 124.32 seconds
Started Mar 24 02:20:02 PM PDT 24
Finished Mar 24 02:22:07 PM PDT 24
Peak memory 280804 kb
Host smart-cc8a5409-5cbe-49f4-8363-97347c2e4d4a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497340741 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.flash_ctrl_ro.1497340741
Directory /workspace/4.flash_ctrl_ro/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw.3467551422
Short name T643
Test name
Test status
Simulation time 27406477100 ps
CPU time 722.95 seconds
Started Mar 24 02:20:03 PM PDT 24
Finished Mar 24 02:32:07 PM PDT 24
Peak memory 314404 kb
Host smart-86c91155-77e7-4e49-9d0b-a817a2ad7e94
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467551422 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ct
rl_rw.3467551422
Directory /workspace/4.flash_ctrl_rw/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict_all_en.1667213368
Short name T990
Test name
Test status
Simulation time 29465300 ps
CPU time 30.77 seconds
Started Mar 24 02:20:21 PM PDT 24
Finished Mar 24 02:20:53 PM PDT 24
Peak memory 273320 kb
Host smart-bfc1e85e-87e0-4797-b145-7721f4f98afa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667213368 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict_all_en.1667213368
Directory /workspace/4.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_cm.4204422653
Short name T13
Test name
Test status
Simulation time 1973381700 ps
CPU time 4878.46 seconds
Started Mar 24 02:20:31 PM PDT 24
Finished Mar 24 03:41:50 PM PDT 24
Peak memory 286392 kb
Host smart-f92d381e-0a21-4d22-a578-23c35b7fce1a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204422653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.4204422653
Directory /workspace/4.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_info_access.2725433514
Short name T497
Test name
Test status
Simulation time 1957632200 ps
CPU time 72.83 seconds
Started Mar 24 02:20:31 PM PDT 24
Finished Mar 24 02:21:44 PM PDT 24
Peak memory 264368 kb
Host smart-c26f152c-9b8b-49e6-8bbe-f5746788bded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725433514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.2725433514
Directory /workspace/4.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_address.3944231556
Short name T102
Test name
Test status
Simulation time 4330177600 ps
CPU time 81.38 seconds
Started Mar 24 02:20:12 PM PDT 24
Finished Mar 24 02:21:34 PM PDT 24
Peak memory 265088 kb
Host smart-806c96aa-f38e-4e1f-926d-b120b66cbc02
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944231556 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_serr_address.3944231556
Directory /workspace/4.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke.4149652883
Short name T373
Test name
Test status
Simulation time 77948600 ps
CPU time 168.37 seconds
Started Mar 24 02:19:29 PM PDT 24
Finished Mar 24 02:22:17 PM PDT 24
Peak memory 277968 kb
Host smart-b79ef415-fcea-4491-ba44-388c1297cc54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149652883 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.4149652883
Directory /workspace/4.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke_hw.395014583
Short name T771
Test name
Test status
Simulation time 66823500 ps
CPU time 23.48 seconds
Started Mar 24 02:19:38 PM PDT 24
Finished Mar 24 02:20:01 PM PDT 24
Peak memory 258640 kb
Host smart-832e43ff-f5b9-4a9c-ba1e-5ac05e41c5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395014583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.395014583
Directory /workspace/4.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/4.flash_ctrl_stress_all.1708115459
Short name T987
Test name
Test status
Simulation time 7750366300 ps
CPU time 1161.12 seconds
Started Mar 24 02:20:36 PM PDT 24
Finished Mar 24 02:39:57 PM PDT 24
Peak memory 284816 kb
Host smart-8e8bc06c-aa7d-4c39-9dc5-0a366272b7b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708115459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stres
s_all.1708115459
Directory /workspace/4.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.flash_ctrl_sw_op.2599879450
Short name T430
Test name
Test status
Simulation time 30817500 ps
CPU time 26.27 seconds
Started Mar 24 02:19:41 PM PDT 24
Finished Mar 24 02:20:07 PM PDT 24
Peak memory 261224 kb
Host smart-32476dcc-7e37-4a99-ba21-7b7fa94d419e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599879450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.2599879450
Directory /workspace/4.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_wo.3185328289
Short name T531
Test name
Test status
Simulation time 2879675100 ps
CPU time 240.21 seconds
Started Mar 24 02:19:58 PM PDT 24
Finished Mar 24 02:23:59 PM PDT 24
Peak memory 258852 kb
Host smart-128f189b-cc8c-4dd4-8ae2-7dc05ef89b5b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185328289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.flash_ctrl_wo.3185328289
Directory /workspace/4.flash_ctrl_wo/latest

Test location /workspace/coverage/default/40.flash_ctrl_alert_test.1312182355
Short name T534
Test name
Test status
Simulation time 95816400 ps
CPU time 13.63 seconds
Started Mar 24 02:30:10 PM PDT 24
Finished Mar 24 02:30:24 PM PDT 24
Peak memory 257892 kb
Host smart-4695e03e-756a-4334-9fbb-c598f9002bb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312182355 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test.
1312182355
Directory /workspace/40.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.flash_ctrl_connect.322531819
Short name T421
Test name
Test status
Simulation time 49316500 ps
CPU time 15.8 seconds
Started Mar 24 02:30:05 PM PDT 24
Finished Mar 24 02:30:21 PM PDT 24
Peak memory 275412 kb
Host smart-16529e80-68c9-4b0f-996a-8e8e0d40500a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322531819 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.322531819
Directory /workspace/40.flash_ctrl_connect/latest

Test location /workspace/coverage/default/40.flash_ctrl_disable.2375995999
Short name T91
Test name
Test status
Simulation time 35080800 ps
CPU time 22.09 seconds
Started Mar 24 02:30:05 PM PDT 24
Finished Mar 24 02:30:28 PM PDT 24
Peak memory 265084 kb
Host smart-ff7b45e9-0d98-42c5-9ccb-80d75497d19f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375995999 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.flash_ctrl_disable.2375995999
Directory /workspace/40.flash_ctrl_disable/latest

Test location /workspace/coverage/default/40.flash_ctrl_hw_sec_otp.1868246117
Short name T519
Test name
Test status
Simulation time 2830946100 ps
CPU time 107.75 seconds
Started Mar 24 02:30:07 PM PDT 24
Finished Mar 24 02:31:56 PM PDT 24
Peak memory 262300 kb
Host smart-af01d94f-863f-4da5-8833-b960074832c4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868246117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_
hw_sec_otp.1868246117
Directory /workspace/40.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/40.flash_ctrl_otp_reset.100445901
Short name T1031
Test name
Test status
Simulation time 160262300 ps
CPU time 131.05 seconds
Started Mar 24 02:30:06 PM PDT 24
Finished Mar 24 02:32:17 PM PDT 24
Peak memory 260852 kb
Host smart-c5bb18b6-192b-4c98-909f-99eb7e126e07
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100445901 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_ot
p_reset.100445901
Directory /workspace/40.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/40.flash_ctrl_sec_info_access.2282368492
Short name T393
Test name
Test status
Simulation time 1943047700 ps
CPU time 72.02 seconds
Started Mar 24 02:30:07 PM PDT 24
Finished Mar 24 02:31:19 PM PDT 24
Peak memory 263020 kb
Host smart-3b0c69f3-8036-446a-ad61-49a35ed68174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282368492 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.2282368492
Directory /workspace/40.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/40.flash_ctrl_smoke.728501563
Short name T835
Test name
Test status
Simulation time 30127800 ps
CPU time 124.32 seconds
Started Mar 24 02:30:05 PM PDT 24
Finished Mar 24 02:32:10 PM PDT 24
Peak memory 275468 kb
Host smart-ad4bfe01-a900-454a-98c6-427c9da3d58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728501563 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.728501563
Directory /workspace/40.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/41.flash_ctrl_alert_test.3731760525
Short name T979
Test name
Test status
Simulation time 34245400 ps
CPU time 13.76 seconds
Started Mar 24 02:30:16 PM PDT 24
Finished Mar 24 02:30:30 PM PDT 24
Peak memory 257988 kb
Host smart-219cc96a-2194-49d6-9110-3f8c3e401467
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731760525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test.
3731760525
Directory /workspace/41.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.flash_ctrl_connect.2740653646
Short name T509
Test name
Test status
Simulation time 26605400 ps
CPU time 15.85 seconds
Started Mar 24 02:30:17 PM PDT 24
Finished Mar 24 02:30:33 PM PDT 24
Peak memory 275608 kb
Host smart-a2722342-5fc9-4909-98b7-c15dbda39ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740653646 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.2740653646
Directory /workspace/41.flash_ctrl_connect/latest

Test location /workspace/coverage/default/41.flash_ctrl_disable.2433668276
Short name T1008
Test name
Test status
Simulation time 10250600 ps
CPU time 22.08 seconds
Started Mar 24 02:30:17 PM PDT 24
Finished Mar 24 02:30:39 PM PDT 24
Peak memory 265136 kb
Host smart-4fd1ac25-103b-4552-96dc-0d2028f9b9f2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433668276 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.flash_ctrl_disable.2433668276
Directory /workspace/41.flash_ctrl_disable/latest

Test location /workspace/coverage/default/41.flash_ctrl_hw_sec_otp.302751114
Short name T799
Test name
Test status
Simulation time 1668434600 ps
CPU time 67.83 seconds
Started Mar 24 02:30:11 PM PDT 24
Finished Mar 24 02:31:19 PM PDT 24
Peak memory 262504 kb
Host smart-6144310e-edcf-45c8-a840-b34b1735e076
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302751114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_h
w_sec_otp.302751114
Directory /workspace/41.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/41.flash_ctrl_otp_reset.2076810419
Short name T133
Test name
Test status
Simulation time 36960800 ps
CPU time 131.52 seconds
Started Mar 24 02:30:11 PM PDT 24
Finished Mar 24 02:32:23 PM PDT 24
Peak memory 259628 kb
Host smart-1277d7a4-8108-4a69-82de-f3dff24032bd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076810419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_o
tp_reset.2076810419
Directory /workspace/41.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/41.flash_ctrl_sec_info_access.3963242355
Short name T164
Test name
Test status
Simulation time 19991047200 ps
CPU time 95.14 seconds
Started Mar 24 02:30:16 PM PDT 24
Finished Mar 24 02:31:51 PM PDT 24
Peak memory 262984 kb
Host smart-aff649e9-502b-490c-80a5-07cc69e3cee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963242355 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.3963242355
Directory /workspace/41.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/41.flash_ctrl_smoke.3178454264
Short name T1001
Test name
Test status
Simulation time 33150400 ps
CPU time 73.28 seconds
Started Mar 24 02:30:10 PM PDT 24
Finished Mar 24 02:31:23 PM PDT 24
Peak memory 275808 kb
Host smart-6c352391-4ca1-4946-b392-16ea29633a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178454264 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.3178454264
Directory /workspace/41.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/42.flash_ctrl_alert_test.3363883560
Short name T565
Test name
Test status
Simulation time 97887500 ps
CPU time 13.67 seconds
Started Mar 24 02:30:22 PM PDT 24
Finished Mar 24 02:30:36 PM PDT 24
Peak memory 264824 kb
Host smart-fa9247ed-c972-4e14-ba2a-673e28ef75d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363883560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test.
3363883560
Directory /workspace/42.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.flash_ctrl_connect.2575472229
Short name T514
Test name
Test status
Simulation time 41041900 ps
CPU time 15.92 seconds
Started Mar 24 02:30:26 PM PDT 24
Finished Mar 24 02:30:42 PM PDT 24
Peak memory 275224 kb
Host smart-4ab1ef14-f107-404c-9ef5-518ce8d624d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575472229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.2575472229
Directory /workspace/42.flash_ctrl_connect/latest

Test location /workspace/coverage/default/42.flash_ctrl_disable.2436161767
Short name T900
Test name
Test status
Simulation time 20970700 ps
CPU time 22.8 seconds
Started Mar 24 02:30:19 PM PDT 24
Finished Mar 24 02:30:43 PM PDT 24
Peak memory 264856 kb
Host smart-05c68794-cd1a-48b6-ae87-764c0eac1382
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436161767 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.flash_ctrl_disable.2436161767
Directory /workspace/42.flash_ctrl_disable/latest

Test location /workspace/coverage/default/42.flash_ctrl_hw_sec_otp.374409250
Short name T605
Test name
Test status
Simulation time 42647073800 ps
CPU time 187.18 seconds
Started Mar 24 02:30:15 PM PDT 24
Finished Mar 24 02:33:22 PM PDT 24
Peak memory 262492 kb
Host smart-e3792dd7-043a-4d5e-a676-c779e04cd665
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374409250 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_h
w_sec_otp.374409250
Directory /workspace/42.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/42.flash_ctrl_otp_reset.3053048957
Short name T1036
Test name
Test status
Simulation time 39783900 ps
CPU time 110.08 seconds
Started Mar 24 02:30:20 PM PDT 24
Finished Mar 24 02:32:11 PM PDT 24
Peak memory 260824 kb
Host smart-058b0971-e723-441d-9b5e-cdcb5083034e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053048957 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_o
tp_reset.3053048957
Directory /workspace/42.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/42.flash_ctrl_smoke.1289000372
Short name T529
Test name
Test status
Simulation time 1362768800 ps
CPU time 213.43 seconds
Started Mar 24 02:30:22 PM PDT 24
Finished Mar 24 02:33:55 PM PDT 24
Peak memory 281120 kb
Host smart-ab50a2d3-c774-4964-8ba4-820a336aee73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289000372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.1289000372
Directory /workspace/42.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/43.flash_ctrl_alert_test.120386555
Short name T490
Test name
Test status
Simulation time 99840000 ps
CPU time 13.97 seconds
Started Mar 24 02:30:24 PM PDT 24
Finished Mar 24 02:30:38 PM PDT 24
Peak memory 258764 kb
Host smart-16eefffe-ef71-4db5-84e5-5263a3a3719d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120386555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test.120386555
Directory /workspace/43.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.flash_ctrl_connect.2822460396
Short name T622
Test name
Test status
Simulation time 22045400 ps
CPU time 15.98 seconds
Started Mar 24 02:30:26 PM PDT 24
Finished Mar 24 02:30:42 PM PDT 24
Peak memory 275400 kb
Host smart-e33875bc-6e33-4442-85ab-08030dd45472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822460396 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.2822460396
Directory /workspace/43.flash_ctrl_connect/latest

Test location /workspace/coverage/default/43.flash_ctrl_disable.2167716045
Short name T437
Test name
Test status
Simulation time 17224200 ps
CPU time 22.14 seconds
Started Mar 24 02:30:25 PM PDT 24
Finished Mar 24 02:30:47 PM PDT 24
Peak memory 273252 kb
Host smart-0d2b9331-83a3-464e-bf4c-263a7637cd31
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167716045 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.flash_ctrl_disable.2167716045
Directory /workspace/43.flash_ctrl_disable/latest

Test location /workspace/coverage/default/43.flash_ctrl_hw_sec_otp.4168939077
Short name T689
Test name
Test status
Simulation time 2483130800 ps
CPU time 52.3 seconds
Started Mar 24 02:30:26 PM PDT 24
Finished Mar 24 02:31:19 PM PDT 24
Peak memory 262160 kb
Host smart-9b3b2f84-235f-45a4-b4de-b35eb207990a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168939077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_
hw_sec_otp.4168939077
Directory /workspace/43.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/43.flash_ctrl_otp_reset.1355834483
Short name T563
Test name
Test status
Simulation time 103531900 ps
CPU time 132.54 seconds
Started Mar 24 02:30:24 PM PDT 24
Finished Mar 24 02:32:37 PM PDT 24
Peak memory 263456 kb
Host smart-f5f51253-8391-4291-b0a5-838cd56ce191
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355834483 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_o
tp_reset.1355834483
Directory /workspace/43.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/43.flash_ctrl_sec_info_access.3979679945
Short name T958
Test name
Test status
Simulation time 2083463500 ps
CPU time 67.62 seconds
Started Mar 24 02:30:24 PM PDT 24
Finished Mar 24 02:31:31 PM PDT 24
Peak memory 262412 kb
Host smart-1e3993ff-ab40-4099-bf02-ef8d725fd10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979679945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.3979679945
Directory /workspace/43.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/43.flash_ctrl_smoke.500859659
Short name T612
Test name
Test status
Simulation time 74590200 ps
CPU time 98.91 seconds
Started Mar 24 02:30:20 PM PDT 24
Finished Mar 24 02:32:01 PM PDT 24
Peak memory 275156 kb
Host smart-95fc4457-0448-4930-8556-fa95aaf633ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500859659 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.500859659
Directory /workspace/43.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/44.flash_ctrl_alert_test.194633887
Short name T522
Test name
Test status
Simulation time 103539400 ps
CPU time 13.9 seconds
Started Mar 24 02:30:30 PM PDT 24
Finished Mar 24 02:30:44 PM PDT 24
Peak memory 264768 kb
Host smart-3b82a968-1317-4eb4-9b71-fd01b0c584ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194633887 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.194633887
Directory /workspace/44.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.flash_ctrl_connect.3448142953
Short name T774
Test name
Test status
Simulation time 30041200 ps
CPU time 15.71 seconds
Started Mar 24 02:30:30 PM PDT 24
Finished Mar 24 02:30:45 PM PDT 24
Peak memory 275212 kb
Host smart-b1017889-0304-4495-a895-86ef372564d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448142953 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.3448142953
Directory /workspace/44.flash_ctrl_connect/latest

Test location /workspace/coverage/default/44.flash_ctrl_disable.415555090
Short name T634
Test name
Test status
Simulation time 20690400 ps
CPU time 22.12 seconds
Started Mar 24 02:30:27 PM PDT 24
Finished Mar 24 02:30:50 PM PDT 24
Peak memory 264836 kb
Host smart-603ee334-c6c0-432f-bd23-558030e71fb0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415555090 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.flash_ctrl_disable.415555090
Directory /workspace/44.flash_ctrl_disable/latest

Test location /workspace/coverage/default/44.flash_ctrl_hw_sec_otp.1487444902
Short name T1
Test name
Test status
Simulation time 4992008700 ps
CPU time 135.47 seconds
Started Mar 24 02:30:28 PM PDT 24
Finished Mar 24 02:32:44 PM PDT 24
Peak memory 261760 kb
Host smart-b54b2188-3e34-4be2-b855-667a9976719a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487444902 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_
hw_sec_otp.1487444902
Directory /workspace/44.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/44.flash_ctrl_otp_reset.1521892415
Short name T687
Test name
Test status
Simulation time 70322000 ps
CPU time 132.15 seconds
Started Mar 24 02:30:26 PM PDT 24
Finished Mar 24 02:32:38 PM PDT 24
Peak memory 259312 kb
Host smart-7835353b-fa8a-4af5-bd75-b4d6ff898724
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521892415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_o
tp_reset.1521892415
Directory /workspace/44.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/44.flash_ctrl_sec_info_access.3901536776
Short name T608
Test name
Test status
Simulation time 28023821300 ps
CPU time 92.47 seconds
Started Mar 24 02:30:32 PM PDT 24
Finished Mar 24 02:32:04 PM PDT 24
Peak memory 262384 kb
Host smart-4c9f40e8-fbd4-4aa7-9a31-4e47407527b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901536776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.3901536776
Directory /workspace/44.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/44.flash_ctrl_smoke.2114699267
Short name T962
Test name
Test status
Simulation time 97667800 ps
CPU time 122.75 seconds
Started Mar 24 02:30:24 PM PDT 24
Finished Mar 24 02:32:27 PM PDT 24
Peak memory 277300 kb
Host smart-854e0400-4308-460b-8d1d-2ae6c9c5c37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114699267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.2114699267
Directory /workspace/44.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/45.flash_ctrl_alert_test.1735090805
Short name T818
Test name
Test status
Simulation time 172038400 ps
CPU time 14.47 seconds
Started Mar 24 02:30:29 PM PDT 24
Finished Mar 24 02:30:44 PM PDT 24
Peak memory 258248 kb
Host smart-b853ea2c-acf1-4fa7-8bcf-413d3b9ed5ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735090805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.
1735090805
Directory /workspace/45.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.flash_ctrl_connect.1871161622
Short name T833
Test name
Test status
Simulation time 20931300 ps
CPU time 15.9 seconds
Started Mar 24 02:30:29 PM PDT 24
Finished Mar 24 02:30:45 PM PDT 24
Peak memory 275208 kb
Host smart-b3fde6d3-61dc-42af-b9d8-1e252e3f3097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871161622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.1871161622
Directory /workspace/45.flash_ctrl_connect/latest

Test location /workspace/coverage/default/45.flash_ctrl_disable.3370353351
Short name T89
Test name
Test status
Simulation time 10695600 ps
CPU time 21.88 seconds
Started Mar 24 02:30:30 PM PDT 24
Finished Mar 24 02:30:52 PM PDT 24
Peak memory 273168 kb
Host smart-1bd9c526-4253-47ba-9105-6bf78fdeec93
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370353351 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.flash_ctrl_disable.3370353351
Directory /workspace/45.flash_ctrl_disable/latest

Test location /workspace/coverage/default/45.flash_ctrl_hw_sec_otp.2346337864
Short name T556
Test name
Test status
Simulation time 3047376700 ps
CPU time 196.54 seconds
Started Mar 24 02:30:31 PM PDT 24
Finished Mar 24 02:33:48 PM PDT 24
Peak memory 262520 kb
Host smart-9059bceb-bdcd-4960-88fc-2ccc931be3a9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346337864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_
hw_sec_otp.2346337864
Directory /workspace/45.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/45.flash_ctrl_otp_reset.1086121509
Short name T3
Test name
Test status
Simulation time 49623900 ps
CPU time 110.77 seconds
Started Mar 24 02:30:30 PM PDT 24
Finished Mar 24 02:32:21 PM PDT 24
Peak memory 260864 kb
Host smart-12ccba6c-322e-4add-8c17-de5217a7f4fc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086121509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_o
tp_reset.1086121509
Directory /workspace/45.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/45.flash_ctrl_sec_info_access.2078566023
Short name T387
Test name
Test status
Simulation time 7795995000 ps
CPU time 64.72 seconds
Started Mar 24 02:30:30 PM PDT 24
Finished Mar 24 02:31:35 PM PDT 24
Peak memory 262964 kb
Host smart-9cebefde-1d02-49fc-b40c-ceb274817676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078566023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.2078566023
Directory /workspace/45.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/45.flash_ctrl_smoke.4023276165
Short name T600
Test name
Test status
Simulation time 28873700 ps
CPU time 172.51 seconds
Started Mar 24 02:30:30 PM PDT 24
Finished Mar 24 02:33:23 PM PDT 24
Peak memory 279084 kb
Host smart-ab154e37-bcc7-4494-8f7f-653e8cd49e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023276165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.4023276165
Directory /workspace/45.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/46.flash_ctrl_alert_test.1834737119
Short name T648
Test name
Test status
Simulation time 26275400 ps
CPU time 13.31 seconds
Started Mar 24 02:30:34 PM PDT 24
Finished Mar 24 02:30:47 PM PDT 24
Peak memory 264848 kb
Host smart-a8f5f7c2-67a4-4207-8291-7189d147a48a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834737119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.
1834737119
Directory /workspace/46.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.flash_ctrl_connect.2555613394
Short name T920
Test name
Test status
Simulation time 21095100 ps
CPU time 15.56 seconds
Started Mar 24 02:30:40 PM PDT 24
Finished Mar 24 02:30:56 PM PDT 24
Peak memory 275184 kb
Host smart-d9e13b77-d9ba-40bd-95b5-95791561f05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555613394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.2555613394
Directory /workspace/46.flash_ctrl_connect/latest

Test location /workspace/coverage/default/46.flash_ctrl_hw_sec_otp.157635293
Short name T685
Test name
Test status
Simulation time 3067080000 ps
CPU time 62.22 seconds
Started Mar 24 02:30:34 PM PDT 24
Finished Mar 24 02:31:37 PM PDT 24
Peak memory 262452 kb
Host smart-cef5e3e7-d623-4211-b261-8fefcbe6ff53
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157635293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_h
w_sec_otp.157635293
Directory /workspace/46.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/46.flash_ctrl_otp_reset.2976067356
Short name T376
Test name
Test status
Simulation time 56174800 ps
CPU time 109.91 seconds
Started Mar 24 02:30:37 PM PDT 24
Finished Mar 24 02:32:27 PM PDT 24
Peak memory 260708 kb
Host smart-ee3250a0-fb35-4514-9d3a-9d220f5b8536
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976067356 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_o
tp_reset.2976067356
Directory /workspace/46.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/46.flash_ctrl_sec_info_access.1089442338
Short name T709
Test name
Test status
Simulation time 16001123200 ps
CPU time 67.3 seconds
Started Mar 24 02:30:34 PM PDT 24
Finished Mar 24 02:31:41 PM PDT 24
Peak memory 263532 kb
Host smart-15fdb231-9cd6-4622-b56e-3bd90cc51545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089442338 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.1089442338
Directory /workspace/46.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/46.flash_ctrl_smoke.3102966879
Short name T54
Test name
Test status
Simulation time 43870800 ps
CPU time 99.87 seconds
Started Mar 24 02:30:35 PM PDT 24
Finished Mar 24 02:32:15 PM PDT 24
Peak memory 275228 kb
Host smart-70279d9a-b078-4af1-a7cb-b76cabfb6684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102966879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.3102966879
Directory /workspace/46.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/47.flash_ctrl_alert_test.3599911431
Short name T468
Test name
Test status
Simulation time 156877100 ps
CPU time 13.63 seconds
Started Mar 24 02:30:39 PM PDT 24
Finished Mar 24 02:30:53 PM PDT 24
Peak memory 257972 kb
Host smart-c5f3595c-a793-4834-9e2c-df72d30bbda3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599911431 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test.
3599911431
Directory /workspace/47.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.flash_ctrl_connect.769388057
Short name T745
Test name
Test status
Simulation time 13259800 ps
CPU time 15.31 seconds
Started Mar 24 02:30:42 PM PDT 24
Finished Mar 24 02:30:58 PM PDT 24
Peak memory 275444 kb
Host smart-64140760-6036-407e-94e4-4d4af743754d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769388057 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.769388057
Directory /workspace/47.flash_ctrl_connect/latest

Test location /workspace/coverage/default/47.flash_ctrl_hw_sec_otp.2739000227
Short name T953
Test name
Test status
Simulation time 57413049600 ps
CPU time 133.72 seconds
Started Mar 24 02:30:42 PM PDT 24
Finished Mar 24 02:32:56 PM PDT 24
Peak memory 262328 kb
Host smart-d431c866-ca12-47bd-8db5-c880db848ddf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739000227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_
hw_sec_otp.2739000227
Directory /workspace/47.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/47.flash_ctrl_otp_reset.2886767160
Short name T649
Test name
Test status
Simulation time 75280000 ps
CPU time 132.71 seconds
Started Mar 24 02:30:47 PM PDT 24
Finished Mar 24 02:32:59 PM PDT 24
Peak memory 259648 kb
Host smart-cf265045-8032-47c7-ad19-f5419e2cf301
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886767160 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_o
tp_reset.2886767160
Directory /workspace/47.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/47.flash_ctrl_sec_info_access.2344128905
Short name T395
Test name
Test status
Simulation time 21959309900 ps
CPU time 86.39 seconds
Started Mar 24 02:30:39 PM PDT 24
Finished Mar 24 02:32:05 PM PDT 24
Peak memory 263032 kb
Host smart-5eb7a49a-78dd-424d-a4ac-4ed77622e3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344128905 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.2344128905
Directory /workspace/47.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/47.flash_ctrl_smoke.2324552227
Short name T372
Test name
Test status
Simulation time 53999700 ps
CPU time 171.26 seconds
Started Mar 24 02:30:35 PM PDT 24
Finished Mar 24 02:33:27 PM PDT 24
Peak memory 280100 kb
Host smart-0f9dab9e-0306-475d-8b0d-c5fead3ef0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324552227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.2324552227
Directory /workspace/47.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/48.flash_ctrl_alert_test.1772549082
Short name T637
Test name
Test status
Simulation time 37600200 ps
CPU time 13.75 seconds
Started Mar 24 02:30:44 PM PDT 24
Finished Mar 24 02:30:58 PM PDT 24
Peak memory 264360 kb
Host smart-e1df59a1-ba36-480a-b8c2-a18ff2f24e88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772549082 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.
1772549082
Directory /workspace/48.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.flash_ctrl_connect.3578483475
Short name T822
Test name
Test status
Simulation time 52506200 ps
CPU time 15.86 seconds
Started Mar 24 02:30:39 PM PDT 24
Finished Mar 24 02:30:55 PM PDT 24
Peak memory 275524 kb
Host smart-4481090c-6439-4402-8933-7615fa22155e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578483475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.3578483475
Directory /workspace/48.flash_ctrl_connect/latest

Test location /workspace/coverage/default/48.flash_ctrl_disable.1761227199
Short name T581
Test name
Test status
Simulation time 16152000 ps
CPU time 22.02 seconds
Started Mar 24 02:30:42 PM PDT 24
Finished Mar 24 02:31:04 PM PDT 24
Peak memory 265032 kb
Host smart-a670db03-4d7a-4f71-bbc0-3c90e5012bdb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761227199 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.flash_ctrl_disable.1761227199
Directory /workspace/48.flash_ctrl_disable/latest

Test location /workspace/coverage/default/48.flash_ctrl_hw_sec_otp.3804400563
Short name T653
Test name
Test status
Simulation time 2136777600 ps
CPU time 119.4 seconds
Started Mar 24 02:30:39 PM PDT 24
Finished Mar 24 02:32:39 PM PDT 24
Peak memory 262312 kb
Host smart-ea42773d-2ced-47d9-8f33-75fa8253724b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804400563 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_
hw_sec_otp.3804400563
Directory /workspace/48.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/48.flash_ctrl_otp_reset.3234445780
Short name T670
Test name
Test status
Simulation time 140277100 ps
CPU time 133.7 seconds
Started Mar 24 02:30:42 PM PDT 24
Finished Mar 24 02:32:56 PM PDT 24
Peak memory 259572 kb
Host smart-07d68932-c627-404e-aead-63808dd32806
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234445780 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_o
tp_reset.3234445780
Directory /workspace/48.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/48.flash_ctrl_sec_info_access.2777979418
Short name T965
Test name
Test status
Simulation time 5502571800 ps
CPU time 61.16 seconds
Started Mar 24 02:30:42 PM PDT 24
Finished Mar 24 02:31:43 PM PDT 24
Peak memory 264044 kb
Host smart-4926dffa-bb65-43eb-8691-0ecf23cd3c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777979418 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.2777979418
Directory /workspace/48.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/48.flash_ctrl_smoke.3997262133
Short name T460
Test name
Test status
Simulation time 22173500 ps
CPU time 146.41 seconds
Started Mar 24 02:30:38 PM PDT 24
Finished Mar 24 02:33:04 PM PDT 24
Peak memory 277016 kb
Host smart-4da7882f-6b9a-4889-8023-1d2ab4d365e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997262133 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.3997262133
Directory /workspace/48.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/49.flash_ctrl_alert_test.481549081
Short name T850
Test name
Test status
Simulation time 59291100 ps
CPU time 13.67 seconds
Started Mar 24 02:30:51 PM PDT 24
Finished Mar 24 02:31:04 PM PDT 24
Peak memory 258024 kb
Host smart-ee54c45f-89fa-45b2-8740-104f7ae2d3fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481549081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.481549081
Directory /workspace/49.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.flash_ctrl_disable.2650049419
Short name T978
Test name
Test status
Simulation time 27814900 ps
CPU time 22.11 seconds
Started Mar 24 02:30:51 PM PDT 24
Finished Mar 24 02:31:14 PM PDT 24
Peak memory 264988 kb
Host smart-01c3fb2b-c842-4594-8c08-d4ff2626626d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650049419 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.flash_ctrl_disable.2650049419
Directory /workspace/49.flash_ctrl_disable/latest

Test location /workspace/coverage/default/49.flash_ctrl_hw_sec_otp.800712738
Short name T583
Test name
Test status
Simulation time 43373673500 ps
CPU time 209.43 seconds
Started Mar 24 02:30:45 PM PDT 24
Finished Mar 24 02:34:15 PM PDT 24
Peak memory 262456 kb
Host smart-5faf5620-91a3-4223-81c7-c3a98b9446b9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800712738 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_h
w_sec_otp.800712738
Directory /workspace/49.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/49.flash_ctrl_otp_reset.581799161
Short name T144
Test name
Test status
Simulation time 137652000 ps
CPU time 134.24 seconds
Started Mar 24 02:30:47 PM PDT 24
Finished Mar 24 02:33:02 PM PDT 24
Peak memory 263828 kb
Host smart-a09d0788-6374-4a94-b452-e9d7b476c0c2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581799161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_ot
p_reset.581799161
Directory /workspace/49.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/49.flash_ctrl_sec_info_access.441532361
Short name T417
Test name
Test status
Simulation time 1755189200 ps
CPU time 58.11 seconds
Started Mar 24 02:30:50 PM PDT 24
Finished Mar 24 02:31:48 PM PDT 24
Peak memory 262840 kb
Host smart-a0919145-37ca-4030-9e95-5679f2721952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441532361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.441532361
Directory /workspace/49.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/49.flash_ctrl_smoke.712178919
Short name T682
Test name
Test status
Simulation time 382533100 ps
CPU time 73.99 seconds
Started Mar 24 02:30:44 PM PDT 24
Finished Mar 24 02:31:58 PM PDT 24
Peak memory 274584 kb
Host smart-13862e18-f7d9-4bb3-b8f4-912c171c2bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712178919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.712178919
Directory /workspace/49.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_alert_test.401100592
Short name T528
Test name
Test status
Simulation time 64243000 ps
CPU time 13.65 seconds
Started Mar 24 02:21:31 PM PDT 24
Finished Mar 24 02:21:45 PM PDT 24
Peak memory 258108 kb
Host smart-1a38598f-f47f-4786-8fca-298b8196f0a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401100592 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.401100592
Directory /workspace/5.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.flash_ctrl_connect.1180686787
Short name T368
Test name
Test status
Simulation time 28964700 ps
CPU time 15.75 seconds
Started Mar 24 02:21:29 PM PDT 24
Finished Mar 24 02:21:45 PM PDT 24
Peak memory 275084 kb
Host smart-17b88ed6-edd0-47d7-9b13-1cab8e5a867d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180686787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.1180686787
Directory /workspace/5.flash_ctrl_connect/latest

Test location /workspace/coverage/default/5.flash_ctrl_disable.2683159278
Short name T698
Test name
Test status
Simulation time 17406600 ps
CPU time 21.35 seconds
Started Mar 24 02:21:30 PM PDT 24
Finished Mar 24 02:21:51 PM PDT 24
Peak memory 280284 kb
Host smart-17482b53-a44b-4e88-9eb6-db2595e4466c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683159278 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_disable.2683159278
Directory /workspace/5.flash_ctrl_disable/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_mp.4273113960
Short name T971
Test name
Test status
Simulation time 50018773900 ps
CPU time 2255.35 seconds
Started Mar 24 02:21:04 PM PDT 24
Finished Mar 24 02:58:40 PM PDT 24
Peak memory 264888 kb
Host smart-bed720e4-9bef-4d45-86d7-d2fe04a63d2d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273113960 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_err
or_mp.4273113960
Directory /workspace/5.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_prog_win.1136262625
Short name T300
Test name
Test status
Simulation time 6422002200 ps
CPU time 824.73 seconds
Started Mar 24 02:21:05 PM PDT 24
Finished Mar 24 02:34:50 PM PDT 24
Peak memory 264928 kb
Host smart-1e1eb0cc-5ea4-44fe-b6f6-e3212e5fa5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136262625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.1136262625
Directory /workspace/5.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/5.flash_ctrl_fetch_code.1086324283
Short name T716
Test name
Test status
Simulation time 439527600 ps
CPU time 20.38 seconds
Started Mar 24 02:21:03 PM PDT 24
Finished Mar 24 02:21:24 PM PDT 24
Peak memory 264796 kb
Host smart-edfd519f-1057-4e2d-bf6e-60aaeaa5fa12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086324283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetch_code.1086324283
Directory /workspace/5.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.572188174
Short name T161
Test name
Test status
Simulation time 10034059900 ps
CPU time 59.66 seconds
Started Mar 24 02:21:31 PM PDT 24
Finished Mar 24 02:22:31 PM PDT 24
Peak memory 272800 kb
Host smart-502ed5b3-be65-4bab-94f2-66a7d217e99e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572188174 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.572188174
Directory /workspace/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_read_seed_err.2017527994
Short name T470
Test name
Test status
Simulation time 15522600 ps
CPU time 13.92 seconds
Started Mar 24 02:21:31 PM PDT 24
Finished Mar 24 02:21:45 PM PDT 24
Peak memory 265144 kb
Host smart-6ad51558-3e1d-4cf2-ba3f-c19900a31e08
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017527994 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_seed_err.2017527994
Directory /workspace/5.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_rma_reset.204373349
Short name T138
Test name
Test status
Simulation time 40123207800 ps
CPU time 806.34 seconds
Started Mar 24 02:20:58 PM PDT 24
Finished Mar 24 02:34:24 PM PDT 24
Peak memory 263240 kb
Host smart-46ebf9df-482f-4687-a53f-86332514dbc8
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204373349 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.flash_ctrl_hw_rma_reset.204373349
Directory /workspace/5.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_sec_otp.3168057907
Short name T545
Test name
Test status
Simulation time 6610947000 ps
CPU time 62.16 seconds
Started Mar 24 02:20:58 PM PDT 24
Finished Mar 24 02:22:00 PM PDT 24
Peak memory 262372 kb
Host smart-396a93c9-e3c2-40ac-bc0b-c8455c81dc39
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168057907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_h
w_sec_otp.3168057907
Directory /workspace/5.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr.2147476060
Short name T863
Test name
Test status
Simulation time 14075999500 ps
CPU time 100.21 seconds
Started Mar 24 02:21:21 PM PDT 24
Finished Mar 24 02:23:01 PM PDT 24
Peak memory 260500 kb
Host smart-fbe2d1b3-0515-4f90-b4b5-2de933a0cee9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147476060 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.flash_ctrl_intr_wr.2147476060
Directory /workspace/5.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr_slow_flash.3713406736
Short name T451
Test name
Test status
Simulation time 440152890100 ps
CPU time 409.33 seconds
Started Mar 24 02:21:25 PM PDT 24
Finished Mar 24 02:28:15 PM PDT 24
Peak memory 261256 kb
Host smart-19b55d00-dbc0-43eb-b290-39e10661b34e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371
3406736 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.3713406736
Directory /workspace/5.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_invalid_op.3499666627
Short name T855
Test name
Test status
Simulation time 2089118200 ps
CPU time 74.13 seconds
Started Mar 24 02:21:04 PM PDT 24
Finished Mar 24 02:22:19 PM PDT 24
Peak memory 260268 kb
Host smart-c6e86ff7-a1c9-461c-b78a-80ea49d8e3e6
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499666627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.3499666627
Directory /workspace/5.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/5.flash_ctrl_lcmgr_intg.1599783753
Short name T594
Test name
Test status
Simulation time 15121700 ps
CPU time 13.17 seconds
Started Mar 24 02:21:29 PM PDT 24
Finished Mar 24 02:21:43 PM PDT 24
Peak memory 264912 kb
Host smart-e4b107f4-e37b-4f61-9a97-090c70dea0da
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599783753 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.flash_ctrl_lcmgr_intg.1599783753
Directory /workspace/5.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/5.flash_ctrl_mp_regions.3133043049
Short name T1017
Test name
Test status
Simulation time 79366018100 ps
CPU time 470.26 seconds
Started Mar 24 02:21:04 PM PDT 24
Finished Mar 24 02:28:55 PM PDT 24
Peak memory 272960 kb
Host smart-f2248dba-7fd0-487f-a84b-8b3e32c56d1e
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133043049 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 5.flash_ctrl_mp_regions.3133043049
Directory /workspace/5.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/5.flash_ctrl_otp_reset.1824135804
Short name T450
Test name
Test status
Simulation time 41054000 ps
CPU time 133.42 seconds
Started Mar 24 02:21:00 PM PDT 24
Finished Mar 24 02:23:14 PM PDT 24
Peak memory 260704 kb
Host smart-4993bad9-e82d-418b-8b61-b6302bcdd205
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824135804 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ot
p_reset.1824135804
Directory /workspace/5.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_phy_arb.2682426840
Short name T635
Test name
Test status
Simulation time 1425114200 ps
CPU time 572.05 seconds
Started Mar 24 02:20:57 PM PDT 24
Finished Mar 24 02:30:30 PM PDT 24
Peak memory 261304 kb
Host smart-239eb344-5997-4e0c-8672-3842766048bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2682426840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.2682426840
Directory /workspace/5.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/5.flash_ctrl_prog_reset.1183833681
Short name T639
Test name
Test status
Simulation time 32183700 ps
CPU time 13.18 seconds
Started Mar 24 02:21:28 PM PDT 24
Finished Mar 24 02:21:41 PM PDT 24
Peak memory 260320 kb
Host smart-a43d604a-f58b-4967-9ea7-6551aa17b1f1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183833681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_prog_res
et.1183833681
Directory /workspace/5.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_rand_ops.1078939893
Short name T553
Test name
Test status
Simulation time 163673800 ps
CPU time 219.44 seconds
Started Mar 24 02:20:53 PM PDT 24
Finished Mar 24 02:24:33 PM PDT 24
Peak memory 277904 kb
Host smart-eb44961d-916b-4bb6-9445-5dbb15e41618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078939893 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.1078939893
Directory /workspace/5.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/5.flash_ctrl_re_evict.1894525039
Short name T876
Test name
Test status
Simulation time 72299000 ps
CPU time 33.66 seconds
Started Mar 24 02:21:28 PM PDT 24
Finished Mar 24 02:22:01 PM PDT 24
Peak memory 277892 kb
Host smart-70b62658-5af6-4103-8fa6-b1670fa2d7d4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894525039 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla
sh_ctrl_re_evict.1894525039
Directory /workspace/5.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro.1389689045
Short name T1015
Test name
Test status
Simulation time 518692100 ps
CPU time 125.29 seconds
Started Mar 24 02:21:11 PM PDT 24
Finished Mar 24 02:23:16 PM PDT 24
Peak memory 280696 kb
Host smart-dc49e0d9-61b2-4b96-b3e8-4c92d9b8d987
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389689045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.flash_ctrl_ro.1389689045
Directory /workspace/5.flash_ctrl_ro/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict.1683340862
Short name T211
Test name
Test status
Simulation time 35697700 ps
CPU time 28.78 seconds
Started Mar 24 02:21:25 PM PDT 24
Finished Mar 24 02:21:54 PM PDT 24
Peak memory 275324 kb
Host smart-c6eb602c-af9a-414b-90fc-6e703bfe5579
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683340862 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla
sh_ctrl_rw_evict.1683340862
Directory /workspace/5.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict_all_en.865186837
Short name T523
Test name
Test status
Simulation time 140594600 ps
CPU time 28.05 seconds
Started Mar 24 02:21:29 PM PDT 24
Finished Mar 24 02:21:57 PM PDT 24
Peak memory 273596 kb
Host smart-20463dd1-8d3e-4111-ad68-b091d06bc504
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865186837 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict_all_en.865186837
Directory /workspace/5.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/5.flash_ctrl_sec_info_access.1746988509
Short name T369
Test name
Test status
Simulation time 1387434700 ps
CPU time 55.51 seconds
Started Mar 24 02:21:31 PM PDT 24
Finished Mar 24 02:22:27 PM PDT 24
Peak memory 262760 kb
Host smart-a910738d-523f-4c4f-a64e-c0649c9e4475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746988509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.1746988509
Directory /workspace/5.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/5.flash_ctrl_smoke.3868467570
Short name T1054
Test name
Test status
Simulation time 45638400 ps
CPU time 97.8 seconds
Started Mar 24 02:20:45 PM PDT 24
Finished Mar 24 02:22:24 PM PDT 24
Peak memory 276560 kb
Host smart-6a40b8d3-ebc1-4f99-acba-d8a617055b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868467570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.3868467570
Directory /workspace/5.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_wo.2042965039
Short name T779
Test name
Test status
Simulation time 19938735300 ps
CPU time 192.71 seconds
Started Mar 24 02:21:08 PM PDT 24
Finished Mar 24 02:24:21 PM PDT 24
Peak memory 259504 kb
Host smart-594db21f-f181-4712-8b2e-7d7ed63d91fe
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042965039 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.flash_ctrl_wo.2042965039
Directory /workspace/5.flash_ctrl_wo/latest

Test location /workspace/coverage/default/50.flash_ctrl_connect.322478889
Short name T487
Test name
Test status
Simulation time 21350000 ps
CPU time 15.73 seconds
Started Mar 24 02:30:51 PM PDT 24
Finished Mar 24 02:31:07 PM PDT 24
Peak memory 275188 kb
Host smart-93de7102-3f9c-4fd3-b561-bf2021ad43ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322478889 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.322478889
Directory /workspace/50.flash_ctrl_connect/latest

Test location /workspace/coverage/default/50.flash_ctrl_otp_reset.1943492088
Short name T1024
Test name
Test status
Simulation time 81410200 ps
CPU time 130.69 seconds
Started Mar 24 02:30:54 PM PDT 24
Finished Mar 24 02:33:05 PM PDT 24
Peak memory 259672 kb
Host smart-374ccc42-bb66-4dd9-b98d-9ad2bcafbae0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943492088 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_o
tp_reset.1943492088
Directory /workspace/50.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/51.flash_ctrl_connect.1376332620
Short name T410
Test name
Test status
Simulation time 14522300 ps
CPU time 13.39 seconds
Started Mar 24 02:30:51 PM PDT 24
Finished Mar 24 02:31:04 PM PDT 24
Peak memory 275512 kb
Host smart-34e002f9-5593-4c62-acc2-708e904f3fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376332620 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.1376332620
Directory /workspace/51.flash_ctrl_connect/latest

Test location /workspace/coverage/default/51.flash_ctrl_otp_reset.2412067550
Short name T134
Test name
Test status
Simulation time 45921000 ps
CPU time 131.82 seconds
Started Mar 24 02:30:49 PM PDT 24
Finished Mar 24 02:33:01 PM PDT 24
Peak memory 259412 kb
Host smart-fd3872f0-a79d-4872-9289-5780b1587795
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412067550 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_o
tp_reset.2412067550
Directory /workspace/51.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/52.flash_ctrl_connect.3567269203
Short name T736
Test name
Test status
Simulation time 21989000 ps
CPU time 15.76 seconds
Started Mar 24 02:30:51 PM PDT 24
Finished Mar 24 02:31:07 PM PDT 24
Peak memory 275052 kb
Host smart-e86c6401-3b2e-4ff3-93dc-4cc1c04fb6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567269203 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.3567269203
Directory /workspace/52.flash_ctrl_connect/latest

Test location /workspace/coverage/default/52.flash_ctrl_otp_reset.3886819871
Short name T554
Test name
Test status
Simulation time 36903300 ps
CPU time 130.63 seconds
Started Mar 24 02:30:51 PM PDT 24
Finished Mar 24 02:33:02 PM PDT 24
Peak memory 259688 kb
Host smart-497a14d2-e78b-4b04-a510-48de92bb803a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886819871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_o
tp_reset.3886819871
Directory /workspace/52.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/53.flash_ctrl_connect.3358956398
Short name T761
Test name
Test status
Simulation time 41963200 ps
CPU time 13.4 seconds
Started Mar 24 02:30:51 PM PDT 24
Finished Mar 24 02:31:04 PM PDT 24
Peak memory 275132 kb
Host smart-04c7834a-34e1-4c96-83a8-3199a3d29540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358956398 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.3358956398
Directory /workspace/53.flash_ctrl_connect/latest

Test location /workspace/coverage/default/53.flash_ctrl_otp_reset.761020621
Short name T1046
Test name
Test status
Simulation time 69239500 ps
CPU time 134.38 seconds
Started Mar 24 02:30:51 PM PDT 24
Finished Mar 24 02:33:05 PM PDT 24
Peak memory 264084 kb
Host smart-8d49d0a8-dcfe-4148-b764-85efbd482326
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761020621 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_ot
p_reset.761020621
Directory /workspace/53.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/54.flash_ctrl_connect.196952027
Short name T766
Test name
Test status
Simulation time 16690700 ps
CPU time 15.72 seconds
Started Mar 24 02:30:56 PM PDT 24
Finished Mar 24 02:31:11 PM PDT 24
Peak memory 275440 kb
Host smart-1a1678df-7c1b-432c-826d-b224162f25c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196952027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.196952027
Directory /workspace/54.flash_ctrl_connect/latest

Test location /workspace/coverage/default/54.flash_ctrl_otp_reset.3323211050
Short name T645
Test name
Test status
Simulation time 599482300 ps
CPU time 110.64 seconds
Started Mar 24 02:30:59 PM PDT 24
Finished Mar 24 02:32:50 PM PDT 24
Peak memory 260856 kb
Host smart-e394221f-eb50-424c-9685-3000d66c91bc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323211050 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_o
tp_reset.3323211050
Directory /workspace/54.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/55.flash_ctrl_connect.1562377823
Short name T896
Test name
Test status
Simulation time 15535000 ps
CPU time 15.94 seconds
Started Mar 24 02:30:56 PM PDT 24
Finished Mar 24 02:31:12 PM PDT 24
Peak memory 275108 kb
Host smart-b952c022-824c-458d-8c08-31587b3b7e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562377823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.1562377823
Directory /workspace/55.flash_ctrl_connect/latest

Test location /workspace/coverage/default/56.flash_ctrl_connect.3317455195
Short name T438
Test name
Test status
Simulation time 26831800 ps
CPU time 15.66 seconds
Started Mar 24 02:30:59 PM PDT 24
Finished Mar 24 02:31:15 PM PDT 24
Peak memory 275544 kb
Host smart-27600504-add1-4cd6-b85f-a66ec01f3855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317455195 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.3317455195
Directory /workspace/56.flash_ctrl_connect/latest

Test location /workspace/coverage/default/56.flash_ctrl_otp_reset.1516156909
Short name T623
Test name
Test status
Simulation time 76759800 ps
CPU time 110.27 seconds
Started Mar 24 02:30:59 PM PDT 24
Finished Mar 24 02:32:50 PM PDT 24
Peak memory 263640 kb
Host smart-15625d31-23b1-4c72-89bc-c3992f974452
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516156909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_o
tp_reset.1516156909
Directory /workspace/56.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/57.flash_ctrl_connect.1696988461
Short name T617
Test name
Test status
Simulation time 37250500 ps
CPU time 13.2 seconds
Started Mar 24 02:30:58 PM PDT 24
Finished Mar 24 02:31:11 PM PDT 24
Peak memory 275508 kb
Host smart-5a659e7b-ea55-4719-8f45-e79e4fe91efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696988461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.1696988461
Directory /workspace/57.flash_ctrl_connect/latest

Test location /workspace/coverage/default/57.flash_ctrl_otp_reset.3670123921
Short name T763
Test name
Test status
Simulation time 41446700 ps
CPU time 133.31 seconds
Started Mar 24 02:30:56 PM PDT 24
Finished Mar 24 02:33:09 PM PDT 24
Peak memory 259548 kb
Host smart-1468e761-e555-4fd7-a3e0-61303393a395
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670123921 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_o
tp_reset.3670123921
Directory /workspace/57.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/58.flash_ctrl_connect.2971866509
Short name T367
Test name
Test status
Simulation time 14399400 ps
CPU time 15.71 seconds
Started Mar 24 02:30:59 PM PDT 24
Finished Mar 24 02:31:15 PM PDT 24
Peak memory 275204 kb
Host smart-b09ff982-50bc-4c5f-9d83-45ad61a704cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971866509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.2971866509
Directory /workspace/58.flash_ctrl_connect/latest

Test location /workspace/coverage/default/58.flash_ctrl_otp_reset.155326909
Short name T904
Test name
Test status
Simulation time 35572800 ps
CPU time 111.77 seconds
Started Mar 24 02:30:57 PM PDT 24
Finished Mar 24 02:32:49 PM PDT 24
Peak memory 259680 kb
Host smart-a31ee8f5-2cce-4460-a445-30c432d347a3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155326909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_ot
p_reset.155326909
Directory /workspace/58.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/59.flash_ctrl_connect.2869604500
Short name T413
Test name
Test status
Simulation time 15172400 ps
CPU time 13.62 seconds
Started Mar 24 02:30:59 PM PDT 24
Finished Mar 24 02:31:13 PM PDT 24
Peak memory 275380 kb
Host smart-95548d73-f45c-42dc-ad08-08213816542c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869604500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.2869604500
Directory /workspace/59.flash_ctrl_connect/latest

Test location /workspace/coverage/default/59.flash_ctrl_otp_reset.2834517715
Short name T667
Test name
Test status
Simulation time 42054000 ps
CPU time 132.98 seconds
Started Mar 24 02:30:55 PM PDT 24
Finished Mar 24 02:33:08 PM PDT 24
Peak memory 263076 kb
Host smart-6d30f280-3df3-45b9-b45e-f597cd734592
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834517715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_o
tp_reset.2834517715
Directory /workspace/59.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_alert_test.3396062709
Short name T515
Test name
Test status
Simulation time 55900500 ps
CPU time 13.95 seconds
Started Mar 24 02:22:14 PM PDT 24
Finished Mar 24 02:22:28 PM PDT 24
Peak memory 258952 kb
Host smart-c0ba81d7-201b-4569-ac94-31d7d3f420d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396062709 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.3
396062709
Directory /workspace/6.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.flash_ctrl_connect.3072963444
Short name T777
Test name
Test status
Simulation time 58495400 ps
CPU time 15.84 seconds
Started Mar 24 02:22:12 PM PDT 24
Finished Mar 24 02:22:28 PM PDT 24
Peak memory 275140 kb
Host smart-53516e57-88a2-4f67-939b-122eb1c1e639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072963444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.3072963444
Directory /workspace/6.flash_ctrl_connect/latest

Test location /workspace/coverage/default/6.flash_ctrl_disable.1629057939
Short name T1021
Test name
Test status
Simulation time 10357500 ps
CPU time 21.97 seconds
Started Mar 24 02:22:10 PM PDT 24
Finished Mar 24 02:22:32 PM PDT 24
Peak memory 264960 kb
Host smart-d2be3473-b0a8-4689-a8e9-b46f913ce544
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629057939 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_disable.1629057939
Directory /workspace/6.flash_ctrl_disable/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_mp.3461635442
Short name T16
Test name
Test status
Simulation time 3799546400 ps
CPU time 2354.61 seconds
Started Mar 24 02:21:41 PM PDT 24
Finished Mar 24 03:00:56 PM PDT 24
Peak memory 264908 kb
Host smart-43fd5c6f-b194-4526-8339-22668be8f76b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461635442 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_err
or_mp.3461635442
Directory /workspace/6.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_prog_win.2103517245
Short name T1029
Test name
Test status
Simulation time 820935900 ps
CPU time 829.85 seconds
Started Mar 24 02:21:42 PM PDT 24
Finished Mar 24 02:35:32 PM PDT 24
Peak memory 264900 kb
Host smart-99026d0e-fcbe-445c-99de-2deb199d4a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103517245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.2103517245
Directory /workspace/6.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/6.flash_ctrl_fetch_code.1058178683
Short name T49
Test name
Test status
Simulation time 514321800 ps
CPU time 22.65 seconds
Started Mar 24 02:21:35 PM PDT 24
Finished Mar 24 02:21:58 PM PDT 24
Peak memory 264832 kb
Host smart-621846d8-de77-4717-8abd-1a4aaa4a8d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058178683 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetch_code.1058178683
Directory /workspace/6.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.2767248362
Short name T910
Test name
Test status
Simulation time 10011830400 ps
CPU time 107.38 seconds
Started Mar 24 02:22:13 PM PDT 24
Finished Mar 24 02:24:00 PM PDT 24
Peak memory 314008 kb
Host smart-057b6923-1266-40ba-8223-06c18663150f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767248362 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.2767248362
Directory /workspace/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_read_seed_err.1667313486
Short name T206
Test name
Test status
Simulation time 15100500 ps
CPU time 13.29 seconds
Started Mar 24 02:22:13 PM PDT 24
Finished Mar 24 02:22:27 PM PDT 24
Peak memory 264876 kb
Host smart-94d57c28-bd6a-4eea-8503-e6dcde9f96eb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667313486 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_seed_err.1667313486
Directory /workspace/6.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_rma_reset.818731360
Short name T710
Test name
Test status
Simulation time 40118829900 ps
CPU time 858.17 seconds
Started Mar 24 02:21:35 PM PDT 24
Finished Mar 24 02:35:53 PM PDT 24
Peak memory 264200 kb
Host smart-4bc6ab04-ea08-498e-8657-473b9e80cf20
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818731360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.flash_ctrl_hw_rma_reset.818731360
Directory /workspace/6.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_sec_otp.993590319
Short name T772
Test name
Test status
Simulation time 625178300 ps
CPU time 62.57 seconds
Started Mar 24 02:21:28 PM PDT 24
Finished Mar 24 02:22:31 PM PDT 24
Peak memory 261824 kb
Host smart-5c4d5db2-4581-40ac-98b2-ac23314f35b2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993590319 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw
_sec_otp.993590319
Directory /workspace/6.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd.275272053
Short name T353
Test name
Test status
Simulation time 7458959000 ps
CPU time 157.76 seconds
Started Mar 24 02:21:57 PM PDT 24
Finished Mar 24 02:24:35 PM PDT 24
Peak memory 293768 kb
Host smart-aeb5bf4e-380c-4345-8701-93e8550add1b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275272053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash
_ctrl_intr_rd.275272053
Directory /workspace/6.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd_slow_flash.3199101756
Short name T322
Test name
Test status
Simulation time 104660979100 ps
CPU time 248.16 seconds
Started Mar 24 02:22:08 PM PDT 24
Finished Mar 24 02:26:16 PM PDT 24
Peak memory 284556 kb
Host smart-93e7d62c-a5e4-4315-a827-415a6c9ff5ca
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199101756 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd_slow_flash.3199101756
Directory /workspace/6.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr.5067385
Short name T22
Test name
Test status
Simulation time 6797400700 ps
CPU time 85.42 seconds
Started Mar 24 02:22:02 PM PDT 24
Finished Mar 24 02:23:28 PM PDT 24
Peak memory 265016 kb
Host smart-fbf73b10-5e66-49d8-9dbc-ae7f77a6c8df
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5067385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UV
M_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.flash_ctrl_intr_wr.5067385
Directory /workspace/6.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.3953524813
Short name T551
Test name
Test status
Simulation time 222574608000 ps
CPU time 469.05 seconds
Started Mar 24 02:22:09 PM PDT 24
Finished Mar 24 02:29:58 PM PDT 24
Peak memory 265048 kb
Host smart-97674175-5841-42c7-833b-f7fdd59c3e18
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395
3524813 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.3953524813
Directory /workspace/6.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_invalid_op.889586248
Short name T933
Test name
Test status
Simulation time 3783110700 ps
CPU time 72.62 seconds
Started Mar 24 02:21:46 PM PDT 24
Finished Mar 24 02:23:00 PM PDT 24
Peak memory 260452 kb
Host smart-fff11cf4-32ab-416f-b206-7ce1d68ee5a6
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889586248 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.889586248
Directory /workspace/6.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/6.flash_ctrl_lcmgr_intg.2848711702
Short name T783
Test name
Test status
Simulation time 15893800 ps
CPU time 13.56 seconds
Started Mar 24 02:22:13 PM PDT 24
Finished Mar 24 02:22:27 PM PDT 24
Peak memory 259460 kb
Host smart-4319a933-9905-4a3c-ad95-367f6351edfb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848711702 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.flash_ctrl_lcmgr_intg.2848711702
Directory /workspace/6.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/6.flash_ctrl_mp_regions.2719300121
Short name T541
Test name
Test status
Simulation time 8257244000 ps
CPU time 206.29 seconds
Started Mar 24 02:21:37 PM PDT 24
Finished Mar 24 02:25:03 PM PDT 24
Peak memory 264912 kb
Host smart-c62e7eb6-a162-469b-8704-170d2f2a2139
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719300121 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 6.flash_ctrl_mp_regions.2719300121
Directory /workspace/6.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/6.flash_ctrl_otp_reset.2953954591
Short name T720
Test name
Test status
Simulation time 143826100 ps
CPU time 112.59 seconds
Started Mar 24 02:21:35 PM PDT 24
Finished Mar 24 02:23:28 PM PDT 24
Peak memory 264284 kb
Host smart-68659c46-54d1-4410-a938-5d01ffb2ae25
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953954591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ot
p_reset.2953954591
Directory /workspace/6.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_phy_arb.164500848
Short name T235
Test name
Test status
Simulation time 1577824900 ps
CPU time 360.03 seconds
Started Mar 24 02:21:30 PM PDT 24
Finished Mar 24 02:27:31 PM PDT 24
Peak memory 262252 kb
Host smart-6d008d43-fc58-4058-9798-49cb3cbeeb0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=164500848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.164500848
Directory /workspace/6.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/6.flash_ctrl_prog_reset.1382470774
Short name T964
Test name
Test status
Simulation time 22566000 ps
CPU time 13.39 seconds
Started Mar 24 02:22:07 PM PDT 24
Finished Mar 24 02:22:21 PM PDT 24
Peak memory 264844 kb
Host smart-fdb88309-b652-48a7-9adf-0b1b366d3ddc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382470774 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_prog_res
et.1382470774
Directory /workspace/6.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_rand_ops.1295033172
Short name T63
Test name
Test status
Simulation time 35475100 ps
CPU time 346.99 seconds
Started Mar 24 02:21:30 PM PDT 24
Finished Mar 24 02:27:17 PM PDT 24
Peak memory 279256 kb
Host smart-68793356-5a64-417b-a7e9-f4830e3d6fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295033172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.1295033172
Directory /workspace/6.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/6.flash_ctrl_re_evict.4122086225
Short name T797
Test name
Test status
Simulation time 46918200 ps
CPU time 32.93 seconds
Started Mar 24 02:22:08 PM PDT 24
Finished Mar 24 02:22:41 PM PDT 24
Peak memory 273332 kb
Host smart-90691be1-02f6-4201-b2bf-e1550e4f1261
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122086225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla
sh_ctrl_re_evict.4122086225
Directory /workspace/6.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro.3421336359
Short name T897
Test name
Test status
Simulation time 444427800 ps
CPU time 105.8 seconds
Started Mar 24 02:21:52 PM PDT 24
Finished Mar 24 02:23:38 PM PDT 24
Peak memory 289052 kb
Host smart-6e48c508-22f4-46d5-9978-c8317d572ff5
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421336359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.flash_ctrl_ro.3421336359
Directory /workspace/6.flash_ctrl_ro/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw.320029564
Short name T575
Test name
Test status
Simulation time 18360082700 ps
CPU time 504.34 seconds
Started Mar 24 02:21:59 PM PDT 24
Finished Mar 24 02:30:23 PM PDT 24
Peak memory 314104 kb
Host smart-89f89b68-4cbe-49d0-bcaf-6905b92e9e3d
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320029564 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctr
l_rw.320029564
Directory /workspace/6.flash_ctrl_rw/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict.2471983088
Short name T212
Test name
Test status
Simulation time 56314300 ps
CPU time 31.28 seconds
Started Mar 24 02:22:07 PM PDT 24
Finished Mar 24 02:22:39 PM PDT 24
Peak memory 272508 kb
Host smart-28680e15-f87a-4e40-b150-ca77e40185d2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471983088 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla
sh_ctrl_rw_evict.2471983088
Directory /workspace/6.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict_all_en.1559586357
Short name T586
Test name
Test status
Simulation time 107801000 ps
CPU time 29.92 seconds
Started Mar 24 02:22:09 PM PDT 24
Finished Mar 24 02:22:39 PM PDT 24
Peak memory 273252 kb
Host smart-f002a5e9-08a5-42cc-9d9b-0d2f2bb75ec4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559586357 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict_all_en.1559586357
Directory /workspace/6.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/6.flash_ctrl_sec_info_access.3477835785
Short name T400
Test name
Test status
Simulation time 2185459300 ps
CPU time 79.49 seconds
Started Mar 24 02:22:10 PM PDT 24
Finished Mar 24 02:23:29 PM PDT 24
Peak memory 262748 kb
Host smart-af70d42f-8bd1-4858-8e56-6a863c3b2e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477835785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.3477835785
Directory /workspace/6.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/6.flash_ctrl_smoke.2685980095
Short name T420
Test name
Test status
Simulation time 234189100 ps
CPU time 148.96 seconds
Started Mar 24 02:21:31 PM PDT 24
Finished Mar 24 02:24:00 PM PDT 24
Peak memory 275980 kb
Host smart-b0c83395-3ef5-486c-8a65-642eb1d04983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685980095 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.2685980095
Directory /workspace/6.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/6.flash_ctrl_wo.1724912523
Short name T786
Test name
Test status
Simulation time 8697113900 ps
CPU time 209.78 seconds
Started Mar 24 02:21:51 PM PDT 24
Finished Mar 24 02:25:21 PM PDT 24
Peak memory 264988 kb
Host smart-49b675e5-e5da-4509-8184-b639b4b28d0f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724912523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.flash_ctrl_wo.1724912523
Directory /workspace/6.flash_ctrl_wo/latest

Test location /workspace/coverage/default/60.flash_ctrl_connect.1138911273
Short name T499
Test name
Test status
Simulation time 80056500 ps
CPU time 13.21 seconds
Started Mar 24 02:31:01 PM PDT 24
Finished Mar 24 02:31:14 PM PDT 24
Peak memory 275548 kb
Host smart-519f5e16-f224-4fed-9c29-ac8974d443be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138911273 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.1138911273
Directory /workspace/60.flash_ctrl_connect/latest

Test location /workspace/coverage/default/60.flash_ctrl_otp_reset.872614397
Short name T909
Test name
Test status
Simulation time 39812100 ps
CPU time 130.66 seconds
Started Mar 24 02:30:59 PM PDT 24
Finished Mar 24 02:33:10 PM PDT 24
Peak memory 259788 kb
Host smart-6b49d373-2720-45ef-bb54-0b3a392697a9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872614397 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_ot
p_reset.872614397
Directory /workspace/60.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/61.flash_ctrl_connect.2311721816
Short name T494
Test name
Test status
Simulation time 26861700 ps
CPU time 15.78 seconds
Started Mar 24 02:31:01 PM PDT 24
Finished Mar 24 02:31:17 PM PDT 24
Peak memory 275604 kb
Host smart-d24cfcd2-ecc0-449d-8d7d-4e8437aa041a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311721816 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.2311721816
Directory /workspace/61.flash_ctrl_connect/latest

Test location /workspace/coverage/default/61.flash_ctrl_otp_reset.3867037100
Short name T466
Test name
Test status
Simulation time 38004600 ps
CPU time 109.68 seconds
Started Mar 24 02:31:00 PM PDT 24
Finished Mar 24 02:32:50 PM PDT 24
Peak memory 259588 kb
Host smart-4072300b-1cd6-4583-a7c6-664f68de4809
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867037100 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_o
tp_reset.3867037100
Directory /workspace/61.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/62.flash_ctrl_connect.3523057705
Short name T455
Test name
Test status
Simulation time 14015000 ps
CPU time 13.38 seconds
Started Mar 24 02:30:59 PM PDT 24
Finished Mar 24 02:31:12 PM PDT 24
Peak memory 274636 kb
Host smart-51460c98-0faa-4bbf-b309-d5824487dc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523057705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.3523057705
Directory /workspace/62.flash_ctrl_connect/latest

Test location /workspace/coverage/default/62.flash_ctrl_otp_reset.1724348927
Short name T867
Test name
Test status
Simulation time 82225700 ps
CPU time 130.9 seconds
Started Mar 24 02:31:07 PM PDT 24
Finished Mar 24 02:33:19 PM PDT 24
Peak memory 259760 kb
Host smart-02f742e4-59e8-4a25-9919-2ccb37889952
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724348927 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_o
tp_reset.1724348927
Directory /workspace/62.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/63.flash_ctrl_connect.14066224
Short name T673
Test name
Test status
Simulation time 16393200 ps
CPU time 15.73 seconds
Started Mar 24 02:31:07 PM PDT 24
Finished Mar 24 02:31:23 PM PDT 24
Peak memory 275056 kb
Host smart-387d6389-8800-4c96-ac5a-aa6a48d291c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14066224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.14066224
Directory /workspace/63.flash_ctrl_connect/latest

Test location /workspace/coverage/default/63.flash_ctrl_otp_reset.2115763586
Short name T644
Test name
Test status
Simulation time 287972200 ps
CPU time 132.36 seconds
Started Mar 24 02:31:03 PM PDT 24
Finished Mar 24 02:33:15 PM PDT 24
Peak memory 260616 kb
Host smart-39e8bd16-dfdb-4ad3-93ee-2cdd3f2071ac
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115763586 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_o
tp_reset.2115763586
Directory /workspace/63.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/64.flash_ctrl_connect.194438733
Short name T1014
Test name
Test status
Simulation time 38962300 ps
CPU time 15.89 seconds
Started Mar 24 02:31:00 PM PDT 24
Finished Mar 24 02:31:16 PM PDT 24
Peak memory 275552 kb
Host smart-4d0f924c-6988-4035-8d3a-6dbcf6ab9712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194438733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.194438733
Directory /workspace/64.flash_ctrl_connect/latest

Test location /workspace/coverage/default/65.flash_ctrl_connect.965231553
Short name T179
Test name
Test status
Simulation time 28504600 ps
CPU time 15.36 seconds
Started Mar 24 02:31:06 PM PDT 24
Finished Mar 24 02:31:22 PM PDT 24
Peak memory 275188 kb
Host smart-950d9fba-0f0b-4a49-ba39-f900e4c4fb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965231553 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.965231553
Directory /workspace/65.flash_ctrl_connect/latest

Test location /workspace/coverage/default/65.flash_ctrl_otp_reset.1719804137
Short name T938
Test name
Test status
Simulation time 157113600 ps
CPU time 110.21 seconds
Started Mar 24 02:31:09 PM PDT 24
Finished Mar 24 02:32:59 PM PDT 24
Peak memory 261896 kb
Host smart-7a0272a6-fdb2-44a3-a1be-84b5f3aeb59a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719804137 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_o
tp_reset.1719804137
Directory /workspace/65.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/66.flash_ctrl_connect.2785002641
Short name T851
Test name
Test status
Simulation time 18194800 ps
CPU time 16.01 seconds
Started Mar 24 02:31:06 PM PDT 24
Finished Mar 24 02:31:23 PM PDT 24
Peak memory 274536 kb
Host smart-0721b7e9-4679-4e30-bae5-dcc086ffef08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785002641 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.2785002641
Directory /workspace/66.flash_ctrl_connect/latest

Test location /workspace/coverage/default/66.flash_ctrl_otp_reset.275354349
Short name T135
Test name
Test status
Simulation time 68185500 ps
CPU time 130.69 seconds
Started Mar 24 02:31:07 PM PDT 24
Finished Mar 24 02:33:18 PM PDT 24
Peak memory 264484 kb
Host smart-7af53a19-de8c-4c34-998f-7d2ccbaf38a8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275354349 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_ot
p_reset.275354349
Directory /workspace/66.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/67.flash_ctrl_connect.1760900670
Short name T263
Test name
Test status
Simulation time 86401500 ps
CPU time 13.58 seconds
Started Mar 24 02:31:06 PM PDT 24
Finished Mar 24 02:31:20 PM PDT 24
Peak memory 275520 kb
Host smart-2465bc76-b3da-4014-8399-c2094a179012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760900670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.1760900670
Directory /workspace/67.flash_ctrl_connect/latest

Test location /workspace/coverage/default/67.flash_ctrl_otp_reset.1209240267
Short name T906
Test name
Test status
Simulation time 37388000 ps
CPU time 132.42 seconds
Started Mar 24 02:31:05 PM PDT 24
Finished Mar 24 02:33:19 PM PDT 24
Peak memory 263428 kb
Host smart-22807545-5a2b-4931-bdfd-695491567d5d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209240267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_o
tp_reset.1209240267
Directory /workspace/67.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/68.flash_ctrl_connect.2162475061
Short name T569
Test name
Test status
Simulation time 18926700 ps
CPU time 15.84 seconds
Started Mar 24 02:31:06 PM PDT 24
Finished Mar 24 02:31:23 PM PDT 24
Peak memory 274528 kb
Host smart-de300fcd-936f-49cc-bace-2f8aca80942a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162475061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.2162475061
Directory /workspace/68.flash_ctrl_connect/latest

Test location /workspace/coverage/default/68.flash_ctrl_otp_reset.4136705751
Short name T568
Test name
Test status
Simulation time 145823800 ps
CPU time 114.78 seconds
Started Mar 24 02:31:06 PM PDT 24
Finished Mar 24 02:33:01 PM PDT 24
Peak memory 260664 kb
Host smart-9906fe8d-e2f4-4468-9cf3-1a4c1696993b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136705751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_o
tp_reset.4136705751
Directory /workspace/68.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/69.flash_ctrl_connect.2695845268
Short name T989
Test name
Test status
Simulation time 39545000 ps
CPU time 13.23 seconds
Started Mar 24 02:31:07 PM PDT 24
Finished Mar 24 02:31:20 PM PDT 24
Peak memory 275260 kb
Host smart-bda4fbcd-98e6-4abe-a076-7c93ee592498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695845268 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.2695845268
Directory /workspace/69.flash_ctrl_connect/latest

Test location /workspace/coverage/default/69.flash_ctrl_otp_reset.3205676886
Short name T464
Test name
Test status
Simulation time 42401600 ps
CPU time 130.53 seconds
Started Mar 24 02:31:06 PM PDT 24
Finished Mar 24 02:33:18 PM PDT 24
Peak memory 260796 kb
Host smart-d805b60e-6973-446b-ba9b-222b2bcdb804
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205676886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_o
tp_reset.3205676886
Directory /workspace/69.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_alert_test.4024825284
Short name T491
Test name
Test status
Simulation time 80590700 ps
CPU time 13.69 seconds
Started Mar 24 02:22:42 PM PDT 24
Finished Mar 24 02:22:55 PM PDT 24
Peak memory 257908 kb
Host smart-728ce18a-bcc5-4a24-85ad-eb27415a6a75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024825284 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.4
024825284
Directory /workspace/7.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.flash_ctrl_connect.1326375754
Short name T884
Test name
Test status
Simulation time 50296400 ps
CPU time 16.35 seconds
Started Mar 24 02:22:37 PM PDT 24
Finished Mar 24 02:22:53 PM PDT 24
Peak memory 275476 kb
Host smart-d0ebd374-a28b-4f92-8afb-660c1f9ec3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326375754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.1326375754
Directory /workspace/7.flash_ctrl_connect/latest

Test location /workspace/coverage/default/7.flash_ctrl_disable.3630717816
Short name T795
Test name
Test status
Simulation time 15071200 ps
CPU time 22.13 seconds
Started Mar 24 02:22:36 PM PDT 24
Finished Mar 24 02:22:58 PM PDT 24
Peak memory 264908 kb
Host smart-102a2c89-808b-437e-82ea-0158ff4ba197
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630717816 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_disable.3630717816
Directory /workspace/7.flash_ctrl_disable/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_mp.2108458343
Short name T105
Test name
Test status
Simulation time 13848023400 ps
CPU time 2146.59 seconds
Started Mar 24 02:22:24 PM PDT 24
Finished Mar 24 02:58:11 PM PDT 24
Peak memory 264520 kb
Host smart-c3e01707-61f4-440b-b4d8-8bc014365406
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108458343 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_err
or_mp.2108458343
Directory /workspace/7.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_prog_win.1737093260
Short name T527
Test name
Test status
Simulation time 1226070100 ps
CPU time 987.44 seconds
Started Mar 24 02:22:24 PM PDT 24
Finished Mar 24 02:38:53 PM PDT 24
Peak memory 273060 kb
Host smart-12efaa20-3644-4070-a241-1ee323b14a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737093260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.1737093260
Directory /workspace/7.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/7.flash_ctrl_fetch_code.1390430732
Short name T983
Test name
Test status
Simulation time 3792039000 ps
CPU time 29.15 seconds
Started Mar 24 02:22:19 PM PDT 24
Finished Mar 24 02:22:48 PM PDT 24
Peak memory 264780 kb
Host smart-5691e935-7536-4a73-9237-76c574483ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390430732 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetch_code.1390430732
Directory /workspace/7.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.2009645604
Short name T127
Test name
Test status
Simulation time 10011790300 ps
CPU time 320.09 seconds
Started Mar 24 02:22:42 PM PDT 24
Finished Mar 24 02:28:02 PM PDT 24
Peak memory 319396 kb
Host smart-a714e545-55d3-4f9d-8d6e-547c1f1d8cb6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009645604 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.2009645604
Directory /workspace/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_sec_otp.3760552944
Short name T802
Test name
Test status
Simulation time 2938770000 ps
CPU time 101.27 seconds
Started Mar 24 02:22:19 PM PDT 24
Finished Mar 24 02:24:00 PM PDT 24
Peak memory 262392 kb
Host smart-8391c887-12e2-402d-8cef-cf8567c63284
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760552944 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_h
w_sec_otp.3760552944
Directory /workspace/7.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd_slow_flash.3348748841
Short name T950
Test name
Test status
Simulation time 39081174600 ps
CPU time 241.95 seconds
Started Mar 24 02:22:29 PM PDT 24
Finished Mar 24 02:26:32 PM PDT 24
Peak memory 284508 kb
Host smart-61c5c45f-ea8e-4260-8fc8-b160937a80c8
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348748841 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd_slow_flash.3348748841
Directory /workspace/7.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr.807487943
Short name T23
Test name
Test status
Simulation time 3597310100 ps
CPU time 97.13 seconds
Started Mar 24 02:22:30 PM PDT 24
Finished Mar 24 02:24:08 PM PDT 24
Peak memory 261932 kb
Host smart-465e56d1-7ec2-4e37-a771-da46c71aa89d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807487943 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 7.flash_ctrl_intr_wr.807487943
Directory /workspace/7.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr_slow_flash.1759487828
Short name T633
Test name
Test status
Simulation time 176897657400 ps
CPU time 362.31 seconds
Started Mar 24 02:22:28 PM PDT 24
Finished Mar 24 02:28:32 PM PDT 24
Peak memory 260904 kb
Host smart-b4279c7c-91bd-4dc7-8357-1dade5127e4a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175
9487828 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.1759487828
Directory /workspace/7.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_invalid_op.4083253249
Short name T641
Test name
Test status
Simulation time 3035588400 ps
CPU time 78.21 seconds
Started Mar 24 02:22:23 PM PDT 24
Finished Mar 24 02:23:42 PM PDT 24
Peak memory 262520 kb
Host smart-04c2db79-9f5b-4f5e-aaa2-88f37ef1324a
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083253249 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.4083253249
Directory /workspace/7.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/7.flash_ctrl_lcmgr_intg.2825434635
Short name T297
Test name
Test status
Simulation time 154561700 ps
CPU time 13.37 seconds
Started Mar 24 02:22:43 PM PDT 24
Finished Mar 24 02:22:56 PM PDT 24
Peak memory 265200 kb
Host smart-ad699827-76d4-4a72-add6-95208c108b21
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825434635 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.flash_ctrl_lcmgr_intg.2825434635
Directory /workspace/7.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/7.flash_ctrl_mp_regions.1579940347
Short name T281
Test name
Test status
Simulation time 6653199500 ps
CPU time 148.86 seconds
Started Mar 24 02:22:18 PM PDT 24
Finished Mar 24 02:24:48 PM PDT 24
Peak memory 262380 kb
Host smart-3f953b8c-ba8c-4e6f-ae6f-0e91d5e19cba
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579940347 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 7.flash_ctrl_mp_regions.1579940347
Directory /workspace/7.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/7.flash_ctrl_otp_reset.2949962489
Short name T532
Test name
Test status
Simulation time 36228400 ps
CPU time 133.06 seconds
Started Mar 24 02:22:18 PM PDT 24
Finished Mar 24 02:24:31 PM PDT 24
Peak memory 259816 kb
Host smart-61e639bd-4418-4fc4-8f7f-4095bc9cc44b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949962489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ot
p_reset.2949962489
Directory /workspace/7.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_phy_arb.728020053
Short name T918
Test name
Test status
Simulation time 717016800 ps
CPU time 350.35 seconds
Started Mar 24 02:22:18 PM PDT 24
Finished Mar 24 02:28:08 PM PDT 24
Peak memory 261460 kb
Host smart-32692c92-1fcc-409d-9edb-563898490bfe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=728020053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.728020053
Directory /workspace/7.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/7.flash_ctrl_prog_reset.3561143455
Short name T738
Test name
Test status
Simulation time 110856900 ps
CPU time 13.25 seconds
Started Mar 24 02:22:28 PM PDT 24
Finished Mar 24 02:22:43 PM PDT 24
Peak memory 259836 kb
Host smart-8bf9cfc6-e2da-4354-99d7-e8b274baf750
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561143455 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_prog_res
et.3561143455
Directory /workspace/7.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_rand_ops.104600688
Short name T1045
Test name
Test status
Simulation time 5884101300 ps
CPU time 553.98 seconds
Started Mar 24 02:22:18 PM PDT 24
Finished Mar 24 02:31:33 PM PDT 24
Peak memory 282876 kb
Host smart-80813154-8809-43a9-bc25-ff2993f784b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104600688 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.104600688
Directory /workspace/7.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/7.flash_ctrl_re_evict.3613010420
Short name T981
Test name
Test status
Simulation time 2088974800 ps
CPU time 38.38 seconds
Started Mar 24 02:22:35 PM PDT 24
Finished Mar 24 02:23:14 PM PDT 24
Peak memory 267108 kb
Host smart-25c19c3d-eb08-4fda-85dc-d49f70b29068
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613010420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla
sh_ctrl_re_evict.3613010420
Directory /workspace/7.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro.4196249577
Short name T473
Test name
Test status
Simulation time 3556584000 ps
CPU time 109.53 seconds
Started Mar 24 02:22:25 PM PDT 24
Finished Mar 24 02:24:15 PM PDT 24
Peak memory 281064 kb
Host smart-bf17d033-28f3-4a62-8c28-619209199841
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196249577 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.flash_ctrl_ro.4196249577
Directory /workspace/7.flash_ctrl_ro/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw.2626535350
Short name T701
Test name
Test status
Simulation time 3238070300 ps
CPU time 565.43 seconds
Started Mar 24 02:22:25 PM PDT 24
Finished Mar 24 02:31:51 PM PDT 24
Peak memory 309400 kb
Host smart-ec8eb20f-b955-4ec0-91fb-e235b8d3761e
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626535350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ct
rl_rw.2626535350
Directory /workspace/7.flash_ctrl_rw/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict.1065549940
Short name T216
Test name
Test status
Simulation time 86020300 ps
CPU time 30.93 seconds
Started Mar 24 02:22:35 PM PDT 24
Finished Mar 24 02:23:06 PM PDT 24
Peak memory 273280 kb
Host smart-9ac454f3-b44e-43ff-a440-1b300fbe43ae
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065549940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla
sh_ctrl_rw_evict.1065549940
Directory /workspace/7.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict_all_en.1507753770
Short name T213
Test name
Test status
Simulation time 32601600 ps
CPU time 31.12 seconds
Started Mar 24 02:22:35 PM PDT 24
Finished Mar 24 02:23:06 PM PDT 24
Peak memory 273284 kb
Host smart-cd9efbdf-590d-4abc-8ae1-f913a3eaf696
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507753770 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict_all_en.1507753770
Directory /workspace/7.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/7.flash_ctrl_sec_info_access.764627917
Short name T397
Test name
Test status
Simulation time 1167085700 ps
CPU time 58.63 seconds
Started Mar 24 02:22:35 PM PDT 24
Finished Mar 24 02:23:34 PM PDT 24
Peak memory 262756 kb
Host smart-dc87831a-90e9-4b6a-bad5-6684bdcc352f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764627917 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.764627917
Directory /workspace/7.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/7.flash_ctrl_smoke.606701448
Short name T463
Test name
Test status
Simulation time 27949100 ps
CPU time 100.7 seconds
Started Mar 24 02:22:13 PM PDT 24
Finished Mar 24 02:23:54 PM PDT 24
Peak memory 276364 kb
Host smart-22d8a35f-54bf-432c-93c9-340b590f8205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606701448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.606701448
Directory /workspace/7.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/7.flash_ctrl_wo.3995844351
Short name T561
Test name
Test status
Simulation time 2656141300 ps
CPU time 143.77 seconds
Started Mar 24 02:22:25 PM PDT 24
Finished Mar 24 02:24:49 PM PDT 24
Peak memory 259048 kb
Host smart-f6215aa6-f119-4faf-9e49-b0596ffa001f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995844351 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.flash_ctrl_wo.3995844351
Directory /workspace/7.flash_ctrl_wo/latest

Test location /workspace/coverage/default/70.flash_ctrl_connect.3261337239
Short name T857
Test name
Test status
Simulation time 65759000 ps
CPU time 15.65 seconds
Started Mar 24 02:31:09 PM PDT 24
Finished Mar 24 02:31:25 PM PDT 24
Peak memory 275580 kb
Host smart-3ff1d8bf-6728-432c-b51a-cd4240f427fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261337239 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.3261337239
Directory /workspace/70.flash_ctrl_connect/latest

Test location /workspace/coverage/default/70.flash_ctrl_otp_reset.25251262
Short name T317
Test name
Test status
Simulation time 41617700 ps
CPU time 132.26 seconds
Started Mar 24 02:31:09 PM PDT 24
Finished Mar 24 02:33:21 PM PDT 24
Peak memory 260684 kb
Host smart-fe388fa3-761a-44b3-ae98-ec4e14947e16
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25251262 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_otp
_reset.25251262
Directory /workspace/70.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/71.flash_ctrl_connect.3810285651
Short name T426
Test name
Test status
Simulation time 42316300 ps
CPU time 15.8 seconds
Started Mar 24 02:31:06 PM PDT 24
Finished Mar 24 02:31:22 PM PDT 24
Peak memory 275108 kb
Host smart-fb86c273-33e0-416f-9a7f-1807fa83a11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810285651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.3810285651
Directory /workspace/71.flash_ctrl_connect/latest

Test location /workspace/coverage/default/71.flash_ctrl_otp_reset.4291026074
Short name T610
Test name
Test status
Simulation time 223503600 ps
CPU time 131.61 seconds
Started Mar 24 02:31:07 PM PDT 24
Finished Mar 24 02:33:19 PM PDT 24
Peak memory 259980 kb
Host smart-24bcea63-c45a-46d6-ba1a-8b655e39f9c9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291026074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_o
tp_reset.4291026074
Directory /workspace/71.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/72.flash_ctrl_connect.3779432767
Short name T598
Test name
Test status
Simulation time 17065800 ps
CPU time 15.82 seconds
Started Mar 24 02:31:11 PM PDT 24
Finished Mar 24 02:31:27 PM PDT 24
Peak memory 275264 kb
Host smart-9918ca2f-3d68-4ab0-9fcd-fd4d7c9140a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779432767 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.3779432767
Directory /workspace/72.flash_ctrl_connect/latest

Test location /workspace/coverage/default/72.flash_ctrl_otp_reset.3494034670
Short name T1018
Test name
Test status
Simulation time 135338100 ps
CPU time 111.8 seconds
Started Mar 24 02:31:12 PM PDT 24
Finished Mar 24 02:33:04 PM PDT 24
Peak memory 259480 kb
Host smart-3595213a-343d-4512-944a-c25193b13d1a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494034670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_o
tp_reset.3494034670
Directory /workspace/72.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/73.flash_ctrl_connect.3610517571
Short name T587
Test name
Test status
Simulation time 67095900 ps
CPU time 13.45 seconds
Started Mar 24 02:31:12 PM PDT 24
Finished Mar 24 02:31:25 PM PDT 24
Peak memory 275552 kb
Host smart-2b1c44e1-8622-448c-ad86-5f34b3b717f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610517571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.3610517571
Directory /workspace/73.flash_ctrl_connect/latest

Test location /workspace/coverage/default/73.flash_ctrl_otp_reset.3394477353
Short name T852
Test name
Test status
Simulation time 38176800 ps
CPU time 134.21 seconds
Started Mar 24 02:31:12 PM PDT 24
Finished Mar 24 02:33:27 PM PDT 24
Peak memory 263616 kb
Host smart-2d15e464-3345-46c8-a6c7-ade54caedfbf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394477353 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_o
tp_reset.3394477353
Directory /workspace/73.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/74.flash_ctrl_connect.2064515499
Short name T544
Test name
Test status
Simulation time 38836000 ps
CPU time 15.85 seconds
Started Mar 24 02:31:12 PM PDT 24
Finished Mar 24 02:31:27 PM PDT 24
Peak memory 275444 kb
Host smart-47dd5ed6-095d-46c2-aadf-f4e6a4e47896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064515499 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.2064515499
Directory /workspace/74.flash_ctrl_connect/latest

Test location /workspace/coverage/default/74.flash_ctrl_otp_reset.2169072666
Short name T844
Test name
Test status
Simulation time 38798000 ps
CPU time 130.31 seconds
Started Mar 24 02:31:11 PM PDT 24
Finished Mar 24 02:33:22 PM PDT 24
Peak memory 259688 kb
Host smart-8d36010b-568e-4bd3-8b39-371dae73be73
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169072666 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_o
tp_reset.2169072666
Directory /workspace/74.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/75.flash_ctrl_connect.3685429737
Short name T659
Test name
Test status
Simulation time 17176700 ps
CPU time 16.04 seconds
Started Mar 24 02:31:12 PM PDT 24
Finished Mar 24 02:31:29 PM PDT 24
Peak memory 275204 kb
Host smart-4c667621-3599-4d2b-a557-c3235531c830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685429737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.3685429737
Directory /workspace/75.flash_ctrl_connect/latest

Test location /workspace/coverage/default/75.flash_ctrl_otp_reset.650479725
Short name T907
Test name
Test status
Simulation time 44069900 ps
CPU time 109.59 seconds
Started Mar 24 02:31:13 PM PDT 24
Finished Mar 24 02:33:03 PM PDT 24
Peak memory 260928 kb
Host smart-3561656d-772a-48d4-9a62-2bcc52997257
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650479725 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_ot
p_reset.650479725
Directory /workspace/75.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/76.flash_ctrl_connect.874457766
Short name T1056
Test name
Test status
Simulation time 48010800 ps
CPU time 15.82 seconds
Started Mar 24 02:31:16 PM PDT 24
Finished Mar 24 02:31:32 PM PDT 24
Peak memory 275220 kb
Host smart-d379fd0f-2bcc-4527-a6e5-430b6a5ba261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874457766 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.874457766
Directory /workspace/76.flash_ctrl_connect/latest

Test location /workspace/coverage/default/76.flash_ctrl_otp_reset.1454007890
Short name T824
Test name
Test status
Simulation time 159330100 ps
CPU time 133.64 seconds
Started Mar 24 02:31:22 PM PDT 24
Finished Mar 24 02:33:35 PM PDT 24
Peak memory 259756 kb
Host smart-e7316b48-ea21-4d8c-9b5e-2b4e94dc50da
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454007890 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_o
tp_reset.1454007890
Directory /workspace/76.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/77.flash_ctrl_connect.2150877055
Short name T692
Test name
Test status
Simulation time 13214200 ps
CPU time 15.74 seconds
Started Mar 24 02:31:16 PM PDT 24
Finished Mar 24 02:31:32 PM PDT 24
Peak memory 274532 kb
Host smart-38a4aec3-9627-4468-9fbc-73f755718cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150877055 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.2150877055
Directory /workspace/77.flash_ctrl_connect/latest

Test location /workspace/coverage/default/77.flash_ctrl_otp_reset.1375576053
Short name T732
Test name
Test status
Simulation time 125637000 ps
CPU time 131.6 seconds
Started Mar 24 02:31:23 PM PDT 24
Finished Mar 24 02:33:35 PM PDT 24
Peak memory 264292 kb
Host smart-3d26706b-f2ff-48c9-83f5-0ceda0f4d89e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375576053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_o
tp_reset.1375576053
Directory /workspace/77.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/78.flash_ctrl_connect.3640843460
Short name T567
Test name
Test status
Simulation time 22213700 ps
CPU time 13.28 seconds
Started Mar 24 02:31:14 PM PDT 24
Finished Mar 24 02:31:28 PM PDT 24
Peak memory 275188 kb
Host smart-61fe1053-a5aa-4741-b4d0-5069cc660ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640843460 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.3640843460
Directory /workspace/78.flash_ctrl_connect/latest

Test location /workspace/coverage/default/78.flash_ctrl_otp_reset.1170613209
Short name T84
Test name
Test status
Simulation time 77384100 ps
CPU time 111.55 seconds
Started Mar 24 02:31:16 PM PDT 24
Finished Mar 24 02:33:08 PM PDT 24
Peak memory 260780 kb
Host smart-ea02a682-d3d8-42f8-9823-907b83289f77
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170613209 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_o
tp_reset.1170613209
Directory /workspace/78.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/79.flash_ctrl_connect.357222947
Short name T1027
Test name
Test status
Simulation time 47618200 ps
CPU time 15.77 seconds
Started Mar 24 02:31:16 PM PDT 24
Finished Mar 24 02:31:32 PM PDT 24
Peak memory 275168 kb
Host smart-99550609-9b45-42a8-b4b4-217edb98cea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357222947 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.357222947
Directory /workspace/79.flash_ctrl_connect/latest

Test location /workspace/coverage/default/79.flash_ctrl_otp_reset.1234446459
Short name T721
Test name
Test status
Simulation time 83106300 ps
CPU time 111.01 seconds
Started Mar 24 02:31:17 PM PDT 24
Finished Mar 24 02:33:09 PM PDT 24
Peak memory 259616 kb
Host smart-4e884403-0c45-401a-bdae-012413a1ec6b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234446459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_o
tp_reset.1234446459
Directory /workspace/79.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_alert_test.2578299926
Short name T504
Test name
Test status
Simulation time 364837900 ps
CPU time 13.85 seconds
Started Mar 24 02:23:29 PM PDT 24
Finished Mar 24 02:23:43 PM PDT 24
Peak memory 264900 kb
Host smart-c1596eae-ac16-4370-bf7b-4d2b8824b17b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578299926 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.2
578299926
Directory /workspace/8.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.flash_ctrl_connect.557889369
Short name T712
Test name
Test status
Simulation time 29940600 ps
CPU time 13.26 seconds
Started Mar 24 02:23:18 PM PDT 24
Finished Mar 24 02:23:32 PM PDT 24
Peak memory 275076 kb
Host smart-6f1ecfaa-1b39-4151-987c-68611e356544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557889369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.557889369
Directory /workspace/8.flash_ctrl_connect/latest

Test location /workspace/coverage/default/8.flash_ctrl_disable.1452926176
Short name T449
Test name
Test status
Simulation time 28145900 ps
CPU time 21.75 seconds
Started Mar 24 02:23:14 PM PDT 24
Finished Mar 24 02:23:36 PM PDT 24
Peak memory 272944 kb
Host smart-50fd4f7e-fbb8-4f64-8255-1dff3412a321
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452926176 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_disable.1452926176
Directory /workspace/8.flash_ctrl_disable/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_mp.1616356866
Short name T839
Test name
Test status
Simulation time 118921705600 ps
CPU time 2372.85 seconds
Started Mar 24 02:23:03 PM PDT 24
Finished Mar 24 03:02:37 PM PDT 24
Peak memory 264824 kb
Host smart-b648b736-7730-40f8-966c-e2b758f71082
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616356866 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_err
or_mp.1616356866
Directory /workspace/8.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_prog_win.1388908772
Short name T482
Test name
Test status
Simulation time 766429700 ps
CPU time 860.47 seconds
Started Mar 24 02:23:02 PM PDT 24
Finished Mar 24 02:37:23 PM PDT 24
Peak memory 273100 kb
Host smart-387ed46a-49b4-40dd-8f83-d805cbaf0f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388908772 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.1388908772
Directory /workspace/8.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.3988032425
Short name T140
Test name
Test status
Simulation time 10022044800 ps
CPU time 61.41 seconds
Started Mar 24 02:23:24 PM PDT 24
Finished Mar 24 02:24:26 PM PDT 24
Peak memory 271784 kb
Host smart-39ddf6ef-468d-4f28-9bff-77015c15f93d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988032425 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.3988032425
Directory /workspace/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.1709351485
Short name T731
Test name
Test status
Simulation time 23601800 ps
CPU time 13.36 seconds
Started Mar 24 02:23:25 PM PDT 24
Finished Mar 24 02:23:38 PM PDT 24
Peak memory 264900 kb
Host smart-7c91278f-40f4-45a3-a9b3-dc7d3f5333ee
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709351485 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_seed_err.1709351485
Directory /workspace/8.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_rma_reset.4053742557
Short name T954
Test name
Test status
Simulation time 160196440500 ps
CPU time 982.37 seconds
Started Mar 24 02:22:53 PM PDT 24
Finished Mar 24 02:39:16 PM PDT 24
Peak memory 263152 kb
Host smart-038028f4-34c8-4c46-b534-cb2b50a812e6
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053742557 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.flash_ctrl_hw_rma_reset.4053742557
Directory /workspace/8.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_sec_otp.2451738526
Short name T690
Test name
Test status
Simulation time 1219676100 ps
CPU time 106.19 seconds
Started Mar 24 02:22:52 PM PDT 24
Finished Mar 24 02:24:39 PM PDT 24
Peak memory 262412 kb
Host smart-0bf46fbf-06b1-40c3-815d-0bb877dbe8a6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451738526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_h
w_sec_otp.2451738526
Directory /workspace/8.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.643524779
Short name T32
Test name
Test status
Simulation time 19119409300 ps
CPU time 252.5 seconds
Started Mar 24 02:23:08 PM PDT 24
Finished Mar 24 02:27:21 PM PDT 24
Peak memory 284444 kb
Host smart-844b2b3c-c4ad-43cf-9fd6-c71027b11f29
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643524779 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd_slow_flash.643524779
Directory /workspace/8.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr.309243171
Short name T428
Test name
Test status
Simulation time 4177537500 ps
CPU time 95.23 seconds
Started Mar 24 02:23:08 PM PDT 24
Finished Mar 24 02:24:44 PM PDT 24
Peak memory 260944 kb
Host smart-39d72330-80e0-4023-9779-cfc206e89d6a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309243171 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 8.flash_ctrl_intr_wr.309243171
Directory /workspace/8.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr_slow_flash.2263649651
Short name T663
Test name
Test status
Simulation time 709585067800 ps
CPU time 840.99 seconds
Started Mar 24 02:23:09 PM PDT 24
Finished Mar 24 02:37:10 PM PDT 24
Peak memory 260924 kb
Host smart-0bdb51b1-9a43-464a-92b7-22cc504adde1
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226
3649651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.2263649651
Directory /workspace/8.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_invalid_op.201266155
Short name T218
Test name
Test status
Simulation time 6514830200 ps
CPU time 62.4 seconds
Started Mar 24 02:23:03 PM PDT 24
Finished Mar 24 02:24:06 PM PDT 24
Peak memory 260296 kb
Host smart-176ef22b-0f4e-4426-a3ea-456465a9baec
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201266155 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.201266155
Directory /workspace/8.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/8.flash_ctrl_mp_regions.2051017792
Short name T78
Test name
Test status
Simulation time 52992082100 ps
CPU time 429.71 seconds
Started Mar 24 02:22:56 PM PDT 24
Finished Mar 24 02:30:06 PM PDT 24
Peak memory 274372 kb
Host smart-4880cbee-2c27-40ed-bfd4-721c1dfd6d23
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051017792 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 8.flash_ctrl_mp_regions.2051017792
Directory /workspace/8.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/8.flash_ctrl_otp_reset.3083054582
Short name T674
Test name
Test status
Simulation time 44710900 ps
CPU time 132.3 seconds
Started Mar 24 02:22:57 PM PDT 24
Finished Mar 24 02:25:09 PM PDT 24
Peak memory 263444 kb
Host smart-b5bbd708-6bad-43cd-9d31-f8699aa9808e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083054582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ot
p_reset.3083054582
Directory /workspace/8.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_phy_arb.1215171072
Short name T1003
Test name
Test status
Simulation time 66221100 ps
CPU time 362.52 seconds
Started Mar 24 02:22:51 PM PDT 24
Finished Mar 24 02:28:54 PM PDT 24
Peak memory 262228 kb
Host smart-396caa52-9384-4312-8264-17f0e4c5885f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1215171072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.1215171072
Directory /workspace/8.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/8.flash_ctrl_prog_reset.2323121157
Short name T539
Test name
Test status
Simulation time 31096300 ps
CPU time 13.26 seconds
Started Mar 24 02:23:08 PM PDT 24
Finished Mar 24 02:23:21 PM PDT 24
Peak memory 259980 kb
Host smart-a4f1ae2f-c786-4f87-93cf-d860471229c0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323121157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_prog_res
et.2323121157
Directory /workspace/8.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_rand_ops.2494772571
Short name T107
Test name
Test status
Simulation time 997171200 ps
CPU time 1037.65 seconds
Started Mar 24 02:22:52 PM PDT 24
Finished Mar 24 02:40:10 PM PDT 24
Peak memory 285592 kb
Host smart-fcac1c9a-2c72-4b72-a67b-0e8fa59fd226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494772571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.2494772571
Directory /workspace/8.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/8.flash_ctrl_re_evict.4082284255
Short name T549
Test name
Test status
Simulation time 547865200 ps
CPU time 36.99 seconds
Started Mar 24 02:23:13 PM PDT 24
Finished Mar 24 02:23:50 PM PDT 24
Peak memory 273292 kb
Host smart-40fd89ff-b100-4aaa-ac31-3db9daf92d20
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082284255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla
sh_ctrl_re_evict.4082284255
Directory /workspace/8.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro.2693158429
Short name T576
Test name
Test status
Simulation time 1058439000 ps
CPU time 102.56 seconds
Started Mar 24 02:23:04 PM PDT 24
Finished Mar 24 02:24:47 PM PDT 24
Peak memory 280736 kb
Host smart-2b0f587c-9c77-4d59-8733-cecf26db2fb2
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693158429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.flash_ctrl_ro.2693158429
Directory /workspace/8.flash_ctrl_ro/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw.2605457125
Short name T723
Test name
Test status
Simulation time 7271924000 ps
CPU time 557.8 seconds
Started Mar 24 02:23:01 PM PDT 24
Finished Mar 24 02:32:19 PM PDT 24
Peak memory 312420 kb
Host smart-ae7b94d4-5b15-4477-945f-4c0ab5afc5ac
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605457125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ct
rl_rw.2605457125
Directory /workspace/8.flash_ctrl_rw/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict.4250391190
Short name T869
Test name
Test status
Simulation time 51181900 ps
CPU time 33.03 seconds
Started Mar 24 02:23:15 PM PDT 24
Finished Mar 24 02:23:48 PM PDT 24
Peak memory 272468 kb
Host smart-aefb5b01-8179-4c4e-8659-2df8c9bc7113
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250391190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla
sh_ctrl_rw_evict.4250391190
Directory /workspace/8.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict_all_en.1967613191
Short name T782
Test name
Test status
Simulation time 77345300 ps
CPU time 30.54 seconds
Started Mar 24 02:23:15 PM PDT 24
Finished Mar 24 02:23:46 PM PDT 24
Peak memory 267132 kb
Host smart-1a66a0c9-cc0d-4ce0-bba3-cc8d7ea4b586
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967613191 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict_all_en.1967613191
Directory /workspace/8.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/8.flash_ctrl_sec_info_access.2160693419
Short name T381
Test name
Test status
Simulation time 801371800 ps
CPU time 55.39 seconds
Started Mar 24 02:23:16 PM PDT 24
Finished Mar 24 02:24:12 PM PDT 24
Peak memory 263260 kb
Host smart-83d8b47a-2671-4f19-9bfe-8788f674449e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160693419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.2160693419
Directory /workspace/8.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/8.flash_ctrl_smoke.1835450936
Short name T573
Test name
Test status
Simulation time 19361300 ps
CPU time 148.07 seconds
Started Mar 24 02:22:47 PM PDT 24
Finished Mar 24 02:25:16 PM PDT 24
Peak memory 276968 kb
Host smart-5543378e-a4f8-449a-bb58-df86252324a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835450936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.1835450936
Directory /workspace/8.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/8.flash_ctrl_wo.3410834382
Short name T1019
Test name
Test status
Simulation time 2262778600 ps
CPU time 202.54 seconds
Started Mar 24 02:23:01 PM PDT 24
Finished Mar 24 02:26:24 PM PDT 24
Peak memory 264920 kb
Host smart-4e025a9f-ad5b-4dfc-877b-f0f4f938a1d2
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410834382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.flash_ctrl_wo.3410834382
Directory /workspace/8.flash_ctrl_wo/latest

Test location /workspace/coverage/default/9.flash_ctrl_alert_test.2987840437
Short name T457
Test name
Test status
Simulation time 43401900 ps
CPU time 13.95 seconds
Started Mar 24 02:24:00 PM PDT 24
Finished Mar 24 02:24:14 PM PDT 24
Peak memory 257992 kb
Host smart-869bd167-8baf-4c5e-b8f3-660234890248
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987840437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.2
987840437
Directory /workspace/9.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.flash_ctrl_connect.1230334284
Short name T791
Test name
Test status
Simulation time 14754400 ps
CPU time 15.79 seconds
Started Mar 24 02:23:54 PM PDT 24
Finished Mar 24 02:24:10 PM PDT 24
Peak memory 274560 kb
Host smart-61382742-2cbe-416f-96a6-2a6845a97702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230334284 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.1230334284
Directory /workspace/9.flash_ctrl_connect/latest

Test location /workspace/coverage/default/9.flash_ctrl_disable.4155745552
Short name T893
Test name
Test status
Simulation time 31877500 ps
CPU time 20.51 seconds
Started Mar 24 02:23:54 PM PDT 24
Finished Mar 24 02:24:14 PM PDT 24
Peak memory 265116 kb
Host smart-d6acb7ff-213d-4804-8886-4b2177d370ed
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155745552 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_disable.4155745552
Directory /workspace/9.flash_ctrl_disable/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_mp.3032698634
Short name T1006
Test name
Test status
Simulation time 6343186100 ps
CPU time 2463.66 seconds
Started Mar 24 02:23:36 PM PDT 24
Finished Mar 24 03:04:40 PM PDT 24
Peak memory 264856 kb
Host smart-9aa18d6e-5b3c-4d11-8d29-7d609b1eb04b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032698634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_err
or_mp.3032698634
Directory /workspace/9.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_prog_win.3107960213
Short name T959
Test name
Test status
Simulation time 1340231400 ps
CPU time 793.65 seconds
Started Mar 24 02:23:33 PM PDT 24
Finished Mar 24 02:36:47 PM PDT 24
Peak memory 272996 kb
Host smart-59d66ad5-90eb-4a07-919e-802b96d79e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107960213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.3107960213
Directory /workspace/9.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/9.flash_ctrl_fetch_code.2356367027
Short name T892
Test name
Test status
Simulation time 142274100 ps
CPU time 24.57 seconds
Started Mar 24 02:23:34 PM PDT 24
Finished Mar 24 02:23:59 PM PDT 24
Peak memory 264780 kb
Host smart-7ff3ab91-952b-44b9-99b6-71423be0af4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356367027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetch_code.2356367027
Directory /workspace/9.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.1632831679
Short name T957
Test name
Test status
Simulation time 18685900 ps
CPU time 13.58 seconds
Started Mar 24 02:24:01 PM PDT 24
Finished Mar 24 02:24:14 PM PDT 24
Peak memory 264916 kb
Host smart-15e42280-1940-4eac-89ed-5f635437b0c7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632831679 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_seed_err.1632831679
Directory /workspace/9.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_rma_reset.3155170136
Short name T724
Test name
Test status
Simulation time 160187016600 ps
CPU time 926.1 seconds
Started Mar 24 02:23:29 PM PDT 24
Finished Mar 24 02:38:56 PM PDT 24
Peak memory 262660 kb
Host smart-63c91039-30ae-4b48-b502-60e8bfc5d7c7
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155170136 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.flash_ctrl_hw_rma_reset.3155170136
Directory /workspace/9.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_sec_otp.2568712920
Short name T804
Test name
Test status
Simulation time 2611542900 ps
CPU time 120.4 seconds
Started Mar 24 02:23:29 PM PDT 24
Finished Mar 24 02:25:30 PM PDT 24
Peak memory 262476 kb
Host smart-b5417a2b-2336-4b8a-8153-1e3cefdeac0c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568712920 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_h
w_sec_otp.2568712920
Directory /workspace/9.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.905368531
Short name T972
Test name
Test status
Simulation time 38814832800 ps
CPU time 214.55 seconds
Started Mar 24 02:23:51 PM PDT 24
Finished Mar 24 02:27:26 PM PDT 24
Peak memory 289508 kb
Host smart-701a3a1e-d398-4ed1-9a27-552f0489e9bd
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905368531 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd_slow_flash.905368531
Directory /workspace/9.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr.3696225209
Short name T24
Test name
Test status
Simulation time 50068020100 ps
CPU time 131.88 seconds
Started Mar 24 02:23:41 PM PDT 24
Finished Mar 24 02:25:53 PM PDT 24
Peak memory 260952 kb
Host smart-c649fc97-9d59-40c6-a812-2d78631a707b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696225209 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.flash_ctrl_intr_wr.3696225209
Directory /workspace/9.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr_slow_flash.586613329
Short name T557
Test name
Test status
Simulation time 575348314800 ps
CPU time 486.04 seconds
Started Mar 24 02:23:50 PM PDT 24
Finished Mar 24 02:31:56 PM PDT 24
Peak memory 261384 kb
Host smart-0957649b-0c88-4c37-99f1-63fe74d09136
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586
613329 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.586613329
Directory /workspace/9.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_invalid_op.1661992476
Short name T219
Test name
Test status
Simulation time 3246344600 ps
CPU time 74.36 seconds
Started Mar 24 02:23:35 PM PDT 24
Finished Mar 24 02:24:50 PM PDT 24
Peak memory 260264 kb
Host smart-7a31fcb0-4fb8-4d68-9bcf-c3c3c0cde38e
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661992476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.1661992476
Directory /workspace/9.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/9.flash_ctrl_lcmgr_intg.3775888908
Short name T459
Test name
Test status
Simulation time 54960200 ps
CPU time 13.5 seconds
Started Mar 24 02:23:59 PM PDT 24
Finished Mar 24 02:24:12 PM PDT 24
Peak memory 264896 kb
Host smart-fadbb1da-abca-41f2-ac26-0bd418b605b2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775888908 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.flash_ctrl_lcmgr_intg.3775888908
Directory /workspace/9.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/9.flash_ctrl_mp_regions.1156102970
Short name T95
Test name
Test status
Simulation time 31498209600 ps
CPU time 593.71 seconds
Started Mar 24 02:23:29 PM PDT 24
Finished Mar 24 02:33:23 PM PDT 24
Peak memory 274268 kb
Host smart-208c2c45-c4e3-4ff0-af61-fd3483cbb2f0
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156102970 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.flash_ctrl_mp_regions.1156102970
Directory /workspace/9.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/9.flash_ctrl_otp_reset.3900103228
Short name T885
Test name
Test status
Simulation time 44686000 ps
CPU time 129.82 seconds
Started Mar 24 02:23:30 PM PDT 24
Finished Mar 24 02:25:40 PM PDT 24
Peak memory 260632 kb
Host smart-bfc6e7c6-2551-4f3e-a97b-a2e2a92d20ef
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900103228 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ot
p_reset.3900103228
Directory /workspace/9.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_phy_arb.976297557
Short name T696
Test name
Test status
Simulation time 48084800 ps
CPU time 67.83 seconds
Started Mar 24 02:23:30 PM PDT 24
Finished Mar 24 02:24:38 PM PDT 24
Peak memory 261404 kb
Host smart-e3465f7e-2487-4d3d-8250-82fff1b84f4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=976297557 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.976297557
Directory /workspace/9.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/9.flash_ctrl_prog_reset.3228927517
Short name T433
Test name
Test status
Simulation time 36612000 ps
CPU time 13.39 seconds
Started Mar 24 02:23:52 PM PDT 24
Finished Mar 24 02:24:05 PM PDT 24
Peak memory 264924 kb
Host smart-974ccc86-a20c-413d-a776-0276dbeab163
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228927517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_prog_res
et.3228927517
Directory /workspace/9.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_rand_ops.1301930785
Short name T489
Test name
Test status
Simulation time 210939300 ps
CPU time 1216.92 seconds
Started Mar 24 02:23:30 PM PDT 24
Finished Mar 24 02:43:47 PM PDT 24
Peak memory 286232 kb
Host smart-9517964e-a721-4842-b9bc-49caf81df242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301930785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.1301930785
Directory /workspace/9.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/9.flash_ctrl_re_evict.4213338122
Short name T879
Test name
Test status
Simulation time 453163600 ps
CPU time 37.49 seconds
Started Mar 24 02:23:53 PM PDT 24
Finished Mar 24 02:24:31 PM PDT 24
Peak memory 273272 kb
Host smart-3c056d5e-769e-4048-8546-10c4903f8ed8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213338122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla
sh_ctrl_re_evict.4213338122
Directory /workspace/9.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro.2652062322
Short name T921
Test name
Test status
Simulation time 441055600 ps
CPU time 93.36 seconds
Started Mar 24 02:23:35 PM PDT 24
Finished Mar 24 02:25:08 PM PDT 24
Peak memory 280888 kb
Host smart-27abb7bd-cd2e-4a02-b994-502c5882d191
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652062322 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.flash_ctrl_ro.2652062322
Directory /workspace/9.flash_ctrl_ro/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw.3591299387
Short name T671
Test name
Test status
Simulation time 10342226500 ps
CPU time 406.46 seconds
Started Mar 24 02:23:34 PM PDT 24
Finished Mar 24 02:30:20 PM PDT 24
Peak memory 309400 kb
Host smart-13d2e609-89b3-47e3-a89e-b6124014ffcb
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591299387 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ct
rl_rw.3591299387
Directory /workspace/9.flash_ctrl_rw/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict.3993934347
Short name T664
Test name
Test status
Simulation time 31989600 ps
CPU time 30.74 seconds
Started Mar 24 02:23:51 PM PDT 24
Finished Mar 24 02:24:22 PM PDT 24
Peak memory 267136 kb
Host smart-b0f77442-d075-431f-8558-a3c2e7a56cea
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993934347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla
sh_ctrl_rw_evict.3993934347
Directory /workspace/9.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict_all_en.2874853148
Short name T50
Test name
Test status
Simulation time 42022300 ps
CPU time 30.93 seconds
Started Mar 24 02:23:49 PM PDT 24
Finished Mar 24 02:24:20 PM PDT 24
Peak memory 273304 kb
Host smart-8be8d44c-2f0b-4852-a4fd-9b5be372c67f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874853148 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict_all_en.2874853148
Directory /workspace/9.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/9.flash_ctrl_sec_info_access.3357330786
Short name T647
Test name
Test status
Simulation time 1413543400 ps
CPU time 64.15 seconds
Started Mar 24 02:23:55 PM PDT 24
Finished Mar 24 02:25:00 PM PDT 24
Peak memory 262676 kb
Host smart-52da9a13-facc-4a3f-b1eb-f22c95a4cf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357330786 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.3357330786
Directory /workspace/9.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/9.flash_ctrl_smoke.4195956164
Short name T630
Test name
Test status
Simulation time 29350800 ps
CPU time 123.64 seconds
Started Mar 24 02:23:29 PM PDT 24
Finished Mar 24 02:25:33 PM PDT 24
Peak memory 276328 kb
Host smart-38db17ae-37a4-4d20-a8a6-5eaae406e460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195956164 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.4195956164
Directory /workspace/9.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/9.flash_ctrl_wo.1630122212
Short name T966
Test name
Test status
Simulation time 1970635300 ps
CPU time 135.79 seconds
Started Mar 24 02:23:34 PM PDT 24
Finished Mar 24 02:25:50 PM PDT 24
Peak memory 259764 kb
Host smart-f35cad9c-24eb-41d2-9110-9c1494ca2c52
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630122212 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.flash_ctrl_wo.1630122212
Directory /workspace/9.flash_ctrl_wo/latest
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