Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	145841	1		T1	1		T2	2		T13	1
all_values[1]	145841	1		T1	1		T2	2		T13	1
all_values[2]	145841	1		T1	1		T2	2		T13	1
all_values[3]	145841	1		T1	1		T2	2		T13	1
all_values[4]	145841	1		T1	1		T2	2		T13	1
all_values[5]	145841	1		T1	1		T2	2		T13	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	297657	1		T1	6		T2	12		T13	6
auto[1]	577389	1		T22	3828		T27	4444		T37	13776

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	430168	1		T1	4		T2	7		T13	4
auto[1]	444878	1		T1	2		T2	5		T13	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	145672	1		T1	1		T2	2		T13	1
all_values[0]	auto[1]	auto[1]	169	1		T279	3		T280	1		T281	4
all_values[1]	auto[0]	auto[1]	145684	1		T1	1		T2	2		T13	1
all_values[1]	auto[1]	auto[1]	157	1		T279	4		T280	6		T281	3
all_values[2]	auto[0]	auto[0]	1510	1		T1	1		T2	2		T13	1
all_values[2]	auto[0]	auto[1]	48	1		T279	1		T280	3		T342	2
all_values[2]	auto[1]	auto[0]	144216	1		T22	957		T27	1111		T37	3444
all_values[2]	auto[1]	auto[1]	67	1		T279	1		T280	2		T281	1
all_values[3]	auto[0]	auto[0]	1530	1		T1	1		T2	2		T13	1
all_values[3]	auto[0]	auto[1]	52	1		T279	3		T280	3		T340	1
all_values[3]	auto[1]	auto[0]	50534	1		T22	957		T27	1111		T37	861
all_values[3]	auto[1]	auto[1]	93725	1		T37	2583		T32	670		T38	6339
all_values[4]	auto[0]	auto[0]	1066	1		T1	1		T2	1		T13	1
all_values[4]	auto[0]	auto[1]	514	1		T2	1		T4	1		T35	1
all_values[4]	auto[1]	auto[0]	85644	1		T22	1		T27	1		T37	2583
all_values[4]	auto[1]	auto[1]	58617	1		T22	956		T27	1110		T37	861
all_values[5]	auto[0]	auto[0]	1471	1		T1	1		T2	2		T13	1
all_values[5]	auto[0]	auto[1]	110	1		T39	1		T40	1		T41	1
all_values[5]	auto[1]	auto[0]	144197	1		T22	957		T27	1111		T37	3444
all_values[5]	auto[1]	auto[1]	63	1		T281	1		T340	1		T342	3