Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1249 |
1 |
|
T2 |
1 |
|
T43 |
1 |
|
T20 |
5 |
| others[1] |
1285 |
1 |
|
T3 |
1 |
|
T43 |
1 |
|
T20 |
4 |
| others[2] |
1220 |
1 |
|
T43 |
3 |
|
T20 |
2 |
|
T8 |
11 |
| others[3] |
2075 |
1 |
|
T35 |
1 |
|
T43 |
3 |
|
T20 |
4 |
| false |
654 |
1 |
|
T8 |
6 |
|
T21 |
2 |
|
T124 |
1 |
| true |
342 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
109 |
1 |
|
T20 |
3 |
|
T251 |
1 |
|
T389 |
1 |
| others[1] |
106 |
1 |
|
T20 |
3 |
|
T78 |
1 |
|
T388 |
1 |
| others[2] |
102 |
1 |
|
T20 |
5 |
|
T206 |
1 |
|
T210 |
1 |
| others[3] |
184 |
1 |
|
T20 |
2 |
|
T55 |
1 |
|
T251 |
1 |
| false |
54 |
1 |
|
T20 |
2 |
|
T90 |
2 |
|
T114 |
4 |
| true |
6270 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
209 |
1 |
|
T20 |
3 |
|
T52 |
1 |
|
T222 |
1 |
| others[1] |
242 |
1 |
|
T20 |
3 |
|
T290 |
1 |
|
T90 |
17 |
| others[2] |
236 |
1 |
|
T20 |
2 |
|
T210 |
1 |
|
T388 |
1 |
| others[3] |
381 |
1 |
|
T35 |
1 |
|
T20 |
3 |
|
T26 |
1 |
| false |
127 |
1 |
|
T251 |
1 |
|
T90 |
6 |
|
T114 |
4 |
| true |
5630 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1016 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T43 |
2 |
| others[1] |
1099 |
1 |
|
T43 |
3 |
|
T20 |
4 |
|
T8 |
12 |
| others[2] |
1067 |
1 |
|
T43 |
1 |
|
T20 |
1 |
|
T8 |
10 |
| others[3] |
1772 |
1 |
|
T2 |
1 |
|
T43 |
2 |
|
T20 |
6 |
| false |
517 |
1 |
|
T35 |
1 |
|
T20 |
2 |
|
T8 |
5 |
| true |
1354 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T58 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
206 |
1 |
|
T20 |
2 |
|
T36 |
1 |
|
T387 |
1 |
| others[1] |
216 |
1 |
|
T19 |
1 |
|
T20 |
1 |
|
T24 |
1 |
| others[2] |
230 |
1 |
|
T35 |
1 |
|
T20 |
2 |
|
T23 |
1 |
| others[3] |
374 |
1 |
|
T20 |
2 |
|
T39 |
1 |
|
T78 |
1 |
| false |
128 |
1 |
|
T165 |
1 |
|
T251 |
1 |
|
T90 |
8 |
| true |
5671 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T20 |
3 |
|
T90 |
6 |
|
T114 |
10 |
| others[1] |
226 |
1 |
|
T20 |
2 |
|
T90 |
12 |
|
T114 |
12 |
| others[2] |
222 |
1 |
|
T19 |
1 |
|
T39 |
1 |
|
T290 |
1 |
| others[3] |
325 |
1 |
|
T20 |
2 |
|
T165 |
1 |
|
T319 |
1 |
| false |
118 |
1 |
|
T90 |
5 |
|
T114 |
8 |
|
T91 |
6 |
| true |
5718 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1312 |
1 |
|
T43 |
1 |
|
T20 |
4 |
|
T8 |
11 |
| others[1] |
1275 |
1 |
|
T43 |
3 |
|
T20 |
2 |
|
T8 |
14 |
| others[2] |
1308 |
1 |
|
T2 |
1 |
|
T35 |
1 |
|
T43 |
3 |
| others[3] |
1929 |
1 |
|
T3 |
1 |
|
T20 |
5 |
|
T8 |
11 |
| false |
642 |
1 |
|
T43 |
1 |
|
T20 |
2 |
|
T8 |
8 |
| true |
359 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1278 |
1 |
|
T3 |
1 |
|
T35 |
1 |
|
T43 |
2 |
| others[1] |
1172 |
1 |
|
T20 |
3 |
|
T8 |
10 |
|
T22 |
1 |
| others[2] |
1261 |
1 |
|
T20 |
4 |
|
T8 |
14 |
|
T21 |
6 |
| others[3] |
2139 |
1 |
|
T2 |
1 |
|
T43 |
4 |
|
T20 |
5 |
| false |
633 |
1 |
|
T43 |
2 |
|
T20 |
1 |
|
T8 |
5 |
| true |
342 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
92 |
1 |
|
T20 |
5 |
|
T206 |
1 |
|
T210 |
1 |
| others[1] |
104 |
1 |
|
T20 |
4 |
|
T90 |
5 |
|
T114 |
5 |
| others[2] |
103 |
1 |
|
T20 |
3 |
|
T251 |
1 |
|
T387 |
2 |
| others[3] |
182 |
1 |
|
T35 |
1 |
|
T20 |
3 |
|
T165 |
1 |
| false |
64 |
1 |
|
T90 |
3 |
|
T114 |
2 |
|
T91 |
5 |
| true |
6280 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T23 |
1 |
|
T39 |
1 |
|
T33 |
1 |
| others[1] |
208 |
1 |
|
T19 |
1 |
|
T20 |
2 |
|
T55 |
1 |
| others[2] |
227 |
1 |
|
T20 |
1 |
|
T40 |
1 |
|
T251 |
1 |
| others[3] |
379 |
1 |
|
T20 |
3 |
|
T24 |
1 |
|
T52 |
1 |
| false |
121 |
1 |
|
T90 |
4 |
|
T114 |
4 |
|
T91 |
5 |
| true |
5662 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
959 |
1 |
|
T43 |
3 |
|
T20 |
2 |
|
T8 |
8 |
| others[1] |
1100 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T43 |
2 |
| others[2] |
1088 |
1 |
|
T43 |
1 |
|
T20 |
3 |
|
T8 |
8 |
| others[3] |
1783 |
1 |
|
T3 |
1 |
|
T43 |
2 |
|
T20 |
3 |
| false |
534 |
1 |
|
T35 |
1 |
|
T20 |
3 |
|
T8 |
9 |
| true |
1361 |
1 |
|
T17 |
1 |
|
T19 |
1 |
|
T58 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
252 |
1 |
|
T20 |
1 |
|
T222 |
1 |
|
T392 |
1 |
| others[1] |
229 |
1 |
|
T55 |
1 |
|
T25 |
1 |
|
T290 |
1 |
| others[2] |
222 |
1 |
|
T20 |
1 |
|
T387 |
1 |
|
T90 |
10 |
| others[3] |
356 |
1 |
|
T20 |
3 |
|
T24 |
1 |
|
T36 |
1 |
| false |
113 |
1 |
|
T391 |
1 |
|
T90 |
9 |
|
T114 |
6 |
| true |
5653 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T20 |
1 |
|
T392 |
1 |
|
T387 |
1 |
| others[1] |
213 |
1 |
|
T35 |
1 |
|
T20 |
1 |
|
T290 |
1 |
| others[2] |
207 |
1 |
|
T20 |
1 |
|
T55 |
1 |
|
T90 |
12 |
| others[3] |
369 |
1 |
|
T20 |
4 |
|
T40 |
1 |
|
T78 |
1 |
| false |
90 |
1 |
|
T165 |
1 |
|
T89 |
1 |
|
T90 |
4 |
| true |
5720 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1230 |
1 |
|
T3 |
1 |
|
T43 |
1 |
|
T20 |
1 |
| others[1] |
1249 |
1 |
|
T43 |
2 |
|
T20 |
5 |
|
T8 |
11 |
| others[2] |
1197 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T43 |
1 |
| others[3] |
2134 |
1 |
|
T35 |
1 |
|
T43 |
4 |
|
T20 |
6 |
| false |
640 |
1 |
|
T20 |
1 |
|
T8 |
9 |
|
T21 |
2 |
| true |
375 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T58 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1207 |
1 |
|
T35 |
1 |
|
T43 |
1 |
|
T20 |
5 |
| others[1] |
1217 |
1 |
|
T43 |
2 |
|
T20 |
2 |
|
T8 |
12 |
| others[2] |
1283 |
1 |
|
T2 |
1 |
|
T43 |
3 |
|
T20 |
2 |
| others[3] |
2142 |
1 |
|
T3 |
1 |
|
T43 |
1 |
|
T20 |
6 |
| false |
637 |
1 |
|
T43 |
1 |
|
T8 |
4 |
|
T21 |
4 |
| true |
339 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
85 |
1 |
|
T387 |
1 |
|
T90 |
2 |
|
T114 |
6 |
| others[1] |
96 |
1 |
|
T20 |
2 |
|
T78 |
1 |
|
T90 |
4 |
| others[2] |
103 |
1 |
|
T20 |
4 |
|
T206 |
1 |
|
T389 |
1 |
| others[3] |
161 |
1 |
|
T20 |
3 |
|
T391 |
1 |
|
T210 |
1 |
| false |
59 |
1 |
|
T35 |
1 |
|
T20 |
6 |
|
T90 |
1 |
| true |
6321 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
252 |
1 |
|
T20 |
1 |
|
T23 |
1 |
|
T26 |
1 |
| others[1] |
187 |
1 |
|
T20 |
1 |
|
T165 |
1 |
|
T394 |
1 |
| others[2] |
218 |
1 |
|
T36 |
1 |
|
T251 |
1 |
|
T388 |
1 |
| others[3] |
396 |
1 |
|
T35 |
1 |
|
T20 |
4 |
|
T52 |
1 |
| false |
115 |
1 |
|
T119 |
1 |
|
T177 |
1 |
|
T90 |
3 |
| true |
5657 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1048 |
1 |
|
T3 |
1 |
|
T19 |
1 |
|
T43 |
3 |
| others[1] |
1068 |
1 |
|
T43 |
2 |
|
T20 |
3 |
|
T8 |
6 |
| others[2] |
998 |
1 |
|
T2 |
1 |
|
T35 |
1 |
|
T20 |
2 |
| others[3] |
1775 |
1 |
|
T43 |
3 |
|
T20 |
6 |
|
T8 |
29 |
| false |
574 |
1 |
|
T20 |
3 |
|
T8 |
7 |
|
T21 |
6 |
| true |
1362 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T55 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T20 |
2 |
|
T36 |
1 |
|
T40 |
1 |
| others[1] |
233 |
1 |
|
T20 |
1 |
|
T23 |
1 |
|
T176 |
1 |
| others[2] |
218 |
1 |
|
T90 |
5 |
|
T104 |
1 |
|
T114 |
11 |
| others[3] |
347 |
1 |
|
T20 |
2 |
|
T55 |
1 |
|
T165 |
1 |
| false |
96 |
1 |
|
T388 |
1 |
|
T177 |
1 |
|
T387 |
1 |
| true |
5692 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
213 |
1 |
|
T19 |
1 |
|
T20 |
1 |
|
T90 |
9 |
| others[1] |
226 |
1 |
|
T20 |
2 |
|
T319 |
1 |
|
T89 |
1 |
| others[2] |
211 |
1 |
|
T20 |
1 |
|
T212 |
1 |
|
T395 |
1 |
| others[3] |
366 |
1 |
|
T20 |
1 |
|
T55 |
1 |
|
T39 |
1 |
| false |
137 |
1 |
|
T20 |
2 |
|
T90 |
6 |
|
T114 |
5 |
| true |
5672 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1274 |
1 |
|
T35 |
1 |
|
T43 |
1 |
|
T20 |
2 |
| others[1] |
1215 |
1 |
|
T43 |
2 |
|
T20 |
3 |
|
T8 |
13 |
| others[2] |
1216 |
1 |
|
T2 |
1 |
|
T43 |
2 |
|
T20 |
2 |
| others[3] |
2098 |
1 |
|
T3 |
1 |
|
T43 |
2 |
|
T20 |
7 |
| false |
662 |
1 |
|
T43 |
1 |
|
T20 |
1 |
|
T8 |
4 |
| true |
360 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1242 |
1 |
|
T3 |
1 |
|
T43 |
2 |
|
T20 |
1 |
| others[1] |
1236 |
1 |
|
T35 |
1 |
|
T43 |
1 |
|
T20 |
1 |
| others[2] |
1271 |
1 |
|
T43 |
1 |
|
T20 |
4 |
|
T8 |
12 |
| others[3] |
2037 |
1 |
|
T2 |
1 |
|
T43 |
3 |
|
T20 |
6 |
| false |
689 |
1 |
|
T43 |
1 |
|
T20 |
3 |
|
T8 |
8 |
| true |
350 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
90 |
1 |
|
T251 |
1 |
|
T387 |
1 |
|
T90 |
5 |
| others[1] |
107 |
1 |
|
T20 |
5 |
|
T206 |
1 |
|
T90 |
4 |
| others[2] |
103 |
1 |
|
T20 |
6 |
|
T389 |
1 |
|
T387 |
1 |
| others[3] |
181 |
1 |
|
T20 |
2 |
|
T388 |
1 |
|
T395 |
1 |
| false |
50 |
1 |
|
T20 |
2 |
|
T210 |
1 |
|
T251 |
1 |
| true |
6294 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T52 |
1 |
|
T392 |
1 |
|
T119 |
1 |
| others[1] |
236 |
1 |
|
T20 |
1 |
|
T23 |
1 |
|
T206 |
1 |
| others[2] |
209 |
1 |
|
T20 |
2 |
|
T55 |
1 |
|
T24 |
1 |
| others[3] |
374 |
1 |
|
T20 |
3 |
|
T222 |
1 |
|
T77 |
1 |
| false |
129 |
1 |
|
T20 |
1 |
|
T25 |
1 |
|
T210 |
1 |
| true |
5653 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1071 |
1 |
|
T2 |
1 |
|
T43 |
1 |
|
T20 |
2 |
| others[1] |
1029 |
1 |
|
T4 |
1 |
|
T43 |
1 |
|
T20 |
5 |
| others[2] |
1025 |
1 |
|
T3 |
1 |
|
T19 |
1 |
|
T35 |
1 |
| others[3] |
1757 |
1 |
|
T20 |
6 |
|
T8 |
15 |
|
T55 |
1 |
| false |
547 |
1 |
|
T43 |
3 |
|
T20 |
1 |
|
T8 |
3 |
| true |
1396 |
1 |
|
T17 |
1 |
|
T58 |
1 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
222 |
1 |
|
T20 |
1 |
|
T40 |
1 |
|
T90 |
11 |
| others[1] |
220 |
1 |
|
T20 |
1 |
|
T25 |
1 |
|
T290 |
1 |
| others[2] |
228 |
1 |
|
T35 |
1 |
|
T20 |
3 |
|
T39 |
1 |
| others[3] |
371 |
1 |
|
T19 |
1 |
|
T20 |
4 |
|
T24 |
1 |
| false |
113 |
1 |
|
T89 |
1 |
|
T90 |
6 |
|
T114 |
5 |
| true |
5671 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
230 |
1 |
|
T36 |
1 |
|
T392 |
1 |
|
T391 |
1 |
| others[1] |
216 |
1 |
|
T20 |
4 |
|
T90 |
14 |
|
T114 |
10 |
| others[2] |
229 |
1 |
|
T319 |
1 |
|
T90 |
7 |
|
T114 |
8 |
| others[3] |
322 |
1 |
|
T20 |
2 |
|
T55 |
1 |
|
T90 |
18 |
| false |
109 |
1 |
|
T20 |
1 |
|
T90 |
2 |
|
T114 |
8 |
| true |
5719 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1286 |
1 |
|
T43 |
2 |
|
T20 |
4 |
|
T8 |
9 |
| others[1] |
1213 |
1 |
|
T20 |
2 |
|
T8 |
7 |
|
T21 |
7 |
| others[2] |
1271 |
1 |
|
T35 |
1 |
|
T43 |
2 |
|
T20 |
3 |
| others[3] |
2041 |
1 |
|
T2 |
1 |
|
T43 |
4 |
|
T20 |
2 |
| false |
651 |
1 |
|
T3 |
1 |
|
T20 |
4 |
|
T8 |
6 |
| true |
363 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1276 |
1 |
|
T19 |
1 |
|
T35 |
1 |
|
T43 |
1 |
| others[1] |
1333 |
1 |
|
T43 |
2 |
|
T20 |
3 |
|
T8 |
9 |
| others[2] |
1195 |
1 |
|
T43 |
1 |
|
T20 |
2 |
|
T8 |
10 |
| others[3] |
2006 |
1 |
|
T2 |
1 |
|
T43 |
3 |
|
T20 |
7 |
| false |
671 |
1 |
|
T3 |
1 |
|
T43 |
1 |
|
T20 |
1 |
| true |
344 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T58 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
97 |
1 |
|
T20 |
2 |
|
T90 |
7 |
|
T114 |
3 |
| others[1] |
113 |
1 |
|
T20 |
4 |
|
T251 |
1 |
|
T90 |
1 |
| others[2] |
96 |
1 |
|
T20 |
4 |
|
T210 |
1 |
|
T388 |
1 |
| others[3] |
151 |
1 |
|
T20 |
3 |
|
T78 |
1 |
|
T206 |
1 |
| false |
51 |
1 |
|
T20 |
2 |
|
T389 |
1 |
|
T90 |
5 |
| true |
6317 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
219 |
1 |
|
T78 |
1 |
|
T251 |
1 |
|
T395 |
1 |
| others[1] |
222 |
1 |
|
T20 |
2 |
|
T394 |
1 |
|
T388 |
1 |
| others[2] |
226 |
1 |
|
T20 |
1 |
|
T90 |
9 |
|
T114 |
11 |
| others[3] |
395 |
1 |
|
T20 |
2 |
|
T24 |
1 |
|
T25 |
1 |
| false |
109 |
1 |
|
T20 |
1 |
|
T222 |
1 |
|
T90 |
7 |
| true |
5654 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |