Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1077 |
1 |
|
T2 |
1 |
|
T43 |
2 |
|
T20 |
2 |
| others[1] |
1030 |
1 |
|
T17 |
1 |
|
T43 |
2 |
|
T20 |
3 |
| others[2] |
1035 |
1 |
|
T43 |
3 |
|
T20 |
5 |
|
T8 |
10 |
| others[3] |
1817 |
1 |
|
T3 |
1 |
|
T35 |
1 |
|
T43 |
1 |
| false |
543 |
1 |
|
T20 |
1 |
|
T8 |
5 |
|
T21 |
3 |
| true |
1323 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T58 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
255 |
1 |
|
T20 |
1 |
|
T25 |
1 |
|
T392 |
1 |
| others[1] |
232 |
1 |
|
T20 |
1 |
|
T251 |
1 |
|
T177 |
1 |
| others[2] |
205 |
1 |
|
T20 |
1 |
|
T90 |
14 |
|
T114 |
7 |
| others[3] |
348 |
1 |
|
T20 |
1 |
|
T23 |
1 |
|
T165 |
1 |
| false |
131 |
1 |
|
T19 |
1 |
|
T90 |
2 |
|
T114 |
4 |
| true |
5654 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T20 |
2 |
|
T210 |
1 |
|
T389 |
1 |
| others[1] |
228 |
1 |
|
T20 |
1 |
|
T78 |
1 |
|
T90 |
11 |
| others[2] |
198 |
1 |
|
T20 |
3 |
|
T251 |
1 |
|
T387 |
1 |
| others[3] |
336 |
1 |
|
T35 |
1 |
|
T20 |
1 |
|
T39 |
1 |
| false |
119 |
1 |
|
T20 |
1 |
|
T392 |
1 |
|
T251 |
1 |
| true |
5713 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1275 |
1 |
|
T43 |
1 |
|
T8 |
12 |
|
T21 |
10 |
| others[1] |
1225 |
1 |
|
T2 |
1 |
|
T43 |
1 |
|
T8 |
12 |
| others[2] |
1255 |
1 |
|
T43 |
5 |
|
T20 |
4 |
|
T8 |
12 |
| others[3] |
2054 |
1 |
|
T43 |
1 |
|
T20 |
7 |
|
T8 |
18 |
| false |
655 |
1 |
|
T3 |
1 |
|
T35 |
1 |
|
T20 |
4 |
| true |
361 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1249 |
1 |
|
T35 |
1 |
|
T43 |
2 |
|
T20 |
2 |
| others[1] |
1292 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T19 |
1 |
| others[2] |
1199 |
1 |
|
T43 |
1 |
|
T20 |
4 |
|
T8 |
11 |
| others[3] |
2092 |
1 |
|
T43 |
1 |
|
T20 |
6 |
|
T8 |
19 |
| false |
644 |
1 |
|
T20 |
1 |
|
T8 |
11 |
|
T21 |
3 |
| true |
349 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T58 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
94 |
1 |
|
T20 |
2 |
|
T210 |
1 |
|
T388 |
1 |
| others[1] |
120 |
1 |
|
T20 |
7 |
|
T251 |
1 |
|
T90 |
8 |
| others[2] |
109 |
1 |
|
T20 |
1 |
|
T206 |
1 |
|
T90 |
5 |
| others[3] |
179 |
1 |
|
T20 |
4 |
|
T251 |
1 |
|
T90 |
8 |
| false |
51 |
1 |
|
T35 |
1 |
|
T20 |
1 |
|
T36 |
1 |
| true |
6272 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
237 |
1 |
|
T20 |
2 |
|
T322 |
1 |
|
T319 |
1 |
| others[1] |
243 |
1 |
|
T23 |
1 |
|
T26 |
1 |
|
T36 |
1 |
| others[2] |
217 |
1 |
|
T20 |
1 |
|
T39 |
1 |
|
T392 |
1 |
| others[3] |
347 |
1 |
|
T20 |
1 |
|
T77 |
1 |
|
T78 |
1 |
| false |
117 |
1 |
|
T35 |
1 |
|
T20 |
1 |
|
T55 |
1 |
| true |
5664 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1057 |
1 |
|
T43 |
3 |
|
T20 |
3 |
|
T8 |
12 |
| others[1] |
1043 |
1 |
|
T4 |
1 |
|
T43 |
1 |
|
T20 |
4 |
| others[2] |
1009 |
1 |
|
T43 |
2 |
|
T20 |
2 |
|
T8 |
12 |
| others[3] |
1790 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T35 |
1 |
| false |
559 |
1 |
|
T43 |
1 |
|
T20 |
3 |
|
T8 |
4 |
| true |
1367 |
1 |
|
T17 |
1 |
|
T19 |
1 |
|
T23 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
208 |
1 |
|
T20 |
2 |
|
T290 |
1 |
|
T319 |
1 |
| others[1] |
205 |
1 |
|
T20 |
2 |
|
T39 |
1 |
|
T89 |
1 |
| others[2] |
226 |
1 |
|
T251 |
1 |
|
T389 |
1 |
|
T90 |
10 |
| others[3] |
399 |
1 |
|
T19 |
1 |
|
T20 |
5 |
|
T55 |
1 |
| false |
105 |
1 |
|
T20 |
1 |
|
T23 |
1 |
|
T90 |
3 |
| true |
5682 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T20 |
1 |
|
T39 |
1 |
|
T177 |
1 |
| others[1] |
218 |
1 |
|
T20 |
1 |
|
T40 |
1 |
|
T392 |
1 |
| others[2] |
222 |
1 |
|
T20 |
3 |
|
T78 |
1 |
|
T210 |
1 |
| others[3] |
348 |
1 |
|
T36 |
1 |
|
T165 |
1 |
|
T391 |
1 |
| false |
102 |
1 |
|
T20 |
1 |
|
T90 |
7 |
|
T114 |
5 |
| true |
5719 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1251 |
1 |
|
T43 |
1 |
|
T20 |
4 |
|
T8 |
10 |
| others[1] |
1280 |
1 |
|
T35 |
1 |
|
T43 |
1 |
|
T20 |
4 |
| others[2] |
1282 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T43 |
2 |
| others[3] |
1985 |
1 |
|
T43 |
4 |
|
T20 |
3 |
|
T8 |
18 |
| false |
648 |
1 |
|
T20 |
1 |
|
T8 |
4 |
|
T21 |
1 |
| true |
379 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1249 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T35 |
1 |
| others[1] |
1241 |
1 |
|
T3 |
1 |
|
T20 |
5 |
|
T8 |
11 |
| others[2] |
1243 |
1 |
|
T43 |
3 |
|
T20 |
1 |
|
T8 |
11 |
| others[3] |
2114 |
1 |
|
T43 |
2 |
|
T20 |
7 |
|
T8 |
16 |
| false |
631 |
1 |
|
T43 |
1 |
|
T8 |
4 |
|
T55 |
1 |
| true |
347 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T58 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
82 |
1 |
|
T20 |
2 |
|
T388 |
1 |
|
T387 |
1 |
| others[1] |
116 |
1 |
|
T20 |
1 |
|
T251 |
1 |
|
T90 |
5 |
| others[2] |
102 |
1 |
|
T20 |
2 |
|
T177 |
1 |
|
T90 |
5 |
| others[3] |
186 |
1 |
|
T20 |
8 |
|
T78 |
1 |
|
T206 |
1 |
| false |
63 |
1 |
|
T20 |
2 |
|
T90 |
7 |
|
T114 |
1 |
| true |
6276 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
238 |
1 |
|
T25 |
1 |
|
T26 |
1 |
|
T119 |
1 |
| others[1] |
227 |
1 |
|
T19 |
1 |
|
T20 |
2 |
|
T36 |
1 |
| others[2] |
232 |
1 |
|
T20 |
1 |
|
T23 |
1 |
|
T42 |
1 |
| others[3] |
360 |
1 |
|
T35 |
1 |
|
T20 |
2 |
|
T165 |
1 |
| false |
120 |
1 |
|
T20 |
1 |
|
T24 |
1 |
|
T176 |
1 |
| true |
5648 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1017 |
1 |
|
T19 |
1 |
|
T35 |
1 |
|
T43 |
2 |
| others[1] |
1069 |
1 |
|
T3 |
1 |
|
T20 |
3 |
|
T8 |
13 |
| others[2] |
1028 |
1 |
|
T43 |
4 |
|
T20 |
4 |
|
T8 |
7 |
| others[3] |
1791 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T20 |
3 |
| false |
558 |
1 |
|
T43 |
2 |
|
T20 |
4 |
|
T8 |
6 |
| true |
1362 |
1 |
|
T4 |
1 |
|
T23 |
1 |
|
T56 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
211 |
1 |
|
T19 |
1 |
|
T20 |
2 |
|
T39 |
1 |
| others[1] |
250 |
1 |
|
T20 |
3 |
|
T290 |
1 |
|
T206 |
1 |
| others[2] |
248 |
1 |
|
T20 |
2 |
|
T24 |
1 |
|
T387 |
1 |
| others[3] |
350 |
1 |
|
T35 |
1 |
|
T40 |
1 |
|
T222 |
1 |
| false |
122 |
1 |
|
T251 |
1 |
|
T90 |
4 |
|
T114 |
7 |
| true |
5644 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
201 |
1 |
|
T35 |
1 |
|
T20 |
2 |
|
T55 |
1 |
| others[1] |
208 |
1 |
|
T20 |
3 |
|
T90 |
8 |
|
T114 |
11 |
| others[2] |
229 |
1 |
|
T20 |
1 |
|
T36 |
1 |
|
T40 |
1 |
| others[3] |
379 |
1 |
|
T78 |
1 |
|
T210 |
1 |
|
T89 |
1 |
| false |
96 |
1 |
|
T20 |
1 |
|
T389 |
1 |
|
T387 |
1 |
| true |
5712 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1187 |
1 |
|
T43 |
3 |
|
T20 |
4 |
|
T8 |
12 |
| others[1] |
1271 |
1 |
|
T43 |
2 |
|
T20 |
2 |
|
T8 |
6 |
| others[2] |
1257 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T35 |
1 |
| others[3] |
2107 |
1 |
|
T3 |
1 |
|
T43 |
2 |
|
T20 |
6 |
| false |
624 |
1 |
|
T20 |
1 |
|
T8 |
4 |
|
T67 |
1 |
| true |
379 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T58 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1278 |
1 |
|
T43 |
3 |
|
T20 |
2 |
|
T8 |
16 |
| others[1] |
1216 |
1 |
|
T3 |
1 |
|
T20 |
3 |
|
T8 |
7 |
| others[2] |
1260 |
1 |
|
T43 |
3 |
|
T20 |
5 |
|
T8 |
12 |
| others[3] |
2065 |
1 |
|
T20 |
5 |
|
T8 |
15 |
|
T21 |
13 |
| false |
660 |
1 |
|
T2 |
1 |
|
T35 |
1 |
|
T43 |
2 |
| true |
346 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
101 |
1 |
|
T20 |
2 |
|
T55 |
1 |
|
T165 |
1 |
| others[1] |
116 |
1 |
|
T20 |
3 |
|
T210 |
1 |
|
T251 |
1 |
| others[2] |
114 |
1 |
|
T20 |
4 |
|
T89 |
1 |
|
T90 |
5 |
| others[3] |
183 |
1 |
|
T20 |
6 |
|
T206 |
1 |
|
T251 |
1 |
| false |
54 |
1 |
|
T391 |
1 |
|
T90 |
2 |
|
T114 |
1 |
| true |
6257 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
243 |
1 |
|
T20 |
3 |
|
T391 |
1 |
|
T394 |
1 |
| others[1] |
226 |
1 |
|
T20 |
2 |
|
T23 |
1 |
|
T176 |
1 |
| others[2] |
204 |
1 |
|
T20 |
2 |
|
T53 |
1 |
|
T177 |
1 |
| others[3] |
389 |
1 |
|
T20 |
3 |
|
T26 |
1 |
|
T165 |
1 |
| false |
107 |
1 |
|
T35 |
1 |
|
T55 |
1 |
|
T389 |
1 |
| true |
5656 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1052 |
1 |
|
T3 |
1 |
|
T43 |
1 |
|
T58 |
1 |
| others[1] |
1067 |
1 |
|
T2 |
1 |
|
T43 |
2 |
|
T20 |
3 |
| others[2] |
1028 |
1 |
|
T35 |
1 |
|
T43 |
3 |
|
T20 |
2 |
| others[3] |
1821 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T43 |
1 |
| false |
550 |
1 |
|
T43 |
1 |
|
T20 |
2 |
|
T8 |
6 |
| true |
1307 |
1 |
|
T17 |
1 |
|
T55 |
1 |
|
T60 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
252 |
1 |
|
T35 |
1 |
|
T20 |
1 |
|
T25 |
1 |
| others[1] |
193 |
1 |
|
T20 |
3 |
|
T39 |
1 |
|
T90 |
6 |
| others[2] |
220 |
1 |
|
T20 |
2 |
|
T78 |
1 |
|
T90 |
9 |
| others[3] |
341 |
1 |
|
T20 |
1 |
|
T55 |
1 |
|
T206 |
1 |
| false |
100 |
1 |
|
T20 |
1 |
|
T90 |
6 |
|
T114 |
6 |
| true |
5719 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T19 |
1 |
|
T39 |
1 |
|
T90 |
11 |
| others[1] |
227 |
1 |
|
T20 |
1 |
|
T389 |
1 |
|
T212 |
1 |
| others[2] |
216 |
1 |
|
T20 |
3 |
|
T387 |
1 |
|
T90 |
8 |
| others[3] |
362 |
1 |
|
T35 |
1 |
|
T20 |
2 |
|
T391 |
1 |
| false |
103 |
1 |
|
T20 |
3 |
|
T251 |
1 |
|
T90 |
8 |
| true |
5686 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1201 |
1 |
|
T43 |
1 |
|
T20 |
4 |
|
T8 |
9 |
| others[1] |
1214 |
1 |
|
T43 |
1 |
|
T8 |
17 |
|
T55 |
1 |
| others[2] |
1288 |
1 |
|
T2 |
1 |
|
T20 |
3 |
|
T8 |
9 |
| others[3] |
2107 |
1 |
|
T35 |
1 |
|
T43 |
4 |
|
T20 |
5 |
| false |
646 |
1 |
|
T3 |
1 |
|
T43 |
2 |
|
T20 |
3 |
| true |
369 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1227 |
1 |
|
T43 |
3 |
|
T20 |
3 |
|
T8 |
12 |
| others[1] |
1235 |
1 |
|
T20 |
3 |
|
T8 |
14 |
|
T22 |
1 |
| others[2] |
1324 |
1 |
|
T43 |
1 |
|
T20 |
2 |
|
T8 |
9 |
| others[3] |
2035 |
1 |
|
T2 |
1 |
|
T35 |
1 |
|
T43 |
4 |
| false |
657 |
1 |
|
T3 |
1 |
|
T20 |
1 |
|
T8 |
9 |
| true |
347 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
104 |
1 |
|
T35 |
1 |
|
T20 |
5 |
|
T206 |
1 |
| others[1] |
122 |
1 |
|
T20 |
4 |
|
T89 |
1 |
|
T90 |
1 |
| others[2] |
109 |
1 |
|
T20 |
1 |
|
T388 |
1 |
|
T90 |
2 |
| others[3] |
181 |
1 |
|
T20 |
2 |
|
T36 |
1 |
|
T251 |
1 |
| false |
57 |
1 |
|
T20 |
3 |
|
T90 |
3 |
|
T91 |
3 |
| true |
6252 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
263 |
1 |
|
T20 |
3 |
|
T39 |
1 |
|
T40 |
1 |
| others[1] |
232 |
1 |
|
T19 |
1 |
|
T20 |
1 |
|
T55 |
1 |
| others[2] |
210 |
1 |
|
T20 |
1 |
|
T392 |
1 |
|
T391 |
1 |
| others[3] |
347 |
1 |
|
T20 |
4 |
|
T26 |
1 |
|
T77 |
1 |
| false |
127 |
1 |
|
T20 |
1 |
|
T90 |
2 |
|
T114 |
12 |
| true |
5646 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1099 |
1 |
|
T35 |
1 |
|
T43 |
3 |
|
T20 |
3 |
| others[1] |
1042 |
1 |
|
T4 |
1 |
|
T43 |
1 |
|
T20 |
4 |
| others[2] |
988 |
1 |
|
T17 |
1 |
|
T43 |
1 |
|
T20 |
3 |
| others[3] |
1761 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T43 |
3 |
| false |
565 |
1 |
|
T8 |
3 |
|
T60 |
1 |
|
T21 |
3 |
| true |
1370 |
1 |
|
T19 |
1 |
|
T58 |
1 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T19 |
1 |
|
T20 |
1 |
|
T210 |
1 |
| others[1] |
226 |
1 |
|
T20 |
2 |
|
T165 |
1 |
|
T89 |
1 |
| others[2] |
217 |
1 |
|
T20 |
4 |
|
T25 |
1 |
|
T319 |
1 |
| others[3] |
337 |
1 |
|
T20 |
1 |
|
T39 |
1 |
|
T206 |
1 |
| false |
125 |
1 |
|
T20 |
1 |
|
T55 |
1 |
|
T391 |
1 |
| true |
5687 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
207 |
1 |
|
T90 |
12 |
|
T114 |
9 |
|
T91 |
7 |
| others[1] |
214 |
1 |
|
T20 |
2 |
|
T78 |
1 |
|
T251 |
1 |
| others[2] |
238 |
1 |
|
T20 |
1 |
|
T251 |
1 |
|
T90 |
15 |
| others[3] |
356 |
1 |
|
T20 |
2 |
|
T165 |
1 |
|
T39 |
1 |
| false |
106 |
1 |
|
T20 |
1 |
|
T40 |
1 |
|
T206 |
1 |
| true |
5704 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |