Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1343 |
1 |
|
T43 |
1 |
|
T20 |
3 |
|
T8 |
12 |
| others[1] |
1184 |
1 |
|
T43 |
1 |
|
T20 |
6 |
|
T8 |
16 |
| others[2] |
1243 |
1 |
|
T2 |
1 |
|
T43 |
1 |
|
T20 |
2 |
| others[3] |
2066 |
1 |
|
T3 |
1 |
|
T35 |
1 |
|
T43 |
3 |
| false |
632 |
1 |
|
T43 |
2 |
|
T8 |
7 |
|
T21 |
5 |
| true |
357 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1251 |
1 |
|
T20 |
3 |
|
T8 |
9 |
|
T21 |
10 |
| others[1] |
1183 |
1 |
|
T35 |
1 |
|
T43 |
2 |
|
T20 |
1 |
| others[2] |
1238 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T43 |
2 |
| others[3] |
2139 |
1 |
|
T43 |
4 |
|
T20 |
6 |
|
T8 |
14 |
| false |
657 |
1 |
|
T8 |
6 |
|
T21 |
4 |
|
T51 |
5 |
| true |
357 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
113 |
1 |
|
T20 |
2 |
|
T389 |
1 |
|
T387 |
1 |
| others[1] |
88 |
1 |
|
T20 |
2 |
|
T251 |
1 |
|
T90 |
4 |
| others[2] |
110 |
1 |
|
T20 |
3 |
|
T387 |
1 |
|
T90 |
4 |
| others[3] |
168 |
1 |
|
T19 |
1 |
|
T20 |
7 |
|
T36 |
1 |
| false |
50 |
1 |
|
T20 |
1 |
|
T114 |
3 |
|
T393 |
1 |
| true |
6296 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T20 |
3 |
|
T26 |
1 |
|
T36 |
1 |
| others[1] |
213 |
1 |
|
T35 |
1 |
|
T251 |
1 |
|
T53 |
1 |
| others[2] |
209 |
1 |
|
T20 |
2 |
|
T177 |
1 |
|
T90 |
5 |
| others[3] |
394 |
1 |
|
T55 |
1 |
|
T40 |
1 |
|
T77 |
1 |
| false |
101 |
1 |
|
T20 |
1 |
|
T78 |
1 |
|
T322 |
1 |
| true |
5684 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1069 |
1 |
|
T43 |
1 |
|
T20 |
3 |
|
T8 |
8 |
| others[1] |
1054 |
1 |
|
T2 |
1 |
|
T35 |
1 |
|
T43 |
3 |
| others[2] |
1040 |
1 |
|
T43 |
3 |
|
T20 |
3 |
|
T8 |
12 |
| others[3] |
1727 |
1 |
|
T17 |
1 |
|
T43 |
1 |
|
T20 |
5 |
| false |
529 |
1 |
|
T3 |
1 |
|
T20 |
1 |
|
T8 |
7 |
| true |
1406 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T58 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
204 |
1 |
|
T19 |
1 |
|
T20 |
2 |
|
T25 |
1 |
| others[1] |
237 |
1 |
|
T322 |
1 |
|
T212 |
1 |
|
T90 |
7 |
| others[2] |
223 |
1 |
|
T20 |
2 |
|
T392 |
1 |
|
T251 |
1 |
| others[3] |
386 |
1 |
|
T20 |
3 |
|
T24 |
1 |
|
T176 |
1 |
| false |
110 |
1 |
|
T20 |
2 |
|
T89 |
1 |
|
T90 |
6 |
| true |
5665 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
209 |
1 |
|
T20 |
2 |
|
T251 |
1 |
|
T389 |
1 |
| others[1] |
223 |
1 |
|
T20 |
1 |
|
T55 |
1 |
|
T89 |
1 |
| others[2] |
215 |
1 |
|
T20 |
1 |
|
T78 |
1 |
|
T392 |
1 |
| others[3] |
331 |
1 |
|
T20 |
3 |
|
T387 |
1 |
|
T90 |
15 |
| false |
107 |
1 |
|
T90 |
1 |
|
T114 |
6 |
|
T91 |
3 |
| true |
5740 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1263 |
1 |
|
T3 |
1 |
|
T43 |
3 |
|
T20 |
3 |
| others[1] |
1247 |
1 |
|
T43 |
1 |
|
T20 |
2 |
|
T8 |
10 |
| others[2] |
1279 |
1 |
|
T20 |
4 |
|
T8 |
10 |
|
T56 |
1 |
| others[3] |
2020 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T35 |
1 |
| false |
658 |
1 |
|
T8 |
3 |
|
T21 |
5 |
|
T51 |
5 |
| true |
358 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T58 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1196 |
1 |
|
T43 |
2 |
|
T20 |
2 |
|
T8 |
9 |
| others[1] |
1206 |
1 |
|
T3 |
1 |
|
T35 |
1 |
|
T43 |
2 |
| others[2] |
1259 |
1 |
|
T43 |
1 |
|
T20 |
2 |
|
T8 |
8 |
| others[3] |
2118 |
1 |
|
T2 |
1 |
|
T43 |
3 |
|
T20 |
8 |
| false |
693 |
1 |
|
T20 |
1 |
|
T8 |
3 |
|
T21 |
5 |
| true |
353 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
103 |
1 |
|
T35 |
1 |
|
T20 |
2 |
|
T36 |
1 |
| others[1] |
110 |
1 |
|
T20 |
4 |
|
T392 |
1 |
|
T206 |
1 |
| others[2] |
102 |
1 |
|
T20 |
4 |
|
T387 |
1 |
|
T90 |
3 |
| others[3] |
179 |
1 |
|
T20 |
3 |
|
T251 |
1 |
|
T212 |
1 |
| false |
53 |
1 |
|
T20 |
2 |
|
T114 |
5 |
|
T91 |
4 |
| true |
6278 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T20 |
3 |
|
T40 |
1 |
|
T210 |
1 |
| others[1] |
228 |
1 |
|
T20 |
1 |
|
T77 |
1 |
|
T392 |
1 |
| others[2] |
244 |
1 |
|
T35 |
1 |
|
T20 |
2 |
|
T26 |
1 |
| others[3] |
365 |
1 |
|
T222 |
1 |
|
T78 |
1 |
|
T251 |
1 |
| false |
121 |
1 |
|
T20 |
1 |
|
T52 |
1 |
|
T394 |
1 |
| true |
5634 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1044 |
1 |
|
T35 |
1 |
|
T43 |
3 |
|
T20 |
6 |
| others[1] |
1036 |
1 |
|
T3 |
1 |
|
T19 |
1 |
|
T20 |
4 |
| others[2] |
1004 |
1 |
|
T43 |
1 |
|
T20 |
2 |
|
T8 |
16 |
| others[3] |
1848 |
1 |
|
T2 |
1 |
|
T43 |
3 |
|
T20 |
1 |
| false |
517 |
1 |
|
T43 |
1 |
|
T20 |
2 |
|
T8 |
4 |
| true |
1376 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T58 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
198 |
1 |
|
T20 |
2 |
|
T24 |
1 |
|
T36 |
1 |
| others[1] |
249 |
1 |
|
T39 |
1 |
|
T391 |
1 |
|
T290 |
1 |
| others[2] |
246 |
1 |
|
T20 |
1 |
|
T23 |
1 |
|
T222 |
1 |
| others[3] |
380 |
1 |
|
T35 |
1 |
|
T20 |
4 |
|
T25 |
1 |
| false |
112 |
1 |
|
T90 |
4 |
|
T114 |
2 |
|
T91 |
4 |
| true |
5640 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T35 |
1 |
|
T20 |
4 |
|
T36 |
1 |
| others[1] |
227 |
1 |
|
T20 |
2 |
|
T210 |
1 |
|
T388 |
1 |
| others[2] |
211 |
1 |
|
T387 |
1 |
|
T90 |
6 |
|
T114 |
8 |
| others[3] |
368 |
1 |
|
T20 |
2 |
|
T290 |
1 |
|
T206 |
1 |
| false |
126 |
1 |
|
T212 |
1 |
|
T90 |
8 |
|
T114 |
2 |
| true |
5668 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1283 |
1 |
|
T43 |
1 |
|
T20 |
1 |
|
T8 |
9 |
| others[1] |
1248 |
1 |
|
T35 |
1 |
|
T43 |
1 |
|
T20 |
3 |
| others[2] |
1240 |
1 |
|
T43 |
3 |
|
T20 |
2 |
|
T8 |
11 |
| others[3] |
2066 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
| false |
629 |
1 |
|
T43 |
2 |
|
T20 |
2 |
|
T8 |
5 |
| true |
359 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T58 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1249 |
1 |
|
T35 |
1 |
|
T20 |
3 |
|
T8 |
14 |
| others[1] |
1275 |
1 |
|
T43 |
3 |
|
T20 |
8 |
|
T8 |
10 |
| others[2] |
1241 |
1 |
|
T20 |
1 |
|
T8 |
9 |
|
T21 |
6 |
| others[3] |
2057 |
1 |
|
T43 |
4 |
|
T20 |
1 |
|
T8 |
17 |
| false |
662 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T43 |
1 |
| true |
341 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
111 |
1 |
|
T20 |
5 |
|
T391 |
1 |
|
T206 |
1 |
| others[1] |
80 |
1 |
|
T20 |
2 |
|
T251 |
1 |
|
T90 |
4 |
| others[2] |
74 |
1 |
|
T20 |
2 |
|
T78 |
1 |
|
T251 |
1 |
| others[3] |
189 |
1 |
|
T20 |
6 |
|
T210 |
1 |
|
T388 |
1 |
| false |
43 |
1 |
|
T90 |
1 |
|
T114 |
1 |
|
T91 |
1 |
| true |
6328 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
189 |
1 |
|
T20 |
1 |
|
T23 |
1 |
|
T251 |
1 |
| others[1] |
223 |
1 |
|
T20 |
1 |
|
T55 |
1 |
|
T36 |
1 |
| others[2] |
238 |
1 |
|
T20 |
2 |
|
T26 |
1 |
|
T90 |
14 |
| others[3] |
385 |
1 |
|
T35 |
1 |
|
T20 |
3 |
|
T40 |
1 |
| false |
123 |
1 |
|
T52 |
1 |
|
T89 |
1 |
|
T90 |
7 |
| true |
5667 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1047 |
1 |
|
T19 |
1 |
|
T43 |
3 |
|
T20 |
2 |
| others[1] |
1029 |
1 |
|
T20 |
4 |
|
T8 |
13 |
|
T22 |
1 |
| others[2] |
1086 |
1 |
|
T20 |
4 |
|
T8 |
8 |
|
T21 |
6 |
| others[3] |
1779 |
1 |
|
T35 |
1 |
|
T43 |
4 |
|
T20 |
5 |
| false |
532 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T43 |
1 |
| true |
1352 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T58 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T20 |
1 |
|
T389 |
1 |
|
T212 |
1 |
| others[1] |
232 |
1 |
|
T20 |
2 |
|
T36 |
1 |
|
T392 |
1 |
| others[2] |
223 |
1 |
|
T39 |
1 |
|
T251 |
1 |
|
T90 |
15 |
| others[3] |
369 |
1 |
|
T20 |
2 |
|
T290 |
1 |
|
T210 |
1 |
| false |
109 |
1 |
|
T20 |
1 |
|
T90 |
4 |
|
T104 |
1 |
| true |
5671 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T20 |
2 |
|
T40 |
1 |
|
T290 |
1 |
| others[1] |
215 |
1 |
|
T20 |
2 |
|
T90 |
11 |
|
T114 |
9 |
| others[2] |
228 |
1 |
|
T20 |
1 |
|
T39 |
1 |
|
T90 |
18 |
| others[3] |
351 |
1 |
|
T165 |
1 |
|
T319 |
1 |
|
T387 |
1 |
| false |
127 |
1 |
|
T20 |
1 |
|
T78 |
1 |
|
T388 |
1 |
| true |
5678 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1284 |
1 |
|
T3 |
1 |
|
T43 |
3 |
|
T20 |
1 |
| others[1] |
1244 |
1 |
|
T20 |
4 |
|
T8 |
8 |
|
T21 |
5 |
| others[2] |
1237 |
1 |
|
T35 |
1 |
|
T43 |
2 |
|
T20 |
1 |
| others[3] |
2070 |
1 |
|
T2 |
1 |
|
T43 |
2 |
|
T20 |
5 |
| false |
623 |
1 |
|
T43 |
1 |
|
T20 |
4 |
|
T8 |
4 |
| true |
367 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1260 |
1 |
|
T43 |
2 |
|
T20 |
4 |
|
T8 |
16 |
| others[1] |
1231 |
1 |
|
T20 |
2 |
|
T8 |
11 |
|
T22 |
1 |
| others[2] |
1271 |
1 |
|
T2 |
1 |
|
T43 |
1 |
|
T20 |
4 |
| others[3] |
2054 |
1 |
|
T35 |
1 |
|
T43 |
4 |
|
T20 |
5 |
| false |
660 |
1 |
|
T3 |
1 |
|
T43 |
1 |
|
T8 |
5 |
| true |
349 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
108 |
1 |
|
T20 |
1 |
|
T251 |
2 |
|
T387 |
1 |
| others[1] |
105 |
1 |
|
T35 |
1 |
|
T20 |
3 |
|
T387 |
1 |
| others[2] |
98 |
1 |
|
T20 |
4 |
|
T90 |
4 |
|
T114 |
3 |
| others[3] |
188 |
1 |
|
T20 |
7 |
|
T36 |
1 |
|
T206 |
1 |
| false |
47 |
1 |
|
T90 |
3 |
|
T114 |
2 |
|
T91 |
2 |
| true |
6279 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
240 |
1 |
|
T20 |
2 |
|
T77 |
1 |
|
T394 |
1 |
| others[1] |
236 |
1 |
|
T35 |
1 |
|
T39 |
1 |
|
T52 |
1 |
| others[2] |
244 |
1 |
|
T20 |
1 |
|
T391 |
1 |
|
T212 |
1 |
| others[3] |
368 |
1 |
|
T20 |
3 |
|
T26 |
1 |
|
T42 |
1 |
| false |
133 |
1 |
|
T19 |
1 |
|
T20 |
2 |
|
T24 |
1 |
| true |
5604 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1100 |
1 |
|
T20 |
2 |
|
T8 |
14 |
|
T55 |
1 |
| others[1] |
1058 |
1 |
|
T35 |
1 |
|
T43 |
3 |
|
T20 |
4 |
| others[2] |
1064 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T43 |
2 |
| others[3] |
1711 |
1 |
|
T3 |
1 |
|
T43 |
3 |
|
T58 |
1 |
| false |
533 |
1 |
|
T20 |
2 |
|
T8 |
8 |
|
T51 |
5 |
| true |
1359 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
214 |
1 |
|
T20 |
4 |
|
T23 |
1 |
|
T25 |
1 |
| others[1] |
226 |
1 |
|
T36 |
1 |
|
T90 |
6 |
|
T114 |
10 |
| others[2] |
199 |
1 |
|
T20 |
1 |
|
T78 |
1 |
|
T206 |
1 |
| others[3] |
350 |
1 |
|
T19 |
1 |
|
T35 |
1 |
|
T20 |
1 |
| false |
122 |
1 |
|
T20 |
1 |
|
T222 |
1 |
|
T90 |
2 |
| true |
5714 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
223 |
1 |
|
T20 |
2 |
|
T392 |
1 |
|
T210 |
1 |
| others[1] |
221 |
1 |
|
T20 |
2 |
|
T251 |
1 |
|
T395 |
1 |
| others[2] |
199 |
1 |
|
T20 |
1 |
|
T319 |
1 |
|
T90 |
8 |
| others[3] |
349 |
1 |
|
T20 |
1 |
|
T212 |
1 |
|
T387 |
1 |
| false |
115 |
1 |
|
T19 |
1 |
|
T165 |
1 |
|
T90 |
9 |
| true |
5718 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1203 |
1 |
|
T35 |
1 |
|
T20 |
3 |
|
T8 |
13 |
| others[1] |
1264 |
1 |
|
T43 |
2 |
|
T20 |
4 |
|
T8 |
8 |
| others[2] |
1227 |
1 |
|
T3 |
1 |
|
T43 |
1 |
|
T20 |
3 |
| others[3] |
2076 |
1 |
|
T43 |
5 |
|
T20 |
4 |
|
T8 |
20 |
| false |
687 |
1 |
|
T2 |
1 |
|
T20 |
1 |
|
T8 |
5 |
| true |
368 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10 |
1 |
|
T396 |
2 |
|
T160 |
1 |
|
T397 |
1 |
| others[1] |
2 |
1 |
|
T398 |
1 |
|
T399 |
1 |
|
- |
- |
| others[2] |
8 |
1 |
|
T13 |
1 |
|
T75 |
1 |
|
T138 |
1 |
| others[3] |
15 |
1 |
|
T85 |
1 |
|
T156 |
1 |
|
T102 |
1 |
| false |
9 |
1 |
|
T56 |
1 |
|
T400 |
1 |
|
T401 |
1 |
| true |
49 |
1 |
|
T1 |
1 |
|
T60 |
1 |
|
T107 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2 |
1 |
|
T402 |
1 |
|
T403 |
1 |
|
- |
- |
| others[1] |
3 |
1 |
|
T404 |
1 |
|
T405 |
1 |
|
T406 |
1 |
| others[2] |
1 |
1 |
|
T332 |
1 |
|
- |
- |
|
- |
- |
| others[3] |
6 |
1 |
|
T29 |
1 |
|
T30 |
1 |
|
T383 |
1 |
| false |
9 |
1 |
|
T241 |
1 |
|
T381 |
1 |
|
T407 |
1 |
| true |
26 |
1 |
|
T31 |
1 |
|
T386 |
1 |
|
T330 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |