Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10916 |
1 |
|
T5 |
93 |
|
T7 |
56 |
|
T20 |
9 |
| others[1] |
814 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T43 |
2 |
| others[2] |
783 |
1 |
|
T35 |
1 |
|
T20 |
4 |
|
T8 |
11 |
| others[3] |
1298 |
1 |
|
T2 |
1 |
|
T43 |
3 |
|
T20 |
2 |
| false |
408 |
1 |
|
T20 |
2 |
|
T8 |
4 |
|
T22 |
1 |
| true |
448 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T43 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2454 |
1 |
|
T5 |
18 |
|
T7 |
8 |
|
T43 |
2 |
| others[1] |
2449 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
21 |
| others[2] |
2583 |
1 |
|
T5 |
13 |
|
T7 |
13 |
|
T43 |
1 |
| others[3] |
4274 |
1 |
|
T5 |
23 |
|
T7 |
18 |
|
T35 |
1 |
| false |
1372 |
1 |
|
T5 |
18 |
|
T7 |
6 |
|
T20 |
2 |
| true |
1535 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10297 |
1 |
|
T5 |
93 |
|
T7 |
56 |
|
T43 |
2 |
| others[1] |
287 |
1 |
|
T19 |
1 |
|
T43 |
1 |
|
T20 |
1 |
| others[2] |
296 |
1 |
|
T20 |
3 |
|
T22 |
1 |
|
T26 |
1 |
| others[3] |
434 |
1 |
|
T2 |
1 |
|
T20 |
2 |
|
T174 |
1 |
| false |
151 |
1 |
|
T35 |
1 |
|
T20 |
2 |
|
T38 |
1 |
| true |
3202 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10536 |
1 |
|
T5 |
93 |
|
T7 |
56 |
|
T43 |
4 |
| others[1] |
500 |
1 |
|
T2 |
1 |
|
T58 |
1 |
|
T20 |
4 |
| others[2] |
497 |
1 |
|
T3 |
1 |
|
T43 |
2 |
|
T20 |
3 |
| others[3] |
761 |
1 |
|
T20 |
4 |
|
T8 |
8 |
|
T21 |
9 |
| false |
232 |
1 |
|
T43 |
2 |
|
T20 |
2 |
|
T8 |
3 |
| true |
2141 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10292 |
1 |
|
T5 |
93 |
|
T7 |
56 |
|
T20 |
1 |
| others[1] |
240 |
1 |
|
T43 |
1 |
|
T20 |
3 |
|
T27 |
1 |
| others[2] |
256 |
1 |
|
T43 |
1 |
|
T20 |
3 |
|
T55 |
1 |
| others[3] |
435 |
1 |
|
T35 |
1 |
|
T43 |
2 |
|
T20 |
2 |
| false |
138 |
1 |
|
T20 |
1 |
|
T28 |
1 |
|
T110 |
1 |
| true |
3306 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10293 |
1 |
|
T5 |
93 |
|
T7 |
56 |
|
T20 |
2 |
| others[1] |
254 |
1 |
|
T28 |
1 |
|
T206 |
1 |
|
T217 |
1 |
| others[2] |
260 |
1 |
|
T3 |
1 |
|
T43 |
1 |
|
T20 |
3 |
| others[3] |
445 |
1 |
|
T2 |
1 |
|
T35 |
1 |
|
T43 |
3 |
| false |
134 |
1 |
|
T20 |
1 |
|
T36 |
1 |
|
T174 |
1 |
| true |
3281 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10884 |
1 |
|
T3 |
1 |
|
T5 |
93 |
|
T7 |
56 |
| others[1] |
807 |
1 |
|
T43 |
1 |
|
T20 |
2 |
|
T8 |
11 |
| others[2] |
806 |
1 |
|
T20 |
3 |
|
T8 |
13 |
|
T21 |
5 |
| others[3] |
1285 |
1 |
|
T2 |
1 |
|
T35 |
1 |
|
T20 |
1 |
| false |
452 |
1 |
|
T20 |
2 |
|
T8 |
6 |
|
T22 |
1 |
| true |
433 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10840 |
1 |
|
T3 |
1 |
|
T5 |
93 |
|
T7 |
56 |
| others[1] |
760 |
1 |
|
T20 |
2 |
|
T8 |
11 |
|
T21 |
8 |
| others[2] |
802 |
1 |
|
T43 |
2 |
|
T8 |
6 |
|
T21 |
8 |
| others[3] |
1386 |
1 |
|
T2 |
1 |
|
T35 |
1 |
|
T43 |
2 |
| false |
395 |
1 |
|
T43 |
1 |
|
T8 |
6 |
|
T21 |
5 |
| true |
454 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2511 |
1 |
|
T5 |
16 |
|
T7 |
10 |
|
T43 |
2 |
| others[1] |
2526 |
1 |
|
T5 |
18 |
|
T7 |
11 |
|
T43 |
2 |
| others[2] |
2462 |
1 |
|
T2 |
1 |
|
T5 |
21 |
|
T7 |
10 |
| others[3] |
4282 |
1 |
|
T3 |
1 |
|
T5 |
28 |
|
T7 |
19 |
| false |
1352 |
1 |
|
T5 |
10 |
|
T7 |
6 |
|
T43 |
1 |
| true |
1504 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10324 |
1 |
|
T3 |
1 |
|
T5 |
93 |
|
T7 |
56 |
| others[1] |
264 |
1 |
|
T20 |
1 |
|
T55 |
1 |
|
T25 |
1 |
| others[2] |
260 |
1 |
|
T43 |
1 |
|
T20 |
1 |
|
T22 |
1 |
| others[3] |
437 |
1 |
|
T35 |
1 |
|
T43 |
1 |
|
T20 |
2 |
| false |
160 |
1 |
|
T108 |
1 |
|
T221 |
1 |
|
T347 |
1 |
| true |
3192 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10518 |
1 |
|
T5 |
93 |
|
T7 |
56 |
|
T43 |
2 |
| others[1] |
472 |
1 |
|
T43 |
3 |
|
T20 |
3 |
|
T8 |
9 |
| others[2] |
463 |
1 |
|
T2 |
1 |
|
T35 |
1 |
|
T58 |
1 |
| others[3] |
782 |
1 |
|
T19 |
1 |
|
T43 |
3 |
|
T20 |
6 |
| false |
222 |
1 |
|
T20 |
2 |
|
T8 |
3 |
|
T51 |
3 |
| true |
2180 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10281 |
1 |
|
T5 |
93 |
|
T7 |
56 |
|
T43 |
1 |
| others[1] |
229 |
1 |
|
T20 |
2 |
|
T36 |
1 |
|
T392 |
1 |
| others[2] |
250 |
1 |
|
T43 |
2 |
|
T20 |
1 |
|
T391 |
1 |
| others[3] |
465 |
1 |
|
T2 |
1 |
|
T19 |
1 |
|
T35 |
1 |
| false |
137 |
1 |
|
T20 |
1 |
|
T108 |
2 |
|
T110 |
1 |
| true |
3275 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10315 |
1 |
|
T5 |
93 |
|
T7 |
56 |
|
T43 |
2 |
| others[1] |
263 |
1 |
|
T43 |
2 |
|
T22 |
1 |
|
T47 |
1 |
| others[2] |
268 |
1 |
|
T35 |
1 |
|
T20 |
3 |
|
T392 |
1 |
| others[3] |
381 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T19 |
1 |
| false |
136 |
1 |
|
T20 |
1 |
|
T83 |
1 |
|
T237 |
1 |
| true |
3274 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T43 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10847 |
1 |
|
T2 |
1 |
|
T5 |
93 |
|
T7 |
56 |
| others[1] |
781 |
1 |
|
T20 |
3 |
|
T8 |
9 |
|
T21 |
5 |
| others[2] |
829 |
1 |
|
T3 |
1 |
|
T43 |
1 |
|
T20 |
1 |
| others[3] |
1344 |
1 |
|
T43 |
1 |
|
T20 |
2 |
|
T8 |
21 |
| false |
401 |
1 |
|
T8 |
3 |
|
T21 |
4 |
|
T51 |
6 |
| true |
435 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T43 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10826 |
1 |
|
T5 |
93 |
|
T7 |
56 |
|
T43 |
2 |
| others[1] |
792 |
1 |
|
T43 |
1 |
|
T20 |
1 |
|
T8 |
11 |
| others[2] |
761 |
1 |
|
T43 |
3 |
|
T20 |
2 |
|
T8 |
7 |
| others[3] |
1336 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T35 |
1 |
| false |
467 |
1 |
|
T20 |
1 |
|
T8 |
8 |
|
T21 |
5 |
| true |
455 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2530 |
1 |
|
T3 |
1 |
|
T5 |
18 |
|
T7 |
11 |
| others[1] |
2555 |
1 |
|
T5 |
17 |
|
T7 |
11 |
|
T19 |
1 |
| others[2] |
2458 |
1 |
|
T5 |
18 |
|
T7 |
8 |
|
T43 |
3 |
| others[3] |
4237 |
1 |
|
T2 |
1 |
|
T5 |
34 |
|
T7 |
17 |
| false |
1357 |
1 |
|
T5 |
6 |
|
T7 |
9 |
|
T43 |
2 |
| true |
1500 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T35 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10305 |
1 |
|
T3 |
1 |
|
T5 |
93 |
|
T7 |
56 |
| others[1] |
266 |
1 |
|
T43 |
1 |
|
T20 |
1 |
|
T176 |
1 |
| others[2] |
263 |
1 |
|
T35 |
1 |
|
T43 |
1 |
|
T20 |
2 |
| others[3] |
456 |
1 |
|
T2 |
1 |
|
T43 |
2 |
|
T20 |
4 |
| false |
142 |
1 |
|
T392 |
1 |
|
T218 |
1 |
|
T90 |
4 |
| true |
3205 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10508 |
1 |
|
T5 |
93 |
|
T7 |
56 |
|
T43 |
2 |
| others[1] |
467 |
1 |
|
T20 |
3 |
|
T8 |
2 |
|
T21 |
1 |
| others[2] |
470 |
1 |
|
T2 |
1 |
|
T43 |
1 |
|
T20 |
2 |
| others[3] |
754 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T35 |
1 |
| false |
267 |
1 |
|
T8 |
6 |
|
T21 |
3 |
|
T51 |
5 |
| true |
2171 |
1 |
|
T3 |
1 |
|
T19 |
1 |
|
T58 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10299 |
1 |
|
T5 |
93 |
|
T7 |
56 |
|
T20 |
5 |
| others[1] |
244 |
1 |
|
T2 |
1 |
|
T20 |
1 |
|
T36 |
1 |
| others[2] |
271 |
1 |
|
T43 |
2 |
|
T20 |
4 |
|
T25 |
1 |
| others[3] |
417 |
1 |
|
T35 |
1 |
|
T20 |
2 |
|
T28 |
1 |
| false |
136 |
1 |
|
T43 |
1 |
|
T20 |
1 |
|
T166 |
1 |
| true |
3270 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10293 |
1 |
|
T5 |
93 |
|
T7 |
56 |
|
T20 |
1 |
| others[1] |
242 |
1 |
|
T3 |
1 |
|
T43 |
1 |
|
T20 |
1 |
| others[2] |
257 |
1 |
|
T20 |
1 |
|
T166 |
1 |
|
T108 |
1 |
| others[3] |
446 |
1 |
|
T19 |
1 |
|
T35 |
1 |
|
T43 |
1 |
| false |
134 |
1 |
|
T43 |
1 |
|
T20 |
1 |
|
T47 |
1 |
| true |
3265 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10865 |
1 |
|
T5 |
93 |
|
T7 |
56 |
|
T20 |
1 |
| others[1] |
830 |
1 |
|
T43 |
2 |
|
T20 |
1 |
|
T8 |
15 |
| others[2] |
716 |
1 |
|
T20 |
2 |
|
T8 |
10 |
|
T21 |
4 |
| others[3] |
1347 |
1 |
|
T3 |
1 |
|
T35 |
1 |
|
T43 |
1 |
| false |
441 |
1 |
|
T2 |
1 |
|
T8 |
5 |
|
T21 |
4 |
| true |
438 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10856 |
1 |
|
T5 |
93 |
|
T7 |
56 |
|
T43 |
1 |
| others[1] |
788 |
1 |
|
T2 |
1 |
|
T35 |
1 |
|
T43 |
2 |
| others[2] |
798 |
1 |
|
T3 |
1 |
|
T19 |
1 |
|
T20 |
1 |
| others[3] |
1344 |
1 |
|
T20 |
3 |
|
T8 |
18 |
|
T21 |
11 |
| false |
396 |
1 |
|
T20 |
1 |
|
T8 |
3 |
|
T21 |
3 |
| true |
455 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T43 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2516 |
1 |
|
T5 |
22 |
|
T7 |
10 |
|
T43 |
3 |
| others[1] |
2569 |
1 |
|
T3 |
1 |
|
T5 |
13 |
|
T7 |
8 |
| others[2] |
2466 |
1 |
|
T2 |
1 |
|
T5 |
18 |
|
T7 |
15 |
| others[3] |
4263 |
1 |
|
T5 |
25 |
|
T7 |
19 |
|
T43 |
2 |
| false |
1317 |
1 |
|
T5 |
15 |
|
T7 |
4 |
|
T19 |
1 |
| true |
1506 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T35 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10301 |
1 |
|
T5 |
93 |
|
T7 |
56 |
|
T22 |
1 |
| others[1] |
262 |
1 |
|
T20 |
2 |
|
T23 |
1 |
|
T108 |
2 |
| others[2] |
285 |
1 |
|
T43 |
1 |
|
T20 |
2 |
|
T39 |
1 |
| others[3] |
432 |
1 |
|
T35 |
1 |
|
T43 |
2 |
|
T20 |
3 |
| false |
145 |
1 |
|
T77 |
1 |
|
T112 |
1 |
|
T293 |
2 |
| true |
3212 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10504 |
1 |
|
T5 |
93 |
|
T7 |
56 |
|
T43 |
1 |
| others[1] |
501 |
1 |
|
T4 |
1 |
|
T35 |
1 |
|
T43 |
1 |
| others[2] |
460 |
1 |
|
T20 |
2 |
|
T8 |
7 |
|
T21 |
3 |
| others[3] |
783 |
1 |
|
T43 |
4 |
|
T20 |
3 |
|
T8 |
13 |
| false |
222 |
1 |
|
T43 |
2 |
|
T20 |
2 |
|
T8 |
1 |
| true |
2167 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10294 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
93 |
| others[1] |
232 |
1 |
|
T43 |
1 |
|
T20 |
2 |
|
T22 |
1 |
| others[2] |
261 |
1 |
|
T19 |
1 |
|
T43 |
1 |
|
T222 |
1 |
| others[3] |
436 |
1 |
|
T35 |
1 |
|
T20 |
2 |
|
T37 |
1 |
| false |
135 |
1 |
|
T20 |
2 |
|
T36 |
1 |
|
T28 |
1 |
| true |
3279 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T43 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10294 |
1 |
|
T2 |
1 |
|
T5 |
93 |
|
T7 |
56 |
| others[1] |
282 |
1 |
|
T43 |
1 |
|
T20 |
2 |
|
T174 |
1 |
| others[2] |
224 |
1 |
|
T43 |
2 |
|
T20 |
1 |
|
T55 |
1 |
| others[3] |
422 |
1 |
|
T43 |
1 |
|
T47 |
1 |
|
T166 |
1 |
| false |
142 |
1 |
|
T47 |
1 |
|
T40 |
1 |
|
T251 |
1 |
| true |
3273 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10906 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
93 |
| others[1] |
826 |
1 |
|
T43 |
1 |
|
T20 |
2 |
|
T8 |
10 |
| others[2] |
792 |
1 |
|
T43 |
1 |
|
T20 |
1 |
|
T8 |
12 |
| others[3] |
1279 |
1 |
|
T19 |
1 |
|
T35 |
1 |
|
T43 |
1 |
| false |
406 |
1 |
|
T20 |
1 |
|
T8 |
4 |
|
T21 |
4 |
| true |
428 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T43 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10832 |
1 |
|
T2 |
1 |
|
T5 |
93 |
|
T7 |
56 |
| others[1] |
775 |
1 |
|
T20 |
1 |
|
T8 |
12 |
|
T9 |
1 |
| others[2] |
820 |
1 |
|
T19 |
1 |
|
T43 |
1 |
|
T20 |
2 |
| others[3] |
1348 |
1 |
|
T3 |
1 |
|
T20 |
3 |
|
T8 |
18 |
| false |
416 |
1 |
|
T43 |
2 |
|
T20 |
2 |
|
T8 |
3 |
| true |
446 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T43 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2493 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
14 |
| others[1] |
2595 |
1 |
|
T5 |
14 |
|
T7 |
11 |
|
T20 |
4 |
| others[2] |
2534 |
1 |
|
T5 |
17 |
|
T7 |
6 |
|
T43 |
2 |
| others[3] |
4197 |
1 |
|
T5 |
36 |
|
T7 |
21 |
|
T43 |
4 |
| false |
1280 |
1 |
|
T5 |
12 |
|
T7 |
6 |
|
T20 |
2 |
| true |
1538 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10297 |
1 |
|
T5 |
93 |
|
T7 |
56 |
|
T70 |
81 |
| others[1] |
245 |
1 |
|
T3 |
1 |
|
T43 |
1 |
|
T47 |
1 |
| others[2] |
272 |
1 |
|
T35 |
1 |
|
T20 |
2 |
|
T47 |
1 |
| others[3] |
478 |
1 |
|
T43 |
1 |
|
T20 |
3 |
|
T40 |
1 |
| false |
137 |
1 |
|
T109 |
1 |
|
T174 |
1 |
|
T207 |
1 |
| true |
3208 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T17 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |