Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10486 |
1 |
|
T5 |
93 |
|
T7 |
56 |
|
T43 |
1 |
| others[1] |
453 |
1 |
|
T19 |
1 |
|
T43 |
2 |
|
T20 |
2 |
| others[2] |
494 |
1 |
|
T4 |
1 |
|
T43 |
1 |
|
T20 |
5 |
| others[3] |
793 |
1 |
|
T43 |
4 |
|
T58 |
1 |
|
T20 |
6 |
| false |
237 |
1 |
|
T8 |
2 |
|
T21 |
1 |
|
T51 |
3 |
| true |
2174 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10321 |
1 |
|
T5 |
93 |
|
T7 |
56 |
|
T43 |
1 |
| others[1] |
217 |
1 |
|
T20 |
1 |
|
T166 |
1 |
|
T78 |
1 |
| others[2] |
239 |
1 |
|
T20 |
2 |
|
T210 |
1 |
|
T394 |
1 |
| others[3] |
472 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T19 |
1 |
| false |
138 |
1 |
|
T20 |
1 |
|
T174 |
1 |
|
T207 |
1 |
| true |
3250 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T43 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10269 |
1 |
|
T5 |
93 |
|
T7 |
56 |
|
T43 |
1 |
| others[1] |
245 |
1 |
|
T20 |
1 |
|
T55 |
1 |
|
T36 |
1 |
| others[2] |
272 |
1 |
|
T43 |
3 |
|
T20 |
1 |
|
T109 |
1 |
| others[3] |
418 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T19 |
1 |
| false |
143 |
1 |
|
T20 |
2 |
|
T78 |
1 |
|
T290 |
1 |
| true |
3290 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T43 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10858 |
1 |
|
T5 |
93 |
|
T7 |
56 |
|
T43 |
1 |
| others[1] |
809 |
1 |
|
T2 |
1 |
|
T43 |
4 |
|
T20 |
3 |
| others[2] |
816 |
1 |
|
T20 |
1 |
|
T8 |
10 |
|
T21 |
7 |
| others[3] |
1318 |
1 |
|
T3 |
1 |
|
T43 |
1 |
|
T20 |
1 |
| false |
392 |
1 |
|
T35 |
1 |
|
T8 |
5 |
|
T21 |
2 |
| true |
444 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10915 |
1 |
|
T3 |
1 |
|
T5 |
93 |
|
T7 |
56 |
| others[1] |
776 |
1 |
|
T20 |
2 |
|
T8 |
13 |
|
T21 |
2 |
| others[2] |
784 |
1 |
|
T35 |
1 |
|
T43 |
1 |
|
T20 |
1 |
| others[3] |
1308 |
1 |
|
T20 |
1 |
|
T8 |
22 |
|
T22 |
1 |
| false |
401 |
1 |
|
T2 |
1 |
|
T43 |
1 |
|
T20 |
1 |
| true |
453 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2500 |
1 |
|
T3 |
1 |
|
T5 |
20 |
|
T7 |
10 |
| others[1] |
2559 |
1 |
|
T5 |
17 |
|
T7 |
13 |
|
T43 |
3 |
| others[2] |
2549 |
1 |
|
T5 |
13 |
|
T7 |
11 |
|
T35 |
1 |
| others[3] |
4175 |
1 |
|
T2 |
1 |
|
T5 |
35 |
|
T7 |
19 |
| false |
1375 |
1 |
|
T5 |
8 |
|
T7 |
3 |
|
T8 |
6 |
| true |
1479 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T58 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10283 |
1 |
|
T5 |
93 |
|
T7 |
56 |
|
T43 |
1 |
| others[1] |
302 |
1 |
|
T3 |
1 |
|
T19 |
1 |
|
T20 |
2 |
| others[2] |
273 |
1 |
|
T2 |
1 |
|
T43 |
1 |
|
T20 |
1 |
| others[3] |
455 |
1 |
|
T43 |
4 |
|
T20 |
2 |
|
T47 |
1 |
| false |
115 |
1 |
|
T36 |
1 |
|
T388 |
1 |
|
T293 |
2 |
| true |
3209 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T35 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10502 |
1 |
|
T3 |
1 |
|
T5 |
93 |
|
T7 |
56 |
| others[1] |
447 |
1 |
|
T17 |
1 |
|
T20 |
3 |
|
T8 |
6 |
| others[2] |
431 |
1 |
|
T20 |
4 |
|
T8 |
5 |
|
T21 |
4 |
| others[3] |
788 |
1 |
|
T43 |
3 |
|
T58 |
1 |
|
T20 |
4 |
| false |
245 |
1 |
|
T43 |
1 |
|
T8 |
1 |
|
T51 |
3 |
| true |
2224 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10301 |
1 |
|
T5 |
93 |
|
T7 |
56 |
|
T20 |
1 |
| others[1] |
274 |
1 |
|
T20 |
1 |
|
T109 |
1 |
|
T222 |
1 |
| others[2] |
230 |
1 |
|
T43 |
2 |
|
T20 |
3 |
|
T206 |
1 |
| others[3] |
428 |
1 |
|
T19 |
1 |
|
T43 |
1 |
|
T20 |
3 |
| false |
124 |
1 |
|
T35 |
1 |
|
T20 |
1 |
|
T23 |
1 |
| true |
3280 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10285 |
1 |
|
T5 |
93 |
|
T7 |
56 |
|
T20 |
2 |
| others[1] |
272 |
1 |
|
T2 |
1 |
|
T43 |
2 |
|
T20 |
2 |
| others[2] |
251 |
1 |
|
T20 |
2 |
|
T166 |
1 |
|
T290 |
1 |
| others[3] |
426 |
1 |
|
T3 |
1 |
|
T35 |
1 |
|
T43 |
1 |
| false |
111 |
1 |
|
T108 |
1 |
|
T32 |
1 |
|
T177 |
1 |
| true |
3292 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10812 |
1 |
|
T3 |
1 |
|
T5 |
93 |
|
T7 |
56 |
| others[1] |
841 |
1 |
|
T43 |
2 |
|
T8 |
7 |
|
T21 |
13 |
| others[2] |
800 |
1 |
|
T20 |
3 |
|
T8 |
19 |
|
T22 |
1 |
| others[3] |
1338 |
1 |
|
T20 |
2 |
|
T8 |
14 |
|
T21 |
14 |
| false |
416 |
1 |
|
T2 |
1 |
|
T35 |
1 |
|
T43 |
1 |
| true |
430 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10875 |
1 |
|
T5 |
93 |
|
T7 |
56 |
|
T35 |
1 |
| others[1] |
837 |
1 |
|
T43 |
1 |
|
T20 |
1 |
|
T8 |
16 |
| others[2] |
793 |
1 |
|
T20 |
1 |
|
T8 |
14 |
|
T23 |
1 |
| others[3] |
1316 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T20 |
4 |
| false |
369 |
1 |
|
T43 |
1 |
|
T8 |
3 |
|
T21 |
1 |
| true |
447 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2486 |
1 |
|
T5 |
13 |
|
T7 |
9 |
|
T43 |
1 |
| others[1] |
2551 |
1 |
|
T5 |
22 |
|
T7 |
11 |
|
T43 |
1 |
| others[2] |
2512 |
1 |
|
T5 |
19 |
|
T7 |
8 |
|
T43 |
4 |
| others[3] |
4277 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
27 |
| false |
1295 |
1 |
|
T5 |
12 |
|
T7 |
7 |
|
T43 |
1 |
| true |
1516 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10305 |
1 |
|
T5 |
93 |
|
T7 |
56 |
|
T35 |
1 |
| others[1] |
270 |
1 |
|
T20 |
1 |
|
T24 |
1 |
|
T26 |
1 |
| others[2] |
285 |
1 |
|
T20 |
4 |
|
T47 |
1 |
|
T206 |
1 |
| others[3] |
435 |
1 |
|
T2 |
1 |
|
T19 |
1 |
|
T43 |
4 |
| false |
124 |
1 |
|
T108 |
1 |
|
T389 |
1 |
|
T110 |
1 |
| true |
3218 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10501 |
1 |
|
T5 |
93 |
|
T7 |
56 |
|
T43 |
1 |
| others[1] |
462 |
1 |
|
T43 |
2 |
|
T20 |
3 |
|
T8 |
4 |
| others[2] |
449 |
1 |
|
T3 |
1 |
|
T43 |
1 |
|
T20 |
6 |
| others[3] |
775 |
1 |
|
T4 |
1 |
|
T43 |
2 |
|
T20 |
5 |
| false |
250 |
1 |
|
T19 |
1 |
|
T43 |
2 |
|
T20 |
1 |
| true |
2200 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T35 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10270 |
1 |
|
T5 |
93 |
|
T7 |
56 |
|
T43 |
1 |
| others[1] |
266 |
1 |
|
T43 |
1 |
|
T20 |
1 |
|
T47 |
2 |
| others[2] |
261 |
1 |
|
T19 |
1 |
|
T43 |
1 |
|
T20 |
2 |
| others[3] |
390 |
1 |
|
T43 |
1 |
|
T20 |
2 |
|
T55 |
1 |
| false |
135 |
1 |
|
T43 |
1 |
|
T25 |
1 |
|
T392 |
1 |
| true |
3315 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10289 |
1 |
|
T5 |
93 |
|
T7 |
56 |
|
T19 |
1 |
| others[1] |
231 |
1 |
|
T2 |
1 |
|
T37 |
1 |
|
T207 |
1 |
| others[2] |
265 |
1 |
|
T3 |
1 |
|
T43 |
1 |
|
T22 |
1 |
| others[3] |
408 |
1 |
|
T43 |
1 |
|
T20 |
5 |
|
T36 |
1 |
| false |
145 |
1 |
|
T43 |
2 |
|
T177 |
1 |
|
T90 |
9 |
| true |
3299 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T43 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10870 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
93 |
| others[1] |
803 |
1 |
|
T35 |
1 |
|
T43 |
1 |
|
T20 |
2 |
| others[2] |
763 |
1 |
|
T43 |
1 |
|
T20 |
1 |
|
T8 |
6 |
| others[3] |
1354 |
1 |
|
T43 |
2 |
|
T8 |
17 |
|
T22 |
1 |
| false |
388 |
1 |
|
T8 |
10 |
|
T55 |
1 |
|
T51 |
6 |
| true |
459 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10854 |
1 |
|
T5 |
93 |
|
T7 |
56 |
|
T43 |
1 |
| others[1] |
787 |
1 |
|
T43 |
1 |
|
T20 |
1 |
|
T8 |
9 |
| others[2] |
808 |
1 |
|
T3 |
1 |
|
T20 |
2 |
|
T8 |
13 |
| others[3] |
1312 |
1 |
|
T17 |
1 |
|
T35 |
1 |
|
T43 |
1 |
| false |
415 |
1 |
|
T2 |
1 |
|
T43 |
1 |
|
T20 |
1 |
| true |
461 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T43 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2466 |
1 |
|
T5 |
13 |
|
T7 |
7 |
|
T43 |
1 |
| others[1] |
2551 |
1 |
|
T2 |
1 |
|
T5 |
18 |
|
T7 |
16 |
| others[2] |
2579 |
1 |
|
T3 |
1 |
|
T5 |
20 |
|
T7 |
12 |
| others[3] |
4240 |
1 |
|
T5 |
33 |
|
T7 |
15 |
|
T43 |
2 |
| false |
1296 |
1 |
|
T5 |
9 |
|
T7 |
6 |
|
T43 |
2 |
| true |
1505 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10316 |
1 |
|
T5 |
93 |
|
T7 |
56 |
|
T35 |
1 |
| others[1] |
267 |
1 |
|
T43 |
2 |
|
T20 |
1 |
|
T22 |
1 |
| others[2] |
277 |
1 |
|
T19 |
1 |
|
T43 |
1 |
|
T20 |
2 |
| others[3] |
436 |
1 |
|
T43 |
2 |
|
T20 |
3 |
|
T109 |
1 |
| false |
129 |
1 |
|
T25 |
1 |
|
T47 |
1 |
|
T52 |
1 |
| true |
3212 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10537 |
1 |
|
T5 |
93 |
|
T7 |
56 |
|
T19 |
1 |
| others[1] |
471 |
1 |
|
T43 |
2 |
|
T20 |
4 |
|
T8 |
2 |
| others[2] |
419 |
1 |
|
T43 |
2 |
|
T20 |
2 |
|
T8 |
2 |
| others[3] |
779 |
1 |
|
T43 |
3 |
|
T58 |
1 |
|
T20 |
4 |
| false |
227 |
1 |
|
T20 |
2 |
|
T8 |
2 |
|
T21 |
3 |
| true |
2204 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10289 |
1 |
|
T5 |
93 |
|
T7 |
56 |
|
T43 |
1 |
| others[1] |
256 |
1 |
|
T3 |
1 |
|
T20 |
1 |
|
T36 |
1 |
| others[2] |
260 |
1 |
|
T35 |
1 |
|
T43 |
1 |
|
T20 |
2 |
| others[3] |
443 |
1 |
|
T43 |
3 |
|
T20 |
1 |
|
T27 |
1 |
| false |
130 |
1 |
|
T22 |
1 |
|
T113 |
1 |
|
T90 |
5 |
| true |
3259 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10283 |
1 |
|
T5 |
93 |
|
T7 |
56 |
|
T43 |
1 |
| others[1] |
235 |
1 |
|
T43 |
1 |
|
T165 |
1 |
|
T39 |
1 |
| others[2] |
252 |
1 |
|
T2 |
1 |
|
T43 |
1 |
|
T20 |
1 |
| others[3] |
409 |
1 |
|
T20 |
6 |
|
T47 |
1 |
|
T109 |
1 |
| false |
128 |
1 |
|
T43 |
1 |
|
T36 |
1 |
|
T108 |
1 |
| true |
3330 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10812 |
1 |
|
T5 |
93 |
|
T7 |
56 |
|
T20 |
1 |
| others[1] |
840 |
1 |
|
T19 |
1 |
|
T35 |
1 |
|
T43 |
1 |
| others[2] |
842 |
1 |
|
T43 |
1 |
|
T20 |
2 |
|
T8 |
10 |
| others[3] |
1289 |
1 |
|
T43 |
2 |
|
T20 |
2 |
|
T8 |
17 |
| false |
420 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T20 |
2 |
| true |
434 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T43 |
4 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |