Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	170839	1		T2	277		T5	550		T7	334
auto[FlashEraseBank]	192876	1		T2	725		T19	26		T35	40

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	180825	1		T2	1002		T5	268		T7	166
auto[FlashOpProgram]	162356	1		T5	141		T7	84		T19	62
auto[FlashOpErase]	16534	1		T5	141		T7	84		T35	27
auto[FlashOpInvalid]	4000	1		T80	200		T232	200		T289	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	180825	1		T2	1002		T5	268		T7	166
op[FlashOpProgram]	162356	1		T5	141		T7	84		T19	62
op[FlashOpErase]	16534	1		T5	141		T7	84		T35	27
read_erase_read	716	1		T35	7		T43	1		T20	2
read_prog_read	1277	1		T35	11		T43	11		T20	3

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	247549	1		T2	1000		T19	33		T35	195
auto[FlashPartInfo]	113104	1		T5	550		T7	334		T19	29
auto[FlashPartInfo1]	741	1		T2	1		T43	6		T36	1
auto[FlashPartInfo2]	2321	1		T2	1		T43	5		T23	21

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	134759	1		T2	1000		T35	80		T43	19
auto[FlashPartData]	auto[FlashOpProgram]	105118	1		T19	33		T35	89		T43	18
auto[FlashPartData]	auto[FlashOpErase]	3768	1		T35	26		T43	2		T20	3
auto[FlashPartData]	auto[FlashOpInvalid]	3904	1		T80	190		T232	200		T289	194
auto[FlashPartInfo]	auto[FlashOpRead]	44147	1		T5	268		T7	166		T35	2
auto[FlashPartInfo]	auto[FlashOpProgram]	56172	1		T5	141		T7	84		T19	29
auto[FlashPartInfo]	auto[FlashOpErase]	12715	1		T5	141		T7	84		T35	1
auto[FlashPartInfo]	auto[FlashOpInvalid]	70	1		T80	8		T289	4		T409	8
auto[FlashPartInfo1]	auto[FlashOpRead]	560	1		T2	1		T43	6		T47	2
auto[FlashPartInfo1]	auto[FlashOpProgram]	166	1		T93	32		T94	1		T116	1
auto[FlashPartInfo1]	auto[FlashOpErase]	7	1		T36	1		T410	2		T116	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	8	1		T116	2		T411	2		T412	4
auto[FlashPartInfo2]	auto[FlashOpRead]	1359	1		T2	1		T43	2		T23	11
auto[FlashPartInfo2]	auto[FlashOpProgram]	900	1		T43	3		T25	1		T47	1
auto[FlashPartInfo2]	auto[FlashOpErase]	44	1		T23	10		T80	1		T112	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	18	1		T80	2		T289	2		T413	2