Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	32287	1		T5	264		T7	160		T35	28
auto[1]	35	1		T172	1		T42	1		T390	2
auto[2]	350	1		T222	44		T130	8		T119	15
auto[3]	303	1		T24	1		T26	1		T52	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	8301	1		T5	66		T7	40		T35	7
evic_idx[1]	8247	1		T5	66		T7	40		T35	7
evic_idx[2]	8215	1		T5	66		T7	40		T35	7
evic_idx[3]	8212	1		T5	66		T7	40		T35	7

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	31652	1		T5	264		T7	160		T70	220
evic_op[2]	647	1		T24	1		T26	1		T30	4

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7817	1		T5	66		T7	40		T70	55
evic_idx[0]	evic_op[1]	auto[1]	7	1		T414	7		-	-		-	-
evic_idx[0]	evic_op[1]	auto[2]	56	1		T222	18		T131	1		T415	37
evic_idx[0]	evic_op[1]	auto[3]	84	1		T416	1		T417	14		T418	35
evic_idx[0]	evic_op[2]	auto[0]	94	1		T30	1		T245	4		T77	8
evic_idx[0]	evic_op[2]	auto[1]	4	1		T172	1		T390	1		T419	1
evic_idx[0]	evic_op[2]	auto[2]	60	1		T119	5		T420	5		T421	12
evic_idx[0]	evic_op[2]	auto[3]	10	1		T213	1		T296	1		T422	1
evic_idx[1]	evic_op[1]	auto[0]	7820	1		T5	66		T7	40		T70	55
evic_idx[1]	evic_op[1]	auto[1]	7	1		T414	7		-	-		-	-
evic_idx[1]	evic_op[1]	auto[2]	22	1		T222	10		T131	1		T415	11
evic_idx[1]	evic_op[1]	auto[3]	61	1		T416	6		T417	7		T418	17
evic_idx[1]	evic_op[2]	auto[0]	94	1		T30	1		T245	4		T77	5
evic_idx[1]	evic_op[2]	auto[1]	5	1		T42	1		T390	1		T423	1
evic_idx[1]	evic_op[2]	auto[2]	56	1		T119	4		T420	8		T421	4
evic_idx[1]	evic_op[2]	auto[3]	13	1		T26	1		T53	1		T215	1
evic_idx[2]	evic_op[1]	auto[0]	7813	1		T5	66		T7	40		T70	55
evic_idx[2]	evic_op[1]	auto[1]	5	1		T414	5		-	-		-	-
evic_idx[2]	evic_op[1]	auto[2]	17	1		T222	9		T131	1		T415	7
evic_idx[2]	evic_op[1]	auto[3]	59	1		T416	6		T417	13		T418	13
evic_idx[2]	evic_op[2]	auto[0]	91	1		T30	1		T245	4		T77	4
evic_idx[2]	evic_op[2]	auto[1]	1	1		T424	1		-	-		-	-
evic_idx[2]	evic_op[2]	auto[2]	49	1		T119	4		T420	8		T421	3
evic_idx[2]	evic_op[2]	auto[3]	11	1		T121	1		T333	1		T425	1
evic_idx[3]	evic_op[1]	auto[0]	7813	1		T5	66		T7	40		T70	55
evic_idx[3]	evic_op[1]	auto[1]	4	1		T414	4		-	-		-	-
evic_idx[3]	evic_op[1]	auto[2]	13	1		T222	7		T131	1		T415	5
evic_idx[3]	evic_op[1]	auto[3]	54	1		T416	6		T417	12		T418	11
evic_idx[3]	evic_op[2]	auto[0]	85	1		T30	1		T245	4		T77	2
evic_idx[3]	evic_op[2]	auto[1]	2	1		T419	1		T424	1		-	-
evic_idx[3]	evic_op[2]	auto[2]	61	1		T119	2		T420	10		T421	5
evic_idx[3]	evic_op[2]	auto[3]	11	1		T24	1		T52	1		T294	1