Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

---

Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	9555	1		T345	1724		T346	7831		-	-
rd_lvl[2]	11002	1		T38	5466		T345	1639		T346	3897
rd_lvl[3]	5823	1		T38	435		T237	2728		T345	454
rd_lvl[4]	8328	1		T237	1532		T347	2342		T345	1041
rd_lvl[5]	6616	1		T37	1582		T38	1		T347	845
rd_lvl[6]	8031	1		T37	1001		T347	1		T199	1202
rd_lvl[7]	2987	1		T347	1		T199	796		T345	286
rd_lvl[8]	8094	1		T348	1521		T349	1342		T345	713
rd_lvl[9]	3421	1		T238	529		T350	516		T348	259
rd_lvl[10]	2263	1		T238	293		T350	201		T345	136
rd_lvl[11]	3049	1		T351	424		T345	1190		T352	483
rd_lvl[12]	4528	1		T38	1		T347	1		T353	436
rd_lvl[13]	3877	1		T38	1		T34	486		T353	388
rd_lvl[14]	2706	1		T354	514		T34	362		T355	399
rd_lvl[15]	3055	1		T32	390		T354	388		T33	215