Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	145841	1		T1	1		T2	2		T13	1
all_pins[1]	145841	1		T1	1		T2	2		T13	1
all_pins[2]	145841	1		T1	1		T2	2		T13	1
all_pins[3]	145841	1		T1	1		T2	2		T13	1
all_pins[4]	145841	1		T1	1		T2	2		T13	1
all_pins[5]	145841	1		T1	1		T2	2		T13	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	725032	1		T1	6		T2	12		T13	6
values[0x1]	150014	1		T22	956		T27	1110		T37	3803
transitions[0x0=>0x1]	136246	1		T22	956		T27	1110		T37	3444
transitions[0x1=>0x0]	136225	1		T22	956		T27	1110		T37	3444

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	145672	1		T1	1		T2	2		T13	1
all_pins[0]	values[0x1]	169	1		T279	3		T280	1		T281	4
all_pins[0]	transitions[0x0=>0x1]	89	1		T280	1		T281	1		T342	2
all_pins[0]	transitions[0x1=>0x0]	77	1		T279	1		T280	6		T340	1
all_pins[1]	values[0x0]	145684	1		T1	1		T2	2		T13	1
all_pins[1]	values[0x1]	157	1		T279	4		T280	6		T281	3
all_pins[1]	transitions[0x0=>0x1]	123	1		T279	3		T280	5		T281	3
all_pins[1]	transitions[0x1=>0x0]	1852	1		T32	280		T33	510		T358	342
all_pins[2]	values[0x0]	143955	1		T1	1		T2	2		T13	1
all_pins[2]	values[0x1]	1886	1		T32	280		T33	510		T358	342
all_pins[2]	transitions[0x0=>0x1]	45	1		T279	1		T280	1		T281	1
all_pins[2]	transitions[0x1=>0x0]	83657	1		T37	2583		T32	390		T38	5904
all_pins[3]	values[0x0]	60343	1		T1	1		T2	2		T13	1
all_pins[3]	values[0x1]	85498	1		T37	2583		T32	670		T38	5904
all_pins[3]	transitions[0x0=>0x1]	73737	1		T37	2224		T32	390		T38	5546
all_pins[3]	transitions[0x1=>0x0]	50480	1		T22	956		T27	1110		T37	861
all_pins[4]	values[0x0]	83600	1		T1	1		T2	2		T13	1
all_pins[4]	values[0x1]	62241	1		T22	956		T27	1110		T37	1220
all_pins[4]	transitions[0x0=>0x1]	62223	1		T22	956		T27	1110		T37	1220
all_pins[4]	transitions[0x1=>0x0]	45	1		T281	1		T340	1		T342	3
all_pins[5]	values[0x0]	145778	1		T1	1		T2	2		T13	1
all_pins[5]	values[0x1]	63	1		T281	1		T340	1		T342	3
all_pins[5]	transitions[0x0=>0x1]	29	1		T342	2		T344	1		T359	4
all_pins[5]	transitions[0x1=>0x0]	114	1		T279	2		T280	1		T281	2