Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	278	1		T279	4		T280	7		T281	4
all_values[1]	278	1		T279	4		T280	7		T281	4
all_values[2]	278	1		T279	4		T280	7		T281	4
all_values[3]	278	1		T279	4		T280	7		T281	4
all_values[4]	278	1		T279	4		T280	7		T281	4
all_values[5]	278	1		T279	4		T280	7		T281	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	890	1		T279	11		T280	24		T281	12
auto[1]	778	1		T279	13		T280	18		T281	12

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	523	1		T279	7		T280	8		T281	6
auto[1]	1145	1		T279	17		T280	34		T281	18

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	966	1		T279	14		T280	22		T281	14
auto[1]	702	1		T279	10		T280	20		T281	10

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	83	1		T279	2		T280	4		T340	2
all_values[0]	auto[0]	auto[1]	auto[1]	81	1		T279	2		T280	1		T281	3
all_values[0]	auto[1]	auto[0]	auto[1]	56	1		T280	2		T340	2		T341	2
all_values[0]	auto[1]	auto[1]	auto[1]	58	1		T281	1		T342	2		T343	4
all_values[1]	auto[0]	auto[0]	auto[1]	95	1		T279	1		T280	2		T340	2
all_values[1]	auto[0]	auto[1]	auto[1]	69	1		T279	1		T280	2		T281	2
all_values[1]	auto[1]	auto[0]	auto[1]	52	1		T280	1		T281	2		T340	1
all_values[1]	auto[1]	auto[1]	auto[1]	62	1		T279	2		T280	2		T340	1
all_values[2]	auto[0]	auto[0]	auto[0]	92	1		T280	1		T281	2		T340	3
all_values[2]	auto[0]	auto[1]	auto[0]	71	1		T279	2		T280	1		T281	1
all_values[2]	auto[1]	auto[0]	auto[1]	55	1		T279	1		T280	2		T341	1
all_values[2]	auto[1]	auto[1]	auto[1]	60	1		T279	1		T280	3		T281	1
all_values[3]	auto[0]	auto[0]	auto[0]	86	1		T279	1		T280	1		T281	2
all_values[3]	auto[0]	auto[1]	auto[0]	77	1		T280	1		T281	1		T341	1
all_values[3]	auto[1]	auto[0]	auto[1]	61	1		T279	3		T280	3		T341	1
all_values[3]	auto[1]	auto[1]	auto[1]	54	1		T280	2		T281	1		T340	2
all_values[4]	auto[0]	auto[0]	auto[0]	55	1		T340	2		T341	1		T342	1
all_values[4]	auto[0]	auto[0]	auto[1]	31	1		T280	3		T281	1		T340	1
all_values[4]	auto[0]	auto[1]	auto[0]	43	1		T280	2		T341	1		T342	2
all_values[4]	auto[0]	auto[1]	auto[1]	30	1		T279	1		T281	1		T341	1
all_values[4]	auto[1]	auto[0]	auto[1]	68	1		T279	2		T280	2		T281	1
all_values[4]	auto[1]	auto[1]	auto[1]	51	1		T279	1		T281	1		T342	2
all_values[5]	auto[0]	auto[0]	auto[0]	60	1		T279	1		T340	1		T341	3
all_values[5]	auto[0]	auto[0]	auto[1]	29	1		T280	2		T281	1		T342	1
all_values[5]	auto[0]	auto[1]	auto[0]	39	1		T279	3		T280	2		T340	1
all_values[5]	auto[0]	auto[1]	auto[1]	25	1		T342	2		T343	1		T344	1
all_values[5]	auto[1]	auto[0]	auto[1]	67	1		T280	1		T281	3		T344	1
all_values[5]	auto[1]	auto[1]	auto[1]	58	1		T280	2		T340	2		T342	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal