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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.57 95.82 94.18 98.85 92.52 98.31 98.11 98.21


Total test records in report: 1196
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T186 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.2909930783 Mar 26 01:09:56 PM PDT 24 Mar 26 01:10:13 PM PDT 24 127737500 ps
T182 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.869279597 Mar 26 01:10:07 PM PDT 24 Mar 26 01:10:23 PM PDT 24 277374600 ps
T342 /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.4184631824 Mar 26 01:10:54 PM PDT 24 Mar 26 01:11:07 PM PDT 24 54095300 ps
T269 /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.821368680 Mar 26 01:09:05 PM PDT 24 Mar 26 01:09:23 PM PDT 24 101961000 ps
T1058 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2850042569 Mar 26 01:09:05 PM PDT 24 Mar 26 01:09:18 PM PDT 24 21429800 ps
T183 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.4259331631 Mar 26 01:10:09 PM PDT 24 Mar 26 01:22:44 PM PDT 24 3121968300 ps
T184 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2536127690 Mar 26 01:10:40 PM PDT 24 Mar 26 01:10:56 PM PDT 24 94069100 ps
T239 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.2266171524 Mar 26 01:09:19 PM PDT 24 Mar 26 01:09:35 PM PDT 24 118472800 ps
T343 /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.2914787165 Mar 26 01:10:52 PM PDT 24 Mar 26 01:11:06 PM PDT 24 33956200 ps
T1059 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.3698771776 Mar 26 01:09:17 PM PDT 24 Mar 26 01:09:30 PM PDT 24 173155300 ps
T270 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2210034787 Mar 26 01:10:08 PM PDT 24 Mar 26 01:10:24 PM PDT 24 19147800 ps
T240 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.4013447976 Mar 26 01:09:05 PM PDT 24 Mar 26 01:23:58 PM PDT 24 1722559900 ps
T246 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.2926993968 Mar 26 01:09:57 PM PDT 24 Mar 26 01:10:16 PM PDT 24 156322300 ps
T247 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.2065126790 Mar 26 01:09:46 PM PDT 24 Mar 26 01:10:05 PM PDT 24 45558800 ps
T310 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.4239546465 Mar 26 01:09:55 PM PDT 24 Mar 26 01:10:14 PM PDT 24 147372900 ps
T1060 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1421366256 Mar 26 01:10:38 PM PDT 24 Mar 26 01:10:51 PM PDT 24 17978400 ps
T248 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2052660165 Mar 26 01:08:53 PM PDT 24 Mar 26 01:23:32 PM PDT 24 701639000 ps
T1061 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3201122888 Mar 26 01:10:25 PM PDT 24 Mar 26 01:10:38 PM PDT 24 18689700 ps
T1062 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.4088002038 Mar 26 01:10:07 PM PDT 24 Mar 26 01:10:21 PM PDT 24 24777100 ps
T344 /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.2676498225 Mar 26 01:09:30 PM PDT 24 Mar 26 01:09:44 PM PDT 24 87387100 ps
T359 /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.1791465180 Mar 26 01:09:45 PM PDT 24 Mar 26 01:09:59 PM PDT 24 260223500 ps
T249 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.4252238664 Mar 26 01:09:17 PM PDT 24 Mar 26 01:09:37 PM PDT 24 389598800 ps
T271 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1364364421 Mar 26 01:10:08 PM PDT 24 Mar 26 01:10:24 PM PDT 24 201703400 ps
T253 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1510601226 Mar 26 01:09:19 PM PDT 24 Mar 26 01:09:32 PM PDT 24 49885400 ps
T250 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.3391116917 Mar 26 01:10:26 PM PDT 24 Mar 26 01:10:42 PM PDT 24 114582000 ps
T1063 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.80017305 Mar 26 01:09:04 PM PDT 24 Mar 26 01:09:19 PM PDT 24 17513600 ps
T274 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.943261274 Mar 26 01:08:45 PM PDT 24 Mar 26 01:09:02 PM PDT 24 70522700 ps
T1064 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.1208412011 Mar 26 01:09:31 PM PDT 24 Mar 26 01:09:45 PM PDT 24 12813900 ps
T1065 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.3274797333 Mar 26 01:09:04 PM PDT 24 Mar 26 01:09:18 PM PDT 24 16511000 ps
T311 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1015901612 Mar 26 01:09:05 PM PDT 24 Mar 26 01:09:20 PM PDT 24 244238400 ps
T1066 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2678874168 Mar 26 01:09:04 PM PDT 24 Mar 26 01:09:18 PM PDT 24 53480000 ps
T285 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.2649143090 Mar 26 01:09:56 PM PDT 24 Mar 26 01:17:42 PM PDT 24 4634661000 ps
T275 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.1605942448 Mar 26 01:09:45 PM PDT 24 Mar 26 01:16:07 PM PDT 24 258986200 ps
T1067 /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.2934082878 Mar 26 01:10:25 PM PDT 24 Mar 26 01:10:38 PM PDT 24 23982800 ps
T1068 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.4292326379 Mar 26 01:09:19 PM PDT 24 Mar 26 01:10:17 PM PDT 24 670251500 ps
T1069 /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3439473682 Mar 26 01:10:34 PM PDT 24 Mar 26 01:10:47 PM PDT 24 27703800 ps
T277 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.2561920976 Mar 26 01:10:25 PM PDT 24 Mar 26 01:10:44 PM PDT 24 282193200 ps
T312 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.2834003671 Mar 26 01:10:08 PM PDT 24 Mar 26 01:10:25 PM PDT 24 154920100 ps
T276 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.4235458850 Mar 26 01:10:09 PM PDT 24 Mar 26 01:10:28 PM PDT 24 189894100 ps
T1070 /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.2456067732 Mar 26 01:10:34 PM PDT 24 Mar 26 01:10:47 PM PDT 24 27857600 ps
T1071 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.700295356 Mar 26 01:09:56 PM PDT 24 Mar 26 01:10:11 PM PDT 24 45294300 ps
T1072 /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.2165691980 Mar 26 01:10:34 PM PDT 24 Mar 26 01:10:48 PM PDT 24 230513300 ps
T1073 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.1578744316 Mar 26 01:10:07 PM PDT 24 Mar 26 01:10:24 PM PDT 24 55871800 ps
T1074 /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.3289425248 Mar 26 01:09:04 PM PDT 24 Mar 26 01:09:17 PM PDT 24 31081200 ps
T313 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.930571882 Mar 26 01:09:56 PM PDT 24 Mar 26 01:10:13 PM PDT 24 245640700 ps
T1075 /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1637660478 Mar 26 01:10:53 PM PDT 24 Mar 26 01:11:07 PM PDT 24 15556500 ps
T1076 /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.2578841895 Mar 26 01:09:36 PM PDT 24 Mar 26 01:09:56 PM PDT 24 254715900 ps
T314 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.1218258764 Mar 26 01:09:30 PM PDT 24 Mar 26 01:09:48 PM PDT 24 60688400 ps
T1077 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.4270254737 Mar 26 01:09:19 PM PDT 24 Mar 26 01:09:49 PM PDT 24 18639100 ps
T1078 /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.458241187 Mar 26 01:10:53 PM PDT 24 Mar 26 01:11:07 PM PDT 24 26236200 ps
T1079 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.4132650081 Mar 26 01:10:26 PM PDT 24 Mar 26 01:10:43 PM PDT 24 62269500 ps
T361 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.3269146281 Mar 26 01:09:44 PM PDT 24 Mar 26 01:24:22 PM PDT 24 1018946300 ps
T370 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1715138679 Mar 26 01:10:07 PM PDT 24 Mar 26 01:25:11 PM PDT 24 836134200 ps
T1080 /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.4054378684 Mar 26 01:10:55 PM PDT 24 Mar 26 01:11:09 PM PDT 24 16924200 ps
T278 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2753291484 Mar 26 01:09:30 PM PDT 24 Mar 26 01:09:47 PM PDT 24 67872000 ps
T1081 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.3949057905 Mar 26 01:09:36 PM PDT 24 Mar 26 01:09:54 PM PDT 24 51597200 ps
T1082 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.134016757 Mar 26 01:10:37 PM PDT 24 Mar 26 01:10:53 PM PDT 24 62428400 ps
T1083 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2768027503 Mar 26 01:09:18 PM PDT 24 Mar 26 01:09:33 PM PDT 24 26236600 ps
T1084 /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.2945908969 Mar 26 01:09:05 PM PDT 24 Mar 26 01:09:18 PM PDT 24 26410800 ps
T1085 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.1142889724 Mar 26 01:09:44 PM PDT 24 Mar 26 01:09:59 PM PDT 24 14320200 ps
T1086 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.370241634 Mar 26 01:09:04 PM PDT 24 Mar 26 01:09:23 PM PDT 24 38897100 ps
T254 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2546660650 Mar 26 01:09:11 PM PDT 24 Mar 26 01:09:25 PM PDT 24 253963700 ps
T284 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.719349668 Mar 26 01:10:25 PM PDT 24 Mar 26 01:10:45 PM PDT 24 118318400 ps
T1087 /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.2593921577 Mar 26 01:10:38 PM PDT 24 Mar 26 01:10:51 PM PDT 24 38018000 ps
T286 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.3260024478 Mar 26 01:10:09 PM PDT 24 Mar 26 01:10:28 PM PDT 24 57724900 ps
T1088 /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1101522646 Mar 26 01:09:46 PM PDT 24 Mar 26 01:10:04 PM PDT 24 630010500 ps
T255 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.3376641670 Mar 26 01:09:23 PM PDT 24 Mar 26 01:09:36 PM PDT 24 38136900 ps
T283 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.993642623 Mar 26 01:10:25 PM PDT 24 Mar 26 01:10:45 PM PDT 24 96642400 ps
T1089 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.3525976820 Mar 26 01:10:24 PM PDT 24 Mar 26 01:10:39 PM PDT 24 35794600 ps
T364 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.2730181381 Mar 26 01:09:18 PM PDT 24 Mar 26 01:16:56 PM PDT 24 491587800 ps
T1090 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.681717058 Mar 26 01:09:44 PM PDT 24 Mar 26 01:10:02 PM PDT 24 58492200 ps
T315 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1592338248 Mar 26 01:09:20 PM PDT 24 Mar 26 01:09:38 PM PDT 24 705195100 ps
T316 /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.4114339320 Mar 26 01:09:24 PM PDT 24 Mar 26 01:09:42 PM PDT 24 471641800 ps
T282 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.1040124061 Mar 26 01:10:22 PM PDT 24 Mar 26 01:17:48 PM PDT 24 181006100 ps
T1091 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.1583021069 Mar 26 01:10:26 PM PDT 24 Mar 26 01:10:43 PM PDT 24 23097500 ps
T367 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2114301736 Mar 26 01:09:29 PM PDT 24 Mar 26 01:24:25 PM PDT 24 1343283100 ps
T365 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1001564702 Mar 26 01:10:24 PM PDT 24 Mar 26 01:17:55 PM PDT 24 699420700 ps
T256 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2246752379 Mar 26 01:09:04 PM PDT 24 Mar 26 01:09:17 PM PDT 24 214697900 ps
T252 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1245910668 Mar 26 01:09:18 PM PDT 24 Mar 26 01:09:31 PM PDT 24 19180400 ps
T1092 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.794693007 Mar 26 01:09:30 PM PDT 24 Mar 26 01:09:48 PM PDT 24 216654200 ps
T1093 /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1167827796 Mar 26 01:09:44 PM PDT 24 Mar 26 01:10:02 PM PDT 24 148807300 ps
T317 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.2167651456 Mar 26 01:10:25 PM PDT 24 Mar 26 01:10:40 PM PDT 24 62833300 ps
T1094 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.173750267 Mar 26 01:09:45 PM PDT 24 Mar 26 01:10:02 PM PDT 24 29563900 ps
T1095 /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.3323216460 Mar 26 01:10:22 PM PDT 24 Mar 26 01:10:36 PM PDT 24 16800100 ps
T372 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.1570091658 Mar 26 01:10:08 PM PDT 24 Mar 26 01:17:47 PM PDT 24 960543500 ps
T1096 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.446916590 Mar 26 01:09:19 PM PDT 24 Mar 26 01:09:34 PM PDT 24 26043000 ps
T318 /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.2588185802 Mar 26 01:09:56 PM PDT 24 Mar 26 01:10:14 PM PDT 24 221332000 ps
T1097 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1488353815 Mar 26 01:10:24 PM PDT 24 Mar 26 01:10:40 PM PDT 24 20131900 ps
T1098 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.2528630342 Mar 26 01:10:07 PM PDT 24 Mar 26 01:10:23 PM PDT 24 33408100 ps
T1099 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.2376633782 Mar 26 01:10:33 PM PDT 24 Mar 26 01:10:49 PM PDT 24 283100300 ps
T1100 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.3888363846 Mar 26 01:09:18 PM PDT 24 Mar 26 01:09:31 PM PDT 24 33869300 ps
T1101 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.2638645998 Mar 26 01:09:22 PM PDT 24 Mar 26 01:09:38 PM PDT 24 44350800 ps
T287 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.1918337688 Mar 26 01:09:36 PM PDT 24 Mar 26 01:09:57 PM PDT 24 57431100 ps
T1102 /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.3646152278 Mar 26 01:10:51 PM PDT 24 Mar 26 01:11:05 PM PDT 24 16133200 ps
T360 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.1392703794 Mar 26 01:09:17 PM PDT 24 Mar 26 01:09:34 PM PDT 24 67480400 ps
T1103 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.2744258505 Mar 26 01:09:47 PM PDT 24 Mar 26 01:10:06 PM PDT 24 101396200 ps
T1104 /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.4094704986 Mar 26 01:10:37 PM PDT 24 Mar 26 01:10:50 PM PDT 24 18070500 ps
T369 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.3848416637 Mar 26 01:10:08 PM PDT 24 Mar 26 01:16:30 PM PDT 24 7059395500 ps
T1105 /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.1915449389 Mar 26 01:10:52 PM PDT 24 Mar 26 01:11:05 PM PDT 24 31929200 ps
T1106 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2841893748 Mar 26 01:10:24 PM PDT 24 Mar 26 01:10:40 PM PDT 24 11197400 ps
T1107 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.52157067 Mar 26 01:09:44 PM PDT 24 Mar 26 01:09:57 PM PDT 24 42489400 ps
T1108 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3312583847 Mar 26 01:09:05 PM PDT 24 Mar 26 01:09:22 PM PDT 24 98344400 ps
T1109 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3941294927 Mar 26 01:10:21 PM PDT 24 Mar 26 01:10:41 PM PDT 24 305582200 ps
T362 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.3062479037 Mar 26 01:10:24 PM PDT 24 Mar 26 01:16:48 PM PDT 24 684592700 ps
T363 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3688070886 Mar 26 01:09:45 PM PDT 24 Mar 26 01:24:43 PM PDT 24 2924456300 ps
T1110 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.623970604 Mar 26 01:10:24 PM PDT 24 Mar 26 01:10:40 PM PDT 24 15258500 ps
T1111 /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.2346324128 Mar 26 01:09:19 PM PDT 24 Mar 26 01:09:53 PM PDT 24 589169800 ps
T1112 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.863838365 Mar 26 01:10:35 PM PDT 24 Mar 26 01:10:50 PM PDT 24 32331400 ps
T1113 /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.3875776870 Mar 26 01:10:25 PM PDT 24 Mar 26 01:10:38 PM PDT 24 22982700 ps
T1114 /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.1025597858 Mar 26 01:09:17 PM PDT 24 Mar 26 01:09:31 PM PDT 24 16520000 ps
T1115 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.230784956 Mar 26 01:09:30 PM PDT 24 Mar 26 01:10:30 PM PDT 24 2560829900 ps
T1116 /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.543798252 Mar 26 01:10:08 PM PDT 24 Mar 26 01:10:28 PM PDT 24 435855100 ps
T1117 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.1765760121 Mar 26 01:10:40 PM PDT 24 Mar 26 01:10:55 PM PDT 24 37317200 ps
T1118 /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.92406092 Mar 26 01:10:11 PM PDT 24 Mar 26 01:10:24 PM PDT 24 32587600 ps
T1119 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3220612415 Mar 26 01:10:21 PM PDT 24 Mar 26 01:10:35 PM PDT 24 70297600 ps
T1120 /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.148229889 Mar 26 01:10:53 PM PDT 24 Mar 26 01:11:06 PM PDT 24 31668100 ps
T1121 /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.3807143326 Mar 26 01:10:55 PM PDT 24 Mar 26 01:11:09 PM PDT 24 54146400 ps
T1122 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.33478060 Mar 26 01:09:45 PM PDT 24 Mar 26 01:10:01 PM PDT 24 12931100 ps
T1123 /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.2010097044 Mar 26 01:10:52 PM PDT 24 Mar 26 01:11:05 PM PDT 24 31251300 ps
T1124 /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.1011549478 Mar 26 01:10:36 PM PDT 24 Mar 26 01:10:53 PM PDT 24 197882700 ps
T1125 /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.1635954860 Mar 26 01:10:52 PM PDT 24 Mar 26 01:11:06 PM PDT 24 32905200 ps
T1126 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.1569070244 Mar 26 01:09:50 PM PDT 24 Mar 26 01:10:05 PM PDT 24 35949200 ps
T1127 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.776663583 Mar 26 01:10:08 PM PDT 24 Mar 26 01:10:26 PM PDT 24 24587900 ps
T1128 /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.2320891053 Mar 26 01:10:09 PM PDT 24 Mar 26 01:10:23 PM PDT 24 16394900 ps
T1129 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.4274425848 Mar 26 01:08:44 PM PDT 24 Mar 26 01:08:57 PM PDT 24 18030400 ps
T1130 /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.862777700 Mar 26 01:10:55 PM PDT 24 Mar 26 01:11:08 PM PDT 24 42921100 ps
T1131 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.47518817 Mar 26 01:09:21 PM PDT 24 Mar 26 01:10:09 PM PDT 24 1194599900 ps
T1132 /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2852244656 Mar 26 01:10:35 PM PDT 24 Mar 26 01:10:48 PM PDT 24 30455300 ps
T1133 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.1244048058 Mar 26 01:10:10 PM PDT 24 Mar 26 01:10:26 PM PDT 24 38556100 ps
T1134 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.785686173 Mar 26 01:09:04 PM PDT 24 Mar 26 01:09:20 PM PDT 24 166099400 ps
T371 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.357030900 Mar 26 01:10:26 PM PDT 24 Mar 26 01:17:58 PM PDT 24 192192300 ps
T1135 /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.1092187798 Mar 26 01:10:25 PM PDT 24 Mar 26 01:10:39 PM PDT 24 59100900 ps
T1136 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.123317138 Mar 26 01:09:24 PM PDT 24 Mar 26 01:09:37 PM PDT 24 14632800 ps
T1137 /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.1522496579 Mar 26 01:10:51 PM PDT 24 Mar 26 01:11:05 PM PDT 24 17764500 ps
T1138 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.798757429 Mar 26 01:10:26 PM PDT 24 Mar 26 01:10:42 PM PDT 24 79933600 ps
T366 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.972994480 Mar 26 01:09:18 PM PDT 24 Mar 26 01:24:13 PM PDT 24 4330144500 ps
T1139 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.4028986615 Mar 26 01:10:40 PM PDT 24 Mar 26 01:10:55 PM PDT 24 32353400 ps
T1140 /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.169171985 Mar 26 01:10:37 PM PDT 24 Mar 26 01:10:51 PM PDT 24 161157400 ps
T1141 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3858438273 Mar 26 01:10:10 PM PDT 24 Mar 26 01:10:26 PM PDT 24 35706300 ps
T1142 /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.3167426870 Mar 26 01:10:09 PM PDT 24 Mar 26 01:10:23 PM PDT 24 269265300 ps
T1143 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3757853916 Mar 26 01:09:04 PM PDT 24 Mar 26 01:09:48 PM PDT 24 50457400 ps
T1144 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.330684149 Mar 26 01:09:16 PM PDT 24 Mar 26 01:09:33 PM PDT 24 68423900 ps
T1145 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1557001881 Mar 26 01:10:08 PM PDT 24 Mar 26 01:10:22 PM PDT 24 43275200 ps
T1146 /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.1832841329 Mar 26 01:10:08 PM PDT 24 Mar 26 01:10:25 PM PDT 24 326534200 ps
T1147 /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.3266380468 Mar 26 01:10:53 PM PDT 24 Mar 26 01:11:06 PM PDT 24 42185400 ps
T1148 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3772567545 Mar 26 01:09:23 PM PDT 24 Mar 26 01:10:17 PM PDT 24 462317700 ps
T1149 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3945744847 Mar 26 01:09:30 PM PDT 24 Mar 26 01:10:24 PM PDT 24 1650364400 ps
T1150 /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.3532021688 Mar 26 01:10:52 PM PDT 24 Mar 26 01:11:06 PM PDT 24 28978000 ps
T1151 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2564380991 Mar 26 01:10:37 PM PDT 24 Mar 26 01:25:52 PM PDT 24 2010674800 ps
T1152 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.2701747185 Mar 26 01:10:33 PM PDT 24 Mar 26 01:10:49 PM PDT 24 18723100 ps
T1153 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.330905619 Mar 26 01:09:36 PM PDT 24 Mar 26 01:09:52 PM PDT 24 142956800 ps
T1154 /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.2401712220 Mar 26 01:10:52 PM PDT 24 Mar 26 01:11:06 PM PDT 24 17377400 ps
T1155 /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.790556850 Mar 26 01:10:25 PM PDT 24 Mar 26 01:10:59 PM PDT 24 96453400 ps
T1156 /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.2126597664 Mar 26 01:09:44 PM PDT 24 Mar 26 01:09:58 PM PDT 24 18437700 ps
T1157 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.923619737 Mar 26 01:09:07 PM PDT 24 Mar 26 01:10:13 PM PDT 24 4861532000 ps
T1158 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.3721646291 Mar 26 01:09:18 PM PDT 24 Mar 26 01:09:33 PM PDT 24 13165700 ps
T1159 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1099395874 Mar 26 01:10:23 PM PDT 24 Mar 26 01:10:41 PM PDT 24 97770900 ps
T1160 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3615800546 Mar 26 01:10:08 PM PDT 24 Mar 26 01:10:27 PM PDT 24 85239800 ps
T1161 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.4010467719 Mar 26 01:09:28 PM PDT 24 Mar 26 01:09:43 PM PDT 24 92511900 ps
T1162 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.3313820376 Mar 26 01:09:07 PM PDT 24 Mar 26 01:09:38 PM PDT 24 147652800 ps
T1163 /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1908017440 Mar 26 01:10:35 PM PDT 24 Mar 26 01:10:49 PM PDT 24 17397700 ps
T368 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.2849222878 Mar 26 01:09:20 PM PDT 24 Mar 26 01:16:45 PM PDT 24 422706500 ps
T1164 /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.2550340470 Mar 26 01:10:54 PM PDT 24 Mar 26 01:11:07 PM PDT 24 16285600 ps
T1165 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.4141106322 Mar 26 01:09:17 PM PDT 24 Mar 26 01:09:30 PM PDT 24 14478200 ps
T1166 /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.3060332856 Mar 26 01:10:52 PM PDT 24 Mar 26 01:11:05 PM PDT 24 28605700 ps
T1167 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.781851892 Mar 26 01:09:04 PM PDT 24 Mar 26 01:09:20 PM PDT 24 12731300 ps
T1168 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.93619964 Mar 26 01:10:26 PM PDT 24 Mar 26 01:10:43 PM PDT 24 209959300 ps
T1169 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3513002135 Mar 26 01:09:06 PM PDT 24 Mar 26 01:09:22 PM PDT 24 96629200 ps
T1170 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.3287226035 Mar 26 01:09:29 PM PDT 24 Mar 26 01:09:55 PM PDT 24 65085700 ps
T1171 /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1668092357 Mar 26 01:10:22 PM PDT 24 Mar 26 01:10:43 PM PDT 24 170400500 ps
T1172 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.761739936 Mar 26 01:10:26 PM PDT 24 Mar 26 01:10:43 PM PDT 24 57459500 ps
T1173 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.3543884548 Mar 26 01:09:44 PM PDT 24 Mar 26 01:09:59 PM PDT 24 36289800 ps
T1174 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2297368221 Mar 26 01:10:07 PM PDT 24 Mar 26 01:10:24 PM PDT 24 14736700 ps
T1175 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.94982336 Mar 26 01:09:47 PM PDT 24 Mar 26 01:10:05 PM PDT 24 44608100 ps
T1176 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.1320580774 Mar 26 01:09:56 PM PDT 24 Mar 26 01:10:13 PM PDT 24 21361800 ps
T1177 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.745962142 Mar 26 01:10:25 PM PDT 24 Mar 26 01:10:40 PM PDT 24 95461400 ps
T1178 /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.4179564600 Mar 26 01:09:04 PM PDT 24 Mar 26 01:09:22 PM PDT 24 468291700 ps
T1179 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.1715401203 Mar 26 01:09:20 PM PDT 24 Mar 26 01:10:30 PM PDT 24 7201068900 ps
T1180 /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.1907944654 Mar 26 01:09:56 PM PDT 24 Mar 26 01:10:12 PM PDT 24 45870300 ps
T1181 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3896773337 Mar 26 01:09:23 PM PDT 24 Mar 26 01:09:36 PM PDT 24 46387300 ps
T1182 /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.3462290808 Mar 26 01:10:34 PM PDT 24 Mar 26 01:10:48 PM PDT 24 219699000 ps
T1183 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.3050987684 Mar 26 01:09:03 PM PDT 24 Mar 26 01:10:17 PM PDT 24 2988287300 ps
T1184 /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.384105479 Mar 26 01:10:53 PM PDT 24 Mar 26 01:11:06 PM PDT 24 16333000 ps
T1185 /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.3491709868 Mar 26 01:09:29 PM PDT 24 Mar 26 01:10:04 PM PDT 24 175500400 ps
T1186 /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.3668543278 Mar 26 01:10:25 PM PDT 24 Mar 26 01:10:38 PM PDT 24 43960500 ps
T1187 /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.3529361458 Mar 26 01:09:56 PM PDT 24 Mar 26 01:10:15 PM PDT 24 123545300 ps
T1188 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.2898226170 Mar 26 01:10:07 PM PDT 24 Mar 26 01:10:24 PM PDT 24 27294700 ps
T1189 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.1505180629 Mar 26 01:10:33 PM PDT 24 Mar 26 01:10:50 PM PDT 24 159446000 ps
T1190 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.586789718 Mar 26 01:09:19 PM PDT 24 Mar 26 01:09:45 PM PDT 24 18317400 ps
T1191 /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.1692519287 Mar 26 01:10:37 PM PDT 24 Mar 26 01:10:50 PM PDT 24 20424500 ps
T1192 /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.84168604 Mar 26 01:10:08 PM PDT 24 Mar 26 01:10:42 PM PDT 24 179138700 ps
T1193 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.4093785870 Mar 26 01:10:25 PM PDT 24 Mar 26 01:10:44 PM PDT 24 96254300 ps
T288 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1532983939 Mar 26 01:10:33 PM PDT 24 Mar 26 01:25:24 PM PDT 24 882297300 ps
T1194 /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3383765866 Mar 26 01:10:24 PM PDT 24 Mar 26 01:10:58 PM PDT 24 71350800 ps
T1195 /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.3860259631 Mar 26 01:09:45 PM PDT 24 Mar 26 01:09:59 PM PDT 24 57262900 ps
T1196 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.4071236003 Mar 26 01:10:22 PM PDT 24 Mar 26 01:10:39 PM PDT 24 155836300 ps

Test location /workspace/coverage/default/10.flash_ctrl_ro.3250965415
Short name T2
Test name
Test status
Simulation time 4147895400 ps
CPU time 103.08 seconds
Started Mar 26 01:25:15 PM PDT 24
Finished Mar 26 01:26:58 PM PDT 24
Peak memory 280000 kb
Host smart-d727c869-9544-490a-b5ef-37464696fbb1
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250965415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.flash_ctrl_ro.3250965415
Directory /workspace/10.flash_ctrl_ro/latest

Test location /workspace/coverage/default/4.flash_ctrl_stress_all.71252704
Short name T20
Test name
Test status
Simulation time 971172200 ps
CPU time 1693.82 seconds
Started Mar 26 01:24:15 PM PDT 24
Finished Mar 26 01:52:29 PM PDT 24
Peak memory 289256 kb
Host smart-e9c0f27a-9d6d-4c0e-a3ff-b26f967092c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71252704 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stress_
all.71252704
Directory /workspace/4.flash_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.4259331631
Short name T183
Test name
Test status
Simulation time 3121968300 ps
CPU time 755.14 seconds
Started Mar 26 01:10:09 PM PDT 24
Finished Mar 26 01:22:44 PM PDT 24
Peak memory 261588 kb
Host smart-6fd231b4-b5da-4c4e-b03c-31ef2772a4e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259331631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctr
l_tl_intg_err.4259331631
Directory /workspace/10.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.3614768504
Short name T125
Test name
Test status
Simulation time 10012149600 ps
CPU time 129.27 seconds
Started Mar 26 01:25:43 PM PDT 24
Finished Mar 26 01:27:53 PM PDT 24
Peak memory 360020 kb
Host smart-593329bb-e12a-4093-bc89-71d45e5ff8a0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614768504 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.3614768504
Directory /workspace/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_cm.2288992324
Short name T6
Test name
Test status
Simulation time 4354292200 ps
CPU time 4712.84 seconds
Started Mar 26 01:23:52 PM PDT 24
Finished Mar 26 02:42:26 PM PDT 24
Peak memory 285960 kb
Host smart-591a9bd9-3356-4b0e-9577-18a35bf9a163
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288992324 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.2288992324
Directory /workspace/3.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict_all_en.2704459238
Short name T26
Test name
Test status
Simulation time 97827200 ps
CPU time 32.05 seconds
Started Mar 26 01:26:50 PM PDT 24
Finished Mar 26 01:27:22 PM PDT 24
Peak memory 275860 kb
Host smart-5773807a-14c0-4a70-b1fc-b529d77e9231
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704459238 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict_all_en.2704459238
Directory /workspace/20.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/0.flash_ctrl_rma_err.912545137
Short name T79
Test name
Test status
Simulation time 663379202100 ps
CPU time 1134.67 seconds
Started Mar 26 01:23:15 PM PDT 24
Finished Mar 26 01:42:10 PM PDT 24
Peak memory 258632 kb
Host smart-6628c933-2816-43d1-b1a7-ce11bb7c76f2
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912545137 -assert nopostproc +UVM_TEST
NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rma_err.912545137
Directory /workspace/0.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_erase_suspend.3168623718
Short name T129
Test name
Test status
Simulation time 2090388800 ps
CPU time 426.07 seconds
Started Mar 26 01:23:36 PM PDT 24
Finished Mar 26 01:30:42 PM PDT 24
Peak memory 261996 kb
Host smart-b985f2d5-9d9c-409e-b091-1786bcb1125f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3168623718 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.3168623718
Directory /workspace/2.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.869279597
Short name T182
Test name
Test status
Simulation time 277374600 ps
CPU time 14.8 seconds
Started Mar 26 01:10:07 PM PDT 24
Finished Mar 26 01:10:23 PM PDT 24
Peak memory 263700 kb
Host smart-de6f0ef0-d658-4b91-9fca-b23a0a617bb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869279597 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.869279597
Directory /workspace/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd_slow_flash.3249832818
Short name T32
Test name
Test status
Simulation time 127084975000 ps
CPU time 209.91 seconds
Started Mar 26 01:25:27 PM PDT 24
Finished Mar 26 01:28:58 PM PDT 24
Peak memory 288928 kb
Host smart-8da57004-0cad-47e9-b815-83f9da42ba54
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249832818 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd_slow_flash.3249832818
Directory /workspace/11.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/21.flash_ctrl_prog_reset.3332152180
Short name T19
Test name
Test status
Simulation time 2082620100 ps
CPU time 20.95 seconds
Started Mar 26 01:26:54 PM PDT 24
Finished Mar 26 01:27:15 PM PDT 24
Peak memory 259740 kb
Host smart-055d4393-2fc8-4556-b4f3-b7bf45a15a86
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332152180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_prog_re
set.3332152180
Directory /workspace/21.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/33.flash_ctrl_otp_reset.616318238
Short name T138
Test name
Test status
Simulation time 132136600 ps
CPU time 130.17 seconds
Started Mar 26 01:28:02 PM PDT 24
Finished Mar 26 01:30:12 PM PDT 24
Peak memory 263480 kb
Host smart-9abbcc84-4c21-45be-88f3-6882db4d5d49
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616318238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_ot
p_reset.616318238
Directory /workspace/33.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_mp_regions.4228362593
Short name T114
Test name
Test status
Simulation time 11629305500 ps
CPU time 220.27 seconds
Started Mar 26 01:25:28 PM PDT 24
Finished Mar 26 01:29:08 PM PDT 24
Peak memory 271728 kb
Host smart-a6809358-4f20-4907-9f0c-0c620ac46b43
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228362593 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 12.flash_ctrl_mp_regions.4228362593
Directory /workspace/12.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/4.flash_ctrl_mid_op_rst.1093929560
Short name T99
Test name
Test status
Simulation time 7934349900 ps
CPU time 75.41 seconds
Started Mar 26 01:24:13 PM PDT 24
Finished Mar 26 01:25:28 PM PDT 24
Peak memory 259836 kb
Host smart-00d4ef52-e069-40e2-b28f-1c1e6314e419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093929560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.1093929560
Directory /workspace/4.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_host_grant_err.2640410248
Short name T14
Test name
Test status
Simulation time 18809000 ps
CPU time 13.61 seconds
Started Mar 26 01:23:49 PM PDT 24
Finished Mar 26 01:24:03 PM PDT 24
Peak memory 260916 kb
Host smart-11c1d9f8-fc49-422e-b37a-48ff0e84eec6
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640410248 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.2640410248
Directory /workspace/2.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_rma_reset.3516647600
Short name T75
Test name
Test status
Simulation time 40124452000 ps
CPU time 878.55 seconds
Started Mar 26 01:26:00 PM PDT 24
Finished Mar 26 01:40:39 PM PDT 24
Peak memory 262516 kb
Host smart-e93e4a9d-77d8-41b6-b76f-e88ad126ab9f
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516647600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.flash_ctrl_hw_rma_reset.3516647600
Directory /workspace/15.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.1024920572
Short name T185
Test name
Test status
Simulation time 85532700 ps
CPU time 18.46 seconds
Started Mar 26 01:09:45 PM PDT 24
Finished Mar 26 01:10:04 PM PDT 24
Peak memory 263804 kb
Host smart-67994df6-e8ab-4b14-bf4f-6cbfea9229c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024920572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.1
024920572
Directory /workspace/7.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/7.flash_ctrl_fetch_code.852618907
Short name T8
Test name
Test status
Simulation time 565374300 ps
CPU time 25.51 seconds
Started Mar 26 01:24:41 PM PDT 24
Finished Mar 26 01:25:06 PM PDT 24
Peak memory 264116 kb
Host smart-60dfc1b6-7811-4f8e-9ee3-69fc5df37bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852618907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetch_code.852618907
Directory /workspace/7.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.4184631824
Short name T342
Test name
Test status
Simulation time 54095300 ps
CPU time 13.62 seconds
Started Mar 26 01:10:54 PM PDT 24
Finished Mar 26 01:11:07 PM PDT 24
Peak memory 262204 kb
Host smart-dee27de9-ecb8-4d4e-95f4-f440ec0d177c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184631824 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test.
4184631824
Directory /workspace/35.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/11.flash_ctrl_otp_reset.2610082396
Short name T147
Test name
Test status
Simulation time 217194000 ps
CPU time 108.34 seconds
Started Mar 26 01:25:28 PM PDT 24
Finished Mar 26 01:27:18 PM PDT 24
Peak memory 259160 kb
Host smart-1e2c3d2a-03d7-4a21-8df1-eecd560f0656
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610082396 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_o
tp_reset.2610082396
Directory /workspace/11.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/46.flash_ctrl_otp_reset.734156546
Short name T150
Test name
Test status
Simulation time 39729900 ps
CPU time 130.6 seconds
Started Mar 26 01:28:42 PM PDT 24
Finished Mar 26 01:30:53 PM PDT 24
Peak memory 263504 kb
Host smart-45817fae-e7e4-45ae-8ec2-4b6258b642eb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734156546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_ot
p_reset.734156546
Directory /workspace/46.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw.1090636575
Short name T83
Test name
Test status
Simulation time 19995710200 ps
CPU time 542.78 seconds
Started Mar 26 01:25:28 PM PDT 24
Finished Mar 26 01:34:31 PM PDT 24
Peak memory 317824 kb
Host smart-eacbf883-a55e-4a0e-9258-22abe203920a
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090636575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_c
trl_rw.1090636575
Directory /workspace/11.flash_ctrl_rw/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_sec_otp.3009073705
Short name T5
Test name
Test status
Simulation time 7497866400 ps
CPU time 66.16 seconds
Started Mar 26 01:26:29 PM PDT 24
Finished Mar 26 01:27:36 PM PDT 24
Peak memory 261576 kb
Host smart-40a5dc3d-4349-4256-b934-2783740c5ed5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009073705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_
hw_sec_otp.3009073705
Directory /workspace/17.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/22.flash_ctrl_disable.2099718783
Short name T60
Test name
Test status
Simulation time 10102200 ps
CPU time 21.55 seconds
Started Mar 26 01:27:02 PM PDT 24
Finished Mar 26 01:27:23 PM PDT 24
Peak memory 272752 kb
Host smart-362eac38-9cca-48fa-aba8-85170b972a54
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099718783 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.flash_ctrl_disable.2099718783
Directory /workspace/22.flash_ctrl_disable/latest

Test location /workspace/coverage/default/21.flash_ctrl_alert_test.1064279224
Short name T166
Test name
Test status
Simulation time 136015800 ps
CPU time 13.4 seconds
Started Mar 26 01:26:54 PM PDT 24
Finished Mar 26 01:27:08 PM PDT 24
Peak memory 264236 kb
Host smart-a6c6930e-9053-463a-8ba6-8c9414ff3f11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064279224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test.
1064279224
Directory /workspace/21.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.flash_ctrl_sec_info_access.1567204580
Short name T29
Test name
Test status
Simulation time 5709506000 ps
CPU time 70.19 seconds
Started Mar 26 01:29:01 PM PDT 24
Finished Mar 26 01:30:11 PM PDT 24
Peak memory 264240 kb
Host smart-78dddb7d-8dfe-450f-b7bf-66e38de95b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567204580 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.1567204580
Directory /workspace/47.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_ctrl_arb.2357284475
Short name T152
Test name
Test status
Simulation time 577421337100 ps
CPU time 2503.06 seconds
Started Mar 26 01:23:36 PM PDT 24
Finished Mar 26 02:05:20 PM PDT 24
Peak memory 264168 kb
Host smart-fb711c0f-91cc-44c2-92df-544c7ef809d2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357284475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.flash_ctrl_host_ctrl_arb.2357284475
Directory /workspace/2.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_mid_op_rst.2111518002
Short name T126
Test name
Test status
Simulation time 2565544700 ps
CPU time 72.37 seconds
Started Mar 26 01:23:53 PM PDT 24
Finished Mar 26 01:25:06 PM PDT 24
Peak memory 259112 kb
Host smart-02675052-c3e8-48e1-9195-8d545c95aa73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111518002 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.2111518002
Directory /workspace/3.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_sec_otp.2384618723
Short name T324
Test name
Test status
Simulation time 14747623000 ps
CPU time 147.6 seconds
Started Mar 26 01:24:51 PM PDT 24
Finished Mar 26 01:27:19 PM PDT 24
Peak memory 261536 kb
Host smart-8540f703-0bad-4dcb-9445-eab157eb2e7d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384618723 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_h
w_sec_otp.2384618723
Directory /workspace/8.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_derr.3226987138
Short name T64
Test name
Test status
Simulation time 6496053000 ps
CPU time 576.68 seconds
Started Mar 26 01:24:52 PM PDT 24
Finished Mar 26 01:34:28 PM PDT 24
Peak memory 323364 kb
Host smart-08b7b3c6-6a5d-4d99-be1d-b94d0adbb872
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226987138 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.flash_ctrl_rw_derr.3226987138
Directory /workspace/8.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_fs_sup.2384041491
Short name T41
Test name
Test status
Simulation time 1122988400 ps
CPU time 36.58 seconds
Started Mar 26 01:23:30 PM PDT 24
Finished Mar 26 01:24:06 PM PDT 24
Peak memory 272348 kb
Host smart-34cc487f-a06b-48f3-9164-4a39580756ee
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384041491 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.flash_ctrl_fs_sup.2384041491
Directory /workspace/1.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2052660165
Short name T248
Test name
Test status
Simulation time 701639000 ps
CPU time 878.37 seconds
Started Mar 26 01:08:53 PM PDT 24
Finished Mar 26 01:23:32 PM PDT 24
Peak memory 263724 kb
Host smart-b73769d1-7796-4025-bf34-27305de2c1c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052660165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl
_tl_intg_err.2052660165
Directory /workspace/0.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_type.4121236555
Short name T168
Test name
Test status
Simulation time 1047644300 ps
CPU time 2483.31 seconds
Started Mar 26 01:23:16 PM PDT 24
Finished Mar 26 02:04:40 PM PDT 24
Peak memory 264268 kb
Host smart-d5a261ce-f57f-4650-850d-ca4fc316c5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121236555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_type.4121236555
Directory /workspace/0.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd.2832751783
Short name T345
Test name
Test status
Simulation time 1092215800 ps
CPU time 201.63 seconds
Started Mar 26 01:27:51 PM PDT 24
Finished Mar 26 01:31:13 PM PDT 24
Peak memory 293800 kb
Host smart-6c7183af-68f4-43f8-b193-3175281912b3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832751783 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fla
sh_ctrl_intr_rd.2832751783
Directory /workspace/31.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1245910668
Short name T252
Test name
Test status
Simulation time 19180400 ps
CPU time 13.47 seconds
Started Mar 26 01:09:18 PM PDT 24
Finished Mar 26 01:09:31 PM PDT 24
Peak memory 263664 kb
Host smart-7ad96e1a-18a3-4fb9-b48c-d9c28bfb6460
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245910668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_mem_partial_access.1245910668
Directory /workspace/4.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/10.flash_ctrl_lcmgr_intg.3900996700
Short name T677
Test name
Test status
Simulation time 15636000 ps
CPU time 13.46 seconds
Started Mar 26 01:25:16 PM PDT 24
Finished Mar 26 01:25:30 PM PDT 24
Peak memory 258724 kb
Host smart-a580c078-9c0c-4b2b-b6e3-a82d761207f4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900996700 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.flash_ctrl_lcmgr_intg.3900996700
Directory /workspace/10.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/15.flash_ctrl_invalid_op.1010380034
Short name T116
Test name
Test status
Simulation time 3374686600 ps
CPU time 69.28 seconds
Started Mar 26 01:25:59 PM PDT 24
Finished Mar 26 01:27:09 PM PDT 24
Peak memory 258416 kb
Host smart-109385d1-d08a-4d12-9968-607a6bfe0116
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010380034 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.1
010380034
Directory /workspace/15.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_read_seed_err.2226137779
Short name T133
Test name
Test status
Simulation time 25828100 ps
CPU time 13.57 seconds
Started Mar 26 01:23:48 PM PDT 24
Finished Mar 26 01:24:02 PM PDT 24
Peak memory 258352 kb
Host smart-ffed1d61-1e4a-4f08-aa29-140cd3c50d84
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226137779 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_read_seed_err.2226137779
Directory /workspace/2.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb_redun.2284728908
Short name T61
Test name
Test status
Simulation time 704590200 ps
CPU time 23.71 seconds
Started Mar 26 01:23:48 PM PDT 24
Finished Mar 26 01:24:11 PM PDT 24
Peak memory 264460 kb
Host smart-d8830c74-5349-40a1-b26f-60717420d476
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284728908 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.2284728908
Directory /workspace/2.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd_slow_flash.318967061
Short name T38
Test name
Test status
Simulation time 8202238200 ps
CPU time 237.84 seconds
Started Mar 26 01:25:30 PM PDT 24
Finished Mar 26 01:29:29 PM PDT 24
Peak memory 292260 kb
Host smart-3095316f-88fc-4160-a676-b1e5b0323ad2
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318967061 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd_slow_flash.318967061
Directory /workspace/12.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.1918337688
Short name T287
Test name
Test status
Simulation time 57431100 ps
CPU time 20.35 seconds
Started Mar 26 01:09:36 PM PDT 24
Finished Mar 26 01:09:57 PM PDT 24
Peak memory 263752 kb
Host smart-a9387ee5-b3c2-43d1-911c-cd6562a92c90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918337688 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.1
918337688
Directory /workspace/5.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict_all_en.1710343527
Short name T119
Test name
Test status
Simulation time 149106700 ps
CPU time 36.83 seconds
Started Mar 26 01:23:48 PM PDT 24
Finished Mar 26 01:24:25 PM PDT 24
Peak memory 272548 kb
Host smart-482faabb-c7bc-49e6-91fa-243ba5b7c493
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710343527 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict_all_en.1710343527
Directory /workspace/3.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/18.flash_ctrl_disable.1723156100
Short name T376
Test name
Test status
Simulation time 72624600 ps
CPU time 21.91 seconds
Started Mar 26 01:26:39 PM PDT 24
Finished Mar 26 01:27:01 PM PDT 24
Peak memory 272716 kb
Host smart-e6756381-32d1-4355-bc9b-a54a6210cf1f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723156100 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_disable.1723156100
Directory /workspace/18.flash_ctrl_disable/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_mp.2345817158
Short name T89
Test name
Test status
Simulation time 37979648300 ps
CPU time 2380.01 seconds
Started Mar 26 01:24:29 PM PDT 24
Finished Mar 26 02:04:09 PM PDT 24
Peak memory 264304 kb
Host smart-fe0f0350-405a-452d-982c-fc556cd6bbdf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345817158 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_err
or_mp.2345817158
Directory /workspace/5.flash_ctrl_error_mp/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.821368680
Short name T269
Test name
Test status
Simulation time 101961000 ps
CPU time 18.08 seconds
Started Mar 26 01:09:05 PM PDT 24
Finished Mar 26 01:09:23 PM PDT 24
Peak memory 259980 kb
Host smart-b550e9f2-14f8-45eb-b191-0094a74a1402
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821368680 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.flash_ctrl_same_csr_outstanding.821368680
Directory /workspace/1.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.flash_ctrl_wr_intg.2367469173
Short name T10
Test name
Test status
Simulation time 85941400 ps
CPU time 14.32 seconds
Started Mar 26 01:23:35 PM PDT 24
Finished Mar 26 01:23:50 PM PDT 24
Peak memory 259288 kb
Host smart-20d0fbea-d2dc-4b27-a1ef-d1d6ecbf1013
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367469173 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wr_intg.2367469173
Directory /workspace/1.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_ctrl_arb.1065798189
Short name T88
Test name
Test status
Simulation time 263813734100 ps
CPU time 2718.39 seconds
Started Mar 26 01:23:48 PM PDT 24
Finished Mar 26 02:09:07 PM PDT 24
Peak memory 264276 kb
Host smart-f4c011dc-c001-43c5-b5af-6cbc2e2d6f83
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065798189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.flash_ctrl_host_ctrl_arb.1065798189
Directory /workspace/3.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1715138679
Short name T370
Test name
Test status
Simulation time 836134200 ps
CPU time 903.01 seconds
Started Mar 26 01:10:07 PM PDT 24
Finished Mar 26 01:25:11 PM PDT 24
Peak memory 263704 kb
Host smart-96583064-f85d-4f52-b204-5450dba82e66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715138679 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctr
l_tl_intg_err.1715138679
Directory /workspace/13.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_re_evict.4243216107
Short name T414
Test name
Test status
Simulation time 104874500 ps
CPU time 33.55 seconds
Started Mar 26 01:23:46 PM PDT 24
Finished Mar 26 01:24:19 PM PDT 24
Peak memory 273608 kb
Host smart-355593d9-91be-47ee-aa7c-9212a7111b9e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243216107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_re_evict.4243216107
Directory /workspace/2.flash_ctrl_re_evict/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.3289425248
Short name T1074
Test name
Test status
Simulation time 31081200 ps
CPU time 13.36 seconds
Started Mar 26 01:09:04 PM PDT 24
Finished Mar 26 01:09:17 PM PDT 24
Peak memory 262240 kb
Host smart-50355dfe-396c-411d-ac2a-f746a7c25b97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289425248 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.3
289425248
Directory /workspace/1.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/0.flash_ctrl_fs_sup.429041377
Short name T424
Test name
Test status
Simulation time 263375700 ps
CPU time 34.17 seconds
Started Mar 26 01:23:19 PM PDT 24
Finished Mar 26 01:23:53 PM PDT 24
Peak memory 272432 kb
Host smart-3cb69dd5-ee09-4492-94c1-27c5249ef276
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429041377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_fs_sup.429041377
Directory /workspace/0.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/10.flash_ctrl_re_evict.991100572
Short name T416
Test name
Test status
Simulation time 452078600 ps
CPU time 35.93 seconds
Started Mar 26 01:25:16 PM PDT 24
Finished Mar 26 01:25:52 PM PDT 24
Peak memory 268880 kb
Host smart-1761ee4d-4362-4825-872c-ba15d5177cda
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991100572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla
sh_ctrl_re_evict.991100572
Directory /workspace/10.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_re_evict.1892554664
Short name T415
Test name
Test status
Simulation time 137430200 ps
CPU time 38.39 seconds
Started Mar 26 01:25:29 PM PDT 24
Finished Mar 26 01:26:09 PM PDT 24
Peak memory 272652 kb
Host smart-77469dde-fcef-432f-8b0c-82c0ff98ed9c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892554664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl
ash_ctrl_re_evict.1892554664
Directory /workspace/12.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_fetch_code.1606809723
Short name T51
Test name
Test status
Simulation time 2189819000 ps
CPU time 31.22 seconds
Started Mar 26 01:23:37 PM PDT 24
Finished Mar 26 01:24:08 PM PDT 24
Peak memory 264176 kb
Host smart-8b847295-1039-4f2b-90cc-e4066162bb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606809723 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetch_code.1606809723
Directory /workspace/2.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_ack_consistency.1525041884
Short name T65
Test name
Test status
Simulation time 54007800 ps
CPU time 13.76 seconds
Started Mar 26 01:23:28 PM PDT 24
Finished Mar 26 01:23:42 PM PDT 24
Peak memory 277512 kb
Host smart-448028f7-d0d8-4e50-b02a-11cdcbaf2fda
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1525041884 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.1525041884
Directory /workspace/1.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_info_access.937521868
Short name T479
Test name
Test status
Simulation time 2284184100 ps
CPU time 61.55 seconds
Started Mar 26 01:23:20 PM PDT 24
Finished Mar 26 01:24:21 PM PDT 24
Peak memory 261476 kb
Host smart-86ac2a87-0251-4aef-b13c-4adf767f0e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937521868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.937521868
Directory /workspace/0.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict_all_en.3436354191
Short name T556
Test name
Test status
Simulation time 50425100 ps
CPU time 31.63 seconds
Started Mar 26 01:27:29 PM PDT 24
Finished Mar 26 01:28:01 PM PDT 24
Peak memory 273544 kb
Host smart-17362e72-68f1-4fb1-b3e8-eeef73c48aca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436354191 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict_all_en.3436354191
Directory /workspace/26.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/35.flash_ctrl_connect.2150528610
Short name T188
Test name
Test status
Simulation time 50473000 ps
CPU time 15.33 seconds
Started Mar 26 01:28:09 PM PDT 24
Finished Mar 26 01:28:25 PM PDT 24
Peak memory 274864 kb
Host smart-74316abb-4d93-4d0e-bfe9-819d52c289d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150528610 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.2150528610
Directory /workspace/35.flash_ctrl_connect/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_read_seed_err.3938240690
Short name T837
Test name
Test status
Simulation time 24908300 ps
CPU time 13.19 seconds
Started Mar 26 01:23:17 PM PDT 24
Finished Mar 26 01:23:31 PM PDT 24
Peak memory 264544 kb
Host smart-c039f7fc-14a9-41d6-bdf6-3c22878044bb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938240690 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.3938240690
Directory /workspace/0.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw.1739771674
Short name T195
Test name
Test status
Simulation time 18975343400 ps
CPU time 482.94 seconds
Started Mar 26 01:24:11 PM PDT 24
Finished Mar 26 01:32:14 PM PDT 24
Peak memory 313528 kb
Host smart-e2bb205c-14f3-4e53-a2a5-86da62f77ba0
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739771674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ct
rl_rw.1739771674
Directory /workspace/4.flash_ctrl_rw/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.2269536623
Short name T17
Test name
Test status
Simulation time 10020726300 ps
CPU time 64.61 seconds
Started Mar 26 01:26:00 PM PDT 24
Finished Mar 26 01:27:05 PM PDT 24
Peak memory 267424 kb
Host smart-cecc84ae-f14f-4cf3-9f09-586a068e6d8f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269536623 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.2269536623
Directory /workspace/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_access_after_disable.2294513956
Short name T49
Test name
Test status
Simulation time 41998400 ps
CPU time 13.58 seconds
Started Mar 26 01:23:47 PM PDT 24
Finished Mar 26 01:24:01 PM PDT 24
Peak memory 264376 kb
Host smart-0ced9e44-4f2e-4a8f-a86c-269d07ac755c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294513956 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.2294513956
Directory /workspace/2.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.943261274
Short name T274
Test name
Test status
Simulation time 70522700 ps
CPU time 16.59 seconds
Started Mar 26 01:08:45 PM PDT 24
Finished Mar 26 01:09:02 PM PDT 24
Peak memory 263884 kb
Host smart-3188b201-8355-41de-bc00-7fc76455c687
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943261274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.943261274
Directory /workspace/0.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/13.flash_ctrl_lcmgr_intg.1849128158
Short name T682
Test name
Test status
Simulation time 83107800 ps
CPU time 13.25 seconds
Started Mar 26 01:25:50 PM PDT 24
Finished Mar 26 01:26:03 PM PDT 24
Peak memory 259628 kb
Host smart-3dba22e2-19bf-45fe-82e3-96ca47cc10a3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849128158 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.flash_ctrl_lcmgr_intg.1849128158
Directory /workspace/13.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.2730181381
Short name T364
Test name
Test status
Simulation time 491587800 ps
CPU time 458.14 seconds
Started Mar 26 01:09:18 PM PDT 24
Finished Mar 26 01:16:56 PM PDT 24
Peak memory 263544 kb
Host smart-d3e4b863-e7da-4479-84fb-211b74bf094e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730181381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl
_tl_intg_err.2730181381
Directory /workspace/2.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_re_evict.2806740302
Short name T23
Test name
Test status
Simulation time 424068600 ps
CPU time 38.64 seconds
Started Mar 26 01:23:24 PM PDT 24
Finished Mar 26 01:24:03 PM PDT 24
Peak memory 273656 kb
Host smart-3dabe580-a42a-4e3a-ba32-d49fa3c3e789
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806740302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_re_evict.2806740302
Directory /workspace/1.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_win.796422465
Short name T842
Test name
Test status
Simulation time 2826891400 ps
CPU time 818.64 seconds
Started Mar 26 01:23:17 PM PDT 24
Finished Mar 26 01:36:56 PM PDT 24
Peak memory 272500 kb
Host smart-a8b2c8dc-009e-4fd8-93a8-f65689800bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796422465 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.796422465
Directory /workspace/0.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_rma_reset.3339731263
Short name T141
Test name
Test status
Simulation time 80136484700 ps
CPU time 816.5 seconds
Started Mar 26 01:25:31 PM PDT 24
Finished Mar 26 01:39:08 PM PDT 24
Peak memory 262596 kb
Host smart-f54ac400-148b-433e-a98e-4955ea07bc89
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339731263 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.flash_ctrl_hw_rma_reset.3339731263
Directory /workspace/11.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.2242122582
Short name T304
Test name
Test status
Simulation time 10024321300 ps
CPU time 137.82 seconds
Started Mar 26 01:25:16 PM PDT 24
Finished Mar 26 01:27:34 PM PDT 24
Peak memory 279180 kb
Host smart-ae8d2c3b-2ad4-4d48-a4c8-dedff132c87b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242122582 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.2242122582
Directory /workspace/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.2849222878
Short name T368
Test name
Test status
Simulation time 422706500 ps
CPU time 444.49 seconds
Started Mar 26 01:09:20 PM PDT 24
Finished Mar 26 01:16:45 PM PDT 24
Peak memory 263816 kb
Host smart-5e49f0c9-05ed-49e5-bd71-2f810f2b6f69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849222878 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl
_tl_intg_err.2849222878
Directory /workspace/3.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_sec_info_access.1014409643
Short name T381
Test name
Test status
Simulation time 3115166800 ps
CPU time 75.03 seconds
Started Mar 26 01:26:39 PM PDT 24
Finished Mar 26 01:27:54 PM PDT 24
Peak memory 261012 kb
Host smart-ee7e1bc6-d01f-42f2-98d6-0bd25728cbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014409643 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.1014409643
Directory /workspace/18.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/26.flash_ctrl_sec_info_access.2242389811
Short name T402
Test name
Test status
Simulation time 6501221100 ps
CPU time 75.94 seconds
Started Mar 26 01:27:38 PM PDT 24
Finished Mar 26 01:28:54 PM PDT 24
Peak memory 262352 kb
Host smart-f4fd188c-22aa-49a1-af17-f4def17a7b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242389811 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.2242389811
Directory /workspace/26.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/14.flash_ctrl_rand_ops.700207773
Short name T108
Test name
Test status
Simulation time 720899500 ps
CPU time 701.74 seconds
Started Mar 26 01:25:56 PM PDT 24
Finished Mar 26 01:37:38 PM PDT 24
Peak memory 281956 kb
Host smart-d8daa4a7-c3cf-4a84-8e5b-ff63963ea0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700207773 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.700207773
Directory /workspace/14.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_cm.857087227
Short name T192
Test name
Test status
Simulation time 1587832500 ps
CPU time 4645.55 seconds
Started Mar 26 01:23:21 PM PDT 24
Finished Mar 26 02:40:47 PM PDT 24
Peak memory 285968 kb
Host smart-b1d969b5-7f3b-40f2-98d4-03ac087dd2c2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857087227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.857087227
Directory /workspace/0.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/10.flash_ctrl_disable.4068305790
Short name T877
Test name
Test status
Simulation time 33153000 ps
CPU time 20.8 seconds
Started Mar 26 01:25:15 PM PDT 24
Finished Mar 26 01:25:36 PM PDT 24
Peak memory 272652 kb
Host smart-9b923a9c-68e0-4eb8-b941-f438a8c9277f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068305790 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_disable.4068305790
Directory /workspace/10.flash_ctrl_disable/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_dir_rd.2865934988
Short name T291
Test name
Test status
Simulation time 95200100 ps
CPU time 121.88 seconds
Started Mar 26 01:24:05 PM PDT 24
Finished Mar 26 01:26:07 PM PDT 24
Peak memory 264112 kb
Host smart-49e3256b-2ced-4cc1-940c-280bc94a43f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2865934988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.2865934988
Directory /workspace/4.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.2266171524
Short name T239
Test name
Test status
Simulation time 118472800 ps
CPU time 15.81 seconds
Started Mar 26 01:09:19 PM PDT 24
Finished Mar 26 01:09:35 PM PDT 24
Peak memory 261180 kb
Host smart-d80c1779-e0d2-4adc-8f38-cadf053ec9e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266171524 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.2
266171524
Directory /workspace/3.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.flash_ctrl_config_regwen.3495879067
Short name T902
Test name
Test status
Simulation time 73825000 ps
CPU time 13.6 seconds
Started Mar 26 01:23:15 PM PDT 24
Finished Mar 26 01:23:29 PM PDT 24
Peak memory 260724 kb
Host smart-c02965cf-fed4-4044-8f2f-2f0ce14c39d3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495879067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.flash_ctrl_config_regwen.3495879067
Directory /workspace/0.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/12.flash_ctrl_invalid_op.2324881617
Short name T289
Test name
Test status
Simulation time 2173991300 ps
CPU time 87.34 seconds
Started Mar 26 01:25:28 PM PDT 24
Finished Mar 26 01:26:56 PM PDT 24
Peak memory 259932 kb
Host smart-147141f8-3852-4494-ab28-351bc59cca1c
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324881617 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.2
324881617
Directory /workspace/12.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/37.flash_ctrl_sec_info_access.806876051
Short name T332
Test name
Test status
Simulation time 14689855000 ps
CPU time 75.32 seconds
Started Mar 26 01:28:17 PM PDT 24
Finished Mar 26 01:29:33 PM PDT 24
Peak memory 262376 kb
Host smart-c38c22d4-f9ab-45fb-ab75-9a4463e1686c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806876051 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.806876051
Directory /workspace/37.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.1570091658
Short name T372
Test name
Test status
Simulation time 960543500 ps
CPU time 458.33 seconds
Started Mar 26 01:10:08 PM PDT 24
Finished Mar 26 01:17:47 PM PDT 24
Peak memory 260048 kb
Host smart-b6c51741-0421-4b89-b5fe-599c25628276
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570091658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctr
l_tl_intg_err.1570091658
Directory /workspace/12.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_disable.3460355054
Short name T644
Test name
Test status
Simulation time 13479700 ps
CPU time 20.89 seconds
Started Mar 26 01:23:13 PM PDT 24
Finished Mar 26 01:23:34 PM PDT 24
Peak memory 264348 kb
Host smart-414f2b14-4f4a-41ea-b8f8-c42d4916235f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460355054 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_disable.3460355054
Directory /workspace/0.flash_ctrl_disable/latest

Test location /workspace/coverage/default/11.flash_ctrl_disable.4171092712
Short name T375
Test name
Test status
Simulation time 12706300 ps
CPU time 21.47 seconds
Started Mar 26 01:25:28 PM PDT 24
Finished Mar 26 01:25:51 PM PDT 24
Peak memory 272384 kb
Host smart-4c378122-d856-480b-8f71-0ad09525cabb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171092712 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_disable.4171092712
Directory /workspace/11.flash_ctrl_disable/latest

Test location /workspace/coverage/default/12.flash_ctrl_sec_info_access.2450956376
Short name T405
Test name
Test status
Simulation time 1203445500 ps
CPU time 65.64 seconds
Started Mar 26 01:25:44 PM PDT 24
Finished Mar 26 01:26:50 PM PDT 24
Peak memory 262268 kb
Host smart-f1658644-1f80-4d0e-94c2-f3b691efb701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450956376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.2450956376
Directory /workspace/12.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/14.flash_ctrl_disable.1258136310
Short name T980
Test name
Test status
Simulation time 10183600 ps
CPU time 21.87 seconds
Started Mar 26 01:25:58 PM PDT 24
Finished Mar 26 01:26:21 PM PDT 24
Peak memory 272896 kb
Host smart-27b87b17-3024-49de-8b6d-3bbfcf96e0ce
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258136310 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.flash_ctrl_disable.1258136310
Directory /workspace/14.flash_ctrl_disable/latest

Test location /workspace/coverage/default/17.flash_ctrl_disable.1589392244
Short name T373
Test name
Test status
Simulation time 34559100 ps
CPU time 20.48 seconds
Started Mar 26 01:26:28 PM PDT 24
Finished Mar 26 01:26:48 PM PDT 24
Peak memory 272528 kb
Host smart-3af2e7b6-f8f8-4947-a6f6-efcec5fe7199
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589392244 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_disable.1589392244
Directory /workspace/17.flash_ctrl_disable/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_rma_reset.4156563283
Short name T779
Test name
Test status
Simulation time 160197415700 ps
CPU time 940.17 seconds
Started Mar 26 01:26:32 PM PDT 24
Finished Mar 26 01:42:13 PM PDT 24
Peak memory 263516 kb
Host smart-1bab343c-33e4-46eb-9b56-36b192415649
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156563283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 18.flash_ctrl_hw_rma_reset.4156563283
Directory /workspace/18.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_info_access.2256445984
Short name T379
Test name
Test status
Simulation time 1817307600 ps
CPU time 67.21 seconds
Started Mar 26 01:24:14 PM PDT 24
Finished Mar 26 01:25:22 PM PDT 24
Peak memory 262296 kb
Host smart-41e66183-cb0c-4027-8ada-bf204bd7ca1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256445984 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.2256445984
Directory /workspace/2.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/23.flash_ctrl_disable.2877313059
Short name T399
Test name
Test status
Simulation time 13238300 ps
CPU time 20.6 seconds
Started Mar 26 01:27:05 PM PDT 24
Finished Mar 26 01:27:26 PM PDT 24
Peak memory 264428 kb
Host smart-97e53caa-5a31-4dd4-b688-6c4a51192a85
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877313059 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.flash_ctrl_disable.2877313059
Directory /workspace/23.flash_ctrl_disable/latest

Test location /workspace/coverage/default/40.flash_ctrl_disable.3093817948
Short name T159
Test name
Test status
Simulation time 17348500 ps
CPU time 21.3 seconds
Started Mar 26 01:28:30 PM PDT 24
Finished Mar 26 01:28:51 PM PDT 24
Peak memory 272444 kb
Host smart-89a7f7be-4589-4be4-b831-5348c17c72ee
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093817948 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.flash_ctrl_disable.3093817948
Directory /workspace/40.flash_ctrl_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr.3673666520
Short name T104
Test name
Test status
Simulation time 8694486300 ps
CPU time 103.28 seconds
Started Mar 26 01:23:21 PM PDT 24
Finished Mar 26 01:25:05 PM PDT 24
Peak memory 259272 kb
Host smart-b474339e-efae-4b1c-be8b-13aefba6dc17
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673666520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.flash_ctrl_intr_wr.3673666520
Directory /workspace/0.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/1.flash_ctrl_integrity.1070767746
Short name T223
Test name
Test status
Simulation time 10734491600 ps
CPU time 546.11 seconds
Started Mar 26 01:23:29 PM PDT 24
Finished Mar 26 01:32:35 PM PDT 24
Peak memory 324524 kb
Host smart-3ff1c128-386d-4f96-95a5-84aeb1ab8494
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070767746 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_integrity.1070767746
Directory /workspace/1.flash_ctrl_integrity/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1052148072
Short name T44
Test name
Test status
Simulation time 41781300 ps
CPU time 16.75 seconds
Started Mar 26 01:09:17 PM PDT 24
Finished Mar 26 01:09:34 PM PDT 24
Peak memory 260088 kb
Host smart-6a5a0376-cb34-4ba8-801b-6fc48038f8f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052148072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.flash_ctrl_csr_rw.1052148072
Directory /workspace/2.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_ack_consistency.2825381904
Short name T236
Test name
Test status
Simulation time 16489900 ps
CPU time 13.65 seconds
Started Mar 26 01:23:13 PM PDT 24
Finished Mar 26 01:23:27 PM PDT 24
Peak memory 260096 kb
Host smart-46b7c717-3743-494c-953d-beafcbf5ed4c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2825381904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.2825381904
Directory /workspace/0.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/64.flash_ctrl_otp_reset.705237640
Short name T137
Test name
Test status
Simulation time 125743400 ps
CPU time 109 seconds
Started Mar 26 01:29:04 PM PDT 24
Finished Mar 26 01:30:53 PM PDT 24
Peak memory 260196 kb
Host smart-bad359ea-162d-4018-9cce-12a83f7ebd41
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705237640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_ot
p_reset.705237640
Directory /workspace/64.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.1040124061
Short name T282
Test name
Test status
Simulation time 181006100 ps
CPU time 446.6 seconds
Started Mar 26 01:10:22 PM PDT 24
Finished Mar 26 01:17:48 PM PDT 24
Peak memory 261236 kb
Host smart-45554728-136e-4b19-b723-7266860d5c86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040124061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctr
l_tl_intg_err.1040124061
Directory /workspace/16.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1532983939
Short name T288
Test name
Test status
Simulation time 882297300 ps
CPU time 890.72 seconds
Started Mar 26 01:10:33 PM PDT 24
Finished Mar 26 01:25:24 PM PDT 24
Peak memory 263664 kb
Host smart-208b5bf9-01c8-477b-bd71-46918c3d2133
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532983939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctr
l_tl_intg_err.1532983939
Directory /workspace/19.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_access_after_disable.623556274
Short name T48
Test name
Test status
Simulation time 21507500 ps
CPU time 13.41 seconds
Started Mar 26 01:23:14 PM PDT 24
Finished Mar 26 01:23:27 PM PDT 24
Peak memory 260960 kb
Host smart-82953c7a-281a-47cc-8de0-5e80b251af7a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623556274 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.623556274
Directory /workspace/0.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_wr_intg.1120603834
Short name T175
Test name
Test status
Simulation time 167879100 ps
CPU time 14.63 seconds
Started Mar 26 01:23:19 PM PDT 24
Finished Mar 26 01:23:34 PM PDT 24
Peak memory 263912 kb
Host smart-1f5b0750-0ede-4181-b6fb-0796610cde89
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120603834 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wr_intg.1120603834
Directory /workspace/0.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_access_after_disable.1287189940
Short name T50
Test name
Test status
Simulation time 40761400 ps
CPU time 13.47 seconds
Started Mar 26 01:23:33 PM PDT 24
Finished Mar 26 01:23:47 PM PDT 24
Peak memory 260940 kb
Host smart-9883b525-a618-4820-8ef1-00dd72ff1f43
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287189940 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.1287189940
Directory /workspace/1.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_ctrl_arb.2790345685
Short name T87
Test name
Test status
Simulation time 284501280300 ps
CPU time 2890.13 seconds
Started Mar 26 01:24:06 PM PDT 24
Finished Mar 26 02:12:17 PM PDT 24
Peak memory 264188 kb
Host smart-e2c53ae5-1d10-4fd1-b454-673c8a78bfc9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790345685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 4.flash_ctrl_host_ctrl_arb.2790345685
Directory /workspace/4.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_host_grant_err.1074775941
Short name T63
Test name
Test status
Simulation time 45821400 ps
CPU time 13.74 seconds
Started Mar 26 01:24:04 PM PDT 24
Finished Mar 26 01:24:19 PM PDT 24
Peak memory 261456 kb
Host smart-d324f364-2783-4f11-8f9f-787fbfcaef9d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074775941 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.1074775941
Directory /workspace/4.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_derr.487717719
Short name T216
Test name
Test status
Simulation time 8635263600 ps
CPU time 136.69 seconds
Started Mar 26 01:25:06 PM PDT 24
Finished Mar 26 01:27:22 PM PDT 24
Peak memory 280656 kb
Host smart-3bf0f17c-f933-4d72-8480-b178313ffcbc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
487717719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.487717719
Directory /workspace/9.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.2407013355
Short name T46
Test name
Test status
Simulation time 962298300 ps
CPU time 49.1 seconds
Started Mar 26 01:09:08 PM PDT 24
Finished Mar 26 01:09:58 PM PDT 24
Peak memory 260088 kb
Host smart-3cb230ce-d641-4248-8922-65de8d2c0c6b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407013355 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_aliasing.2407013355
Directory /workspace/0.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.3050987684
Short name T1183
Test name
Test status
Simulation time 2988287300 ps
CPU time 74.65 seconds
Started Mar 26 01:09:03 PM PDT 24
Finished Mar 26 01:10:17 PM PDT 24
Peak memory 260028 kb
Host smart-29b318e2-fa41-40c8-8aa6-a767e72d1780
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050987684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_bit_bash.3050987684
Directory /workspace/0.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3757853916
Short name T1143
Test name
Test status
Simulation time 50457400 ps
CPU time 44.46 seconds
Started Mar 26 01:09:04 PM PDT 24
Finished Mar 26 01:09:48 PM PDT 24
Peak memory 260016 kb
Host smart-2fd3b3aa-da36-4ed4-b8f5-a0362ed2e362
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757853916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_hw_reset.3757853916
Directory /workspace/0.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3312583847
Short name T1108
Test name
Test status
Simulation time 98344400 ps
CPU time 16.89 seconds
Started Mar 26 01:09:05 PM PDT 24
Finished Mar 26 01:09:22 PM PDT 24
Peak memory 271936 kb
Host smart-e08cb4cc-8bea-4a4c-8bdf-08884156e636
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312583847 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.3312583847
Directory /workspace/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1015901612
Short name T311
Test name
Test status
Simulation time 244238400 ps
CPU time 14.81 seconds
Started Mar 26 01:09:05 PM PDT 24
Finished Mar 26 01:09:20 PM PDT 24
Peak memory 261304 kb
Host smart-5614e251-4109-4438-a8c8-ddd3c92e1017
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015901612 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_csr_rw.1015901612
Directory /workspace/0.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.2945908969
Short name T1084
Test name
Test status
Simulation time 26410800 ps
CPU time 13.34 seconds
Started Mar 26 01:09:05 PM PDT 24
Finished Mar 26 01:09:18 PM PDT 24
Peak memory 262548 kb
Host smart-a1b18801-4eda-4dec-a8d8-002096f4e7a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945908969 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.2
945908969
Directory /workspace/0.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2246752379
Short name T256
Test name
Test status
Simulation time 214697900 ps
CPU time 13.47 seconds
Started Mar 26 01:09:04 PM PDT 24
Finished Mar 26 01:09:17 PM PDT 24
Peak memory 263176 kb
Host smart-60cede23-18b6-4d70-aac3-9c86f9db9aa5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246752379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_mem_partial_access.2246752379
Directory /workspace/0.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.3274797333
Short name T1065
Test name
Test status
Simulation time 16511000 ps
CPU time 13.49 seconds
Started Mar 26 01:09:04 PM PDT 24
Finished Mar 26 01:09:18 PM PDT 24
Peak memory 262276 kb
Host smart-380b407f-8e5b-4f78-b925-c669209de3fe
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274797333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_me
m_walk.3274797333
Directory /workspace/0.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.4179564600
Short name T1178
Test name
Test status
Simulation time 468291700 ps
CPU time 18.1 seconds
Started Mar 26 01:09:04 PM PDT 24
Finished Mar 26 01:09:22 PM PDT 24
Peak memory 259996 kb
Host smart-e96278dc-a41e-4b10-b1c1-7c46bd7293f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179564600 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.flash_ctrl_same_csr_outstanding.4179564600
Directory /workspace/0.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.4274425848
Short name T1129
Test name
Test status
Simulation time 18030400 ps
CPU time 13.05 seconds
Started Mar 26 01:08:44 PM PDT 24
Finished Mar 26 01:08:57 PM PDT 24
Peak memory 260016 kb
Host smart-0b17e874-4a0a-4cff-a14e-8f4e481855e2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274425848 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors.4274425848
Directory /workspace/0.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2850042569
Short name T1058
Test name
Test status
Simulation time 21429800 ps
CPU time 13 seconds
Started Mar 26 01:09:05 PM PDT 24
Finished Mar 26 01:09:18 PM PDT 24
Peak memory 260064 kb
Host smart-3196c61a-56b7-44f3-964d-6b85b3a76b91
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850042569 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors_with_csr_rw.2850042569
Directory /workspace/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1832215313
Short name T273
Test name
Test status
Simulation time 264625000 ps
CPU time 35.6 seconds
Started Mar 26 01:09:05 PM PDT 24
Finished Mar 26 01:09:40 PM PDT 24
Peak memory 260024 kb
Host smart-30504131-4bcd-4da3-b2d4-72e7abbfbaa3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832215313 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_aliasing.1832215313
Directory /workspace/1.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.923619737
Short name T1157
Test name
Test status
Simulation time 4861532000 ps
CPU time 65.66 seconds
Started Mar 26 01:09:07 PM PDT 24
Finished Mar 26 01:10:13 PM PDT 24
Peak memory 259968 kb
Host smart-a366bcf6-150b-42dc-b62b-cc0759bb1a6c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923619737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.flash_ctrl_csr_bit_bash.923619737
Directory /workspace/1.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.3313820376
Short name T1162
Test name
Test status
Simulation time 147652800 ps
CPU time 31 seconds
Started Mar 26 01:09:07 PM PDT 24
Finished Mar 26 01:09:38 PM PDT 24
Peak memory 259972 kb
Host smart-461ea8a7-4244-4417-b90c-596ac8c6e9ee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313820376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_hw_reset.3313820376
Directory /workspace/1.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.370241634
Short name T1086
Test name
Test status
Simulation time 38897100 ps
CPU time 19.01 seconds
Started Mar 26 01:09:04 PM PDT 24
Finished Mar 26 01:09:23 PM PDT 24
Peak memory 271964 kb
Host smart-429ebc89-e7a6-4c76-9f9d-39e694b744e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370241634 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.370241634
Directory /workspace/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.3149785020
Short name T267
Test name
Test status
Simulation time 32888700 ps
CPU time 16.1 seconds
Started Mar 26 01:09:05 PM PDT 24
Finished Mar 26 01:09:22 PM PDT 24
Peak memory 260148 kb
Host smart-69773277-6b91-4b76-934e-f682310d5097
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149785020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.flash_ctrl_csr_rw.3149785020
Directory /workspace/1.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2546660650
Short name T254
Test name
Test status
Simulation time 253963700 ps
CPU time 13.69 seconds
Started Mar 26 01:09:11 PM PDT 24
Finished Mar 26 01:09:25 PM PDT 24
Peak memory 260684 kb
Host smart-3767a49a-4563-433b-92d7-4b8b7bfbee72
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546660650 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_mem_partial_access.2546660650
Directory /workspace/1.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2678874168
Short name T1066
Test name
Test status
Simulation time 53480000 ps
CPU time 13.63 seconds
Started Mar 26 01:09:04 PM PDT 24
Finished Mar 26 01:09:18 PM PDT 24
Peak memory 262256 kb
Host smart-00785b43-ea56-4db3-b8fa-9279ed4058d0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678874168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_me
m_walk.2678874168
Directory /workspace/1.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.781851892
Short name T1167
Test name
Test status
Simulation time 12731300 ps
CPU time 15.36 seconds
Started Mar 26 01:09:04 PM PDT 24
Finished Mar 26 01:09:20 PM PDT 24
Peak memory 260084 kb
Host smart-850b8796-3e90-484f-9e1b-d8bdf2e7f9bb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781851892 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.flash_ctrl_shadow_reg_errors.781851892
Directory /workspace/1.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.80017305
Short name T1063
Test name
Test status
Simulation time 17513600 ps
CPU time 15.44 seconds
Started Mar 26 01:09:04 PM PDT 24
Finished Mar 26 01:09:19 PM PDT 24
Peak memory 259956 kb
Host smart-9c2df8bd-4ce1-445d-9583-7b42864087e8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80017305 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors_with_csr_rw.80017305
Directory /workspace/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3513002135
Short name T1169
Test name
Test status
Simulation time 96629200 ps
CPU time 16.17 seconds
Started Mar 26 01:09:06 PM PDT 24
Finished Mar 26 01:09:22 PM PDT 24
Peak memory 263764 kb
Host smart-d18a38ac-3069-47bf-ae8a-eed4a03ca543
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513002135 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.3
513002135
Directory /workspace/1.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.4013447976
Short name T240
Test name
Test status
Simulation time 1722559900 ps
CPU time 892.28 seconds
Started Mar 26 01:09:05 PM PDT 24
Finished Mar 26 01:23:58 PM PDT 24
Peak memory 263776 kb
Host smart-13e30346-d839-4bf1-ba92-47bc8c408bb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013447976 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl
_tl_intg_err.4013447976
Directory /workspace/1.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3615800546
Short name T1160
Test name
Test status
Simulation time 85239800 ps
CPU time 18.66 seconds
Started Mar 26 01:10:08 PM PDT 24
Finished Mar 26 01:10:27 PM PDT 24
Peak memory 271560 kb
Host smart-133e2265-be20-456a-a119-0d4f2e62337a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615800546 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.3615800546
Directory /workspace/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.2834003671
Short name T312
Test name
Test status
Simulation time 154920100 ps
CPU time 16.56 seconds
Started Mar 26 01:10:08 PM PDT 24
Finished Mar 26 01:10:25 PM PDT 24
Peak memory 259872 kb
Host smart-5a33886c-fbac-4d80-8e49-215dde1128d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834003671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.flash_ctrl_csr_rw.2834003671
Directory /workspace/10.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.92406092
Short name T1118
Test name
Test status
Simulation time 32587600 ps
CPU time 13.63 seconds
Started Mar 26 01:10:11 PM PDT 24
Finished Mar 26 01:10:24 PM PDT 24
Peak memory 262156 kb
Host smart-22b20f6e-2614-49e9-8df9-ad7e9fbaa47d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92406092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.92406092
Directory /workspace/10.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.84168604
Short name T1192
Test name
Test status
Simulation time 179138700 ps
CPU time 34.11 seconds
Started Mar 26 01:10:08 PM PDT 24
Finished Mar 26 01:10:42 PM PDT 24
Peak memory 260176 kb
Host smart-f7de4c29-165e-4493-a962-37d4e8ec0089
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84168604 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.flash_ctrl_same_csr_outstanding.84168604
Directory /workspace/10.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2297368221
Short name T1174
Test name
Test status
Simulation time 14736700 ps
CPU time 15.65 seconds
Started Mar 26 01:10:07 PM PDT 24
Finished Mar 26 01:10:24 PM PDT 24
Peak memory 259988 kb
Host smart-c48831c4-8c72-4219-a489-bf3396b4bcac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297368221 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors.2297368221
Directory /workspace/10.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1557001881
Short name T1145
Test name
Test status
Simulation time 43275200 ps
CPU time 13.07 seconds
Started Mar 26 01:10:08 PM PDT 24
Finished Mar 26 01:10:22 PM PDT 24
Peak memory 260116 kb
Host smart-0893ad5a-72d2-4c2e-9e02-627b40b8436c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557001881 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors_with_csr_rw.1557001881
Directory /workspace/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.2528630342
Short name T1098
Test name
Test status
Simulation time 33408100 ps
CPU time 16.52 seconds
Started Mar 26 01:10:07 PM PDT 24
Finished Mar 26 01:10:23 PM PDT 24
Peak memory 264080 kb
Host smart-56a1e422-b31b-48db-980a-4c55ffd31021
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528630342 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.
2528630342
Directory /workspace/10.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.776663583
Short name T1127
Test name
Test status
Simulation time 24587900 ps
CPU time 17.84 seconds
Started Mar 26 01:10:08 PM PDT 24
Finished Mar 26 01:10:26 PM PDT 24
Peak memory 271940 kb
Host smart-7bff69e4-edcf-400e-ae28-b16ed4b35aeb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776663583 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.776663583
Directory /workspace/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1364364421
Short name T271
Test name
Test status
Simulation time 201703400 ps
CPU time 14.82 seconds
Started Mar 26 01:10:08 PM PDT 24
Finished Mar 26 01:10:24 PM PDT 24
Peak memory 260036 kb
Host smart-0e8421f1-bf62-479f-a847-01a6d771f4d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364364421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.flash_ctrl_csr_rw.1364364421
Directory /workspace/11.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.3167426870
Short name T1142
Test name
Test status
Simulation time 269265300 ps
CPU time 13.48 seconds
Started Mar 26 01:10:09 PM PDT 24
Finished Mar 26 01:10:23 PM PDT 24
Peak memory 262196 kb
Host smart-b1b22742-a51b-470c-a969-a35c14b26a06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167426870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.
3167426870
Directory /workspace/11.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.1832841329
Short name T1146
Test name
Test status
Simulation time 326534200 ps
CPU time 15.87 seconds
Started Mar 26 01:10:08 PM PDT 24
Finished Mar 26 01:10:25 PM PDT 24
Peak memory 260100 kb
Host smart-dd500184-51cf-46ea-962d-1ece916ee9e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832841329 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.flash_ctrl_same_csr_outstanding.1832841329
Directory /workspace/11.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3858438273
Short name T1141
Test name
Test status
Simulation time 35706300 ps
CPU time 15.76 seconds
Started Mar 26 01:10:10 PM PDT 24
Finished Mar 26 01:10:26 PM PDT 24
Peak memory 259876 kb
Host smart-512fc911-ed97-4cb4-845f-8b4bd028df13
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858438273 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors.3858438273
Directory /workspace/11.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.1578744316
Short name T1073
Test name
Test status
Simulation time 55871800 ps
CPU time 15.59 seconds
Started Mar 26 01:10:07 PM PDT 24
Finished Mar 26 01:10:24 PM PDT 24
Peak memory 260024 kb
Host smart-5a07be6b-c8b4-4390-9df7-c850cb17e44e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578744316 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors_with_csr_rw.1578744316
Directory /workspace/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.2898226170
Short name T1188
Test name
Test status
Simulation time 27294700 ps
CPU time 15.66 seconds
Started Mar 26 01:10:07 PM PDT 24
Finished Mar 26 01:10:24 PM PDT 24
Peak memory 263752 kb
Host smart-3763dd70-a74d-4e57-b721-873367ae2243
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898226170 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.
2898226170
Directory /workspace/11.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.3848416637
Short name T369
Test name
Test status
Simulation time 7059395500 ps
CPU time 382.14 seconds
Started Mar 26 01:10:08 PM PDT 24
Finished Mar 26 01:16:30 PM PDT 24
Peak memory 263820 kb
Host smart-96a34da2-1216-44e1-b80b-084fd5df652a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848416637 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctr
l_tl_intg_err.3848416637
Directory /workspace/11.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2210034787
Short name T270
Test name
Test status
Simulation time 19147800 ps
CPU time 16.19 seconds
Started Mar 26 01:10:08 PM PDT 24
Finished Mar 26 01:10:24 PM PDT 24
Peak memory 260024 kb
Host smart-efd8580b-edb5-40f8-9903-27b4fef6059b
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210034787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.flash_ctrl_csr_rw.2210034787
Directory /workspace/12.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.2320891053
Short name T1128
Test name
Test status
Simulation time 16394900 ps
CPU time 13.34 seconds
Started Mar 26 01:10:09 PM PDT 24
Finished Mar 26 01:10:23 PM PDT 24
Peak memory 262540 kb
Host smart-0b58203a-8e39-41f0-afb9-4c4885ab8bb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320891053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.
2320891053
Directory /workspace/12.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.543798252
Short name T1116
Test name
Test status
Simulation time 435855100 ps
CPU time 18.71 seconds
Started Mar 26 01:10:08 PM PDT 24
Finished Mar 26 01:10:28 PM PDT 24
Peak memory 260040 kb
Host smart-df21b9ef-185f-4dce-9a83-71c87dbf1771
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543798252 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.flash_ctrl_same_csr_outstanding.543798252
Directory /workspace/12.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.1244048058
Short name T1133
Test name
Test status
Simulation time 38556100 ps
CPU time 15.39 seconds
Started Mar 26 01:10:10 PM PDT 24
Finished Mar 26 01:10:26 PM PDT 24
Peak memory 260016 kb
Host smart-3e5021e2-30e7-4d6a-9ea2-71ed7c0d2615
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244048058 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors.1244048058
Directory /workspace/12.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2024829569
Short name T1055
Test name
Test status
Simulation time 12192700 ps
CPU time 15.54 seconds
Started Mar 26 01:10:08 PM PDT 24
Finished Mar 26 01:10:24 PM PDT 24
Peak memory 260000 kb
Host smart-f5940da7-ade4-4fd8-86b8-25f6d97bcd74
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024829569 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors_with_csr_rw.2024829569
Directory /workspace/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.4235458850
Short name T276
Test name
Test status
Simulation time 189894100 ps
CPU time 18.95 seconds
Started Mar 26 01:10:09 PM PDT 24
Finished Mar 26 01:10:28 PM PDT 24
Peak memory 263804 kb
Host smart-3f348797-4b66-4fe1-bdbd-a9866496051c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235458850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.
4235458850
Directory /workspace/12.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3941294927
Short name T1109
Test name
Test status
Simulation time 305582200 ps
CPU time 19.36 seconds
Started Mar 26 01:10:21 PM PDT 24
Finished Mar 26 01:10:41 PM PDT 24
Peak memory 271856 kb
Host smart-9805523b-bc8e-438e-b585-49f592f2300a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941294927 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.3941294927
Directory /workspace/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.761739936
Short name T1172
Test name
Test status
Simulation time 57459500 ps
CPU time 17.45 seconds
Started Mar 26 01:10:26 PM PDT 24
Finished Mar 26 01:10:43 PM PDT 24
Peak memory 259992 kb
Host smart-3b9e5626-a2ed-4bec-9947-a67588a23ee6
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761739936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.flash_ctrl_csr_rw.761739936
Directory /workspace/13.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.3323216460
Short name T1095
Test name
Test status
Simulation time 16800100 ps
CPU time 13.6 seconds
Started Mar 26 01:10:22 PM PDT 24
Finished Mar 26 01:10:36 PM PDT 24
Peak memory 262532 kb
Host smart-da6db29f-e0e1-4d00-a174-d16a92686202
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323216460 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.
3323216460
Directory /workspace/13.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1668092357
Short name T1171
Test name
Test status
Simulation time 170400500 ps
CPU time 20.35 seconds
Started Mar 26 01:10:22 PM PDT 24
Finished Mar 26 01:10:43 PM PDT 24
Peak memory 260104 kb
Host smart-2058d4f5-78d8-4a98-98dd-7999d2ddca82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668092357 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.flash_ctrl_same_csr_outstanding.1668092357
Directory /workspace/13.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.4088002038
Short name T1062
Test name
Test status
Simulation time 24777100 ps
CPU time 13.1 seconds
Started Mar 26 01:10:07 PM PDT 24
Finished Mar 26 01:10:21 PM PDT 24
Peak memory 259880 kb
Host smart-6d55f5d8-0ec7-4132-801f-64a5e7d16d76
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088002038 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors.4088002038
Directory /workspace/13.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1488353815
Short name T1097
Test name
Test status
Simulation time 20131900 ps
CPU time 15.79 seconds
Started Mar 26 01:10:24 PM PDT 24
Finished Mar 26 01:10:40 PM PDT 24
Peak memory 260028 kb
Host smart-3bae8d0c-39c2-4346-95f0-abadb318d68b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488353815 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors_with_csr_rw.1488353815
Directory /workspace/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.3260024478
Short name T286
Test name
Test status
Simulation time 57724900 ps
CPU time 18.77 seconds
Started Mar 26 01:10:09 PM PDT 24
Finished Mar 26 01:10:28 PM PDT 24
Peak memory 263804 kb
Host smart-6fd9b576-2cf2-4c04-bf71-b9a8059a6908
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260024478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.
3260024478
Directory /workspace/13.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.93619964
Short name T1168
Test name
Test status
Simulation time 209959300 ps
CPU time 17.16 seconds
Started Mar 26 01:10:26 PM PDT 24
Finished Mar 26 01:10:43 PM PDT 24
Peak memory 272024 kb
Host smart-f97fc5b8-4c36-4f0f-b688-79eee3d44be9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93619964 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.93619964
Directory /workspace/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3220612415
Short name T1119
Test name
Test status
Simulation time 70297600 ps
CPU time 13.92 seconds
Started Mar 26 01:10:21 PM PDT 24
Finished Mar 26 01:10:35 PM PDT 24
Peak memory 259924 kb
Host smart-f4bfad8c-8613-4667-8f62-e741c235d4e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220612415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.flash_ctrl_csr_rw.3220612415
Directory /workspace/14.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.3668543278
Short name T1186
Test name
Test status
Simulation time 43960500 ps
CPU time 13.41 seconds
Started Mar 26 01:10:25 PM PDT 24
Finished Mar 26 01:10:38 PM PDT 24
Peak memory 260748 kb
Host smart-439696f8-0de5-41ea-b36c-58b27a5128da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668543278 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.
3668543278
Directory /workspace/14.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2356707304
Short name T45
Test name
Test status
Simulation time 119545800 ps
CPU time 19.66 seconds
Started Mar 26 01:10:21 PM PDT 24
Finished Mar 26 01:10:41 PM PDT 24
Peak memory 261760 kb
Host smart-dc70cb1a-58a5-424e-95ba-853f7d1abade
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356707304 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.flash_ctrl_same_csr_outstanding.2356707304
Directory /workspace/14.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.798757429
Short name T1138
Test name
Test status
Simulation time 79933600 ps
CPU time 15.36 seconds
Started Mar 26 01:10:26 PM PDT 24
Finished Mar 26 01:10:42 PM PDT 24
Peak memory 260064 kb
Host smart-f852f3e1-44b3-4ab6-a3e2-df16db3dd1d8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798757429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.flash_ctrl_shadow_reg_errors.798757429
Directory /workspace/14.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.745962142
Short name T1177
Test name
Test status
Simulation time 95461400 ps
CPU time 15.53 seconds
Started Mar 26 01:10:25 PM PDT 24
Finished Mar 26 01:10:40 PM PDT 24
Peak memory 260080 kb
Host smart-84dca3e5-8c09-4678-b29c-b28f8b5bc69e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745962142 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors_with_csr_rw.745962142
Directory /workspace/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.3391116917
Short name T250
Test name
Test status
Simulation time 114582000 ps
CPU time 16.09 seconds
Started Mar 26 01:10:26 PM PDT 24
Finished Mar 26 01:10:42 PM PDT 24
Peak memory 263836 kb
Host smart-d70829c8-17dd-43df-8742-3c7c3302f645
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391116917 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.
3391116917
Directory /workspace/14.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.3062479037
Short name T362
Test name
Test status
Simulation time 684592700 ps
CPU time 383.78 seconds
Started Mar 26 01:10:24 PM PDT 24
Finished Mar 26 01:16:48 PM PDT 24
Peak memory 263720 kb
Host smart-42d284ae-2de8-4704-b3fb-8411ff166620
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062479037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctr
l_tl_intg_err.3062479037
Directory /workspace/14.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.2167651456
Short name T317
Test name
Test status
Simulation time 62833300 ps
CPU time 15.1 seconds
Started Mar 26 01:10:25 PM PDT 24
Finished Mar 26 01:10:40 PM PDT 24
Peak memory 263784 kb
Host smart-430b3f4d-abf5-419d-943a-59c80db8c6e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167651456 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.2167651456
Directory /workspace/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.1583021069
Short name T1091
Test name
Test status
Simulation time 23097500 ps
CPU time 16.4 seconds
Started Mar 26 01:10:26 PM PDT 24
Finished Mar 26 01:10:43 PM PDT 24
Peak memory 259872 kb
Host smart-8f4428c4-4d31-4522-8c06-43a01c64a01f
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583021069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.flash_ctrl_csr_rw.1583021069
Directory /workspace/15.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.3875776870
Short name T1113
Test name
Test status
Simulation time 22982700 ps
CPU time 13.39 seconds
Started Mar 26 01:10:25 PM PDT 24
Finished Mar 26 01:10:38 PM PDT 24
Peak memory 262468 kb
Host smart-ab67db1e-637f-435b-b107-a4f07c27469c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875776870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.
3875776870
Directory /workspace/15.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.790556850
Short name T1155
Test name
Test status
Simulation time 96453400 ps
CPU time 34.31 seconds
Started Mar 26 01:10:25 PM PDT 24
Finished Mar 26 01:10:59 PM PDT 24
Peak memory 260052 kb
Host smart-77b94647-7f39-43a6-ae56-1fef70469c87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790556850 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.flash_ctrl_same_csr_outstanding.790556850
Directory /workspace/15.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2841893748
Short name T1106
Test name
Test status
Simulation time 11197400 ps
CPU time 15.62 seconds
Started Mar 26 01:10:24 PM PDT 24
Finished Mar 26 01:10:40 PM PDT 24
Peak memory 259976 kb
Host smart-7057c50d-f113-49b6-a4c0-5ba206cd7983
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841893748 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors.2841893748
Directory /workspace/15.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3201122888
Short name T1061
Test name
Test status
Simulation time 18689700 ps
CPU time 13.37 seconds
Started Mar 26 01:10:25 PM PDT 24
Finished Mar 26 01:10:38 PM PDT 24
Peak memory 259952 kb
Host smart-1e4eedcb-6dd2-430f-a63b-25e87a05c87e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201122888 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors_with_csr_rw.3201122888
Directory /workspace/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.2561920976
Short name T277
Test name
Test status
Simulation time 282193200 ps
CPU time 18.65 seconds
Started Mar 26 01:10:25 PM PDT 24
Finished Mar 26 01:10:44 PM PDT 24
Peak memory 263884 kb
Host smart-797d1de3-e335-49ce-910c-2b5c3e0cc468
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561920976 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.
2561920976
Directory /workspace/15.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1001564702
Short name T365
Test name
Test status
Simulation time 699420700 ps
CPU time 450.47 seconds
Started Mar 26 01:10:24 PM PDT 24
Finished Mar 26 01:17:55 PM PDT 24
Peak memory 262256 kb
Host smart-35adc0a5-a50d-4b0a-a814-16ab5d5f2d2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001564702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctr
l_tl_intg_err.1001564702
Directory /workspace/15.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.4071236003
Short name T1196
Test name
Test status
Simulation time 155836300 ps
CPU time 16.58 seconds
Started Mar 26 01:10:22 PM PDT 24
Finished Mar 26 01:10:39 PM PDT 24
Peak memory 276716 kb
Host smart-ad86cc0e-f928-4d67-926c-a5dcec6bead0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071236003 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.4071236003
Directory /workspace/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.3525976820
Short name T1089
Test name
Test status
Simulation time 35794600 ps
CPU time 14.35 seconds
Started Mar 26 01:10:24 PM PDT 24
Finished Mar 26 01:10:39 PM PDT 24
Peak memory 259924 kb
Host smart-4f98f792-3ab4-4fbf-baea-1b6aff726a4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525976820 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.flash_ctrl_csr_rw.3525976820
Directory /workspace/16.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.1092187798
Short name T1135
Test name
Test status
Simulation time 59100900 ps
CPU time 13.45 seconds
Started Mar 26 01:10:25 PM PDT 24
Finished Mar 26 01:10:39 PM PDT 24
Peak memory 262648 kb
Host smart-c0987d76-8096-45f9-a68d-ced5c3b7798e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092187798 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test.
1092187798
Directory /workspace/16.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3383765866
Short name T1194
Test name
Test status
Simulation time 71350800 ps
CPU time 33.52 seconds
Started Mar 26 01:10:24 PM PDT 24
Finished Mar 26 01:10:58 PM PDT 24
Peak memory 260180 kb
Host smart-53383741-bfa0-4547-bea6-15eb90a1a1de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383765866 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.flash_ctrl_same_csr_outstanding.3383765866
Directory /workspace/16.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.4076794621
Short name T1054
Test name
Test status
Simulation time 11587100 ps
CPU time 13.23 seconds
Started Mar 26 01:10:25 PM PDT 24
Finished Mar 26 01:10:38 PM PDT 24
Peak memory 260116 kb
Host smart-bcea3a13-7a6c-4d09-809c-567a8bd943ab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076794621 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors.4076794621
Directory /workspace/16.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.623970604
Short name T1110
Test name
Test status
Simulation time 15258500 ps
CPU time 15.53 seconds
Started Mar 26 01:10:24 PM PDT 24
Finished Mar 26 01:10:40 PM PDT 24
Peak memory 259904 kb
Host smart-ac80327b-5469-4e77-8135-6e94c24ac973
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623970604 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors_with_csr_rw.623970604
Directory /workspace/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.993642623
Short name T283
Test name
Test status
Simulation time 96642400 ps
CPU time 19.16 seconds
Started Mar 26 01:10:25 PM PDT 24
Finished Mar 26 01:10:45 PM PDT 24
Peak memory 263796 kb
Host smart-bea4e7f1-98a5-49d7-926b-a33a27b87790
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993642623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.993642623
Directory /workspace/16.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1099395874
Short name T1159
Test name
Test status
Simulation time 97770900 ps
CPU time 17.1 seconds
Started Mar 26 01:10:23 PM PDT 24
Finished Mar 26 01:10:41 PM PDT 24
Peak memory 271864 kb
Host smart-dabd4c4f-be9c-4179-a452-8735aaa410d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099395874 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.1099395874
Directory /workspace/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.4132650081
Short name T1079
Test name
Test status
Simulation time 62269500 ps
CPU time 16.65 seconds
Started Mar 26 01:10:26 PM PDT 24
Finished Mar 26 01:10:43 PM PDT 24
Peak memory 260076 kb
Host smart-43b9ee8e-7c90-4be0-bc89-cb3c8f9f3e6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132650081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.flash_ctrl_csr_rw.4132650081
Directory /workspace/17.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.2934082878
Short name T1067
Test name
Test status
Simulation time 23982800 ps
CPU time 13.27 seconds
Started Mar 26 01:10:25 PM PDT 24
Finished Mar 26 01:10:38 PM PDT 24
Peak memory 262552 kb
Host smart-9425e2ea-b0e7-4aa3-b9af-0dc365b5f3c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934082878 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.
2934082878
Directory /workspace/17.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.3038471368
Short name T268
Test name
Test status
Simulation time 171446300 ps
CPU time 20.26 seconds
Started Mar 26 01:10:23 PM PDT 24
Finished Mar 26 01:10:44 PM PDT 24
Peak memory 260116 kb
Host smart-47c5cb28-70dc-43b5-bb9e-d8c3377431ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038471368 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.flash_ctrl_same_csr_outstanding.3038471368
Directory /workspace/17.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.3911573552
Short name T1053
Test name
Test status
Simulation time 41726800 ps
CPU time 13 seconds
Started Mar 26 01:10:22 PM PDT 24
Finished Mar 26 01:10:36 PM PDT 24
Peak memory 260100 kb
Host smart-06e7fa06-e9a2-4dec-81a0-79c9e648d999
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911573552 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors.3911573552
Directory /workspace/17.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2600210741
Short name T1057
Test name
Test status
Simulation time 17194000 ps
CPU time 15.32 seconds
Started Mar 26 01:10:25 PM PDT 24
Finished Mar 26 01:10:41 PM PDT 24
Peak memory 260108 kb
Host smart-8d846dc4-b4ed-419f-8ff2-1e40b6a4a1f2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600210741 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors_with_csr_rw.2600210741
Directory /workspace/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.719349668
Short name T284
Test name
Test status
Simulation time 118318400 ps
CPU time 20.31 seconds
Started Mar 26 01:10:25 PM PDT 24
Finished Mar 26 01:10:45 PM PDT 24
Peak memory 263740 kb
Host smart-93af274f-b233-4b2b-b4e8-a565fac5df7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719349668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.719349668
Directory /workspace/17.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.357030900
Short name T371
Test name
Test status
Simulation time 192192300 ps
CPU time 450.91 seconds
Started Mar 26 01:10:26 PM PDT 24
Finished Mar 26 01:17:58 PM PDT 24
Peak memory 261804 kb
Host smart-8d6103a7-f741-4aa2-8ee8-a5f9c6e2a570
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357030900 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl
_tl_intg_err.357030900
Directory /workspace/17.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.2376633782
Short name T1099
Test name
Test status
Simulation time 283100300 ps
CPU time 14.98 seconds
Started Mar 26 01:10:33 PM PDT 24
Finished Mar 26 01:10:49 PM PDT 24
Peak memory 276668 kb
Host smart-f3126b50-371b-4061-ae03-95a846f0c143
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376633782 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.2376633782
Directory /workspace/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.1505180629
Short name T1189
Test name
Test status
Simulation time 159446000 ps
CPU time 16.6 seconds
Started Mar 26 01:10:33 PM PDT 24
Finished Mar 26 01:10:50 PM PDT 24
Peak memory 259944 kb
Host smart-66443ac1-66ef-4772-82b3-c0be415ba1b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505180629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.flash_ctrl_csr_rw.1505180629
Directory /workspace/18.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.4094704986
Short name T1104
Test name
Test status
Simulation time 18070500 ps
CPU time 13.31 seconds
Started Mar 26 01:10:37 PM PDT 24
Finished Mar 26 01:10:50 PM PDT 24
Peak memory 261568 kb
Host smart-c0dc2a1d-118e-43b6-9f9e-85d85f102225
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094704986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.
4094704986
Directory /workspace/18.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.2403172468
Short name T266
Test name
Test status
Simulation time 381958300 ps
CPU time 21.36 seconds
Started Mar 26 01:10:33 PM PDT 24
Finished Mar 26 01:10:54 PM PDT 24
Peak memory 263600 kb
Host smart-d898ea3c-d2ba-4a64-9c10-a6cc57342e22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403172468 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.flash_ctrl_same_csr_outstanding.2403172468
Directory /workspace/18.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.2701747185
Short name T1152
Test name
Test status
Simulation time 18723100 ps
CPU time 15.63 seconds
Started Mar 26 01:10:33 PM PDT 24
Finished Mar 26 01:10:49 PM PDT 24
Peak memory 260020 kb
Host smart-89b5dc1f-2daf-4522-9c2d-6280f52e5f6e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701747185 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors.2701747185
Directory /workspace/18.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1421366256
Short name T1060
Test name
Test status
Simulation time 17978400 ps
CPU time 12.96 seconds
Started Mar 26 01:10:38 PM PDT 24
Finished Mar 26 01:10:51 PM PDT 24
Peak memory 259952 kb
Host smart-7f5f7f3b-5e8b-4891-9a14-05514ce92233
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421366256 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors_with_csr_rw.1421366256
Directory /workspace/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.4093785870
Short name T1193
Test name
Test status
Simulation time 96254300 ps
CPU time 18.88 seconds
Started Mar 26 01:10:25 PM PDT 24
Finished Mar 26 01:10:44 PM PDT 24
Peak memory 263860 kb
Host smart-bec0d20e-91d8-4f45-b973-1d491b5f1190
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093785870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.
4093785870
Directory /workspace/18.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2564380991
Short name T1151
Test name
Test status
Simulation time 2010674800 ps
CPU time 914.47 seconds
Started Mar 26 01:10:37 PM PDT 24
Finished Mar 26 01:25:52 PM PDT 24
Peak memory 263668 kb
Host smart-056e5191-571e-4e94-bc5b-9c24dde2aeb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564380991 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctr
l_tl_intg_err.2564380991
Directory /workspace/18.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2536127690
Short name T184
Test name
Test status
Simulation time 94069100 ps
CPU time 16.09 seconds
Started Mar 26 01:10:40 PM PDT 24
Finished Mar 26 01:10:56 PM PDT 24
Peak memory 272004 kb
Host smart-de376422-7ad7-4956-af3b-a6566805ed03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536127690 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.2536127690
Directory /workspace/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.134016757
Short name T1082
Test name
Test status
Simulation time 62428400 ps
CPU time 16.16 seconds
Started Mar 26 01:10:37 PM PDT 24
Finished Mar 26 01:10:53 PM PDT 24
Peak memory 260016 kb
Host smart-85e391b9-cfeb-4c32-ad43-d82fb5779d5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134016757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 19.flash_ctrl_csr_rw.134016757
Directory /workspace/19.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.2165691980
Short name T1072
Test name
Test status
Simulation time 230513300 ps
CPU time 13.49 seconds
Started Mar 26 01:10:34 PM PDT 24
Finished Mar 26 01:10:48 PM PDT 24
Peak memory 262232 kb
Host smart-a014088c-d5f8-4228-945e-3a5921fa175d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165691980 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.
2165691980
Directory /workspace/19.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.1011549478
Short name T1124
Test name
Test status
Simulation time 197882700 ps
CPU time 17.19 seconds
Started Mar 26 01:10:36 PM PDT 24
Finished Mar 26 01:10:53 PM PDT 24
Peak memory 262248 kb
Host smart-d4d94df4-40f9-4b64-bb3a-e6c5e25492c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011549478 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.flash_ctrl_same_csr_outstanding.1011549478
Directory /workspace/19.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.1765760121
Short name T1117
Test name
Test status
Simulation time 37317200 ps
CPU time 15.23 seconds
Started Mar 26 01:10:40 PM PDT 24
Finished Mar 26 01:10:55 PM PDT 24
Peak memory 260052 kb
Host smart-7606ab6a-7312-41f8-8f3b-2c46a9dfa2c1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765760121 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors.1765760121
Directory /workspace/19.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.863838365
Short name T1112
Test name
Test status
Simulation time 32331400 ps
CPU time 15.15 seconds
Started Mar 26 01:10:35 PM PDT 24
Finished Mar 26 01:10:50 PM PDT 24
Peak memory 260292 kb
Host smart-1ae45df2-618d-4b75-b148-d77354ed11f7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863838365 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors_with_csr_rw.863838365
Directory /workspace/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.4028986615
Short name T1139
Test name
Test status
Simulation time 32353400 ps
CPU time 15.68 seconds
Started Mar 26 01:10:40 PM PDT 24
Finished Mar 26 01:10:55 PM PDT 24
Peak memory 263868 kb
Host smart-a4bb3d7f-eaa0-4d27-bc1e-abb58775f1ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028986615 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.
4028986615
Directory /workspace/19.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3772567545
Short name T1148
Test name
Test status
Simulation time 462317700 ps
CPU time 54.81 seconds
Started Mar 26 01:09:23 PM PDT 24
Finished Mar 26 01:10:17 PM PDT 24
Peak memory 259900 kb
Host smart-78aadbf5-fb4f-47f4-8115-2485a0592c64
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772567545 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_aliasing.3772567545
Directory /workspace/2.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.47518817
Short name T1131
Test name
Test status
Simulation time 1194599900 ps
CPU time 47.72 seconds
Started Mar 26 01:09:21 PM PDT 24
Finished Mar 26 01:10:09 PM PDT 24
Peak memory 262588 kb
Host smart-65130acf-9a8a-46eb-be78-f7bfe7a3f219
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47518817 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.flash_ctrl_csr_bit_bash.47518817
Directory /workspace/2.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.586789718
Short name T1190
Test name
Test status
Simulation time 18317400 ps
CPU time 25.41 seconds
Started Mar 26 01:09:19 PM PDT 24
Finished Mar 26 01:09:45 PM PDT 24
Peak memory 259968 kb
Host smart-4db1db84-207a-4ae5-bc01-346fc336e8ba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586789718 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.flash_ctrl_csr_hw_reset.586789718
Directory /workspace/2.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.4252238664
Short name T249
Test name
Test status
Simulation time 389598800 ps
CPU time 19.25 seconds
Started Mar 26 01:09:17 PM PDT 24
Finished Mar 26 01:09:37 PM PDT 24
Peak memory 271844 kb
Host smart-2cb08b35-85d2-46fb-9b2a-ec142d953e15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252238664 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.4252238664
Directory /workspace/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.3118301666
Short name T281
Test name
Test status
Simulation time 19531100 ps
CPU time 13.52 seconds
Started Mar 26 01:09:20 PM PDT 24
Finished Mar 26 01:09:33 PM PDT 24
Peak memory 262616 kb
Host smart-db9f53d6-f084-447e-9e76-41b6ca45141f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118301666 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.3
118301666
Directory /workspace/2.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.3376641670
Short name T255
Test name
Test status
Simulation time 38136900 ps
CPU time 13.35 seconds
Started Mar 26 01:09:23 PM PDT 24
Finished Mar 26 01:09:36 PM PDT 24
Peak memory 263260 kb
Host smart-218f1828-12b8-45c9-9059-7f127f4e5af3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376641670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_mem_partial_access.3376641670
Directory /workspace/2.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3896773337
Short name T1181
Test name
Test status
Simulation time 46387300 ps
CPU time 13.27 seconds
Started Mar 26 01:09:23 PM PDT 24
Finished Mar 26 01:09:36 PM PDT 24
Peak memory 262224 kb
Host smart-05ac6aa3-7a60-4912-aef8-a1a254df9998
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896773337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_me
m_walk.3896773337
Directory /workspace/2.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.4114339320
Short name T316
Test name
Test status
Simulation time 471641800 ps
CPU time 18.25 seconds
Started Mar 26 01:09:24 PM PDT 24
Finished Mar 26 01:09:42 PM PDT 24
Peak memory 261548 kb
Host smart-98abb161-53d6-4e9b-950e-16838c6ebb99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114339320 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.flash_ctrl_same_csr_outstanding.4114339320
Directory /workspace/2.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2768027503
Short name T1083
Test name
Test status
Simulation time 26236600 ps
CPU time 15.58 seconds
Started Mar 26 01:09:18 PM PDT 24
Finished Mar 26 01:09:33 PM PDT 24
Peak memory 260028 kb
Host smart-0236aac6-53fb-438e-af73-3a6134ffe4aa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768027503 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors.2768027503
Directory /workspace/2.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.446916590
Short name T1096
Test name
Test status
Simulation time 26043000 ps
CPU time 15.78 seconds
Started Mar 26 01:09:19 PM PDT 24
Finished Mar 26 01:09:34 PM PDT 24
Peak memory 260104 kb
Host smart-24001be9-7dfa-47cb-9329-12aeea35d1e3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446916590 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors_with_csr_rw.446916590
Directory /workspace/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.785686173
Short name T1134
Test name
Test status
Simulation time 166099400 ps
CPU time 15.93 seconds
Started Mar 26 01:09:04 PM PDT 24
Finished Mar 26 01:09:20 PM PDT 24
Peak memory 263740 kb
Host smart-53028010-84f9-4b7b-89d5-9ce56980e8c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785686173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.785686173
Directory /workspace/2.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.1692519287
Short name T1191
Test name
Test status
Simulation time 20424500 ps
CPU time 13.11 seconds
Started Mar 26 01:10:37 PM PDT 24
Finished Mar 26 01:10:50 PM PDT 24
Peak memory 262540 kb
Host smart-7ae4a418-6680-4bd2-b963-174f214650d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692519287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.
1692519287
Directory /workspace/20.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.2456067732
Short name T1070
Test name
Test status
Simulation time 27857600 ps
CPU time 13.04 seconds
Started Mar 26 01:10:34 PM PDT 24
Finished Mar 26 01:10:47 PM PDT 24
Peak memory 260588 kb
Host smart-74461786-b7db-49d3-8510-7f6500ff2519
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456067732 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.
2456067732
Directory /workspace/21.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.3921551648
Short name T341
Test name
Test status
Simulation time 54520600 ps
CPU time 13.43 seconds
Started Mar 26 01:10:33 PM PDT 24
Finished Mar 26 01:10:47 PM PDT 24
Peak memory 262424 kb
Host smart-16d76d03-6a0f-44fb-8959-16f87499778d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921551648 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.
3921551648
Directory /workspace/22.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.2593921577
Short name T1087
Test name
Test status
Simulation time 38018000 ps
CPU time 13.22 seconds
Started Mar 26 01:10:38 PM PDT 24
Finished Mar 26 01:10:51 PM PDT 24
Peak memory 262512 kb
Host smart-e72f28f7-288e-4171-82fd-7cc8aa6dc3c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593921577 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.
2593921577
Directory /workspace/23.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.169171985
Short name T1140
Test name
Test status
Simulation time 161157400 ps
CPU time 13.49 seconds
Started Mar 26 01:10:37 PM PDT 24
Finished Mar 26 01:10:51 PM PDT 24
Peak memory 262264 kb
Host smart-eb98788b-1eef-4fe1-bca5-871fdfd47612
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169171985 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.169171985
Directory /workspace/24.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1908017440
Short name T1163
Test name
Test status
Simulation time 17397700 ps
CPU time 13.73 seconds
Started Mar 26 01:10:35 PM PDT 24
Finished Mar 26 01:10:49 PM PDT 24
Peak memory 262148 kb
Host smart-0243bbda-f437-44d4-aa57-8687bc0fbbf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908017440 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.
1908017440
Directory /workspace/25.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2852244656
Short name T1132
Test name
Test status
Simulation time 30455300 ps
CPU time 13.34 seconds
Started Mar 26 01:10:35 PM PDT 24
Finished Mar 26 01:10:48 PM PDT 24
Peak memory 262232 kb
Host smart-6638a642-8a4a-44e3-a146-cf566d241fe2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852244656 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.
2852244656
Directory /workspace/26.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3439473682
Short name T1069
Test name
Test status
Simulation time 27703800 ps
CPU time 13.67 seconds
Started Mar 26 01:10:34 PM PDT 24
Finished Mar 26 01:10:47 PM PDT 24
Peak memory 262576 kb
Host smart-72c72dd7-d2d4-4c98-b0ad-615eb2cd7841
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439473682 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.
3439473682
Directory /workspace/27.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.3462290808
Short name T1182
Test name
Test status
Simulation time 219699000 ps
CPU time 13.62 seconds
Started Mar 26 01:10:34 PM PDT 24
Finished Mar 26 01:10:48 PM PDT 24
Peak memory 260656 kb
Host smart-c9506ec6-a8b8-4ff0-b361-24caedbc2621
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462290808 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.
3462290808
Directory /workspace/28.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.1915449389
Short name T1105
Test name
Test status
Simulation time 31929200 ps
CPU time 13.63 seconds
Started Mar 26 01:10:52 PM PDT 24
Finished Mar 26 01:11:05 PM PDT 24
Peak memory 262228 kb
Host smart-590524e4-e4f4-4087-9805-76e858484c16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915449389 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.
1915449389
Directory /workspace/29.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.1715401203
Short name T1179
Test name
Test status
Simulation time 7201068900 ps
CPU time 69.75 seconds
Started Mar 26 01:09:20 PM PDT 24
Finished Mar 26 01:10:30 PM PDT 24
Peak memory 260060 kb
Host smart-35a1e0a0-4daf-427c-b0ad-a4c471c562bc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715401203 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_aliasing.1715401203
Directory /workspace/3.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.4292326379
Short name T1068
Test name
Test status
Simulation time 670251500 ps
CPU time 57.79 seconds
Started Mar 26 01:09:19 PM PDT 24
Finished Mar 26 01:10:17 PM PDT 24
Peak memory 261964 kb
Host smart-59afd864-0150-42f4-8492-0b5f28dbd953
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292326379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_bit_bash.4292326379
Directory /workspace/3.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.4270254737
Short name T1077
Test name
Test status
Simulation time 18639100 ps
CPU time 29.76 seconds
Started Mar 26 01:09:19 PM PDT 24
Finished Mar 26 01:09:49 PM PDT 24
Peak memory 260004 kb
Host smart-7a4df5db-dae8-4dca-9afb-24d5685e4220
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270254737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_hw_reset.4270254737
Directory /workspace/3.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1592338248
Short name T315
Test name
Test status
Simulation time 705195100 ps
CPU time 17.88 seconds
Started Mar 26 01:09:20 PM PDT 24
Finished Mar 26 01:09:38 PM PDT 24
Peak memory 271248 kb
Host smart-874651cc-7f42-4a7e-924a-1335f7c61a71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592338248 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.1592338248
Directory /workspace/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.330684149
Short name T1144
Test name
Test status
Simulation time 68423900 ps
CPU time 15.96 seconds
Started Mar 26 01:09:16 PM PDT 24
Finished Mar 26 01:09:33 PM PDT 24
Peak memory 263688 kb
Host smart-f3482ff3-b079-4938-b1a3-cd7fc8711f19
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330684149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 3.flash_ctrl_csr_rw.330684149
Directory /workspace/3.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.2618556283
Short name T340
Test name
Test status
Simulation time 115106300 ps
CPU time 13.48 seconds
Started Mar 26 01:09:19 PM PDT 24
Finished Mar 26 01:09:33 PM PDT 24
Peak memory 262540 kb
Host smart-0c2851c9-2683-4c27-9b24-94ddf366103b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618556283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.2
618556283
Directory /workspace/3.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1510601226
Short name T253
Test name
Test status
Simulation time 49885400 ps
CPU time 13.58 seconds
Started Mar 26 01:09:19 PM PDT 24
Finished Mar 26 01:09:32 PM PDT 24
Peak memory 263612 kb
Host smart-bd25b652-3475-4ce5-88c7-e9a758f5044a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510601226 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_mem_partial_access.1510601226
Directory /workspace/3.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.123317138
Short name T1136
Test name
Test status
Simulation time 14632800 ps
CPU time 13.23 seconds
Started Mar 26 01:09:24 PM PDT 24
Finished Mar 26 01:09:37 PM PDT 24
Peak memory 262328 kb
Host smart-fe02bb89-0e12-4ec3-b2d0-57ff015f6acf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123317138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mem
_walk.123317138
Directory /workspace/3.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.2346324128
Short name T1111
Test name
Test status
Simulation time 589169800 ps
CPU time 34.49 seconds
Started Mar 26 01:09:19 PM PDT 24
Finished Mar 26 01:09:53 PM PDT 24
Peak memory 263604 kb
Host smart-9d4529cf-463b-4084-88a0-6ae33c84207b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346324128 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.flash_ctrl_same_csr_outstanding.2346324128
Directory /workspace/3.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.3721646291
Short name T1158
Test name
Test status
Simulation time 13165700 ps
CPU time 15.34 seconds
Started Mar 26 01:09:18 PM PDT 24
Finished Mar 26 01:09:33 PM PDT 24
Peak memory 260068 kb
Host smart-d1472228-9445-4c2c-a329-9054970d80f3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721646291 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors.3721646291
Directory /workspace/3.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.3698771776
Short name T1059
Test name
Test status
Simulation time 173155300 ps
CPU time 13.25 seconds
Started Mar 26 01:09:17 PM PDT 24
Finished Mar 26 01:09:30 PM PDT 24
Peak memory 260044 kb
Host smart-e4526b8c-ce2d-480d-b46c-0185015bdfab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698771776 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors_with_csr_rw.3698771776
Directory /workspace/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.2401712220
Short name T1154
Test name
Test status
Simulation time 17377400 ps
CPU time 13.25 seconds
Started Mar 26 01:10:52 PM PDT 24
Finished Mar 26 01:11:06 PM PDT 24
Peak memory 262132 kb
Host smart-36821181-4e12-46b4-b10f-1fd711fdcfef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401712220 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.
2401712220
Directory /workspace/30.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.3266380468
Short name T1147
Test name
Test status
Simulation time 42185400 ps
CPU time 13.58 seconds
Started Mar 26 01:10:53 PM PDT 24
Finished Mar 26 01:11:06 PM PDT 24
Peak memory 262304 kb
Host smart-a819c23a-1d10-420c-bc1d-598307aaaa01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266380468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.
3266380468
Directory /workspace/31.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.3060332856
Short name T1166
Test name
Test status
Simulation time 28605700 ps
CPU time 13.32 seconds
Started Mar 26 01:10:52 PM PDT 24
Finished Mar 26 01:11:05 PM PDT 24
Peak memory 262260 kb
Host smart-d5aee86f-3cbc-4824-9d04-c01ca9e77d2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060332856 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.
3060332856
Directory /workspace/32.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1614685216
Short name T280
Test name
Test status
Simulation time 18189600 ps
CPU time 13.74 seconds
Started Mar 26 01:10:53 PM PDT 24
Finished Mar 26 01:11:06 PM PDT 24
Peak memory 262344 kb
Host smart-0123eee6-01e7-4e54-be8d-a1b08ac118f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614685216 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.
1614685216
Directory /workspace/33.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.1522496579
Short name T1137
Test name
Test status
Simulation time 17764500 ps
CPU time 13.51 seconds
Started Mar 26 01:10:51 PM PDT 24
Finished Mar 26 01:11:05 PM PDT 24
Peak memory 260672 kb
Host smart-a74cf093-b9c8-4cf2-9663-d86527ed6bd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522496579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.
1522496579
Directory /workspace/34.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1637660478
Short name T1075
Test name
Test status
Simulation time 15556500 ps
CPU time 13.39 seconds
Started Mar 26 01:10:53 PM PDT 24
Finished Mar 26 01:11:07 PM PDT 24
Peak memory 262196 kb
Host smart-e6ab9d6d-5194-4aa3-8a28-949d67bbfe73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637660478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.
1637660478
Directory /workspace/36.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.3646152278
Short name T1102
Test name
Test status
Simulation time 16133200 ps
CPU time 13.38 seconds
Started Mar 26 01:10:51 PM PDT 24
Finished Mar 26 01:11:05 PM PDT 24
Peak memory 260748 kb
Host smart-9f0fec4f-a31f-470b-b60f-c169311ff035
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646152278 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test.
3646152278
Directory /workspace/37.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.2010097044
Short name T1123
Test name
Test status
Simulation time 31251300 ps
CPU time 13.52 seconds
Started Mar 26 01:10:52 PM PDT 24
Finished Mar 26 01:11:05 PM PDT 24
Peak memory 262128 kb
Host smart-f91a1dc4-59fe-4ba2-8ebd-9be98988bce6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010097044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.
2010097044
Directory /workspace/38.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.862777700
Short name T1130
Test name
Test status
Simulation time 42921100 ps
CPU time 13.13 seconds
Started Mar 26 01:10:55 PM PDT 24
Finished Mar 26 01:11:08 PM PDT 24
Peak memory 262592 kb
Host smart-18087fda-e299-4a28-8969-c025edb624df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862777700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.862777700
Directory /workspace/39.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.230784956
Short name T1115
Test name
Test status
Simulation time 2560829900 ps
CPU time 60.16 seconds
Started Mar 26 01:09:30 PM PDT 24
Finished Mar 26 01:10:30 PM PDT 24
Peak memory 260080 kb
Host smart-c34f2e63-8193-4959-b4b9-4b5a3d189994
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230784956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.flash_ctrl_csr_aliasing.230784956
Directory /workspace/4.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3945744847
Short name T1149
Test name
Test status
Simulation time 1650364400 ps
CPU time 53.3 seconds
Started Mar 26 01:09:30 PM PDT 24
Finished Mar 26 01:10:24 PM PDT 24
Peak memory 259936 kb
Host smart-c1a7d43a-a956-4945-9e81-a28d3827cbfa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945744847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_bit_bash.3945744847
Directory /workspace/4.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.3287226035
Short name T1170
Test name
Test status
Simulation time 65085700 ps
CPU time 25.53 seconds
Started Mar 26 01:09:29 PM PDT 24
Finished Mar 26 01:09:55 PM PDT 24
Peak memory 260040 kb
Host smart-f8cf27c0-03e2-4436-b808-efa4a9b2166e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287226035 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_hw_reset.3287226035
Directory /workspace/4.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.3949057905
Short name T1081
Test name
Test status
Simulation time 51597200 ps
CPU time 17.72 seconds
Started Mar 26 01:09:36 PM PDT 24
Finished Mar 26 01:09:54 PM PDT 24
Peak memory 263640 kb
Host smart-28103718-4014-4377-bf1e-2f92f51c0173
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949057905 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.3949057905
Directory /workspace/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.4010467719
Short name T1161
Test name
Test status
Simulation time 92511900 ps
CPU time 14.34 seconds
Started Mar 26 01:09:28 PM PDT 24
Finished Mar 26 01:09:43 PM PDT 24
Peak memory 263748 kb
Host smart-1283910c-70ad-49c9-a765-46b14f00e7a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010467719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.flash_ctrl_csr_rw.4010467719
Directory /workspace/4.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.1025597858
Short name T1114
Test name
Test status
Simulation time 16520000 ps
CPU time 13.54 seconds
Started Mar 26 01:09:17 PM PDT 24
Finished Mar 26 01:09:31 PM PDT 24
Peak memory 262432 kb
Host smart-4c7c9a72-0dd9-4644-9efc-5d7806ee9cf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025597858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.1
025597858
Directory /workspace/4.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.4141106322
Short name T1165
Test name
Test status
Simulation time 14478200 ps
CPU time 13.32 seconds
Started Mar 26 01:09:17 PM PDT 24
Finished Mar 26 01:09:30 PM PDT 24
Peak memory 261964 kb
Host smart-c3dad4fc-b997-4a9a-96e6-2bfb3673c421
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141106322 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_me
m_walk.4141106322
Directory /workspace/4.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.2578841895
Short name T1076
Test name
Test status
Simulation time 254715900 ps
CPU time 19.07 seconds
Started Mar 26 01:09:36 PM PDT 24
Finished Mar 26 01:09:56 PM PDT 24
Peak memory 260060 kb
Host smart-dbcff0f5-e021-4e3b-b03d-191eb483e2e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578841895 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.flash_ctrl_same_csr_outstanding.2578841895
Directory /workspace/4.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.3888363846
Short name T1100
Test name
Test status
Simulation time 33869300 ps
CPU time 13.11 seconds
Started Mar 26 01:09:18 PM PDT 24
Finished Mar 26 01:09:31 PM PDT 24
Peak memory 259968 kb
Host smart-4689b9f3-99a3-4e91-b270-20c6f9079c6a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888363846 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors.3888363846
Directory /workspace/4.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.2638645998
Short name T1101
Test name
Test status
Simulation time 44350800 ps
CPU time 15.34 seconds
Started Mar 26 01:09:22 PM PDT 24
Finished Mar 26 01:09:38 PM PDT 24
Peak memory 259948 kb
Host smart-edc03e2c-3a44-4ad6-8ae1-96372f95cd7a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638645998 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors_with_csr_rw.2638645998
Directory /workspace/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.1392703794
Short name T360
Test name
Test status
Simulation time 67480400 ps
CPU time 16.38 seconds
Started Mar 26 01:09:17 PM PDT 24
Finished Mar 26 01:09:34 PM PDT 24
Peak memory 263920 kb
Host smart-602ec963-6623-459e-87cb-7ce11709a945
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392703794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.1
392703794
Directory /workspace/4.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.972994480
Short name T366
Test name
Test status
Simulation time 4330144500 ps
CPU time 894.39 seconds
Started Mar 26 01:09:18 PM PDT 24
Finished Mar 26 01:24:13 PM PDT 24
Peak memory 262380 kb
Host smart-3a29553a-1984-4449-a5fd-e557e6dbf777
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972994480 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_
tl_intg_err.972994480
Directory /workspace/4.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.384105479
Short name T1184
Test name
Test status
Simulation time 16333000 ps
CPU time 13.56 seconds
Started Mar 26 01:10:53 PM PDT 24
Finished Mar 26 01:11:06 PM PDT 24
Peak memory 262632 kb
Host smart-805923c7-1c36-4af5-8713-c33a00f7bd02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384105479 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.384105479
Directory /workspace/40.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.458241187
Short name T1078
Test name
Test status
Simulation time 26236200 ps
CPU time 13.54 seconds
Started Mar 26 01:10:53 PM PDT 24
Finished Mar 26 01:11:07 PM PDT 24
Peak memory 262416 kb
Host smart-25a66712-e5dd-4373-a448-d1633e5a7906
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458241187 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.458241187
Directory /workspace/41.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.3532021688
Short name T1150
Test name
Test status
Simulation time 28978000 ps
CPU time 13.36 seconds
Started Mar 26 01:10:52 PM PDT 24
Finished Mar 26 01:11:06 PM PDT 24
Peak memory 262660 kb
Host smart-da250710-0b0a-4ab4-a838-ee845813abfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532021688 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.
3532021688
Directory /workspace/42.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.2550340470
Short name T1164
Test name
Test status
Simulation time 16285600 ps
CPU time 13.66 seconds
Started Mar 26 01:10:54 PM PDT 24
Finished Mar 26 01:11:07 PM PDT 24
Peak memory 262372 kb
Host smart-3362f6db-902b-46b2-b21b-4a1567abaec6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550340470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.
2550340470
Directory /workspace/43.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.4054378684
Short name T1080
Test name
Test status
Simulation time 16924200 ps
CPU time 13.5 seconds
Started Mar 26 01:10:55 PM PDT 24
Finished Mar 26 01:11:09 PM PDT 24
Peak memory 262608 kb
Host smart-04e8b98e-7e51-4932-a9aa-4ca836d20b80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054378684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.
4054378684
Directory /workspace/44.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.2914787165
Short name T343
Test name
Test status
Simulation time 33956200 ps
CPU time 13.26 seconds
Started Mar 26 01:10:52 PM PDT 24
Finished Mar 26 01:11:06 PM PDT 24
Peak memory 262288 kb
Host smart-80595a44-4734-4906-b635-9bad2921aabc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914787165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.
2914787165
Directory /workspace/45.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.1635954860
Short name T1125
Test name
Test status
Simulation time 32905200 ps
CPU time 13.5 seconds
Started Mar 26 01:10:52 PM PDT 24
Finished Mar 26 01:11:06 PM PDT 24
Peak memory 260652 kb
Host smart-a47c4fbd-7207-4d3c-950e-80308519fc99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635954860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.
1635954860
Directory /workspace/46.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.3008978528
Short name T279
Test name
Test status
Simulation time 220246700 ps
CPU time 13.45 seconds
Started Mar 26 01:10:55 PM PDT 24
Finished Mar 26 01:11:09 PM PDT 24
Peak memory 260736 kb
Host smart-4f96e72b-1898-4203-b96d-1571ef4de149
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008978528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.
3008978528
Directory /workspace/47.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.3807143326
Short name T1121
Test name
Test status
Simulation time 54146400 ps
CPU time 13.53 seconds
Started Mar 26 01:10:55 PM PDT 24
Finished Mar 26 01:11:09 PM PDT 24
Peak memory 262472 kb
Host smart-3d545450-f60f-4148-827b-b8aa9d2e4525
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807143326 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.
3807143326
Directory /workspace/48.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.148229889
Short name T1120
Test name
Test status
Simulation time 31668100 ps
CPU time 13.41 seconds
Started Mar 26 01:10:53 PM PDT 24
Finished Mar 26 01:11:06 PM PDT 24
Peak memory 262512 kb
Host smart-699d8ca2-f35e-4693-8c23-1c127ef58a63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148229889 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.148229889
Directory /workspace/49.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.1218258764
Short name T314
Test name
Test status
Simulation time 60688400 ps
CPU time 17.25 seconds
Started Mar 26 01:09:30 PM PDT 24
Finished Mar 26 01:09:48 PM PDT 24
Peak memory 269992 kb
Host smart-07da3111-77cf-40fb-b008-d241bc94a46b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218258764 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.1218258764
Directory /workspace/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.794693007
Short name T1092
Test name
Test status
Simulation time 216654200 ps
CPU time 17.79 seconds
Started Mar 26 01:09:30 PM PDT 24
Finished Mar 26 01:09:48 PM PDT 24
Peak memory 263556 kb
Host smart-96065c10-36c4-42a6-aaf3-48c081b02772
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794693007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.flash_ctrl_csr_rw.794693007
Directory /workspace/5.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.2676498225
Short name T344
Test name
Test status
Simulation time 87387100 ps
CPU time 13.69 seconds
Started Mar 26 01:09:30 PM PDT 24
Finished Mar 26 01:09:44 PM PDT 24
Peak memory 262328 kb
Host smart-83ce5169-25a0-440c-bd47-17ac8ce3d29e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676498225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.2
676498225
Directory /workspace/5.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.3491709868
Short name T1185
Test name
Test status
Simulation time 175500400 ps
CPU time 34.66 seconds
Started Mar 26 01:09:29 PM PDT 24
Finished Mar 26 01:10:04 PM PDT 24
Peak memory 261720 kb
Host smart-fdefb37f-4e81-4ecd-a87e-20b5be967d70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491709868 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.flash_ctrl_same_csr_outstanding.3491709868
Directory /workspace/5.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.330905619
Short name T1153
Test name
Test status
Simulation time 142956800 ps
CPU time 15.52 seconds
Started Mar 26 01:09:36 PM PDT 24
Finished Mar 26 01:09:52 PM PDT 24
Peak memory 259968 kb
Host smart-cad4feda-6238-4c70-8b8d-813e606812a9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330905619 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.flash_ctrl_shadow_reg_errors.330905619
Directory /workspace/5.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.1208412011
Short name T1064
Test name
Test status
Simulation time 12813900 ps
CPU time 13.03 seconds
Started Mar 26 01:09:31 PM PDT 24
Finished Mar 26 01:09:45 PM PDT 24
Peak memory 260004 kb
Host smart-f75bf7e2-d4d9-4c98-8ab5-da21c9fb439c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208412011 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors_with_csr_rw.1208412011
Directory /workspace/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2114301736
Short name T367
Test name
Test status
Simulation time 1343283100 ps
CPU time 896.08 seconds
Started Mar 26 01:09:29 PM PDT 24
Finished Mar 26 01:24:25 PM PDT 24
Peak memory 260048 kb
Host smart-34d01395-7c59-40e4-9b5f-b37a4aa8c1c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114301736 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl
_tl_intg_err.2114301736
Directory /workspace/5.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.2744258505
Short name T1103
Test name
Test status
Simulation time 101396200 ps
CPU time 19.59 seconds
Started Mar 26 01:09:47 PM PDT 24
Finished Mar 26 01:10:06 PM PDT 24
Peak memory 270324 kb
Host smart-796c7718-00f2-49e0-a56e-161f70d27454
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744258505 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.2744258505
Directory /workspace/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.681717058
Short name T1090
Test name
Test status
Simulation time 58492200 ps
CPU time 17.48 seconds
Started Mar 26 01:09:44 PM PDT 24
Finished Mar 26 01:10:02 PM PDT 24
Peak memory 260068 kb
Host smart-d51657e8-e216-4128-9e1d-7ddd6bd66fee
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681717058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 6.flash_ctrl_csr_rw.681717058
Directory /workspace/6.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.2126597664
Short name T1156
Test name
Test status
Simulation time 18437700 ps
CPU time 13.63 seconds
Started Mar 26 01:09:44 PM PDT 24
Finished Mar 26 01:09:58 PM PDT 24
Peak memory 262468 kb
Host smart-8cecf8b6-dd3b-4b52-834a-ffd9f83e1948
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126597664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.2
126597664
Directory /workspace/6.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1167827796
Short name T1093
Test name
Test status
Simulation time 148807300 ps
CPU time 18.11 seconds
Started Mar 26 01:09:44 PM PDT 24
Finished Mar 26 01:10:02 PM PDT 24
Peak memory 260112 kb
Host smart-bf05de83-3ff1-47d3-a040-d3631e6ef3f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167827796 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.flash_ctrl_same_csr_outstanding.1167827796
Directory /workspace/6.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.33478060
Short name T1122
Test name
Test status
Simulation time 12931100 ps
CPU time 15.93 seconds
Started Mar 26 01:09:45 PM PDT 24
Finished Mar 26 01:10:01 PM PDT 24
Peak memory 260060 kb
Host smart-f3413dbd-d3cf-4d46-950b-45e008b49b6a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33478060 -assert nopostproc +UVM_TESTNAME=flash_ctrl_b
ase_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.flash_ctrl_shadow_reg_errors.33478060
Directory /workspace/6.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.1142889724
Short name T1085
Test name
Test status
Simulation time 14320200 ps
CPU time 15.64 seconds
Started Mar 26 01:09:44 PM PDT 24
Finished Mar 26 01:09:59 PM PDT 24
Peak memory 259984 kb
Host smart-04012488-5914-4947-af33-16a004288381
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142889724 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors_with_csr_rw.1142889724
Directory /workspace/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2753291484
Short name T278
Test name
Test status
Simulation time 67872000 ps
CPU time 16.38 seconds
Started Mar 26 01:09:30 PM PDT 24
Finished Mar 26 01:09:47 PM PDT 24
Peak memory 263728 kb
Host smart-b5ae8e9c-629f-492a-a7ca-d924a257e33f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753291484 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.2
753291484
Directory /workspace/6.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3688070886
Short name T363
Test name
Test status
Simulation time 2924456300 ps
CPU time 897.92 seconds
Started Mar 26 01:09:45 PM PDT 24
Finished Mar 26 01:24:43 PM PDT 24
Peak memory 263688 kb
Host smart-a7910ee5-0ce7-4d66-bffc-12c7c844f782
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688070886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl
_tl_intg_err.3688070886
Directory /workspace/6.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.94982336
Short name T1175
Test name
Test status
Simulation time 44608100 ps
CPU time 18.68 seconds
Started Mar 26 01:09:47 PM PDT 24
Finished Mar 26 01:10:05 PM PDT 24
Peak memory 271968 kb
Host smart-70a3535e-755b-4db3-9d55-53041771b4fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94982336 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.94982336
Directory /workspace/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.3533741891
Short name T181
Test name
Test status
Simulation time 21962100 ps
CPU time 15.84 seconds
Started Mar 26 01:09:50 PM PDT 24
Finished Mar 26 01:10:06 PM PDT 24
Peak memory 259916 kb
Host smart-b71b1437-4015-41fc-a085-686e0e737181
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533741891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.flash_ctrl_csr_rw.3533741891
Directory /workspace/7.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.3860259631
Short name T1195
Test name
Test status
Simulation time 57262900 ps
CPU time 13.65 seconds
Started Mar 26 01:09:45 PM PDT 24
Finished Mar 26 01:09:59 PM PDT 24
Peak memory 262252 kb
Host smart-58fe86c0-36de-4db5-8e2b-090fb19c0687
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860259631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.3
860259631
Directory /workspace/7.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1101522646
Short name T1088
Test name
Test status
Simulation time 630010500 ps
CPU time 18.02 seconds
Started Mar 26 01:09:46 PM PDT 24
Finished Mar 26 01:10:04 PM PDT 24
Peak memory 260116 kb
Host smart-bbd2fa87-fb5c-4fcd-b1e2-461126be1ae1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101522646 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.flash_ctrl_same_csr_outstanding.1101522646
Directory /workspace/7.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.1569070244
Short name T1126
Test name
Test status
Simulation time 35949200 ps
CPU time 15.32 seconds
Started Mar 26 01:09:50 PM PDT 24
Finished Mar 26 01:10:05 PM PDT 24
Peak memory 259900 kb
Host smart-50a058c0-096b-4a93-add4-891cd639d19e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569070244 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors.1569070244
Directory /workspace/7.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.3543884548
Short name T1173
Test name
Test status
Simulation time 36289800 ps
CPU time 15.29 seconds
Started Mar 26 01:09:44 PM PDT 24
Finished Mar 26 01:09:59 PM PDT 24
Peak memory 259980 kb
Host smart-cc73e476-ff9b-49d9-a132-97af2360e9c5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543884548 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors_with_csr_rw.3543884548
Directory /workspace/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.3269146281
Short name T361
Test name
Test status
Simulation time 1018946300 ps
CPU time 877.82 seconds
Started Mar 26 01:09:44 PM PDT 24
Finished Mar 26 01:24:22 PM PDT 24
Peak memory 261272 kb
Host smart-2afc00a9-8bde-4c2c-bad4-bbc7462e0b93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269146281 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl
_tl_intg_err.3269146281
Directory /workspace/7.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.930571882
Short name T313
Test name
Test status
Simulation time 245640700 ps
CPU time 15.68 seconds
Started Mar 26 01:09:56 PM PDT 24
Finished Mar 26 01:10:13 PM PDT 24
Peak memory 271796 kb
Host smart-50eaadc7-7aab-481b-a78f-655a4969cc9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930571882 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.930571882
Directory /workspace/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.4239546465
Short name T310
Test name
Test status
Simulation time 147372900 ps
CPU time 16.61 seconds
Started Mar 26 01:09:55 PM PDT 24
Finished Mar 26 01:10:14 PM PDT 24
Peak memory 259964 kb
Host smart-c89aee7e-b803-46ec-ac3d-ff71da63c526
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239546465 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.flash_ctrl_csr_rw.4239546465
Directory /workspace/8.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.1791465180
Short name T359
Test name
Test status
Simulation time 260223500 ps
CPU time 13.46 seconds
Started Mar 26 01:09:45 PM PDT 24
Finished Mar 26 01:09:59 PM PDT 24
Peak memory 260688 kb
Host smart-58a606d1-5b8b-4140-8c0b-588c94240681
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791465180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.1
791465180
Directory /workspace/8.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.2588185802
Short name T318
Test name
Test status
Simulation time 221332000 ps
CPU time 16.05 seconds
Started Mar 26 01:09:56 PM PDT 24
Finished Mar 26 01:10:14 PM PDT 24
Peak memory 260140 kb
Host smart-871faf5f-d616-4852-a787-47bcef3beb0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588185802 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.flash_ctrl_same_csr_outstanding.2588185802
Directory /workspace/8.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.52157067
Short name T1107
Test name
Test status
Simulation time 42489400 ps
CPU time 13.38 seconds
Started Mar 26 01:09:44 PM PDT 24
Finished Mar 26 01:09:57 PM PDT 24
Peak memory 259920 kb
Host smart-74082a02-f30c-4038-848d-ebf808ba11f3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52157067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_b
ase_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.flash_ctrl_shadow_reg_errors.52157067
Directory /workspace/8.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.173750267
Short name T1094
Test name
Test status
Simulation time 29563900 ps
CPU time 16.01 seconds
Started Mar 26 01:09:45 PM PDT 24
Finished Mar 26 01:10:02 PM PDT 24
Peak memory 260056 kb
Host smart-ca025d26-c543-4336-aef6-c78e34f6d28b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173750267 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors_with_csr_rw.173750267
Directory /workspace/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.2065126790
Short name T247
Test name
Test status
Simulation time 45558800 ps
CPU time 19 seconds
Started Mar 26 01:09:46 PM PDT 24
Finished Mar 26 01:10:05 PM PDT 24
Peak memory 263884 kb
Host smart-fc2c4e60-9923-44b1-8b3f-87fa2c7500bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065126790 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.2
065126790
Directory /workspace/8.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.1605942448
Short name T275
Test name
Test status
Simulation time 258986200 ps
CPU time 382.41 seconds
Started Mar 26 01:09:45 PM PDT 24
Finished Mar 26 01:16:07 PM PDT 24
Peak memory 261624 kb
Host smart-86b9f2f0-4a09-4f9d-a452-00687094c534
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605942448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl
_tl_intg_err.1605942448
Directory /workspace/8.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.2926993968
Short name T246
Test name
Test status
Simulation time 156322300 ps
CPU time 17.67 seconds
Started Mar 26 01:09:57 PM PDT 24
Finished Mar 26 01:10:16 PM PDT 24
Peak memory 272016 kb
Host smart-05820892-3809-479f-b234-7d477a0fb204
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926993968 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.2926993968
Directory /workspace/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.700295356
Short name T1071
Test name
Test status
Simulation time 45294300 ps
CPU time 13.9 seconds
Started Mar 26 01:09:56 PM PDT 24
Finished Mar 26 01:10:11 PM PDT 24
Peak memory 259968 kb
Host smart-606c4c4b-90e5-4265-8695-a93ffcce7b45
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700295356 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 9.flash_ctrl_csr_rw.700295356
Directory /workspace/9.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.1907944654
Short name T1180
Test name
Test status
Simulation time 45870300 ps
CPU time 13.45 seconds
Started Mar 26 01:09:56 PM PDT 24
Finished Mar 26 01:10:12 PM PDT 24
Peak memory 262204 kb
Host smart-abd1c8ae-5e9b-4648-87bb-1bbe2768032f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907944654 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.1
907944654
Directory /workspace/9.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.3529361458
Short name T1187
Test name
Test status
Simulation time 123545300 ps
CPU time 17.81 seconds
Started Mar 26 01:09:56 PM PDT 24
Finished Mar 26 01:10:15 PM PDT 24
Peak memory 261988 kb
Host smart-a735f35b-746a-461d-9648-e89e407c9222
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529361458 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.flash_ctrl_same_csr_outstanding.3529361458
Directory /workspace/9.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.1320580774
Short name T1176
Test name
Test status
Simulation time 21361800 ps
CPU time 15.59 seconds
Started Mar 26 01:09:56 PM PDT 24
Finished Mar 26 01:10:13 PM PDT 24
Peak memory 260136 kb
Host smart-2e7f05ef-a684-45f6-804c-0f835c93d6ae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320580774 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors.1320580774
Directory /workspace/9.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2745443413
Short name T1056
Test name
Test status
Simulation time 33550500 ps
CPU time 15.73 seconds
Started Mar 26 01:09:57 PM PDT 24
Finished Mar 26 01:10:14 PM PDT 24
Peak memory 260128 kb
Host smart-b5be5c5a-c4fe-4897-8a08-f06d91c08bc8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745443413 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors_with_csr_rw.2745443413
Directory /workspace/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.2909930783
Short name T186
Test name
Test status
Simulation time 127737500 ps
CPU time 16.11 seconds
Started Mar 26 01:09:56 PM PDT 24
Finished Mar 26 01:10:13 PM PDT 24
Peak memory 263740 kb
Host smart-9fe6f1b7-f401-4adb-a093-0577ebab1c23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909930783 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.2
909930783
Directory /workspace/9.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.2649143090
Short name T285
Test name
Test status
Simulation time 4634661000 ps
CPU time 465.14 seconds
Started Mar 26 01:09:56 PM PDT 24
Finished Mar 26 01:17:42 PM PDT 24
Peak memory 260084 kb
Host smart-8fef2fcd-a158-4bb2-ad4d-a0d620e4d85a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649143090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl
_tl_intg_err.2649143090
Directory /workspace/9.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_alert_test.3507162131
Short name T782
Test name
Test status
Simulation time 20748300 ps
CPU time 13.23 seconds
Started Mar 26 01:23:17 PM PDT 24
Finished Mar 26 01:23:31 PM PDT 24
Peak memory 257500 kb
Host smart-8c4f689f-d9cd-4dff-a1e7-e82402d8e8aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507162131 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.3
507162131
Directory /workspace/0.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.flash_ctrl_connect.2465301732
Short name T808
Test name
Test status
Simulation time 15654600 ps
CPU time 15.36 seconds
Started Mar 26 01:23:18 PM PDT 24
Finished Mar 26 01:23:33 PM PDT 24
Peak memory 275032 kb
Host smart-88bcf419-28e7-470f-b5fa-ed72a32b5964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465301732 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.2465301732
Directory /workspace/0.flash_ctrl_connect/latest

Test location /workspace/coverage/default/0.flash_ctrl_derr_detect.2191938377
Short name T211
Test name
Test status
Simulation time 180457100 ps
CPU time 104.18 seconds
Started Mar 26 01:23:15 PM PDT 24
Finished Mar 26 01:25:00 PM PDT 24
Peak memory 272604 kb
Host smart-fdba7a3f-eb1e-48a9-831d-5bec7f2e8c45
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191938377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_derr_detect.2191938377
Directory /workspace/0.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/0.flash_ctrl_erase_suspend.2509203092
Short name T130
Test name
Test status
Simulation time 2048394200 ps
CPU time 424.92 seconds
Started Mar 26 01:23:19 PM PDT 24
Finished Mar 26 01:30:24 PM PDT 24
Peak memory 262072 kb
Host smart-85ee0f8b-ae3c-4af0-84cf-c7d47af00ada
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2509203092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.2509203092
Directory /workspace/0.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_mp.1295296456
Short name T410
Test name
Test status
Simulation time 5163848900 ps
CPU time 2101.69 seconds
Started Mar 26 01:23:13 PM PDT 24
Finished Mar 26 01:58:15 PM PDT 24
Peak memory 264008 kb
Host smart-f2f1faf7-216c-476c-a531-0dffcaf89c7b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295296456 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_err
or_mp.1295296456
Directory /workspace/0.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/0.flash_ctrl_fetch_code.3674108748
Short name T992
Test name
Test status
Simulation time 1697637800 ps
CPU time 26.77 seconds
Started Mar 26 01:23:21 PM PDT 24
Finished Mar 26 01:23:48 PM PDT 24
Peak memory 263932 kb
Host smart-045dd5e1-cc1b-480b-a950-2ddf2503e398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674108748 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetch_code.3674108748
Directory /workspace/0.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/0.flash_ctrl_full_mem_access.1607299789
Short name T93
Test name
Test status
Simulation time 203473457800 ps
CPU time 3456.34 seconds
Started Mar 26 01:23:17 PM PDT 24
Finished Mar 26 02:20:53 PM PDT 24
Peak memory 261120 kb
Host smart-1f6a11ee-c97a-4da7-8ef7-a97a0cf13f48
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607299789 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_c
trl_full_mem_access.1607299789
Directory /workspace/0.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_ctrl_arb.2898127986
Short name T594
Test name
Test status
Simulation time 535558803000 ps
CPU time 1979.19 seconds
Started Mar 26 01:23:14 PM PDT 24
Finished Mar 26 01:56:14 PM PDT 24
Peak memory 264232 kb
Host smart-542377f9-d9b1-4240-9671-60cd6d05d1b5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898127986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.flash_ctrl_host_ctrl_arb.2898127986
Directory /workspace/0.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_dir_rd.3028142792
Short name T955
Test name
Test status
Simulation time 20517800 ps
CPU time 23.64 seconds
Started Mar 26 01:23:14 PM PDT 24
Finished Mar 26 01:23:37 PM PDT 24
Peak memory 263280 kb
Host smart-bf607e44-14aa-4e4f-988f-7807c12d0dff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3028142792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.3028142792
Directory /workspace/0.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.1958426650
Short name T760
Test name
Test status
Simulation time 10012317500 ps
CPU time 119.26 seconds
Started Mar 26 01:23:18 PM PDT 24
Finished Mar 26 01:25:18 PM PDT 24
Peak memory 297784 kb
Host smart-9d1e4158-3964-4b02-9ae7-6a1847a2958d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958426650 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.1958426650
Directory /workspace/0.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma.3041430453
Short name T909
Test name
Test status
Simulation time 334804112900 ps
CPU time 1975.93 seconds
Started Mar 26 01:23:16 PM PDT 24
Finished Mar 26 01:56:12 PM PDT 24
Peak memory 263184 kb
Host smart-3f5fedeb-2b9a-44c0-82b3-065929cb13fd
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041430453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.flash_ctrl_hw_rma.3041430453
Directory /workspace/0.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma_reset.4118577116
Short name T891
Test name
Test status
Simulation time 40124034600 ps
CPU time 919.45 seconds
Started Mar 26 01:23:11 PM PDT 24
Finished Mar 26 01:38:31 PM PDT 24
Peak memory 263532 kb
Host smart-c988fbba-7b99-4fd4-baa3-bd8ed09e115d
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118577116 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.flash_ctrl_hw_rma_reset.4118577116
Directory /workspace/0.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_sec_otp.3109670646
Short name T734
Test name
Test status
Simulation time 7549574100 ps
CPU time 137.93 seconds
Started Mar 26 01:23:16 PM PDT 24
Finished Mar 26 01:25:35 PM PDT 24
Peak memory 261620 kb
Host smart-c51e9f13-ca1d-4c59-8443-6829d74f7a85
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109670646 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_h
w_sec_otp.3109670646
Directory /workspace/0.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd_slow_flash.2576211382
Short name T583
Test name
Test status
Simulation time 16533454700 ps
CPU time 234.27 seconds
Started Mar 26 01:23:20 PM PDT 24
Finished Mar 26 01:27:14 PM PDT 24
Peak memory 283996 kb
Host smart-191efbc7-bcd0-4146-845f-6d9a06294c17
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576211382 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd_slow_flash.2576211382
Directory /workspace/0.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr_slow_flash.2691236987
Short name T753
Test name
Test status
Simulation time 42358628300 ps
CPU time 313.73 seconds
Started Mar 26 01:23:19 PM PDT 24
Finished Mar 26 01:28:33 PM PDT 24
Peak memory 260592 kb
Host smart-c12368e7-ddfd-43e2-8cf0-9ac84f2663de
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269
1236987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.2691236987
Directory /workspace/0.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_invalid_op.2557221155
Short name T661
Test name
Test status
Simulation time 2482681700 ps
CPU time 86.23 seconds
Started Mar 26 01:23:17 PM PDT 24
Finished Mar 26 01:24:43 PM PDT 24
Peak memory 259800 kb
Host smart-2c56df41-c85d-4600-befd-c7346c5e3279
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557221155 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.2557221155
Directory /workspace/0.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_lcmgr_intg.4250769397
Short name T582
Test name
Test status
Simulation time 97455600 ps
CPU time 13.53 seconds
Started Mar 26 01:23:19 PM PDT 24
Finished Mar 26 01:23:32 PM PDT 24
Peak memory 258884 kb
Host smart-0d418260-44c3-499d-83db-d7a71e3b8395
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250769397 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_lcmgr_intg.4250769397
Directory /workspace/0.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_mid_op_rst.193490362
Short name T263
Test name
Test status
Simulation time 3962532000 ps
CPU time 75.63 seconds
Started Mar 26 01:23:19 PM PDT 24
Finished Mar 26 01:24:34 PM PDT 24
Peak memory 259004 kb
Host smart-c1867500-5921-4656-bf5a-13aa3704919d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193490362 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.193490362
Directory /workspace/0.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/0.flash_ctrl_mp_regions.3036459071
Short name T98
Test name
Test status
Simulation time 51392628800 ps
CPU time 437.23 seconds
Started Mar 26 01:23:15 PM PDT 24
Finished Mar 26 01:30:33 PM PDT 24
Peak memory 273556 kb
Host smart-e4aa9edf-f881-43a4-9754-84f3e6c647b1
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036459071 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_mp_regions.3036459071
Directory /workspace/0.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/0.flash_ctrl_otp_reset.2682497999
Short name T930
Test name
Test status
Simulation time 39275900 ps
CPU time 132.09 seconds
Started Mar 26 01:23:17 PM PDT 24
Finished Mar 26 01:25:29 PM PDT 24
Peak memory 259032 kb
Host smart-2ec0f06c-d026-4f0b-a165-bcf4f7aadf20
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682497999 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ot
p_reset.2682497999
Directory /workspace/0.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_oversize_error.3379702409
Short name T1035
Test name
Test status
Simulation time 953840700 ps
CPU time 132.4 seconds
Started Mar 26 01:23:15 PM PDT 24
Finished Mar 26 01:25:27 PM PDT 24
Peak memory 280784 kb
Host smart-01377df4-ed8e-413c-bf35-a607e859063b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379702409 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_oversize_error.3379702409
Directory /workspace/0.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb.1647549555
Short name T202
Test name
Test status
Simulation time 2691035200 ps
CPU time 129.76 seconds
Started Mar 26 01:23:11 PM PDT 24
Finished Mar 26 01:25:21 PM PDT 24
Peak memory 261476 kb
Host smart-6e2eb082-566e-45aa-b4a2-9777ed05c1e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1647549555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.1647549555
Directory /workspace/0.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb_redun.576549073
Short name T73
Test name
Test status
Simulation time 826744400 ps
CPU time 68.53 seconds
Started Mar 26 01:23:18 PM PDT 24
Finished Mar 26 01:24:27 PM PDT 24
Peak memory 272852 kb
Host smart-bdca4900-b201-4aa5-a098-f8605a713022
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576549073 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.576549073
Directory /workspace/0.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_host_grant_err.758427783
Short name T11
Test name
Test status
Simulation time 15511800 ps
CPU time 13.63 seconds
Started Mar 26 01:23:18 PM PDT 24
Finished Mar 26 01:23:32 PM PDT 24
Peak memory 264544 kb
Host smart-04cd6be4-978d-4beb-9336-c958e9d522a2
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758427783 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.758427783
Directory /workspace/0.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_prog_reset.3347661817
Short name T697
Test name
Test status
Simulation time 93850700 ps
CPU time 13.83 seconds
Started Mar 26 01:23:24 PM PDT 24
Finished Mar 26 01:23:38 PM PDT 24
Peak memory 259204 kb
Host smart-1ac7ff4c-78b2-4b6d-8e38-55387e19f179
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347661817 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_prog_res
et.3347661817
Directory /workspace/0.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_rand_ops.555103325
Short name T926
Test name
Test status
Simulation time 150986500 ps
CPU time 625.88 seconds
Started Mar 26 01:23:14 PM PDT 24
Finished Mar 26 01:33:40 PM PDT 24
Peak memory 281800 kb
Host smart-d0b9dc7a-4a03-4e51-8be6-cd02785a2cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555103325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.555103325
Directory /workspace/0.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_buff_evict.1440380437
Short name T297
Test name
Test status
Simulation time 81218400 ps
CPU time 101.43 seconds
Started Mar 26 01:23:17 PM PDT 24
Finished Mar 26 01:24:58 PM PDT 24
Peak memory 264244 kb
Host smart-ffca39ac-5d9e-45c7-8583-a79312e0d42b
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1440380437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.1440380437
Directory /workspace/0.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_intg.1286815505
Short name T774
Test name
Test status
Simulation time 84273200 ps
CPU time 31.39 seconds
Started Mar 26 01:23:13 PM PDT 24
Finished Mar 26 01:23:45 PM PDT 24
Peak memory 273512 kb
Host smart-a5a9d5af-fdf0-456d-a7b5-e15729b07afd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286815505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_rd_intg.1286815505
Directory /workspace/0.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_ooo.2374016842
Short name T899
Test name
Test status
Simulation time 133022400 ps
CPU time 43 seconds
Started Mar 26 01:23:22 PM PDT 24
Finished Mar 26 01:24:05 PM PDT 24
Peak memory 272528 kb
Host smart-568fbdb9-a4c4-4878-9716-780ff0988023
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374016842 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_rd_ooo.2374016842
Directory /workspace/0.flash_ctrl_rd_ooo/latest

Test location /workspace/coverage/default/0.flash_ctrl_re_evict.3613287801
Short name T971
Test name
Test status
Simulation time 71163800 ps
CPU time 29.99 seconds
Started Mar 26 01:23:18 PM PDT 24
Finished Mar 26 01:23:48 PM PDT 24
Peak memory 272648 kb
Host smart-6381ed1d-2c87-4b3b-ad33-7e2e80e3ce28
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613287801 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_re_evict.3613287801
Directory /workspace/0.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep.1836057805
Short name T580
Test name
Test status
Simulation time 32257700 ps
CPU time 13.86 seconds
Started Mar 26 01:23:16 PM PDT 24
Finished Mar 26 01:23:30 PM PDT 24
Peak memory 264124 kb
Host smart-5167f578-114a-4ff8-a0bc-9459c1aaf02d
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1836057805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep
.1836057805
Directory /workspace/0.flash_ctrl_read_word_sweep/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_derr.2055008361
Short name T212
Test name
Test status
Simulation time 68076300 ps
CPU time 22.45 seconds
Started Mar 26 01:23:16 PM PDT 24
Finished Mar 26 01:23:39 PM PDT 24
Peak memory 264332 kb
Host smart-e69e6202-5edd-4075-8418-c2c94620c5c0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055008361 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_derr.2055008361
Directory /workspace/0.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_serr.794596948
Short name T547
Test name
Test status
Simulation time 305261800 ps
CPU time 20.98 seconds
Started Mar 26 01:23:17 PM PDT 24
Finished Mar 26 01:23:38 PM PDT 24
Peak memory 263592 kb
Host smart-f8ed2d1e-37ef-42de-9ec6-0a449650daab
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794596948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_read_word_sweep_serr.794596948
Directory /workspace/0.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro.2973607888
Short name T932
Test name
Test status
Simulation time 598583400 ps
CPU time 105.01 seconds
Started Mar 26 01:23:17 PM PDT 24
Finished Mar 26 01:25:02 PM PDT 24
Peak memory 280160 kb
Host smart-e4ce2cd6-f874-40a1-a10c-0791fb887bae
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973607888 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_ro.2973607888
Directory /workspace/0.flash_ctrl_ro/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_serr.3781905043
Short name T177
Test name
Test status
Simulation time 749225900 ps
CPU time 120.59 seconds
Started Mar 26 01:23:14 PM PDT 24
Finished Mar 26 01:25:15 PM PDT 24
Peak memory 293160 kb
Host smart-6f9ce1ec-eb78-42e7-bf38-f17ca339d694
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781905043 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.flash_ctrl_ro_serr.3781905043
Directory /workspace/0.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw.4163993089
Short name T693
Test name
Test status
Simulation time 13046699100 ps
CPU time 549.42 seconds
Started Mar 26 01:23:16 PM PDT 24
Finished Mar 26 01:32:26 PM PDT 24
Peak memory 313380 kb
Host smart-36d84fc1-b8ae-4a40-be28-f9e275c37a62
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163993089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ct
rl_rw.4163993089
Directory /workspace/0.flash_ctrl_rw/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict.2245539622
Short name T660
Test name
Test status
Simulation time 50518000 ps
CPU time 31.01 seconds
Started Mar 26 01:23:19 PM PDT 24
Finished Mar 26 01:23:50 PM PDT 24
Peak memory 272548 kb
Host smart-b74c1f74-1b70-4cbe-b948-102123af53c4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245539622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_rw_evict.2245539622
Directory /workspace/0.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict_all_en.10747738
Short name T213
Test name
Test status
Simulation time 91298600 ps
CPU time 28.64 seconds
Started Mar 26 01:23:11 PM PDT 24
Finished Mar 26 01:23:40 PM PDT 24
Peak memory 272616 kb
Host smart-ab7b949b-5d02-43c6-b200-07f08451e1f6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10747738 -assert nopostproc +UVM_TESTNAME=fl
ash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 0.flash_ctrl_rw_evict_all_en.10747738
Directory /workspace/0.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_address.4186389051
Short name T872
Test name
Test status
Simulation time 1784299800 ps
CPU time 99.35 seconds
Started Mar 26 01:23:15 PM PDT 24
Finished Mar 26 01:24:55 PM PDT 24
Peak memory 272456 kb
Host smart-14b14191-aa06-4285-a6dc-7c5dbc56a539
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186389051 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_serr_address.4186389051
Directory /workspace/0.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_counter.1307437638
Short name T621
Test name
Test status
Simulation time 966776600 ps
CPU time 75.35 seconds
Started Mar 26 01:23:16 PM PDT 24
Finished Mar 26 01:24:31 PM PDT 24
Peak memory 272488 kb
Host smart-b0eee8ea-e8cd-471f-a72f-1ab283363bad
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307437638 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_serr_counter.1307437638
Directory /workspace/0.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke.230730640
Short name T919
Test name
Test status
Simulation time 61578500 ps
CPU time 74.75 seconds
Started Mar 26 01:23:15 PM PDT 24
Finished Mar 26 01:24:30 PM PDT 24
Peak memory 275528 kb
Host smart-b7deab0e-41e5-423c-a01e-23b5bfe2e3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230730640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.230730640
Directory /workspace/0.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke_hw.4079465317
Short name T511
Test name
Test status
Simulation time 70412100 ps
CPU time 26.08 seconds
Started Mar 26 01:23:16 PM PDT 24
Finished Mar 26 01:23:42 PM PDT 24
Peak memory 258084 kb
Host smart-3424363d-1e4e-4dca-8ed7-1d09211a42e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079465317 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.4079465317
Directory /workspace/0.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/0.flash_ctrl_stress_all.2495555878
Short name T999
Test name
Test status
Simulation time 3244014600 ps
CPU time 1132.17 seconds
Started Mar 26 01:23:11 PM PDT 24
Finished Mar 26 01:42:04 PM PDT 24
Peak memory 295364 kb
Host smart-7bf63d45-d91c-44b4-abec-3ddd3d0efe5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495555878 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stres
s_all.2495555878
Directory /workspace/0.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.flash_ctrl_sw_op.211311504
Short name T898
Test name
Test status
Simulation time 49184200 ps
CPU time 25.89 seconds
Started Mar 26 01:23:16 PM PDT 24
Finished Mar 26 01:23:42 PM PDT 24
Peak memory 258008 kb
Host smart-61fad0d7-84dd-457e-901a-bb5589bd3cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211311504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.211311504
Directory /workspace/0.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_wo.358478930
Short name T998
Test name
Test status
Simulation time 6078414200 ps
CPU time 195.32 seconds
Started Mar 26 01:23:17 PM PDT 24
Finished Mar 26 01:26:32 PM PDT 24
Peak memory 263792 kb
Host smart-f165d9dd-32da-4207-815b-85da3b08d3fd
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358478930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.flash_ctrl_wo.358478930
Directory /workspace/0.flash_ctrl_wo/latest

Test location /workspace/coverage/default/0.flash_ctrl_write_word_sweep.320535285
Short name T440
Test name
Test status
Simulation time 860672300 ps
CPU time 16.92 seconds
Started Mar 26 01:23:14 PM PDT 24
Finished Mar 26 01:23:31 PM PDT 24
Peak memory 259140 kb
Host smart-539e0066-9a3f-4b42-afb5-ab126142d434
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=320535285 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_swee
p.320535285
Directory /workspace/0.flash_ctrl_write_word_sweep/latest

Test location /workspace/coverage/default/1.flash_ctrl_alert_test.3762084634
Short name T441
Test name
Test status
Simulation time 97504500 ps
CPU time 13.56 seconds
Started Mar 26 01:23:30 PM PDT 24
Finished Mar 26 01:23:44 PM PDT 24
Peak memory 257256 kb
Host smart-4bf36897-76e6-41c6-a6a7-f06acb18f247
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762084634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.3
762084634
Directory /workspace/1.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.flash_ctrl_config_regwen.2758749988
Short name T4
Test name
Test status
Simulation time 34494400 ps
CPU time 13.73 seconds
Started Mar 26 01:23:31 PM PDT 24
Finished Mar 26 01:23:45 PM PDT 24
Peak memory 264216 kb
Host smart-894f8579-2f8a-43ff-a8c5-88358fd28c5b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758749988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.flash_ctrl_config_regwen.2758749988
Directory /workspace/1.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/1.flash_ctrl_connect.181392402
Short name T449
Test name
Test status
Simulation time 66140400 ps
CPU time 12.96 seconds
Started Mar 26 01:23:34 PM PDT 24
Finished Mar 26 01:23:48 PM PDT 24
Peak memory 275056 kb
Host smart-8fe3fc7c-c5d7-49f2-a4aa-cce649c90caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181392402 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.181392402
Directory /workspace/1.flash_ctrl_connect/latest

Test location /workspace/coverage/default/1.flash_ctrl_derr_detect.1335249191
Short name T228
Test name
Test status
Simulation time 122806400 ps
CPU time 106.55 seconds
Started Mar 26 01:23:24 PM PDT 24
Finished Mar 26 01:25:10 PM PDT 24
Peak memory 270800 kb
Host smart-59c2bee8-a992-4e46-a22f-c93f57d74263
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335249191 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_derr_detect.1335249191
Directory /workspace/1.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/1.flash_ctrl_disable.4005815959
Short name T167
Test name
Test status
Simulation time 15761700 ps
CPU time 20.51 seconds
Started Mar 26 01:23:27 PM PDT 24
Finished Mar 26 01:23:48 PM PDT 24
Peak memory 272552 kb
Host smart-47623eae-5eb6-4b87-ac9d-9e686e57e1c9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005815959 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_disable.4005815959
Directory /workspace/1.flash_ctrl_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_erase_suspend.889454185
Short name T1006
Test name
Test status
Simulation time 4260516100 ps
CPU time 383.95 seconds
Started Mar 26 01:23:14 PM PDT 24
Finished Mar 26 01:29:38 PM PDT 24
Peak memory 262092 kb
Host smart-b8faca8c-b39f-45a4-98fb-8dcea5677e7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=889454185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.889454185
Directory /workspace/1.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_mp.4087901113
Short name T947
Test name
Test status
Simulation time 54345312100 ps
CPU time 2218.85 seconds
Started Mar 26 01:23:23 PM PDT 24
Finished Mar 26 02:00:22 PM PDT 24
Peak memory 263564 kb
Host smart-201ef210-3e27-44a9-9780-29470ab2e71e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087901113 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_err
or_mp.4087901113
Directory /workspace/1.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_type.2005580027
Short name T169
Test name
Test status
Simulation time 1080452900 ps
CPU time 2931.01 seconds
Started Mar 26 01:23:31 PM PDT 24
Finished Mar 26 02:12:23 PM PDT 24
Peak memory 264232 kb
Host smart-cfb19a99-1573-4e86-8ed8-fdc15ecdd800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005580027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_type.2005580027
Directory /workspace/1.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_win.3903403925
Short name T309
Test name
Test status
Simulation time 2660989000 ps
CPU time 924.37 seconds
Started Mar 26 01:23:23 PM PDT 24
Finished Mar 26 01:38:48 PM PDT 24
Peak memory 272436 kb
Host smart-02c90d5c-6471-4031-85a1-16e8bfcf2adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903403925 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.3903403925
Directory /workspace/1.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/1.flash_ctrl_fetch_code.3865279232
Short name T259
Test name
Test status
Simulation time 3761314100 ps
CPU time 30.51 seconds
Started Mar 26 01:23:26 PM PDT 24
Finished Mar 26 01:23:57 PM PDT 24
Peak memory 264224 kb
Host smart-a15142d5-5675-4424-8f20-d08e4640ac20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865279232 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetch_code.3865279232
Directory /workspace/1.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/1.flash_ctrl_full_mem_access.1113473239
Short name T861
Test name
Test status
Simulation time 84116797800 ps
CPU time 2589.21 seconds
Started Mar 26 01:23:24 PM PDT 24
Finished Mar 26 02:06:34 PM PDT 24
Peak memory 262744 kb
Host smart-1d48d619-eaf9-459e-9372-de8a12d45685
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113473239 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_c
trl_full_mem_access.1113473239
Directory /workspace/1.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_ctrl_arb.674073360
Short name T1038
Test name
Test status
Simulation time 544758278900 ps
CPU time 1917.59 seconds
Started Mar 26 01:23:15 PM PDT 24
Finished Mar 26 01:55:13 PM PDT 24
Peak memory 264256 kb
Host smart-99f48edc-0ef1-4cbe-8ee5-728cc1ab5bb8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674073360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TES
T_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.flash_ctrl_host_ctrl_arb.674073360
Directory /workspace/1.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_dir_rd.3887286701
Short name T778
Test name
Test status
Simulation time 130623600 ps
CPU time 120.4 seconds
Started Mar 26 01:23:21 PM PDT 24
Finished Mar 26 01:25:22 PM PDT 24
Peak memory 264064 kb
Host smart-f6246ba9-2e3e-4a43-8b7c-a1e6d0741b1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3887286701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.3887286701
Directory /workspace/1.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.2215210260
Short name T934
Test name
Test status
Simulation time 10021434200 ps
CPU time 59.1 seconds
Started Mar 26 01:23:26 PM PDT 24
Finished Mar 26 01:24:26 PM PDT 24
Peak memory 263368 kb
Host smart-8e248c1e-c3d5-4ecc-b242-e55ba56c5020
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215210260 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.2215210260
Directory /workspace/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_read_seed_err.3156262307
Short name T776
Test name
Test status
Simulation time 21047600 ps
CPU time 13.18 seconds
Started Mar 26 01:23:35 PM PDT 24
Finished Mar 26 01:23:49 PM PDT 24
Peak memory 258368 kb
Host smart-2f71718c-22cb-48cf-907d-dab5958c06dc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156262307 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_read_seed_err.3156262307
Directory /workspace/1.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma.3789699269
Short name T706
Test name
Test status
Simulation time 85494580400 ps
CPU time 1839.06 seconds
Started Mar 26 01:23:16 PM PDT 24
Finished Mar 26 01:53:56 PM PDT 24
Peak memory 262608 kb
Host smart-28c476cb-d46e-4cf1-93c0-e5d3f4bc1ec1
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789699269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.flash_ctrl_hw_rma.3789699269
Directory /workspace/1.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma_reset.1540111248
Short name T163
Test name
Test status
Simulation time 40124256600 ps
CPU time 801.07 seconds
Started Mar 26 01:23:21 PM PDT 24
Finished Mar 26 01:36:42 PM PDT 24
Peak memory 262332 kb
Host smart-5285aed3-7b27-44aa-a044-c9df0e96b8a3
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540111248 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.flash_ctrl_hw_rma_reset.1540111248
Directory /workspace/1.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_sec_otp.2998877496
Short name T528
Test name
Test status
Simulation time 2254065800 ps
CPU time 81.2 seconds
Started Mar 26 01:23:19 PM PDT 24
Finished Mar 26 01:24:40 PM PDT 24
Peak memory 261620 kb
Host smart-3311fd03-7be6-423d-b471-148b261aff16
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998877496 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_h
w_sec_otp.2998877496
Directory /workspace/1.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.820610118
Short name T1026
Test name
Test status
Simulation time 50781817100 ps
CPU time 210.24 seconds
Started Mar 26 01:23:34 PM PDT 24
Finished Mar 26 01:27:04 PM PDT 24
Peak memory 290436 kb
Host smart-54cc2ef4-3630-4103-b8a3-12a657006ce6
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820610118 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd_slow_flash.820610118
Directory /workspace/1.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr.1838951405
Short name T952
Test name
Test status
Simulation time 24509710400 ps
CPU time 101.4 seconds
Started Mar 26 01:23:30 PM PDT 24
Finished Mar 26 01:25:11 PM PDT 24
Peak memory 260104 kb
Host smart-15ea734f-3894-494f-a844-7fc48eec7a43
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838951405 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.flash_ctrl_intr_wr.1838951405
Directory /workspace/1.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr_slow_flash.860198340
Short name T22
Test name
Test status
Simulation time 162724611900 ps
CPU time 416.28 seconds
Started Mar 26 01:23:33 PM PDT 24
Finished Mar 26 01:30:29 PM PDT 24
Peak memory 260240 kb
Host smart-38f59890-7947-4f1f-9d89-42a1c1db5702
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860
198340 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.860198340
Directory /workspace/1.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_invalid_op.1164631378
Short name T412
Test name
Test status
Simulation time 1695571500 ps
CPU time 69.06 seconds
Started Mar 26 01:23:22 PM PDT 24
Finished Mar 26 01:24:32 PM PDT 24
Peak memory 259696 kb
Host smart-3a01a322-b412-4bb1-843e-6e127d57f598
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164631378 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.1164631378
Directory /workspace/1.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_lcmgr_intg.956271505
Short name T900
Test name
Test status
Simulation time 46532700 ps
CPU time 13.43 seconds
Started Mar 26 01:23:30 PM PDT 24
Finished Mar 26 01:23:43 PM PDT 24
Peak memory 258768 kb
Host smart-498cb2cd-bc01-4247-83e8-17c87c1415a0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956271505 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_lcmgr_intg.956271505
Directory /workspace/1.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_mid_op_rst.3881173897
Short name T128
Test name
Test status
Simulation time 880785900 ps
CPU time 70.41 seconds
Started Mar 26 01:23:23 PM PDT 24
Finished Mar 26 01:24:34 PM PDT 24
Peak memory 259040 kb
Host smart-60f021b4-8979-4d22-a7c8-66d328f0290f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881173897 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.3881173897
Directory /workspace/1.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/1.flash_ctrl_mp_regions.654404255
Short name T117
Test name
Test status
Simulation time 40512705300 ps
CPU time 227.84 seconds
Started Mar 26 01:23:15 PM PDT 24
Finished Mar 26 01:27:03 PM PDT 24
Peak memory 273020 kb
Host smart-1f1b6e49-487d-4306-9396-39b87730c35f
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654404255 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_mp_regions.654404255
Directory /workspace/1.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/1.flash_ctrl_otp_reset.3354590308
Short name T335
Test name
Test status
Simulation time 180267800 ps
CPU time 131.89 seconds
Started Mar 26 01:23:14 PM PDT 24
Finished Mar 26 01:25:26 PM PDT 24
Peak memory 263620 kb
Host smart-8aa3ba25-6401-4aef-a58a-71a86e068181
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354590308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ot
p_reset.3354590308
Directory /workspace/1.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb.3389111287
Short name T1048
Test name
Test status
Simulation time 29377700 ps
CPU time 68.62 seconds
Started Mar 26 01:23:16 PM PDT 24
Finished Mar 26 01:24:25 PM PDT 24
Peak memory 261652 kb
Host smart-4fafb54f-734c-4d7e-bd54-1a9d19dbf269
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3389111287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.3389111287
Directory /workspace/1.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb_redun.468841096
Short name T74
Test name
Test status
Simulation time 923362000 ps
CPU time 27.42 seconds
Started Mar 26 01:23:35 PM PDT 24
Finished Mar 26 01:24:03 PM PDT 24
Peak memory 262304 kb
Host smart-c09a8634-8169-4918-a9a5-e48762281c9e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468841096 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.468841096
Directory /workspace/1.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_host_grant_err.2748737718
Short name T62
Test name
Test status
Simulation time 23183100 ps
CPU time 13.4 seconds
Started Mar 26 01:23:36 PM PDT 24
Finished Mar 26 01:23:50 PM PDT 24
Peak memory 264444 kb
Host smart-9f399401-b9db-44f8-826c-a0aa0d26dae0
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748737718 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.2748737718
Directory /workspace/1.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_prog_reset.1496840837
Short name T659
Test name
Test status
Simulation time 21022600 ps
CPU time 13.27 seconds
Started Mar 26 01:23:36 PM PDT 24
Finished Mar 26 01:23:50 PM PDT 24
Peak memory 264172 kb
Host smart-d2138327-0775-422e-bb0e-25f9edc7807d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496840837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_prog_res
et.1496840837
Directory /workspace/1.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_rand_ops.3531604251
Short name T846
Test name
Test status
Simulation time 182595200 ps
CPU time 1074.67 seconds
Started Mar 26 01:23:17 PM PDT 24
Finished Mar 26 01:41:12 PM PDT 24
Peak memory 282332 kb
Host smart-b3530844-2a22-41a1-8dfa-4639afae629c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531604251 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.3531604251
Directory /workspace/1.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_buff_evict.686086590
Short name T245
Test name
Test status
Simulation time 655705700 ps
CPU time 101.56 seconds
Started Mar 26 01:23:21 PM PDT 24
Finished Mar 26 01:25:03 PM PDT 24
Peak memory 264120 kb
Host smart-bc0edb74-4524-45cf-b848-695b452c68ff
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=686086590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.686086590
Directory /workspace/1.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_intg.518230229
Short name T356
Test name
Test status
Simulation time 62675300 ps
CPU time 31.91 seconds
Started Mar 26 01:23:26 PM PDT 24
Finished Mar 26 01:23:58 PM PDT 24
Peak memory 273624 kb
Host smart-313f818f-75df-4ab6-9daf-c558c440b49f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518230229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t
est +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.flash_ctrl_rd_intg.518230229
Directory /workspace/1.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_derr.914316997
Short name T1052
Test name
Test status
Simulation time 35867600 ps
CPU time 22.05 seconds
Started Mar 26 01:23:30 PM PDT 24
Finished Mar 26 01:23:52 PM PDT 24
Peak memory 264336 kb
Host smart-f19c62ed-c1c0-46f1-95f8-c1369cc83889
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914316997 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_derr.914316997
Directory /workspace/1.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_serr.3413423985
Short name T607
Test name
Test status
Simulation time 42684400 ps
CPU time 20.6 seconds
Started Mar 26 01:23:29 PM PDT 24
Finished Mar 26 01:23:50 PM PDT 24
Peak memory 264220 kb
Host smart-d36db81b-5735-44dc-8d96-39517a65890b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413423985 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fl
ash_ctrl_read_word_sweep_serr.3413423985
Directory /workspace/1.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rma_err.2254264326
Short name T154
Test name
Test status
Simulation time 59792094000 ps
CPU time 1084.29 seconds
Started Mar 26 01:23:28 PM PDT 24
Finished Mar 26 01:41:33 PM PDT 24
Peak memory 380820 kb
Host smart-df325211-6e26-4452-82b7-5b2b397334bf
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254264326 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rma_err.2254264326
Directory /workspace/1.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro.2198411148
Short name T766
Test name
Test status
Simulation time 582023900 ps
CPU time 110.27 seconds
Started Mar 26 01:23:31 PM PDT 24
Finished Mar 26 01:25:21 PM PDT 24
Peak memory 280176 kb
Host smart-4944a121-032d-4e1f-a605-badf62f79a92
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198411148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.flash_ctrl_ro.2198411148
Directory /workspace/1.flash_ctrl_ro/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw.2845686213
Short name T711
Test name
Test status
Simulation time 2416696100 ps
CPU time 365.67 seconds
Started Mar 26 01:23:26 PM PDT 24
Finished Mar 26 01:29:32 PM PDT 24
Peak memory 313352 kb
Host smart-4e964551-38b2-48d8-9d8d-67f8dccd07ae
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845686213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ct
rl_rw.2845686213
Directory /workspace/1.flash_ctrl_rw/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict.53292420
Short name T894
Test name
Test status
Simulation time 83946100 ps
CPU time 32.02 seconds
Started Mar 26 01:23:32 PM PDT 24
Finished Mar 26 01:24:04 PM PDT 24
Peak memory 272496 kb
Host smart-ad215ae6-ffba-4593-bfba-127fa44f64c3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53292420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash
_ctrl_rw_evict.53292420
Directory /workspace/1.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict_all_en.1879546153
Short name T420
Test name
Test status
Simulation time 219517200 ps
CPU time 37.56 seconds
Started Mar 26 01:23:33 PM PDT 24
Finished Mar 26 01:24:11 PM PDT 24
Peak memory 272564 kb
Host smart-b64c6271-2653-4ed8-90f7-be6eaec95a52
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879546153 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict_all_en.1879546153
Directory /workspace/1.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_serr.3624919530
Short name T775
Test name
Test status
Simulation time 6078024200 ps
CPU time 446.49 seconds
Started Mar 26 01:23:30 PM PDT 24
Finished Mar 26 01:30:57 PM PDT 24
Peak memory 319272 kb
Host smart-d059691e-9e74-4c23-ae63-2d38326a3c01
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624919530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_s
err.3624919530
Directory /workspace/1.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_cm.145511636
Short name T15
Test name
Test status
Simulation time 1034539500 ps
CPU time 4790.13 seconds
Started Mar 26 01:23:33 PM PDT 24
Finished Mar 26 02:43:24 PM PDT 24
Peak memory 282088 kb
Host smart-e341ba5e-ad56-4f06-a245-f37112fecc9a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145511636 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.145511636
Directory /workspace/1.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_info_access.3720294532
Short name T657
Test name
Test status
Simulation time 2484685000 ps
CPU time 60.5 seconds
Started Mar 26 01:23:36 PM PDT 24
Finished Mar 26 01:24:37 PM PDT 24
Peak memory 263128 kb
Host smart-dffb2ce4-d0d3-482c-ac0e-abd425c4e057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720294532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.3720294532
Directory /workspace/1.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_address.2951966658
Short name T39
Test name
Test status
Simulation time 1209553800 ps
CPU time 58.5 seconds
Started Mar 26 01:23:33 PM PDT 24
Finished Mar 26 01:24:32 PM PDT 24
Peak memory 264384 kb
Host smart-39cb5765-e36d-497b-8f89-0e7e9037ef87
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951966658 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_serr_address.2951966658
Directory /workspace/1.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke.3880024570
Short name T496
Test name
Test status
Simulation time 137975500 ps
CPU time 146.63 seconds
Started Mar 26 01:23:19 PM PDT 24
Finished Mar 26 01:25:45 PM PDT 24
Peak memory 277508 kb
Host smart-fbfd949e-713a-4abd-bd11-0a91b1d8a360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880024570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.3880024570
Directory /workspace/1.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke_hw.2527017644
Short name T668
Test name
Test status
Simulation time 45872700 ps
CPU time 25.75 seconds
Started Mar 26 01:23:21 PM PDT 24
Finished Mar 26 01:23:47 PM PDT 24
Peak memory 257876 kb
Host smart-f9da8994-287c-414c-9e70-82177746e580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527017644 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.2527017644
Directory /workspace/1.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/1.flash_ctrl_stress_all.1849085463
Short name T476
Test name
Test status
Simulation time 426880300 ps
CPU time 959.62 seconds
Started Mar 26 01:23:27 PM PDT 24
Finished Mar 26 01:39:27 PM PDT 24
Peak memory 284180 kb
Host smart-56005860-3a37-4e20-8a1a-a660d1b39017
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849085463 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stres
s_all.1849085463
Directory /workspace/1.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.flash_ctrl_sw_op.32808572
Short name T472
Test name
Test status
Simulation time 25106300 ps
CPU time 25.42 seconds
Started Mar 26 01:23:21 PM PDT 24
Finished Mar 26 01:23:47 PM PDT 24
Peak memory 260488 kb
Host smart-e61b9cc5-af23-4b5b-bad5-75a8ab7590c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32808572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.32808572
Directory /workspace/1.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_wo.1905973433
Short name T490
Test name
Test status
Simulation time 6972801400 ps
CPU time 151.18 seconds
Started Mar 26 01:23:28 PM PDT 24
Finished Mar 26 01:26:00 PM PDT 24
Peak memory 258724 kb
Host smart-2764c690-ae7f-473e-8d8e-ceb6b37b9ac3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905973433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.flash_ctrl_wo.1905973433
Directory /workspace/1.flash_ctrl_wo/latest

Test location /workspace/coverage/default/10.flash_ctrl_alert_test.3217414086
Short name T470
Test name
Test status
Simulation time 34567800 ps
CPU time 13.61 seconds
Started Mar 26 01:25:17 PM PDT 24
Finished Mar 26 01:25:31 PM PDT 24
Peak memory 264272 kb
Host smart-ff8c0837-1e16-49e8-a2a9-1552222210d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217414086 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.
3217414086
Directory /workspace/10.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.flash_ctrl_connect.3848432594
Short name T208
Test name
Test status
Simulation time 53587000 ps
CPU time 15.7 seconds
Started Mar 26 01:25:17 PM PDT 24
Finished Mar 26 01:25:33 PM PDT 24
Peak memory 275244 kb
Host smart-99949989-4845-4385-bd5e-dc1c2a9d1981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848432594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.3848432594
Directory /workspace/10.flash_ctrl_connect/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_read_seed_err.4154585183
Short name T612
Test name
Test status
Simulation time 28780000 ps
CPU time 13.36 seconds
Started Mar 26 01:25:18 PM PDT 24
Finished Mar 26 01:25:31 PM PDT 24
Peak memory 257316 kb
Host smart-581bc178-0868-4d02-8db4-dddae68eac26
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154585183 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_seed_err.4154585183
Directory /workspace/10.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_rma_reset.2536639990
Short name T144
Test name
Test status
Simulation time 80141456600 ps
CPU time 866.15 seconds
Started Mar 26 01:25:17 PM PDT 24
Finished Mar 26 01:39:44 PM PDT 24
Peak memory 262672 kb
Host smart-598ffbed-cdcc-4126-9912-bc43837c0dc3
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536639990 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.flash_ctrl_hw_rma_reset.2536639990
Directory /workspace/10.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_sec_otp.3357844687
Short name T708
Test name
Test status
Simulation time 21770642100 ps
CPU time 104.63 seconds
Started Mar 26 01:25:18 PM PDT 24
Finished Mar 26 01:27:03 PM PDT 24
Peak memory 261504 kb
Host smart-d00c6f7b-b4a3-4d28-a800-af77ac115347
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357844687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_
hw_sec_otp.3357844687
Directory /workspace/10.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd.2450913145
Short name T33
Test name
Test status
Simulation time 2116791600 ps
CPU time 157.12 seconds
Started Mar 26 01:25:17 PM PDT 24
Finished Mar 26 01:27:54 PM PDT 24
Peak memory 291732 kb
Host smart-07230761-258b-4bea-af63-d26d9b8927da
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450913145 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla
sh_ctrl_intr_rd.2450913145
Directory /workspace/10.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd_slow_flash.1921311313
Short name T355
Test name
Test status
Simulation time 10984244200 ps
CPU time 215.78 seconds
Started Mar 26 01:25:16 PM PDT 24
Finished Mar 26 01:28:52 PM PDT 24
Peak memory 291980 kb
Host smart-09fab587-4a6d-44b7-a85d-650442579920
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921311313 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd_slow_flash.1921311313
Directory /workspace/10.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/10.flash_ctrl_invalid_op.168935098
Short name T863
Test name
Test status
Simulation time 3906971000 ps
CPU time 90.99 seconds
Started Mar 26 01:25:16 PM PDT 24
Finished Mar 26 01:26:47 PM PDT 24
Peak memory 259984 kb
Host smart-345fe86c-be56-495b-9867-f28fdf348829
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168935098 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.168935098
Directory /workspace/10.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/10.flash_ctrl_mp_regions.1259784223
Short name T512
Test name
Test status
Simulation time 14332929700 ps
CPU time 134.6 seconds
Started Mar 26 01:25:26 PM PDT 24
Finished Mar 26 01:27:41 PM PDT 24
Peak memory 264292 kb
Host smart-290cdb8a-2d90-4d2b-8c2a-567551be3f3b
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259784223 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.flash_ctrl_mp_regions.1259784223
Directory /workspace/10.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/10.flash_ctrl_otp_reset.3342567324
Short name T709
Test name
Test status
Simulation time 38442800 ps
CPU time 128.15 seconds
Started Mar 26 01:25:19 PM PDT 24
Finished Mar 26 01:27:27 PM PDT 24
Peak memory 260292 kb
Host smart-af9b1cc7-1bf1-4089-bd7b-a497924d9f8b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342567324 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_o
tp_reset.3342567324
Directory /workspace/10.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_phy_arb.4088454443
Short name T193
Test name
Test status
Simulation time 958455700 ps
CPU time 482.5 seconds
Started Mar 26 01:25:17 PM PDT 24
Finished Mar 26 01:33:19 PM PDT 24
Peak memory 261560 kb
Host smart-170fdd5a-6717-4f83-ac9b-4e8fcdd418d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4088454443 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.4088454443
Directory /workspace/10.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/10.flash_ctrl_prog_reset.2012070545
Short name T545
Test name
Test status
Simulation time 18555700 ps
CPU time 13.32 seconds
Started Mar 26 01:25:16 PM PDT 24
Finished Mar 26 01:25:29 PM PDT 24
Peak memory 264128 kb
Host smart-ebedfbb0-d84b-49cb-9fcb-5e158c73d585
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012070545 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_prog_re
set.2012070545
Directory /workspace/10.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_rand_ops.1934164711
Short name T112
Test name
Test status
Simulation time 72744600 ps
CPU time 385.63 seconds
Started Mar 26 01:25:04 PM PDT 24
Finished Mar 26 01:31:30 PM PDT 24
Peak memory 280536 kb
Host smart-9a438bd4-2bd1-4e83-ba61-478700caf7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934164711 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.1934164711
Directory /workspace/10.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw.574248297
Short name T678
Test name
Test status
Simulation time 13426510000 ps
CPU time 503.64 seconds
Started Mar 26 01:25:17 PM PDT 24
Finished Mar 26 01:33:41 PM PDT 24
Peak memory 313380 kb
Host smart-69b453f1-6b90-436a-80a3-bb67888a3c1d
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574248297 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ct
rl_rw.574248297
Directory /workspace/10.flash_ctrl_rw/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict.605096791
Short name T968
Test name
Test status
Simulation time 184870200 ps
CPU time 32.93 seconds
Started Mar 26 01:25:21 PM PDT 24
Finished Mar 26 01:25:54 PM PDT 24
Peak memory 265340 kb
Host smart-ec8faae9-9083-4273-970c-d7c56461ae80
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605096791 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla
sh_ctrl_rw_evict.605096791
Directory /workspace/10.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict_all_en.1471828819
Short name T1016
Test name
Test status
Simulation time 48240900 ps
CPU time 30.52 seconds
Started Mar 26 01:25:17 PM PDT 24
Finished Mar 26 01:25:48 PM PDT 24
Peak memory 272624 kb
Host smart-550514b7-76f1-46e5-bd85-b202b5b7b676
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471828819 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict_all_en.1471828819
Directory /workspace/10.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/10.flash_ctrl_sec_info_access.2847065296
Short name T642
Test name
Test status
Simulation time 943369600 ps
CPU time 61.15 seconds
Started Mar 26 01:25:15 PM PDT 24
Finished Mar 26 01:26:17 PM PDT 24
Peak memory 262696 kb
Host smart-bcedeee7-1654-45b3-8f5b-6f4be4b58f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847065296 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.2847065296
Directory /workspace/10.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/10.flash_ctrl_smoke.3905791685
Short name T800
Test name
Test status
Simulation time 25477800 ps
CPU time 119.72 seconds
Started Mar 26 01:25:03 PM PDT 24
Finished Mar 26 01:27:03 PM PDT 24
Peak memory 276248 kb
Host smart-cac2a3ce-7d17-4712-99d6-6b1f7916a74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905791685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.3905791685
Directory /workspace/10.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/10.flash_ctrl_wo.3140618084
Short name T111
Test name
Test status
Simulation time 2112845400 ps
CPU time 148.41 seconds
Started Mar 26 01:25:17 PM PDT 24
Finished Mar 26 01:27:45 PM PDT 24
Peak memory 258432 kb
Host smart-fb3509aa-3114-47ea-84b1-ec87f0033e0a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140618084 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.flash_ctrl_wo.3140618084
Directory /workspace/10.flash_ctrl_wo/latest

Test location /workspace/coverage/default/11.flash_ctrl_alert_test.654273887
Short name T627
Test name
Test status
Simulation time 172705000 ps
CPU time 14.58 seconds
Started Mar 26 01:25:29 PM PDT 24
Finished Mar 26 01:25:44 PM PDT 24
Peak memory 257440 kb
Host smart-45ae038d-b4e8-4a3f-b480-81b9138c331f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654273887 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test.654273887
Directory /workspace/11.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.flash_ctrl_connect.492381384
Short name T561
Test name
Test status
Simulation time 58854400 ps
CPU time 13.23 seconds
Started Mar 26 01:25:27 PM PDT 24
Finished Mar 26 01:25:40 PM PDT 24
Peak memory 274832 kb
Host smart-ecf8617a-377f-4567-9f92-efe01981f9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492381384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.492381384
Directory /workspace/11.flash_ctrl_connect/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.276716645
Short name T1025
Test name
Test status
Simulation time 10018631900 ps
CPU time 92.29 seconds
Started Mar 26 01:25:28 PM PDT 24
Finished Mar 26 01:27:02 PM PDT 24
Peak memory 327628 kb
Host smart-25d370a4-4b3c-4a49-a7e3-36a6346bb765
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276716645 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.276716645
Directory /workspace/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.3096292865
Short name T299
Test name
Test status
Simulation time 49484600 ps
CPU time 13.22 seconds
Started Mar 26 01:25:27 PM PDT 24
Finished Mar 26 01:25:41 PM PDT 24
Peak memory 257580 kb
Host smart-5c53f70a-ba0b-4ca1-ac55-ed3403b56a10
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096292865 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.3096292865
Directory /workspace/11.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_sec_otp.829782027
Short name T522
Test name
Test status
Simulation time 918336300 ps
CPU time 44.37 seconds
Started Mar 26 01:25:18 PM PDT 24
Finished Mar 26 01:26:02 PM PDT 24
Peak memory 261764 kb
Host smart-e7521183-04e4-4a61-a07f-1f5811c68650
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829782027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_h
w_sec_otp.829782027
Directory /workspace/11.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/11.flash_ctrl_invalid_op.1072421269
Short name T844
Test name
Test status
Simulation time 1714328600 ps
CPU time 67.95 seconds
Started Mar 26 01:25:30 PM PDT 24
Finished Mar 26 01:26:39 PM PDT 24
Peak memory 262764 kb
Host smart-63b49705-6907-46ea-bce8-65cbb72a7c97
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072421269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.1
072421269
Directory /workspace/11.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/11.flash_ctrl_lcmgr_intg.3543021908
Short name T918
Test name
Test status
Simulation time 217188300 ps
CPU time 13.67 seconds
Started Mar 26 01:25:28 PM PDT 24
Finished Mar 26 01:25:42 PM PDT 24
Peak memory 264396 kb
Host smart-60f42500-6e7c-4141-84c8-5cb1088b283d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543021908 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.flash_ctrl_lcmgr_intg.3543021908
Directory /workspace/11.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/11.flash_ctrl_mp_regions.1815421780
Short name T91
Test name
Test status
Simulation time 16975968800 ps
CPU time 258.59 seconds
Started Mar 26 01:25:30 PM PDT 24
Finished Mar 26 01:29:49 PM PDT 24
Peak memory 271384 kb
Host smart-ec95d2fe-c235-4ac2-8ae0-058f7c0da143
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815421780 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.flash_ctrl_mp_regions.1815421780
Directory /workspace/11.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/11.flash_ctrl_phy_arb.154272740
Short name T832
Test name
Test status
Simulation time 395186300 ps
CPU time 108.81 seconds
Started Mar 26 01:25:16 PM PDT 24
Finished Mar 26 01:27:05 PM PDT 24
Peak memory 261632 kb
Host smart-b2b49994-a979-4f29-addf-6bc5e4e2a300
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=154272740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.154272740
Directory /workspace/11.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/11.flash_ctrl_prog_reset.4078625486
Short name T513
Test name
Test status
Simulation time 20132500 ps
CPU time 13.54 seconds
Started Mar 26 01:25:29 PM PDT 24
Finished Mar 26 01:25:43 PM PDT 24
Peak memory 264260 kb
Host smart-c202a849-c263-4382-bd8d-e263914ef460
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078625486 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_prog_re
set.4078625486
Directory /workspace/11.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_rand_ops.2607203090
Short name T43
Test name
Test status
Simulation time 819399800 ps
CPU time 993.2 seconds
Started Mar 26 01:25:21 PM PDT 24
Finished Mar 26 01:41:54 PM PDT 24
Peak memory 285400 kb
Host smart-be4c0b89-8c50-429d-9e4d-d7bd6aa2a083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607203090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.2607203090
Directory /workspace/11.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/11.flash_ctrl_re_evict.3977037201
Short name T962
Test name
Test status
Simulation time 121450500 ps
CPU time 36.07 seconds
Started Mar 26 01:25:27 PM PDT 24
Finished Mar 26 01:26:03 PM PDT 24
Peak memory 273656 kb
Host smart-db62bb09-902f-44a8-9161-0e715da6a3c5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977037201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl
ash_ctrl_re_evict.3977037201
Directory /workspace/11.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/11.flash_ctrl_ro.1285979327
Short name T218
Test name
Test status
Simulation time 3837722500 ps
CPU time 118.51 seconds
Started Mar 26 01:25:31 PM PDT 24
Finished Mar 26 01:27:29 PM PDT 24
Peak memory 279956 kb
Host smart-1c5f9c16-a379-4d70-ae8a-8e0d166a9988
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285979327 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.flash_ctrl_ro.1285979327
Directory /workspace/11.flash_ctrl_ro/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict.3513485960
Short name T951
Test name
Test status
Simulation time 115719900 ps
CPU time 30.65 seconds
Started Mar 26 01:25:31 PM PDT 24
Finished Mar 26 01:26:02 PM PDT 24
Peak memory 273592 kb
Host smart-e6cc4b00-9db8-4679-9ffd-b55af461739c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513485960 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl
ash_ctrl_rw_evict.3513485960
Directory /workspace/11.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.357722549
Short name T674
Test name
Test status
Simulation time 121977700 ps
CPU time 37.13 seconds
Started Mar 26 01:25:30 PM PDT 24
Finished Mar 26 01:26:08 PM PDT 24
Peak memory 272484 kb
Host smart-c3cf1d7e-ef6d-4728-b217-0ea1f887fd36
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357722549 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict_all_en.357722549
Directory /workspace/11.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/11.flash_ctrl_sec_info_access.3628519954
Short name T994
Test name
Test status
Simulation time 1740300000 ps
CPU time 55.66 seconds
Started Mar 26 01:25:28 PM PDT 24
Finished Mar 26 01:26:24 PM PDT 24
Peak memory 262056 kb
Host smart-117b8d31-4c4e-462c-8f3d-555186fe78a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628519954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.3628519954
Directory /workspace/11.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/11.flash_ctrl_smoke.2225256242
Short name T467
Test name
Test status
Simulation time 27672400 ps
CPU time 72.89 seconds
Started Mar 26 01:25:19 PM PDT 24
Finished Mar 26 01:26:32 PM PDT 24
Peak memory 274112 kb
Host smart-98bb3410-15b9-461b-8e7b-0640a5b412fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225256242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.2225256242
Directory /workspace/11.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/11.flash_ctrl_wo.1117899020
Short name T585
Test name
Test status
Simulation time 4689763500 ps
CPU time 203.17 seconds
Started Mar 26 01:25:30 PM PDT 24
Finished Mar 26 01:28:54 PM PDT 24
Peak memory 258612 kb
Host smart-92bb91bd-e579-4655-825f-255ef25cebf5
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117899020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.flash_ctrl_wo.1117899020
Directory /workspace/11.flash_ctrl_wo/latest

Test location /workspace/coverage/default/12.flash_ctrl_alert_test.1266864566
Short name T725
Test name
Test status
Simulation time 114535900 ps
CPU time 13.47 seconds
Started Mar 26 01:25:43 PM PDT 24
Finished Mar 26 01:25:57 PM PDT 24
Peak memory 257312 kb
Host smart-7a7f7d96-af7b-4868-8b22-c7827356f0bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266864566 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.
1266864566
Directory /workspace/12.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.flash_ctrl_connect.2748368396
Short name T969
Test name
Test status
Simulation time 17585600 ps
CPU time 15.5 seconds
Started Mar 26 01:25:45 PM PDT 24
Finished Mar 26 01:26:00 PM PDT 24
Peak memory 274880 kb
Host smart-5d6714ba-b545-4a93-a098-9e810162734c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748368396 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.2748368396
Directory /workspace/12.flash_ctrl_connect/latest

Test location /workspace/coverage/default/12.flash_ctrl_disable.320928995
Short name T242
Test name
Test status
Simulation time 56087300 ps
CPU time 21.5 seconds
Started Mar 26 01:25:35 PM PDT 24
Finished Mar 26 01:25:57 PM PDT 24
Peak memory 272536 kb
Host smart-d62b8573-30c1-4c8c-a489-2ab633b5c850
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320928995 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_disable.320928995
Directory /workspace/12.flash_ctrl_disable/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_read_seed_err.1246151323
Short name T680
Test name
Test status
Simulation time 26619900 ps
CPU time 13.32 seconds
Started Mar 26 01:25:45 PM PDT 24
Finished Mar 26 01:25:58 PM PDT 24
Peak memory 258560 kb
Host smart-62e0a75f-07c8-48ee-a85d-0a9f7adb1b33
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246151323 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_seed_err.1246151323
Directory /workspace/12.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_rma_reset.1192118229
Short name T155
Test name
Test status
Simulation time 40121584000 ps
CPU time 853.81 seconds
Started Mar 26 01:25:35 PM PDT 24
Finished Mar 26 01:39:49 PM PDT 24
Peak memory 262460 kb
Host smart-c47b5989-8433-4f75-8b50-856ee2630f8a
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192118229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.flash_ctrl_hw_rma_reset.1192118229
Directory /workspace/12.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_sec_otp.382387098
Short name T427
Test name
Test status
Simulation time 3370262200 ps
CPU time 101.26 seconds
Started Mar 26 01:25:27 PM PDT 24
Finished Mar 26 01:27:10 PM PDT 24
Peak memory 261480 kb
Host smart-d7396e61-3861-4ab3-955c-2e90c62a18af
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382387098 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_h
w_sec_otp.382387098
Directory /workspace/12.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/12.flash_ctrl_lcmgr_intg.1878203345
Short name T305
Test name
Test status
Simulation time 15898000 ps
CPU time 13.35 seconds
Started Mar 26 01:25:43 PM PDT 24
Finished Mar 26 01:25:57 PM PDT 24
Peak memory 259636 kb
Host smart-5b432e66-fb8d-498f-af9f-3aa665ca3f78
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878203345 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.flash_ctrl_lcmgr_intg.1878203345
Directory /workspace/12.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/12.flash_ctrl_otp_reset.3334025058
Short name T302
Test name
Test status
Simulation time 37575800 ps
CPU time 132.78 seconds
Started Mar 26 01:25:29 PM PDT 24
Finished Mar 26 01:27:43 PM PDT 24
Peak memory 263620 kb
Host smart-ad133fd3-8412-40ff-b787-2bdc08c1ba35
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334025058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_o
tp_reset.3334025058
Directory /workspace/12.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_phy_arb.3568645172
Short name T105
Test name
Test status
Simulation time 1395021200 ps
CPU time 395.14 seconds
Started Mar 26 01:25:29 PM PDT 24
Finished Mar 26 01:32:05 PM PDT 24
Peak memory 261372 kb
Host smart-57797091-6b88-47d0-857b-69a77d18909f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3568645172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.3568645172
Directory /workspace/12.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/12.flash_ctrl_prog_reset.3145805214
Short name T497
Test name
Test status
Simulation time 63667300 ps
CPU time 13.44 seconds
Started Mar 26 01:25:30 PM PDT 24
Finished Mar 26 01:25:44 PM PDT 24
Peak memory 264200 kb
Host smart-a2952c17-0fe0-487e-8713-cbd3a2045ec8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145805214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_prog_re
set.3145805214
Directory /workspace/12.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_rand_ops.2168493645
Short name T925
Test name
Test status
Simulation time 4220186100 ps
CPU time 588.52 seconds
Started Mar 26 01:25:30 PM PDT 24
Finished Mar 26 01:35:19 PM PDT 24
Peak memory 281952 kb
Host smart-845344a7-e89a-42f3-8b54-ef16964ac5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168493645 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.2168493645
Directory /workspace/12.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/12.flash_ctrl_ro.1779130962
Short name T1050
Test name
Test status
Simulation time 513449400 ps
CPU time 99.46 seconds
Started Mar 26 01:25:29 PM PDT 24
Finished Mar 26 01:27:09 PM PDT 24
Peak memory 280160 kb
Host smart-064ec1b0-df0c-4c97-9dff-c377302ac267
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779130962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.flash_ctrl_ro.1779130962
Directory /workspace/12.flash_ctrl_ro/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw.2339602726
Short name T628
Test name
Test status
Simulation time 2744747300 ps
CPU time 455.25 seconds
Started Mar 26 01:25:30 PM PDT 24
Finished Mar 26 01:33:06 PM PDT 24
Peak memory 313420 kb
Host smart-82ef6d7a-229b-455e-9ea6-34b9d9be1144
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339602726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_c
trl_rw.2339602726
Directory /workspace/12.flash_ctrl_rw/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict.277954558
Short name T622
Test name
Test status
Simulation time 54462100 ps
CPU time 30.91 seconds
Started Mar 26 01:25:35 PM PDT 24
Finished Mar 26 01:26:06 PM PDT 24
Peak memory 272628 kb
Host smart-6129baed-be37-45c2-8393-af3f07812806
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277954558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla
sh_ctrl_rw_evict.277954558
Directory /workspace/12.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict_all_en.3341594505
Short name T728
Test name
Test status
Simulation time 88987300 ps
CPU time 30.05 seconds
Started Mar 26 01:25:35 PM PDT 24
Finished Mar 26 01:26:05 PM PDT 24
Peak memory 272604 kb
Host smart-a9a95d08-7368-4844-a5f8-cf075e77a020
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341594505 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict_all_en.3341594505
Directory /workspace/12.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/12.flash_ctrl_smoke.2203761196
Short name T801
Test name
Test status
Simulation time 239199000 ps
CPU time 72.78 seconds
Started Mar 26 01:25:30 PM PDT 24
Finished Mar 26 01:26:44 PM PDT 24
Peak memory 273996 kb
Host smart-99e01864-44ad-4217-a45e-c9184da8a297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203761196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.2203761196
Directory /workspace/12.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/12.flash_ctrl_wo.3842847744
Short name T916
Test name
Test status
Simulation time 18996412000 ps
CPU time 185.65 seconds
Started Mar 26 01:25:35 PM PDT 24
Finished Mar 26 01:28:41 PM PDT 24
Peak memory 258640 kb
Host smart-2eea79d9-6ef9-4da0-b3fa-f3e37ed7a65c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842847744 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.flash_ctrl_wo.3842847744
Directory /workspace/12.flash_ctrl_wo/latest

Test location /workspace/coverage/default/13.flash_ctrl_alert_test.3622308790
Short name T882
Test name
Test status
Simulation time 379247100 ps
CPU time 13.81 seconds
Started Mar 26 01:25:59 PM PDT 24
Finished Mar 26 01:26:13 PM PDT 24
Peak memory 257376 kb
Host smart-ec820da8-991e-421c-87d7-192a63d397db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622308790 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test.
3622308790
Directory /workspace/13.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.flash_ctrl_connect.2815329771
Short name T1034
Test name
Test status
Simulation time 48408300 ps
CPU time 16.49 seconds
Started Mar 26 01:25:43 PM PDT 24
Finished Mar 26 01:25:59 PM PDT 24
Peak memory 275076 kb
Host smart-85cfa5bb-b0fb-43b0-af9c-7fb0f06a2d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815329771 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.2815329771
Directory /workspace/13.flash_ctrl_connect/latest

Test location /workspace/coverage/default/13.flash_ctrl_disable.1386110203
Short name T401
Test name
Test status
Simulation time 44527100 ps
CPU time 22.59 seconds
Started Mar 26 01:25:44 PM PDT 24
Finished Mar 26 01:26:07 PM PDT 24
Peak memory 272644 kb
Host smart-85381c9a-23c2-4c7a-8d5d-b1394f8162bb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386110203 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_disable.1386110203
Directory /workspace/13.flash_ctrl_disable/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_read_seed_err.1809902098
Short name T67
Test name
Test status
Simulation time 208885900 ps
CPU time 13.27 seconds
Started Mar 26 01:25:59 PM PDT 24
Finished Mar 26 01:26:12 PM PDT 24
Peak memory 258300 kb
Host smart-b02b9144-61da-4baa-b716-75719ee6c675
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809902098 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.1809902098
Directory /workspace/13.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_rma_reset.222487629
Short name T858
Test name
Test status
Simulation time 80141186200 ps
CPU time 803.41 seconds
Started Mar 26 01:25:42 PM PDT 24
Finished Mar 26 01:39:06 PM PDT 24
Peak memory 258604 kb
Host smart-9ba261d7-05ec-4053-b8b2-5b198e78a808
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222487629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.flash_ctrl_hw_rma_reset.222487629
Directory /workspace/13.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_sec_otp.2819122390
Short name T871
Test name
Test status
Simulation time 10464936800 ps
CPU time 160.99 seconds
Started Mar 26 01:25:44 PM PDT 24
Finished Mar 26 01:28:25 PM PDT 24
Peak memory 261716 kb
Host smart-d5206757-3972-458e-8862-9e87216d30da
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819122390 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_
hw_sec_otp.2819122390
Directory /workspace/13.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd_slow_flash.4053804642
Short name T713
Test name
Test status
Simulation time 33927658100 ps
CPU time 210.21 seconds
Started Mar 26 01:25:41 PM PDT 24
Finished Mar 26 01:29:11 PM PDT 24
Peak memory 288832 kb
Host smart-8ad37852-578f-4cf0-a7d3-f09a53da9812
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053804642 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd_slow_flash.4053804642
Directory /workspace/13.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/13.flash_ctrl_invalid_op.3319782081
Short name T493
Test name
Test status
Simulation time 1005577500 ps
CPU time 91.93 seconds
Started Mar 26 01:25:44 PM PDT 24
Finished Mar 26 01:27:16 PM PDT 24
Peak memory 259796 kb
Host smart-a782936f-9803-4d92-a1d9-9fa73429d258
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319782081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.3
319782081
Directory /workspace/13.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/13.flash_ctrl_mp_regions.2502936727
Short name T903
Test name
Test status
Simulation time 56329666800 ps
CPU time 358.09 seconds
Started Mar 26 01:25:42 PM PDT 24
Finished Mar 26 01:31:41 PM PDT 24
Peak memory 273084 kb
Host smart-b17323e6-dde2-44d6-b353-dd103ed18b9c
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502936727 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 13.flash_ctrl_mp_regions.2502936727
Directory /workspace/13.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/13.flash_ctrl_otp_reset.218590803
Short name T1017
Test name
Test status
Simulation time 74853100 ps
CPU time 110.98 seconds
Started Mar 26 01:25:43 PM PDT 24
Finished Mar 26 01:27:35 PM PDT 24
Peak memory 260168 kb
Host smart-993ea704-4c0c-407a-8c4f-3f0e633f7e9a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218590803 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_ot
p_reset.218590803
Directory /workspace/13.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_phy_arb.230660668
Short name T942
Test name
Test status
Simulation time 433595400 ps
CPU time 56.74 seconds
Started Mar 26 01:25:44 PM PDT 24
Finished Mar 26 01:26:41 PM PDT 24
Peak memory 264080 kb
Host smart-e75bc141-65d9-4266-8f45-cbef56ad9682
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=230660668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.230660668
Directory /workspace/13.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/13.flash_ctrl_prog_reset.3485791700
Short name T1028
Test name
Test status
Simulation time 108517500 ps
CPU time 14.25 seconds
Started Mar 26 01:25:44 PM PDT 24
Finished Mar 26 01:25:59 PM PDT 24
Peak memory 264224 kb
Host smart-a4a65ebf-0698-49b3-8e17-139108dec124
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485791700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_prog_re
set.3485791700
Directory /workspace/13.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_rand_ops.1403607606
Short name T553
Test name
Test status
Simulation time 8218263500 ps
CPU time 1239.17 seconds
Started Mar 26 01:25:45 PM PDT 24
Finished Mar 26 01:46:24 PM PDT 24
Peak memory 284796 kb
Host smart-6ccf8031-eb43-48fe-b9e3-4403b083ad11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403607606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.1403607606
Directory /workspace/13.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/13.flash_ctrl_re_evict.3344971870
Short name T322
Test name
Test status
Simulation time 146810800 ps
CPU time 38.25 seconds
Started Mar 26 01:25:45 PM PDT 24
Finished Mar 26 01:26:24 PM PDT 24
Peak memory 272504 kb
Host smart-66321318-3cdd-4b33-8857-5da68b359147
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344971870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl
ash_ctrl_re_evict.3344971870
Directory /workspace/13.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_ro.3876789044
Short name T986
Test name
Test status
Simulation time 714375500 ps
CPU time 107.72 seconds
Started Mar 26 01:25:42 PM PDT 24
Finished Mar 26 01:27:30 PM PDT 24
Peak memory 288320 kb
Host smart-8557e516-6fac-46f2-b601-71aa2533a6c7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876789044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.flash_ctrl_ro.3876789044
Directory /workspace/13.flash_ctrl_ro/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw.111379681
Short name T205
Test name
Test status
Simulation time 3642951000 ps
CPU time 494.84 seconds
Started Mar 26 01:25:43 PM PDT 24
Finished Mar 26 01:33:58 PM PDT 24
Peak memory 313248 kb
Host smart-8de398c4-dc2e-436b-bb99-41789547c574
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111379681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ct
rl_rw.111379681
Directory /workspace/13.flash_ctrl_rw/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict.1620542487
Short name T229
Test name
Test status
Simulation time 34489800 ps
CPU time 28.19 seconds
Started Mar 26 01:25:49 PM PDT 24
Finished Mar 26 01:26:17 PM PDT 24
Peak memory 273688 kb
Host smart-2a2904ef-1d2c-40e3-b785-12e20c48e5ec
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620542487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl
ash_ctrl_rw_evict.1620542487
Directory /workspace/13.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict_all_en.1175574006
Short name T52
Test name
Test status
Simulation time 41833100 ps
CPU time 32.05 seconds
Started Mar 26 01:25:43 PM PDT 24
Finished Mar 26 01:26:15 PM PDT 24
Peak memory 272528 kb
Host smart-4f99e144-8849-4cd8-948b-fe468c6facca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175574006 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict_all_en.1175574006
Directory /workspace/13.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/13.flash_ctrl_sec_info_access.2164775428
Short name T562
Test name
Test status
Simulation time 5293926500 ps
CPU time 97.75 seconds
Started Mar 26 01:25:42 PM PDT 24
Finished Mar 26 01:27:20 PM PDT 24
Peak memory 261836 kb
Host smart-6cfcd5fa-d154-4b20-9685-d41c2274cfaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164775428 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.2164775428
Directory /workspace/13.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/13.flash_ctrl_smoke.3732755500
Short name T499
Test name
Test status
Simulation time 40287200 ps
CPU time 211.74 seconds
Started Mar 26 01:26:05 PM PDT 24
Finished Mar 26 01:29:37 PM PDT 24
Peak memory 277516 kb
Host smart-83a21ee1-fadc-429d-b067-c8f2f999f44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732755500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.3732755500
Directory /workspace/13.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/13.flash_ctrl_wo.3072040713
Short name T474
Test name
Test status
Simulation time 6405906600 ps
CPU time 131.46 seconds
Started Mar 26 01:25:43 PM PDT 24
Finished Mar 26 01:27:54 PM PDT 24
Peak memory 264228 kb
Host smart-03db3fc9-2147-4e69-bb8f-6b5c1a7be0df
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072040713 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.flash_ctrl_wo.3072040713
Directory /workspace/13.flash_ctrl_wo/latest

Test location /workspace/coverage/default/14.flash_ctrl_alert_test.2118058931
Short name T717
Test name
Test status
Simulation time 103702300 ps
CPU time 13.52 seconds
Started Mar 26 01:26:18 PM PDT 24
Finished Mar 26 01:26:32 PM PDT 24
Peak memory 257272 kb
Host smart-caa9e7c0-a08a-43bf-b71f-daccdaed0666
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118058931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test.
2118058931
Directory /workspace/14.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.flash_ctrl_connect.2962196443
Short name T432
Test name
Test status
Simulation time 27131400 ps
CPU time 15.68 seconds
Started Mar 26 01:25:59 PM PDT 24
Finished Mar 26 01:26:15 PM PDT 24
Peak memory 274468 kb
Host smart-eb0f44ec-4dab-46cc-a713-bc5890bbf8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962196443 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.2962196443
Directory /workspace/14.flash_ctrl_connect/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.3394558521
Short name T244
Test name
Test status
Simulation time 10012671200 ps
CPU time 121.51 seconds
Started Mar 26 01:25:58 PM PDT 24
Finished Mar 26 01:28:01 PM PDT 24
Peak memory 329788 kb
Host smart-66a96b69-c146-4f2d-a9f7-7884daa63b1f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394558521 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.3394558521
Directory /workspace/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_read_seed_err.3261132233
Short name T648
Test name
Test status
Simulation time 16110100 ps
CPU time 13.37 seconds
Started Mar 26 01:25:55 PM PDT 24
Finished Mar 26 01:26:09 PM PDT 24
Peak memory 264528 kb
Host smart-4d115980-b11f-443a-b1a6-fca188d691d7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261132233 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_read_seed_err.3261132233
Directory /workspace/14.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_rma_reset.1034225133
Short name T143
Test name
Test status
Simulation time 80149307000 ps
CPU time 935.19 seconds
Started Mar 26 01:26:00 PM PDT 24
Finished Mar 26 01:41:35 PM PDT 24
Peak memory 262280 kb
Host smart-c21538db-dffb-4ecd-85eb-93d73946e4bb
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034225133 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.flash_ctrl_hw_rma_reset.1034225133
Directory /workspace/14.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_sec_otp.1744320276
Short name T797
Test name
Test status
Simulation time 3294729400 ps
CPU time 242.59 seconds
Started Mar 26 01:25:58 PM PDT 24
Finished Mar 26 01:30:00 PM PDT 24
Peak memory 261692 kb
Host smart-042c210f-b659-4649-9d62-da53faa8fda9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744320276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_
hw_sec_otp.1744320276
Directory /workspace/14.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.1772544407
Short name T37
Test name
Test status
Simulation time 9149505500 ps
CPU time 210.26 seconds
Started Mar 26 01:26:00 PM PDT 24
Finished Mar 26 01:29:30 PM PDT 24
Peak memory 283900 kb
Host smart-e80c76cd-dd11-470e-a3bd-e89a0b7cdae6
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772544407 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd_slow_flash.1772544407
Directory /workspace/14.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/14.flash_ctrl_invalid_op.1652550570
Short name T982
Test name
Test status
Simulation time 1975537200 ps
CPU time 88.61 seconds
Started Mar 26 01:26:00 PM PDT 24
Finished Mar 26 01:27:29 PM PDT 24
Peak memory 259868 kb
Host smart-ad64d902-2a7b-4f33-8ce0-70aaf6f54909
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652550570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.1
652550570
Directory /workspace/14.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/14.flash_ctrl_lcmgr_intg.3949383805
Short name T845
Test name
Test status
Simulation time 25731000 ps
CPU time 13.9 seconds
Started Mar 26 01:25:57 PM PDT 24
Finished Mar 26 01:26:11 PM PDT 24
Peak memory 264428 kb
Host smart-a0fe6430-5b73-49f0-bf92-fa8983b234f8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949383805 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.flash_ctrl_lcmgr_intg.3949383805
Directory /workspace/14.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/14.flash_ctrl_mp_regions.823153927
Short name T809
Test name
Test status
Simulation time 23065912200 ps
CPU time 861.01 seconds
Started Mar 26 01:25:59 PM PDT 24
Finished Mar 26 01:40:20 PM PDT 24
Peak memory 273404 kb
Host smart-c2b7a407-6004-4d34-a463-05b32f115f84
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823153927 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 14.flash_ctrl_mp_regions.823153927
Directory /workspace/14.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/14.flash_ctrl_otp_reset.2458258630
Short name T453
Test name
Test status
Simulation time 36454900 ps
CPU time 128.75 seconds
Started Mar 26 01:25:59 PM PDT 24
Finished Mar 26 01:28:08 PM PDT 24
Peak memory 260292 kb
Host smart-8614cd4e-199b-4271-9c18-502fa606476b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458258630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_o
tp_reset.2458258630
Directory /workspace/14.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_phy_arb.2310647253
Short name T194
Test name
Test status
Simulation time 2018758300 ps
CPU time 425.34 seconds
Started Mar 26 01:25:58 PM PDT 24
Finished Mar 26 01:33:03 PM PDT 24
Peak memory 261416 kb
Host smart-119bc990-e647-4e73-beab-38ac1f3f36f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2310647253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.2310647253
Directory /workspace/14.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/14.flash_ctrl_prog_reset.4099289842
Short name T395
Test name
Test status
Simulation time 52547000 ps
CPU time 13.43 seconds
Started Mar 26 01:25:56 PM PDT 24
Finished Mar 26 01:26:10 PM PDT 24
Peak memory 264252 kb
Host smart-df903183-9c7b-4bf2-b28f-96bb20aaf104
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099289842 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_prog_re
set.4099289842
Directory /workspace/14.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_re_evict.65629316
Short name T222
Test name
Test status
Simulation time 138066400 ps
CPU time 39.36 seconds
Started Mar 26 01:25:55 PM PDT 24
Finished Mar 26 01:26:35 PM PDT 24
Peak memory 265308 kb
Host smart-ea50bdb1-d6cf-4e8a-a50a-95a0f46c7727
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65629316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flas
h_ctrl_re_evict.65629316
Directory /workspace/14.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_ro.1447648770
Short name T196
Test name
Test status
Simulation time 1778268600 ps
CPU time 104.92 seconds
Started Mar 26 01:26:01 PM PDT 24
Finished Mar 26 01:27:46 PM PDT 24
Peak memory 288328 kb
Host smart-b9f274a5-fc32-45c4-ad81-398460fc6310
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447648770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.flash_ctrl_ro.1447648770
Directory /workspace/14.flash_ctrl_ro/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw.3985488146
Short name T841
Test name
Test status
Simulation time 15673846200 ps
CPU time 492.11 seconds
Started Mar 26 01:25:55 PM PDT 24
Finished Mar 26 01:34:07 PM PDT 24
Peak memory 308576 kb
Host smart-f2fd3d22-fcc8-426d-b65c-3e6f7a6af24a
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985488146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_c
trl_rw.3985488146
Directory /workspace/14.flash_ctrl_rw/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict.2529802989
Short name T790
Test name
Test status
Simulation time 30738200 ps
CPU time 30.76 seconds
Started Mar 26 01:25:57 PM PDT 24
Finished Mar 26 01:26:28 PM PDT 24
Peak memory 273596 kb
Host smart-4e7f3fc4-dd15-4a9a-9fc7-1c791f7f15a8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529802989 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_rw_evict.2529802989
Directory /workspace/14.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict_all_en.96717496
Short name T294
Test name
Test status
Simulation time 27797600 ps
CPU time 29.78 seconds
Started Mar 26 01:25:58 PM PDT 24
Finished Mar 26 01:26:28 PM PDT 24
Peak memory 272520 kb
Host smart-293b93f0-2af0-4849-abc5-83927f02ec8d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96717496 -assert nopostproc +UVM_TESTNAME=fl
ash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 14.flash_ctrl_rw_evict_all_en.96717496
Directory /workspace/14.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/14.flash_ctrl_sec_info_access.3916859531
Short name T383
Test name
Test status
Simulation time 1672954800 ps
CPU time 71.59 seconds
Started Mar 26 01:26:01 PM PDT 24
Finished Mar 26 01:27:12 PM PDT 24
Peak memory 262352 kb
Host smart-5f991df9-fcda-43e9-95e6-5771ca54166d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916859531 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.3916859531
Directory /workspace/14.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/14.flash_ctrl_smoke.3883528538
Short name T501
Test name
Test status
Simulation time 61363100 ps
CPU time 190.83 seconds
Started Mar 26 01:25:56 PM PDT 24
Finished Mar 26 01:29:07 PM PDT 24
Peak memory 280296 kb
Host smart-46264c51-82f5-40ea-bece-fa4b9f70a5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883528538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.3883528538
Directory /workspace/14.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/14.flash_ctrl_wo.1394762190
Short name T478
Test name
Test status
Simulation time 3541138700 ps
CPU time 182.62 seconds
Started Mar 26 01:25:55 PM PDT 24
Finished Mar 26 01:28:58 PM PDT 24
Peak memory 258180 kb
Host smart-1dc0b88c-ae12-483a-a968-670e257ba14a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394762190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 14.flash_ctrl_wo.1394762190
Directory /workspace/14.flash_ctrl_wo/latest

Test location /workspace/coverage/default/15.flash_ctrl_alert_test.3135245983
Short name T567
Test name
Test status
Simulation time 37204700 ps
CPU time 13.38 seconds
Started Mar 26 01:26:17 PM PDT 24
Finished Mar 26 01:26:30 PM PDT 24
Peak memory 257464 kb
Host smart-4dd4240e-1bf4-4046-baae-80b2ccd777d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135245983 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test.
3135245983
Directory /workspace/15.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.flash_ctrl_connect.819654026
Short name T855
Test name
Test status
Simulation time 127075900 ps
CPU time 15.76 seconds
Started Mar 26 01:26:17 PM PDT 24
Finished Mar 26 01:26:32 PM PDT 24
Peak memory 275116 kb
Host smart-a29b79b9-c4c7-47be-b668-e1cd3c53b1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819654026 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.819654026
Directory /workspace/15.flash_ctrl_connect/latest

Test location /workspace/coverage/default/15.flash_ctrl_disable.142097558
Short name T696
Test name
Test status
Simulation time 28624400 ps
CPU time 21.95 seconds
Started Mar 26 01:26:18 PM PDT 24
Finished Mar 26 01:26:40 PM PDT 24
Peak memory 272496 kb
Host smart-8a6e0177-3ff3-4fda-a514-b5e9515b7367
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142097558 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.flash_ctrl_disable.142097558
Directory /workspace/15.flash_ctrl_disable/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.1058851265
Short name T170
Test name
Test status
Simulation time 10032809800 ps
CPU time 60.42 seconds
Started Mar 26 01:26:16 PM PDT 24
Finished Mar 26 01:27:17 PM PDT 24
Peak memory 270892 kb
Host smart-5a30f585-ea72-44db-acb2-1dff17fe57ca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058851265 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.1058851265
Directory /workspace/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.3400861811
Short name T300
Test name
Test status
Simulation time 15999200 ps
CPU time 13.19 seconds
Started Mar 26 01:26:16 PM PDT 24
Finished Mar 26 01:26:29 PM PDT 24
Peak memory 257520 kb
Host smart-104f10aa-6bac-4ddd-951c-a40309ea1965
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400861811 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_read_seed_err.3400861811
Directory /workspace/15.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_sec_otp.240264275
Short name T7
Test name
Test status
Simulation time 2353459800 ps
CPU time 44.79 seconds
Started Mar 26 01:25:56 PM PDT 24
Finished Mar 26 01:26:41 PM PDT 24
Peak memory 261756 kb
Host smart-c068dbcf-f4b0-4314-9095-aa91635ac714
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240264275 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_h
w_sec_otp.240264275
Directory /workspace/15.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd_slow_flash.2762403708
Short name T704
Test name
Test status
Simulation time 62398458000 ps
CPU time 197.5 seconds
Started Mar 26 01:26:16 PM PDT 24
Finished Mar 26 01:29:34 PM PDT 24
Peak memory 283628 kb
Host smart-0fce5986-b989-4c17-8d8c-1e35370d8fa5
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762403708 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd_slow_flash.2762403708
Directory /workspace/15.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/15.flash_ctrl_lcmgr_intg.3034890080
Short name T600
Test name
Test status
Simulation time 48112300 ps
CPU time 13.62 seconds
Started Mar 26 01:26:16 PM PDT 24
Finished Mar 26 01:26:29 PM PDT 24
Peak memory 259716 kb
Host smart-7d869b35-fcd7-45fd-ab9e-15b2567e35b5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034890080 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.flash_ctrl_lcmgr_intg.3034890080
Directory /workspace/15.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/15.flash_ctrl_mp_regions.1943629363
Short name T95
Test name
Test status
Simulation time 11755020500 ps
CPU time 794.03 seconds
Started Mar 26 01:25:57 PM PDT 24
Finished Mar 26 01:39:12 PM PDT 24
Peak memory 273604 kb
Host smart-fb9b3785-e1fc-4750-9966-30148c10ac1a
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943629363 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.flash_ctrl_mp_regions.1943629363
Directory /workspace/15.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/15.flash_ctrl_otp_reset.403547560
Short name T1013
Test name
Test status
Simulation time 47614500 ps
CPU time 108.64 seconds
Started Mar 26 01:26:00 PM PDT 24
Finished Mar 26 01:27:49 PM PDT 24
Peak memory 259016 kb
Host smart-b92103b0-1aa5-4b18-8b51-a102e7ecd7e8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403547560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_ot
p_reset.403547560
Directory /workspace/15.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_phy_arb.2047188165
Short name T504
Test name
Test status
Simulation time 13488101400 ps
CPU time 666.85 seconds
Started Mar 26 01:25:56 PM PDT 24
Finished Mar 26 01:37:03 PM PDT 24
Peak memory 261420 kb
Host smart-eebf0fb9-d94d-454a-8e00-254dd5964c75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2047188165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.2047188165
Directory /workspace/15.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/15.flash_ctrl_prog_reset.347990248
Short name T165
Test name
Test status
Simulation time 25469000 ps
CPU time 13.88 seconds
Started Mar 26 01:26:13 PM PDT 24
Finished Mar 26 01:26:27 PM PDT 24
Peak memory 259392 kb
Host smart-b4b0fa16-c5d3-49d4-b1c6-8fc47a7eb04f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347990248 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_prog_res
et.347990248
Directory /workspace/15.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_rand_ops.3590050744
Short name T122
Test name
Test status
Simulation time 1654537600 ps
CPU time 898.78 seconds
Started Mar 26 01:26:00 PM PDT 24
Finished Mar 26 01:40:59 PM PDT 24
Peak memory 285632 kb
Host smart-09ff7b2c-11f7-47be-8c04-bc65f36f9b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590050744 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.3590050744
Directory /workspace/15.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/15.flash_ctrl_re_evict.849160283
Short name T981
Test name
Test status
Simulation time 719115200 ps
CPU time 38.95 seconds
Started Mar 26 01:26:16 PM PDT 24
Finished Mar 26 01:26:55 PM PDT 24
Peak memory 273560 kb
Host smart-efe0266b-650d-47f9-bb13-876978f66efc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849160283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla
sh_ctrl_re_evict.849160283
Directory /workspace/15.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_ro.2303007630
Short name T1032
Test name
Test status
Simulation time 917935500 ps
CPU time 87.11 seconds
Started Mar 26 01:26:01 PM PDT 24
Finished Mar 26 01:27:28 PM PDT 24
Peak memory 280052 kb
Host smart-1757110b-5dcb-49a5-9763-ea160d5b1846
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303007630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.flash_ctrl_ro.2303007630
Directory /workspace/15.flash_ctrl_ro/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw.3180600998
Short name T198
Test name
Test status
Simulation time 1140828800 ps
CPU time 402.47 seconds
Started Mar 26 01:25:57 PM PDT 24
Finished Mar 26 01:32:40 PM PDT 24
Peak memory 317712 kb
Host smart-1703e960-94fb-449f-868b-0974c442b99a
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180600998 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_c
trl_rw.3180600998
Directory /workspace/15.flash_ctrl_rw/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict.299072000
Short name T905
Test name
Test status
Simulation time 76949300 ps
CPU time 30.89 seconds
Started Mar 26 01:26:17 PM PDT 24
Finished Mar 26 01:26:48 PM PDT 24
Peak memory 272152 kb
Host smart-a68ce17f-e4af-4013-a3ac-ea0c1173c9f3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299072000 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla
sh_ctrl_rw_evict.299072000
Directory /workspace/15.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.1250453556
Short name T927
Test name
Test status
Simulation time 33989400 ps
CPU time 31.53 seconds
Started Mar 26 01:26:16 PM PDT 24
Finished Mar 26 01:26:48 PM PDT 24
Peak memory 272524 kb
Host smart-1445ebb4-03fe-474c-bb60-2a09ea5b29af
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250453556 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict_all_en.1250453556
Directory /workspace/15.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/15.flash_ctrl_sec_info_access.3160116492
Short name T933
Test name
Test status
Simulation time 11582189800 ps
CPU time 78.25 seconds
Started Mar 26 01:26:16 PM PDT 24
Finished Mar 26 01:27:34 PM PDT 24
Peak memory 261724 kb
Host smart-87e1e9d3-8a5f-4f98-9548-2ec8df523da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160116492 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.3160116492
Directory /workspace/15.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/15.flash_ctrl_smoke.2794979746
Short name T827
Test name
Test status
Simulation time 37438700 ps
CPU time 99.84 seconds
Started Mar 26 01:25:56 PM PDT 24
Finished Mar 26 01:27:36 PM PDT 24
Peak memory 274228 kb
Host smart-b83e7169-7cb5-483e-a9cb-d10a08ac827d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794979746 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.2794979746
Directory /workspace/15.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/15.flash_ctrl_wo.172440045
Short name T939
Test name
Test status
Simulation time 11695431100 ps
CPU time 142.44 seconds
Started Mar 26 01:26:00 PM PDT 24
Finished Mar 26 01:28:23 PM PDT 24
Peak memory 257824 kb
Host smart-d0c3ecb3-499c-4f65-b32c-d95fcae7d297
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172440045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.flash_ctrl_wo.172440045
Directory /workspace/15.flash_ctrl_wo/latest

Test location /workspace/coverage/default/16.flash_ctrl_alert_test.3375665520
Short name T935
Test name
Test status
Simulation time 56717000 ps
CPU time 13.3 seconds
Started Mar 26 01:26:27 PM PDT 24
Finished Mar 26 01:26:41 PM PDT 24
Peak memory 257420 kb
Host smart-38030dc9-3f2b-4fc8-93f1-0c6d44be2e29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375665520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.
3375665520
Directory /workspace/16.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.flash_ctrl_connect.2957837649
Short name T189
Test name
Test status
Simulation time 23302300 ps
CPU time 16.02 seconds
Started Mar 26 01:26:15 PM PDT 24
Finished Mar 26 01:26:32 PM PDT 24
Peak memory 274832 kb
Host smart-f22eff34-a0ba-4cc4-a678-af4ceae0ebde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957837649 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.2957837649
Directory /workspace/16.flash_ctrl_connect/latest

Test location /workspace/coverage/default/16.flash_ctrl_disable.2086287563
Short name T180
Test name
Test status
Simulation time 23624800 ps
CPU time 20.36 seconds
Started Mar 26 01:26:16 PM PDT 24
Finished Mar 26 01:26:36 PM PDT 24
Peak memory 272552 kb
Host smart-9292e576-c8db-4a54-bc6c-16d895a1846c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086287563 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_disable.2086287563
Directory /workspace/16.flash_ctrl_disable/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.1333157967
Short name T996
Test name
Test status
Simulation time 10011873600 ps
CPU time 328.26 seconds
Started Mar 26 01:26:25 PM PDT 24
Finished Mar 26 01:31:54 PM PDT 24
Peak memory 324340 kb
Host smart-86047ca9-4082-4de6-a561-06a8e44d229c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333157967 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.1333157967
Directory /workspace/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.84135797
Short name T357
Test name
Test status
Simulation time 97678600 ps
CPU time 13.39 seconds
Started Mar 26 01:26:27 PM PDT 24
Finished Mar 26 01:26:40 PM PDT 24
Peak memory 264156 kb
Host smart-87d8d41e-91d3-4465-b511-6988d96fc247
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84135797 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.84135797
Directory /workspace/16.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_rma_reset.240361031
Short name T757
Test name
Test status
Simulation time 80138684600 ps
CPU time 851.74 seconds
Started Mar 26 01:26:15 PM PDT 24
Finished Mar 26 01:40:27 PM PDT 24
Peak memory 262468 kb
Host smart-1a795fd3-86b5-4949-bf67-5c54efea048e
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240361031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.flash_ctrl_hw_rma_reset.240361031
Directory /workspace/16.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_sec_otp.2226291267
Short name T1033
Test name
Test status
Simulation time 20232412700 ps
CPU time 134.08 seconds
Started Mar 26 01:26:18 PM PDT 24
Finished Mar 26 01:28:32 PM PDT 24
Peak memory 261600 kb
Host smart-867f9121-c888-45ec-96ff-ed4aa376b2f2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226291267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_
hw_sec_otp.2226291267
Directory /workspace/16.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.508599494
Short name T354
Test name
Test status
Simulation time 17644327700 ps
CPU time 198.2 seconds
Started Mar 26 01:26:14 PM PDT 24
Finished Mar 26 01:29:33 PM PDT 24
Peak memory 288880 kb
Host smart-cff5013d-e017-4e06-830f-8509ec06aa67
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508599494 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd_slow_flash.508599494
Directory /workspace/16.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/16.flash_ctrl_invalid_op.2931029766
Short name T873
Test name
Test status
Simulation time 1581661200 ps
CPU time 91.43 seconds
Started Mar 26 01:26:14 PM PDT 24
Finished Mar 26 01:27:46 PM PDT 24
Peak memory 258928 kb
Host smart-4471dc33-fdc3-4244-8815-7cf466ccd459
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931029766 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.2
931029766
Directory /workspace/16.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/16.flash_ctrl_lcmgr_intg.65889379
Short name T786
Test name
Test status
Simulation time 16106900 ps
CPU time 13.51 seconds
Started Mar 26 01:26:14 PM PDT 24
Finished Mar 26 01:26:28 PM PDT 24
Peak memory 264352 kb
Host smart-5e91e8fd-97be-4546-8faf-abd9bf31cc31
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65889379 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 16.flash_ctrl_lcmgr_intg.65889379
Directory /workspace/16.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/16.flash_ctrl_mp_regions.1814939407
Short name T578
Test name
Test status
Simulation time 36166777400 ps
CPU time 194.57 seconds
Started Mar 26 01:26:16 PM PDT 24
Finished Mar 26 01:29:31 PM PDT 24
Peak memory 264504 kb
Host smart-83826c6f-d96a-476f-a3e2-70f79bc6c479
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814939407 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 16.flash_ctrl_mp_regions.1814939407
Directory /workspace/16.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/16.flash_ctrl_otp_reset.2709096832
Short name T701
Test name
Test status
Simulation time 126829800 ps
CPU time 109.26 seconds
Started Mar 26 01:26:14 PM PDT 24
Finished Mar 26 01:28:04 PM PDT 24
Peak memory 260144 kb
Host smart-86a3bf7f-8daa-4eb8-852d-f6c1e5df861b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709096832 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_o
tp_reset.2709096832
Directory /workspace/16.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_phy_arb.549047444
Short name T965
Test name
Test status
Simulation time 7849625100 ps
CPU time 611.17 seconds
Started Mar 26 01:26:14 PM PDT 24
Finished Mar 26 01:36:26 PM PDT 24
Peak memory 261608 kb
Host smart-61e0854d-c392-449e-96c5-28e194f275c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=549047444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.549047444
Directory /workspace/16.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/16.flash_ctrl_prog_reset.3999600404
Short name T507
Test name
Test status
Simulation time 260828700 ps
CPU time 13.52 seconds
Started Mar 26 01:26:14 PM PDT 24
Finished Mar 26 01:26:28 PM PDT 24
Peak memory 264184 kb
Host smart-49261c5e-96e1-4166-b934-e02da2e76959
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999600404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_prog_re
set.3999600404
Directory /workspace/16.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_rand_ops.2273806167
Short name T123
Test name
Test status
Simulation time 140905700 ps
CPU time 498.76 seconds
Started Mar 26 01:26:14 PM PDT 24
Finished Mar 26 01:34:33 PM PDT 24
Peak memory 280376 kb
Host smart-e00e2c50-66aa-436b-ba98-4ed6255d6f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273806167 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.2273806167
Directory /workspace/16.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/16.flash_ctrl_re_evict.471610281
Short name T394
Test name
Test status
Simulation time 286476400 ps
CPU time 39.64 seconds
Started Mar 26 01:26:15 PM PDT 24
Finished Mar 26 01:26:55 PM PDT 24
Peak memory 272432 kb
Host smart-f97122ad-f130-4c12-aec5-1c2734587b0d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471610281 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla
sh_ctrl_re_evict.471610281
Directory /workspace/16.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_ro.3677038498
Short name T408
Test name
Test status
Simulation time 913717200 ps
CPU time 121.06 seconds
Started Mar 26 01:26:15 PM PDT 24
Finished Mar 26 01:28:16 PM PDT 24
Peak memory 280104 kb
Host smart-f48bd6a6-29ab-47a5-8863-ae4d0d5bfd92
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677038498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.flash_ctrl_ro.3677038498
Directory /workspace/16.flash_ctrl_ro/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw.2854043044
Short name T204
Test name
Test status
Simulation time 7365887600 ps
CPU time 416.28 seconds
Started Mar 26 01:26:14 PM PDT 24
Finished Mar 26 01:33:11 PM PDT 24
Peak memory 317796 kb
Host smart-27d8a039-a72e-40a8-b5be-6acf770a65b2
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854043044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_c
trl_rw.2854043044
Directory /workspace/16.flash_ctrl_rw/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict.128020139
Short name T867
Test name
Test status
Simulation time 141845400 ps
CPU time 30.55 seconds
Started Mar 26 01:26:14 PM PDT 24
Finished Mar 26 01:26:45 PM PDT 24
Peak memory 272548 kb
Host smart-f982c965-456f-4174-b0a6-1245483f8de4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128020139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla
sh_ctrl_rw_evict.128020139
Directory /workspace/16.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict_all_en.1407271343
Short name T731
Test name
Test status
Simulation time 85367500 ps
CPU time 30.93 seconds
Started Mar 26 01:26:17 PM PDT 24
Finished Mar 26 01:26:48 PM PDT 24
Peak memory 273316 kb
Host smart-d9f177aa-264f-4949-8219-e62813432528
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407271343 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict_all_en.1407271343
Directory /workspace/16.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/16.flash_ctrl_sec_info_access.3955483907
Short name T463
Test name
Test status
Simulation time 673654600 ps
CPU time 65.99 seconds
Started Mar 26 01:26:15 PM PDT 24
Finished Mar 26 01:27:21 PM PDT 24
Peak memory 261436 kb
Host smart-7ecd58b0-e6a3-4119-bd3a-579116b56f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955483907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.3955483907
Directory /workspace/16.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/16.flash_ctrl_smoke.161248809
Short name T589
Test name
Test status
Simulation time 29236800 ps
CPU time 51.39 seconds
Started Mar 26 01:26:14 PM PDT 24
Finished Mar 26 01:27:06 PM PDT 24
Peak memory 269644 kb
Host smart-1d562a18-eaac-4b24-967c-0f2fa4030b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161248809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.161248809
Directory /workspace/16.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/16.flash_ctrl_wo.2427454744
Short name T109
Test name
Test status
Simulation time 5169573300 ps
CPU time 141.53 seconds
Started Mar 26 01:26:16 PM PDT 24
Finished Mar 26 01:28:38 PM PDT 24
Peak memory 258128 kb
Host smart-08fe35ea-55b5-490e-bf80-0037234be9d5
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427454744 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.flash_ctrl_wo.2427454744
Directory /workspace/16.flash_ctrl_wo/latest

Test location /workspace/coverage/default/17.flash_ctrl_alert_test.747459681
Short name T764
Test name
Test status
Simulation time 44407300 ps
CPU time 13.43 seconds
Started Mar 26 01:26:28 PM PDT 24
Finished Mar 26 01:26:42 PM PDT 24
Peak memory 257308 kb
Host smart-353865e3-0c85-4cfc-8164-c3e68c3e3fad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747459681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test.747459681
Directory /workspace/17.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.flash_ctrl_connect.323461859
Short name T735
Test name
Test status
Simulation time 42975800 ps
CPU time 15.82 seconds
Started Mar 26 01:26:29 PM PDT 24
Finished Mar 26 01:26:44 PM PDT 24
Peak memory 274832 kb
Host smart-f879009c-5577-4820-8018-8a3f9a79b4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323461859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.323461859
Directory /workspace/17.flash_ctrl_connect/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.501732300
Short name T743
Test name
Test status
Simulation time 10015854600 ps
CPU time 110.97 seconds
Started Mar 26 01:26:34 PM PDT 24
Finished Mar 26 01:28:25 PM PDT 24
Peak memory 350180 kb
Host smart-b1f481c0-ae80-4628-b0a3-29fb1241ce27
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501732300 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.501732300
Directory /workspace/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.1451506788
Short name T301
Test name
Test status
Simulation time 38653200 ps
CPU time 13.34 seconds
Started Mar 26 01:26:28 PM PDT 24
Finished Mar 26 01:26:41 PM PDT 24
Peak memory 257616 kb
Host smart-e63c2d32-f132-46d9-80d4-77e38a4e626a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451506788 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_read_seed_err.1451506788
Directory /workspace/17.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_rma_reset.1373831713
Short name T162
Test name
Test status
Simulation time 80142738500 ps
CPU time 843.99 seconds
Started Mar 26 01:26:30 PM PDT 24
Finished Mar 26 01:40:34 PM PDT 24
Peak memory 259012 kb
Host smart-e6577f59-681f-4793-91c1-9f92d719d8d9
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373831713 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.flash_ctrl_hw_rma_reset.1373831713
Directory /workspace/17.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.1465340319
Short name T1004
Test name
Test status
Simulation time 9843784300 ps
CPU time 217.13 seconds
Started Mar 26 01:26:27 PM PDT 24
Finished Mar 26 01:30:04 PM PDT 24
Peak memory 288892 kb
Host smart-6ab959aa-8ee0-4039-9f8b-947f2a1a9798
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465340319 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd_slow_flash.1465340319
Directory /workspace/17.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/17.flash_ctrl_invalid_op.4205860821
Short name T468
Test name
Test status
Simulation time 970944300 ps
CPU time 75.03 seconds
Started Mar 26 01:26:28 PM PDT 24
Finished Mar 26 01:27:43 PM PDT 24
Peak memory 259948 kb
Host smart-75373b38-9e93-4026-b64b-0a74456a785b
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205860821 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.4
205860821
Directory /workspace/17.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/17.flash_ctrl_lcmgr_intg.1443167093
Short name T136
Test name
Test status
Simulation time 45995700 ps
CPU time 13.25 seconds
Started Mar 26 01:26:29 PM PDT 24
Finished Mar 26 01:26:42 PM PDT 24
Peak memory 264216 kb
Host smart-650f73a3-fb4c-402a-a216-bd726cf0470a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443167093 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.flash_ctrl_lcmgr_intg.1443167093
Directory /workspace/17.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/17.flash_ctrl_mp_regions.3834862836
Short name T752
Test name
Test status
Simulation time 4220502300 ps
CPU time 292.96 seconds
Started Mar 26 01:26:32 PM PDT 24
Finished Mar 26 01:31:26 PM PDT 24
Peak memory 272248 kb
Host smart-4badde73-196f-4bc0-88a0-2e2c57dd25d7
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834862836 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 17.flash_ctrl_mp_regions.3834862836
Directory /workspace/17.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/17.flash_ctrl_otp_reset.3357414181
Short name T13
Test name
Test status
Simulation time 73602400 ps
CPU time 129.07 seconds
Started Mar 26 01:26:34 PM PDT 24
Finished Mar 26 01:28:43 PM PDT 24
Peak memory 260100 kb
Host smart-7d6d95e0-6751-4e50-b40c-fbdc3ffdab8d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357414181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_o
tp_reset.3357414181
Directory /workspace/17.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_phy_arb.3074912785
Short name T707
Test name
Test status
Simulation time 3096001600 ps
CPU time 329.69 seconds
Started Mar 26 01:26:28 PM PDT 24
Finished Mar 26 01:31:58 PM PDT 24
Peak memory 261620 kb
Host smart-b7ecb494-9c2b-4989-aa2e-0451197a4273
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3074912785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.3074912785
Directory /workspace/17.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/17.flash_ctrl_prog_reset.2857847600
Short name T733
Test name
Test status
Simulation time 153260400 ps
CPU time 13.87 seconds
Started Mar 26 01:26:30 PM PDT 24
Finished Mar 26 01:26:43 PM PDT 24
Peak memory 259356 kb
Host smart-392e2861-4f72-4aa8-89ae-49d83a7c7a9d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857847600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_prog_re
set.2857847600
Directory /workspace/17.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_rand_ops.151203601
Short name T1029
Test name
Test status
Simulation time 279148400 ps
CPU time 376.09 seconds
Started Mar 26 01:26:27 PM PDT 24
Finished Mar 26 01:32:44 PM PDT 24
Peak memory 282056 kb
Host smart-608a481c-2992-45bc-a822-8de353599043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151203601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.151203601
Directory /workspace/17.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/17.flash_ctrl_re_evict.1877677414
Short name T943
Test name
Test status
Simulation time 298241200 ps
CPU time 35.2 seconds
Started Mar 26 01:26:28 PM PDT 24
Finished Mar 26 01:27:04 PM PDT 24
Peak memory 273604 kb
Host smart-b398504a-9058-4597-8bef-bd58bd23e9e4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877677414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl
ash_ctrl_re_evict.1877677414
Directory /workspace/17.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_ro.3942176534
Short name T221
Test name
Test status
Simulation time 996317800 ps
CPU time 115.61 seconds
Started Mar 26 01:26:28 PM PDT 24
Finished Mar 26 01:28:23 PM PDT 24
Peak memory 280136 kb
Host smart-1cab2932-4e71-4fca-b070-660d02ade336
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942176534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.flash_ctrl_ro.3942176534
Directory /workspace/17.flash_ctrl_ro/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw.4285578080
Short name T630
Test name
Test status
Simulation time 3465593900 ps
CPU time 602.86 seconds
Started Mar 26 01:26:28 PM PDT 24
Finished Mar 26 01:36:31 PM PDT 24
Peak memory 313472 kb
Host smart-9cd6b02e-2a48-4c8b-b868-47d8da9e0f9f
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285578080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_c
trl_rw.4285578080
Directory /workspace/17.flash_ctrl_rw/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict.3427783565
Short name T230
Test name
Test status
Simulation time 36622100 ps
CPU time 30.76 seconds
Started Mar 26 01:26:27 PM PDT 24
Finished Mar 26 01:26:58 PM PDT 24
Peak memory 272632 kb
Host smart-321f3cae-86ce-44ab-9c09-5d5ad48ad8d9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427783565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl
ash_ctrl_rw_evict.3427783565
Directory /workspace/17.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict_all_en.230862206
Short name T296
Test name
Test status
Simulation time 39950800 ps
CPU time 30.77 seconds
Started Mar 26 01:26:29 PM PDT 24
Finished Mar 26 01:27:00 PM PDT 24
Peak memory 272556 kb
Host smart-0257a34f-7184-4075-aa94-3a8f97a917c2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230862206 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict_all_en.230862206
Directory /workspace/17.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/17.flash_ctrl_sec_info_access.3305014270
Short name T700
Test name
Test status
Simulation time 13056354900 ps
CPU time 81.07 seconds
Started Mar 26 01:26:29 PM PDT 24
Finished Mar 26 01:27:51 PM PDT 24
Peak memory 263692 kb
Host smart-f6dcb9bf-8fc2-453e-bdaa-ab7a860a3825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305014270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.3305014270
Directory /workspace/17.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/17.flash_ctrl_smoke.3637785954
Short name T758
Test name
Test status
Simulation time 24301700 ps
CPU time 99.21 seconds
Started Mar 26 01:26:28 PM PDT 24
Finished Mar 26 01:28:07 PM PDT 24
Peak memory 275532 kb
Host smart-39d27c41-67ba-491f-8197-9fb073d3eaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637785954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.3637785954
Directory /workspace/17.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/17.flash_ctrl_wo.2441511984
Short name T610
Test name
Test status
Simulation time 4573727100 ps
CPU time 194.11 seconds
Started Mar 26 01:26:32 PM PDT 24
Finished Mar 26 01:29:47 PM PDT 24
Peak memory 264276 kb
Host smart-99391bb5-d838-4884-9552-ae1e0f622a43
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441511984 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.flash_ctrl_wo.2441511984
Directory /workspace/17.flash_ctrl_wo/latest

Test location /workspace/coverage/default/18.flash_ctrl_alert_test.2826044469
Short name T518
Test name
Test status
Simulation time 47081300 ps
CPU time 13.66 seconds
Started Mar 26 01:26:41 PM PDT 24
Finished Mar 26 01:26:55 PM PDT 24
Peak memory 264248 kb
Host smart-df693d93-46d0-41f5-acd1-ce4b2382d919
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826044469 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test.
2826044469
Directory /workspace/18.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.flash_ctrl_connect.2640817083
Short name T260
Test name
Test status
Simulation time 17100500 ps
CPU time 15.7 seconds
Started Mar 26 01:26:39 PM PDT 24
Finished Mar 26 01:26:55 PM PDT 24
Peak memory 275260 kb
Host smart-c67fdca6-7242-4c21-bdcc-06021c0a8f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640817083 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.2640817083
Directory /workspace/18.flash_ctrl_connect/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.1206267053
Short name T124
Test name
Test status
Simulation time 10020345700 ps
CPU time 68.69 seconds
Started Mar 26 01:26:39 PM PDT 24
Finished Mar 26 01:27:48 PM PDT 24
Peak memory 292020 kb
Host smart-b501776b-f217-4695-be62-794c95812988
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206267053 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.1206267053
Directory /workspace/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.804166586
Short name T964
Test name
Test status
Simulation time 15414000 ps
CPU time 13.85 seconds
Started Mar 26 01:26:40 PM PDT 24
Finished Mar 26 01:26:54 PM PDT 24
Peak memory 258456 kb
Host smart-a01922d5-b52e-4f0e-88a0-847813efb775
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804166586 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_read_seed_err.804166586
Directory /workspace/18.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_sec_otp.2966292172
Short name T434
Test name
Test status
Simulation time 15049240200 ps
CPU time 137.95 seconds
Started Mar 26 01:26:28 PM PDT 24
Finished Mar 26 01:28:46 PM PDT 24
Peak memory 261484 kb
Host smart-69b5a336-c049-4728-9dfa-4674f9242f15
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966292172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_
hw_sec_otp.2966292172
Directory /workspace/18.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd_slow_flash.698480058
Short name T1008
Test name
Test status
Simulation time 16973318200 ps
CPU time 180.88 seconds
Started Mar 26 01:26:31 PM PDT 24
Finished Mar 26 01:29:33 PM PDT 24
Peak memory 289920 kb
Host smart-38d38312-28b5-4c35-8d8c-5fcc015db422
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698480058 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd_slow_flash.698480058
Directory /workspace/18.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/18.flash_ctrl_invalid_op.2605646865
Short name T950
Test name
Test status
Simulation time 3326454200 ps
CPU time 67.48 seconds
Started Mar 26 01:26:29 PM PDT 24
Finished Mar 26 01:27:37 PM PDT 24
Peak memory 262648 kb
Host smart-7ee89cfa-f659-4ca5-a236-dae93335e9fa
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605646865 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.2
605646865
Directory /workspace/18.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/18.flash_ctrl_lcmgr_intg.2997468403
Short name T134
Test name
Test status
Simulation time 45414600 ps
CPU time 13.46 seconds
Started Mar 26 01:26:39 PM PDT 24
Finished Mar 26 01:26:52 PM PDT 24
Peak memory 258860 kb
Host smart-a5faaded-be2f-4a61-8eb1-68b9cc82b67c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997468403 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.flash_ctrl_lcmgr_intg.2997468403
Directory /workspace/18.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/18.flash_ctrl_mp_regions.3230659650
Short name T118
Test name
Test status
Simulation time 87621699000 ps
CPU time 385.95 seconds
Started Mar 26 01:26:27 PM PDT 24
Finished Mar 26 01:32:53 PM PDT 24
Peak memory 272768 kb
Host smart-52037501-2eaa-496b-8c42-cfa2d76e8dfe
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230659650 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 18.flash_ctrl_mp_regions.3230659650
Directory /workspace/18.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/18.flash_ctrl_otp_reset.201336616
Short name T901
Test name
Test status
Simulation time 274972100 ps
CPU time 129.25 seconds
Started Mar 26 01:26:29 PM PDT 24
Finished Mar 26 01:28:39 PM PDT 24
Peak memory 258884 kb
Host smart-0fccb737-adbc-44b7-9551-7813fc0a489b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201336616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_ot
p_reset.201336616
Directory /workspace/18.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_phy_arb.1447773239
Short name T200
Test name
Test status
Simulation time 129039600 ps
CPU time 105.39 seconds
Started Mar 26 01:26:28 PM PDT 24
Finished Mar 26 01:28:14 PM PDT 24
Peak memory 260756 kb
Host smart-9bd803a7-06a0-4a1b-9472-f886d21460f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1447773239 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.1447773239
Directory /workspace/18.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/18.flash_ctrl_prog_reset.3766957107
Short name T960
Test name
Test status
Simulation time 18619300 ps
CPU time 13.36 seconds
Started Mar 26 01:26:28 PM PDT 24
Finished Mar 26 01:26:41 PM PDT 24
Peak memory 259180 kb
Host smart-bf9ef62a-94b4-47bc-b57a-feba9b8ab55d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766957107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_prog_re
set.3766957107
Directory /workspace/18.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_rand_ops.4218248853
Short name T718
Test name
Test status
Simulation time 765464700 ps
CPU time 887.85 seconds
Started Mar 26 01:26:30 PM PDT 24
Finished Mar 26 01:41:18 PM PDT 24
Peak memory 283340 kb
Host smart-e7da8f12-b5b9-4578-870b-d6f1dffbaac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218248853 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.4218248853
Directory /workspace/18.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/18.flash_ctrl_re_evict.307379957
Short name T769
Test name
Test status
Simulation time 473480400 ps
CPU time 38.51 seconds
Started Mar 26 01:26:37 PM PDT 24
Finished Mar 26 01:27:16 PM PDT 24
Peak memory 265368 kb
Host smart-ec3e7d09-307e-466b-b774-14902d0b88de
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307379957 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla
sh_ctrl_re_evict.307379957
Directory /workspace/18.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_ro.2368738761
Short name T792
Test name
Test status
Simulation time 376904000 ps
CPU time 88.84 seconds
Started Mar 26 01:26:34 PM PDT 24
Finished Mar 26 01:28:04 PM PDT 24
Peak memory 280440 kb
Host smart-5d81d121-f487-4169-98f1-c6aff85df9f4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368738761 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.flash_ctrl_ro.2368738761
Directory /workspace/18.flash_ctrl_ro/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw.3892642300
Short name T576
Test name
Test status
Simulation time 6832372900 ps
CPU time 432.34 seconds
Started Mar 26 01:26:30 PM PDT 24
Finished Mar 26 01:33:42 PM PDT 24
Peak memory 308600 kb
Host smart-2e8604c6-5a27-4224-b57d-6e5fdab0dcce
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892642300 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_c
trl_rw.3892642300
Directory /workspace/18.flash_ctrl_rw/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict.761375674
Short name T655
Test name
Test status
Simulation time 89121500 ps
CPU time 34.06 seconds
Started Mar 26 01:26:38 PM PDT 24
Finished Mar 26 01:27:12 PM PDT 24
Peak memory 272656 kb
Host smart-1808efd6-2538-4737-a024-1cccaeaaf794
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761375674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla
sh_ctrl_rw_evict.761375674
Directory /workspace/18.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict_all_en.2191876320
Short name T510
Test name
Test status
Simulation time 52406400 ps
CPU time 30.16 seconds
Started Mar 26 01:26:40 PM PDT 24
Finished Mar 26 01:27:11 PM PDT 24
Peak memory 268904 kb
Host smart-59e3a4ad-a353-4d07-ac8f-4632ed1883ee
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191876320 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict_all_en.2191876320
Directory /workspace/18.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/18.flash_ctrl_smoke.658847054
Short name T908
Test name
Test status
Simulation time 54115600 ps
CPU time 72.93 seconds
Started Mar 26 01:26:28 PM PDT 24
Finished Mar 26 01:27:41 PM PDT 24
Peak memory 274136 kb
Host smart-51e2c56e-e815-46fe-99ab-026ab577653e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658847054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.658847054
Directory /workspace/18.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/18.flash_ctrl_wo.1473023917
Short name T928
Test name
Test status
Simulation time 3646091600 ps
CPU time 150.65 seconds
Started Mar 26 01:26:34 PM PDT 24
Finished Mar 26 01:29:04 PM PDT 24
Peak memory 258848 kb
Host smart-a888ec59-abba-41ca-9702-563b18fe87c8
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473023917 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.flash_ctrl_wo.1473023917
Directory /workspace/18.flash_ctrl_wo/latest

Test location /workspace/coverage/default/19.flash_ctrl_alert_test.2864941059
Short name T597
Test name
Test status
Simulation time 142938700 ps
CPU time 13.57 seconds
Started Mar 26 01:26:50 PM PDT 24
Finished Mar 26 01:27:04 PM PDT 24
Peak memory 257336 kb
Host smart-4c32c93f-90c7-4892-9b27-ab931d4f405c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864941059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test.
2864941059
Directory /workspace/19.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.flash_ctrl_connect.2022297300
Short name T772
Test name
Test status
Simulation time 25159300 ps
CPU time 15.56 seconds
Started Mar 26 01:26:54 PM PDT 24
Finished Mar 26 01:27:10 PM PDT 24
Peak memory 275068 kb
Host smart-66f5a49b-7571-4e13-b492-34d6ece902fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022297300 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.2022297300
Directory /workspace/19.flash_ctrl_connect/latest

Test location /workspace/coverage/default/19.flash_ctrl_disable.336250080
Short name T397
Test name
Test status
Simulation time 12457200 ps
CPU time 21.85 seconds
Started Mar 26 01:26:51 PM PDT 24
Finished Mar 26 01:27:13 PM PDT 24
Peak memory 264320 kb
Host smart-2d4fbc79-2c24-46f6-8459-6006d70a5158
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336250080 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.flash_ctrl_disable.336250080
Directory /workspace/19.flash_ctrl_disable/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.1644639580
Short name T805
Test name
Test status
Simulation time 10033460900 ps
CPU time 59.18 seconds
Started Mar 26 01:26:52 PM PDT 24
Finished Mar 26 01:27:51 PM PDT 24
Peak memory 270776 kb
Host smart-d9a36e22-69cf-40fb-a1d8-f6fccecf0757
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644639580 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.1644639580
Directory /workspace/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_read_seed_err.1017362088
Short name T755
Test name
Test status
Simulation time 15103400 ps
CPU time 13.51 seconds
Started Mar 26 01:26:51 PM PDT 24
Finished Mar 26 01:27:05 PM PDT 24
Peak memory 258564 kb
Host smart-a153b071-fbe6-49d5-865a-dc57c8b5e4bc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017362088 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.1017362088
Directory /workspace/19.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_rma_reset.36821573
Short name T970
Test name
Test status
Simulation time 180209396500 ps
CPU time 917.71 seconds
Started Mar 26 01:26:37 PM PDT 24
Finished Mar 26 01:41:55 PM PDT 24
Peak memory 263360 kb
Host smart-86cf6109-3db2-45a4-b85c-240786d5e13e
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36821573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.flash_ctrl_hw_rma_reset.36821573
Directory /workspace/19.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_sec_otp.142689269
Short name T435
Test name
Test status
Simulation time 4760783800 ps
CPU time 54.26 seconds
Started Mar 26 01:26:39 PM PDT 24
Finished Mar 26 01:27:33 PM PDT 24
Peak memory 261828 kb
Host smart-d09171b9-9a03-4d4a-8025-4693bed7708d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142689269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_h
w_sec_otp.142689269
Directory /workspace/19.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd_slow_flash.4263831711
Short name T199
Test name
Test status
Simulation time 9330267300 ps
CPU time 245.25 seconds
Started Mar 26 01:26:42 PM PDT 24
Finished Mar 26 01:30:47 PM PDT 24
Peak memory 288820 kb
Host smart-8d5445c4-d112-494d-8199-036017e9ba40
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263831711 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd_slow_flash.4263831711
Directory /workspace/19.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/19.flash_ctrl_invalid_op.2366213774
Short name T411
Test name
Test status
Simulation time 12673244300 ps
CPU time 72.45 seconds
Started Mar 26 01:26:40 PM PDT 24
Finished Mar 26 01:27:52 PM PDT 24
Peak memory 259800 kb
Host smart-63b13950-0d0b-422b-bba5-f85e39a74380
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366213774 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.2
366213774
Directory /workspace/19.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/19.flash_ctrl_lcmgr_intg.682327666
Short name T945
Test name
Test status
Simulation time 25810600 ps
CPU time 13.46 seconds
Started Mar 26 01:26:52 PM PDT 24
Finished Mar 26 01:27:06 PM PDT 24
Peak memory 264340 kb
Host smart-8d47d7bb-7407-4e6c-aa1c-7030b162f61d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682327666 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.flash_ctrl_lcmgr_intg.682327666
Directory /workspace/19.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/19.flash_ctrl_mp_regions.2554412680
Short name T90
Test name
Test status
Simulation time 15176275100 ps
CPU time 593.06 seconds
Started Mar 26 01:26:38 PM PDT 24
Finished Mar 26 01:36:31 PM PDT 24
Peak memory 272636 kb
Host smart-1a31b341-af8e-467a-a7f8-994f9f43b02b
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554412680 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 19.flash_ctrl_mp_regions.2554412680
Directory /workspace/19.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/19.flash_ctrl_otp_reset.2442164684
Short name T396
Test name
Test status
Simulation time 165610500 ps
CPU time 130.6 seconds
Started Mar 26 01:26:40 PM PDT 24
Finished Mar 26 01:28:50 PM PDT 24
Peak memory 259044 kb
Host smart-de56efb3-bc37-4b19-85b9-a6fb32c5a8f3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442164684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_o
tp_reset.2442164684
Directory /workspace/19.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_phy_arb.4044106641
Short name T201
Test name
Test status
Simulation time 64324600 ps
CPU time 321.84 seconds
Started Mar 26 01:26:38 PM PDT 24
Finished Mar 26 01:32:01 PM PDT 24
Peak memory 261420 kb
Host smart-44d289fb-d430-4e4c-ab6b-3896d1b99b6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4044106641 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.4044106641
Directory /workspace/19.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/19.flash_ctrl_prog_reset.100292058
Short name T319
Test name
Test status
Simulation time 24052500 ps
CPU time 13.8 seconds
Started Mar 26 01:26:41 PM PDT 24
Finished Mar 26 01:26:55 PM PDT 24
Peak memory 259596 kb
Host smart-b7c1e704-2d8f-47ea-bd96-cdb42a06c71d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100292058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_prog_res
et.100292058
Directory /workspace/19.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_rand_ops.2677006688
Short name T120
Test name
Test status
Simulation time 254993700 ps
CPU time 402.17 seconds
Started Mar 26 01:26:40 PM PDT 24
Finished Mar 26 01:33:22 PM PDT 24
Peak memory 280560 kb
Host smart-e4dff6bb-f982-4410-92a0-f3a2f735cb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677006688 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.2677006688
Directory /workspace/19.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/19.flash_ctrl_re_evict.4086189122
Short name T631
Test name
Test status
Simulation time 214230300 ps
CPU time 36.57 seconds
Started Mar 26 01:26:55 PM PDT 24
Finished Mar 26 01:27:31 PM PDT 24
Peak memory 273648 kb
Host smart-b21b84ba-2d03-4f42-ac93-34b56b609a81
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086189122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl
ash_ctrl_re_evict.4086189122
Directory /workspace/19.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_ro.2132465824
Short name T875
Test name
Test status
Simulation time 1433542600 ps
CPU time 92.05 seconds
Started Mar 26 01:26:38 PM PDT 24
Finished Mar 26 01:28:10 PM PDT 24
Peak memory 280056 kb
Host smart-f8264ecf-e396-4518-9475-59fe5c077c7e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132465824 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.flash_ctrl_ro.2132465824
Directory /workspace/19.flash_ctrl_ro/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw.3039325307
Short name T233
Test name
Test status
Simulation time 10197478400 ps
CPU time 569.41 seconds
Started Mar 26 01:26:38 PM PDT 24
Finished Mar 26 01:36:08 PM PDT 24
Peak memory 313524 kb
Host smart-33838ed7-6621-410e-a79b-c6bb7ac480ef
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039325307 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_c
trl_rw.3039325307
Directory /workspace/19.flash_ctrl_rw/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict.1615787879
Short name T1011
Test name
Test status
Simulation time 106852200 ps
CPU time 36.68 seconds
Started Mar 26 01:26:43 PM PDT 24
Finished Mar 26 01:27:20 PM PDT 24
Peak memory 272548 kb
Host smart-1f9f8a1e-fa4b-4c59-8ba7-07ddb58792b9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615787879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl
ash_ctrl_rw_evict.1615787879
Directory /workspace/19.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict_all_en.690603570
Short name T938
Test name
Test status
Simulation time 71368800 ps
CPU time 31.06 seconds
Started Mar 26 01:26:37 PM PDT 24
Finished Mar 26 01:27:08 PM PDT 24
Peak memory 273620 kb
Host smart-03693a48-93da-41d2-9eef-f44035aa8be4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690603570 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict_all_en.690603570
Directory /workspace/19.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/19.flash_ctrl_sec_info_access.1204447528
Short name T557
Test name
Test status
Simulation time 1521837400 ps
CPU time 67.21 seconds
Started Mar 26 01:26:53 PM PDT 24
Finished Mar 26 01:28:00 PM PDT 24
Peak memory 263556 kb
Host smart-ecccca61-e7b7-4267-9b68-ad56c0055ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204447528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.1204447528
Directory /workspace/19.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/19.flash_ctrl_smoke.1362811955
Short name T393
Test name
Test status
Simulation time 44021800 ps
CPU time 147.4 seconds
Started Mar 26 01:26:38 PM PDT 24
Finished Mar 26 01:29:06 PM PDT 24
Peak memory 277628 kb
Host smart-3bee21da-ed52-4777-81a3-8c94830da9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362811955 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.1362811955
Directory /workspace/19.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/19.flash_ctrl_wo.3084136080
Short name T1018
Test name
Test status
Simulation time 2334738500 ps
CPU time 196.75 seconds
Started Mar 26 01:26:38 PM PDT 24
Finished Mar 26 01:29:55 PM PDT 24
Peak memory 258744 kb
Host smart-81eab184-bafb-42b2-9d7a-3135133997ea
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084136080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.flash_ctrl_wo.3084136080
Directory /workspace/19.flash_ctrl_wo/latest

Test location /workspace/coverage/default/2.flash_ctrl_alert_test.2408772608
Short name T670
Test name
Test status
Simulation time 127904600 ps
CPU time 13.53 seconds
Started Mar 26 01:23:51 PM PDT 24
Finished Mar 26 01:24:04 PM PDT 24
Peak memory 257384 kb
Host smart-63414fe6-64dd-45e8-bcdd-57ca2ae55c5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408772608 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.2
408772608
Directory /workspace/2.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.flash_ctrl_config_regwen.600185736
Short name T103
Test name
Test status
Simulation time 21067000 ps
CPU time 13.84 seconds
Started Mar 26 01:23:50 PM PDT 24
Finished Mar 26 01:24:04 PM PDT 24
Peak memory 260896 kb
Host smart-d685ac64-7336-4baa-bae3-4f2de69966de
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600185736 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
flash_ctrl_config_regwen.600185736
Directory /workspace/2.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/2.flash_ctrl_connect.2763841369
Short name T1010
Test name
Test status
Simulation time 22675500 ps
CPU time 15.93 seconds
Started Mar 26 01:23:50 PM PDT 24
Finished Mar 26 01:24:06 PM PDT 24
Peak memory 275076 kb
Host smart-ac9f909b-8d9e-4290-bc6b-b0f1bed53bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763841369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.2763841369
Directory /workspace/2.flash_ctrl_connect/latest

Test location /workspace/coverage/default/2.flash_ctrl_disable.3569837671
Short name T672
Test name
Test status
Simulation time 13450400 ps
CPU time 21.96 seconds
Started Mar 26 01:23:40 PM PDT 24
Finished Mar 26 01:24:02 PM PDT 24
Peak memory 264280 kb
Host smart-b5d688d6-0d28-433e-b160-0759bc1c64e5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569837671 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_disable.3569837671
Directory /workspace/2.flash_ctrl_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_mp.3485410512
Short name T633
Test name
Test status
Simulation time 6528251900 ps
CPU time 2611.05 seconds
Started Mar 26 01:23:41 PM PDT 24
Finished Mar 26 02:07:13 PM PDT 24
Peak memory 261720 kb
Host smart-228f46b5-e23f-4762-8f05-c307346e382a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485410512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_err
or_mp.3485410512
Directory /workspace/2.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_type.1984228130
Short name T173
Test name
Test status
Simulation time 772292600 ps
CPU time 2235.1 seconds
Started Mar 26 01:23:44 PM PDT 24
Finished Mar 26 02:01:00 PM PDT 24
Peak memory 263816 kb
Host smart-e9e5922e-134c-4420-b9b9-169f97f1b86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984228130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_type.1984228130
Directory /workspace/2.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_win.1760409427
Short name T620
Test name
Test status
Simulation time 358274000 ps
CPU time 932.72 seconds
Started Mar 26 01:23:35 PM PDT 24
Finished Mar 26 01:39:08 PM PDT 24
Peak memory 272472 kb
Host smart-24f2461b-a935-4adf-88af-fe726498a95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760409427 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.1760409427
Directory /workspace/2.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/2.flash_ctrl_fs_sup.354902818
Short name T298
Test name
Test status
Simulation time 2585391900 ps
CPU time 34.39 seconds
Started Mar 26 01:23:48 PM PDT 24
Finished Mar 26 01:24:22 PM PDT 24
Peak memory 272456 kb
Host smart-0d8faabd-6aef-491f-b019-a6e035852114
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354902818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_fs_sup.354902818
Directory /workspace/2.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/2.flash_ctrl_full_mem_access.2055192700
Short name T691
Test name
Test status
Simulation time 81403453000 ps
CPU time 2520.37 seconds
Started Mar 26 01:23:43 PM PDT 24
Finished Mar 26 02:05:44 PM PDT 24
Peak memory 264240 kb
Host smart-9e1ddc5f-5e32-47c7-9df9-47ef2882da2d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055192700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_c
trl_full_mem_access.2055192700
Directory /workspace/2.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_dir_rd.2911472078
Short name T736
Test name
Test status
Simulation time 79098600 ps
CPU time 90.88 seconds
Started Mar 26 01:23:43 PM PDT 24
Finished Mar 26 01:25:14 PM PDT 24
Peak memory 261536 kb
Host smart-437aaf49-f71a-43ad-ac5b-7837e70ff4f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2911472078 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.2911472078
Directory /workspace/2.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.2549356945
Short name T907
Test name
Test status
Simulation time 10020036000 ps
CPU time 153.18 seconds
Started Mar 26 01:23:48 PM PDT 24
Finished Mar 26 01:26:22 PM PDT 24
Peak memory 280220 kb
Host smart-cb8944a1-c9ed-472f-8dd0-ca894681f417
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549356945 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.2549356945
Directory /workspace/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma.63294883
Short name T187
Test name
Test status
Simulation time 167435233000 ps
CPU time 2044.56 seconds
Started Mar 26 01:23:35 PM PDT 24
Finished Mar 26 01:57:40 PM PDT 24
Peak memory 263056 kb
Host smart-b763eaed-7f5d-4f9e-bba9-e5c96565fb3f
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63294883 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.flash_ctrl_hw_rma.63294883
Directory /workspace/2.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma_reset.1961389605
Short name T570
Test name
Test status
Simulation time 80129598400 ps
CPU time 789.36 seconds
Started Mar 26 01:23:39 PM PDT 24
Finished Mar 26 01:36:48 PM PDT 24
Peak memory 262460 kb
Host smart-69a376b4-f2ee-4d5a-b00f-0cb190b68dbb
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961389605 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.flash_ctrl_hw_rma_reset.1961389605
Directory /workspace/2.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_sec_otp.2052653938
Short name T1002
Test name
Test status
Simulation time 12542267400 ps
CPU time 134.9 seconds
Started Mar 26 01:23:44 PM PDT 24
Finished Mar 26 01:25:59 PM PDT 24
Peak memory 261580 kb
Host smart-7790ac6e-1103-4d2f-aa1f-21ff03b28f47
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052653938 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_h
w_sec_otp.2052653938
Directory /workspace/2.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd.2905556303
Short name T227
Test name
Test status
Simulation time 2945087400 ps
CPU time 158.78 seconds
Started Mar 26 01:23:46 PM PDT 24
Finished Mar 26 01:26:25 PM PDT 24
Peak memory 292984 kb
Host smart-83346e7c-f394-4422-9e37-e6028b010345
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905556303 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_intr_rd.2905556303
Directory /workspace/2.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd_slow_flash.435387181
Short name T349
Test name
Test status
Simulation time 15827078700 ps
CPU time 199.89 seconds
Started Mar 26 01:23:45 PM PDT 24
Finished Mar 26 01:27:05 PM PDT 24
Peak memory 290424 kb
Host smart-ef3c9081-f919-4ecd-abdf-3e28f37b308e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435387181 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd_slow_flash.435387181
Directory /workspace/2.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr.3934283367
Short name T290
Test name
Test status
Simulation time 4605485500 ps
CPU time 104.3 seconds
Started Mar 26 01:23:47 PM PDT 24
Finished Mar 26 01:25:31 PM PDT 24
Peak memory 264316 kb
Host smart-6414d5b6-3b31-4cb4-95af-89d469263a36
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934283367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.flash_ctrl_intr_wr.3934283367
Directory /workspace/2.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr_slow_flash.3851607124
Short name T525
Test name
Test status
Simulation time 160318063700 ps
CPU time 435.15 seconds
Started Mar 26 01:23:46 PM PDT 24
Finished Mar 26 01:31:01 PM PDT 24
Peak memory 264208 kb
Host smart-133f3377-d8d3-4278-99f3-5d361875ee10
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385
1607124 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.3851607124
Directory /workspace/2.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_invalid_op.3772871633
Short name T703
Test name
Test status
Simulation time 1665688700 ps
CPU time 57.32 seconds
Started Mar 26 01:23:45 PM PDT 24
Finished Mar 26 01:24:43 PM PDT 24
Peak memory 259924 kb
Host smart-2b121df8-5d6e-41b4-8260-2efcdbdf88da
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772871633 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.3772871633
Directory /workspace/2.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_lcmgr_intg.4291397410
Short name T135
Test name
Test status
Simulation time 47401100 ps
CPU time 13.42 seconds
Started Mar 26 01:23:49 PM PDT 24
Finished Mar 26 01:24:02 PM PDT 24
Peak memory 264300 kb
Host smart-13c40d0c-9142-43d0-86a5-295c6bfe23f7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291397410 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.flash_ctrl_lcmgr_intg.4291397410
Directory /workspace/2.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_mid_op_rst.2586598455
Short name T127
Test name
Test status
Simulation time 1315263000 ps
CPU time 69.01 seconds
Started Mar 26 01:23:41 PM PDT 24
Finished Mar 26 01:24:50 PM PDT 24
Peak memory 264084 kb
Host smart-de929087-44a1-4636-a3eb-7e77a90e3bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586598455 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.2586598455
Directory /workspace/2.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/2.flash_ctrl_mp_regions.3607125930
Short name T94
Test name
Test status
Simulation time 10898880100 ps
CPU time 331.74 seconds
Started Mar 26 01:23:36 PM PDT 24
Finished Mar 26 01:29:08 PM PDT 24
Peak memory 273364 kb
Host smart-1660bcb6-1244-4667-a751-25ebb7ad692f
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607125930 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_mp_regions.3607125930
Directory /workspace/2.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/2.flash_ctrl_otp_reset.2340898542
Short name T148
Test name
Test status
Simulation time 124797000 ps
CPU time 130.07 seconds
Started Mar 26 01:23:45 PM PDT 24
Finished Mar 26 01:25:55 PM PDT 24
Peak memory 263492 kb
Host smart-4240052c-da66-4cfc-9edc-8cf8137df74e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340898542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ot
p_reset.2340898542
Directory /workspace/2.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_ack_consistency.1459066848
Short name T9
Test name
Test status
Simulation time 44450800 ps
CPU time 13.72 seconds
Started Mar 26 01:23:51 PM PDT 24
Finished Mar 26 01:24:05 PM PDT 24
Peak memory 275888 kb
Host smart-6c319d91-cbc4-4785-948b-98c9d4863b80
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1459066848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.1459066848
Directory /workspace/2.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb.2319060329
Short name T936
Test name
Test status
Simulation time 823349800 ps
CPU time 211.42 seconds
Started Mar 26 01:23:36 PM PDT 24
Finished Mar 26 01:27:08 PM PDT 24
Peak memory 261404 kb
Host smart-4e52534e-9534-45bd-b43b-74abfe82b767
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2319060329 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.2319060329
Directory /workspace/2.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_prog_reset.3673373053
Short name T559
Test name
Test status
Simulation time 35911900 ps
CPU time 13.18 seconds
Started Mar 26 01:23:45 PM PDT 24
Finished Mar 26 01:23:58 PM PDT 24
Peak memory 264152 kb
Host smart-f8fe17f8-00aa-4233-81c6-6156eebe7cf5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673373053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_prog_res
et.3673373053
Directory /workspace/2.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_rand_ops.2972794328
Short name T616
Test name
Test status
Simulation time 79775000 ps
CPU time 533.95 seconds
Started Mar 26 01:23:37 PM PDT 24
Finished Mar 26 01:32:31 PM PDT 24
Peak memory 282112 kb
Host smart-b6d29d57-090d-4efc-943a-8096f52a5244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972794328 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.2972794328
Directory /workspace/2.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_buff_evict.3830612683
Short name T973
Test name
Test status
Simulation time 3156657700 ps
CPU time 120.38 seconds
Started Mar 26 01:23:35 PM PDT 24
Finished Mar 26 01:25:36 PM PDT 24
Peak memory 264436 kb
Host smart-1c2c9fa2-f7d8-476a-be30-2c45f5e5da13
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3830612683 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.3830612683
Directory /workspace/2.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_intg.2235951844
Short name T726
Test name
Test status
Simulation time 213361600 ps
CPU time 31.44 seconds
Started Mar 26 01:23:51 PM PDT 24
Finished Mar 26 01:24:22 PM PDT 24
Peak memory 272840 kb
Host smart-a51f6a91-419f-4231-b811-2003ee3e1c43
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235951844 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_rd_intg.2235951844
Directory /workspace/2.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_derr.157944893
Short name T226
Test name
Test status
Simulation time 33115000 ps
CPU time 21.58 seconds
Started Mar 26 01:23:39 PM PDT 24
Finished Mar 26 01:24:01 PM PDT 24
Peak memory 264252 kb
Host smart-d00bd96d-72de-4455-97db-4062c041e5ce
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157944893 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_derr.157944893
Directory /workspace/2.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_serr.3284642511
Short name T391
Test name
Test status
Simulation time 24269900 ps
CPU time 22.42 seconds
Started Mar 26 01:23:38 PM PDT 24
Finished Mar 26 01:24:01 PM PDT 24
Peak memory 263996 kb
Host smart-04c5570f-400b-4f6f-8755-0b5cb2a7378a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284642511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fl
ash_ctrl_read_word_sweep_serr.3284642511
Directory /workspace/2.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rma_err.2731992404
Short name T153
Test name
Test status
Simulation time 157501241200 ps
CPU time 968.88 seconds
Started Mar 26 01:23:48 PM PDT 24
Finished Mar 26 01:39:58 PM PDT 24
Peak memory 258484 kb
Host smart-dad819b1-378d-401e-a621-60b2c3d4d15c
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731992404 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rma_err.2731992404
Directory /workspace/2.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro.1130187282
Short name T811
Test name
Test status
Simulation time 2053855600 ps
CPU time 119.48 seconds
Started Mar 26 01:23:44 PM PDT 24
Finished Mar 26 01:25:44 PM PDT 24
Peak memory 280152 kb
Host smart-a5bc2205-6bde-48cb-b481-19ac4677c67d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130187282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.flash_ctrl_ro.1130187282
Directory /workspace/2.flash_ctrl_ro/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw.296807177
Short name T84
Test name
Test status
Simulation time 12385512100 ps
CPU time 485.36 seconds
Started Mar 26 01:23:41 PM PDT 24
Finished Mar 26 01:31:47 PM PDT 24
Peak memory 313380 kb
Host smart-3307c268-feac-4e50-b072-2d8de3323146
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296807177 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctr
l_rw.296807177
Directory /workspace/2.flash_ctrl_rw/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict.4206520871
Short name T515
Test name
Test status
Simulation time 165133700 ps
CPU time 32.72 seconds
Started Mar 26 01:23:35 PM PDT 24
Finished Mar 26 01:24:08 PM PDT 24
Peak memory 265352 kb
Host smart-2263cc25-64f3-4f54-a3db-ad69fde89cdf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206520871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_rw_evict.4206520871
Directory /workspace/2.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict_all_en.2191145485
Short name T520
Test name
Test status
Simulation time 208818500 ps
CPU time 34.99 seconds
Started Mar 26 01:23:36 PM PDT 24
Finished Mar 26 01:24:11 PM PDT 24
Peak memory 272600 kb
Host smart-497b75f4-c687-4774-97a7-e74961e8f678
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191145485 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict_all_en.2191145485
Directory /workspace/2.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_cm.1903683895
Short name T16
Test name
Test status
Simulation time 3119490000 ps
CPU time 4643.95 seconds
Started Mar 26 01:23:38 PM PDT 24
Finished Mar 26 02:41:02 PM PDT 24
Peak memory 287208 kb
Host smart-f4c2142a-f549-449c-b940-cc7521a2111e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903683895 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.1903683895
Directory /workspace/2.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_address.678093419
Short name T824
Test name
Test status
Simulation time 4698089900 ps
CPU time 55.91 seconds
Started Mar 26 01:23:38 PM PDT 24
Finished Mar 26 01:24:35 PM PDT 24
Peak memory 264396 kb
Host smart-c8811582-96da-4c04-a6d6-e074ae2fb083
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678093419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.flash_ctrl_serr_address.678093419
Directory /workspace/2.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_counter.1794200049
Short name T78
Test name
Test status
Simulation time 454154500 ps
CPU time 53.97 seconds
Started Mar 26 01:23:38 PM PDT 24
Finished Mar 26 01:24:32 PM PDT 24
Peak memory 272628 kb
Host smart-0c1fe87c-1b85-4d40-9f93-6b56291c8778
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794200049 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_serr_counter.1794200049
Directory /workspace/2.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke.2872741567
Short name T455
Test name
Test status
Simulation time 51202100 ps
CPU time 148.16 seconds
Started Mar 26 01:23:28 PM PDT 24
Finished Mar 26 01:25:56 PM PDT 24
Peak memory 277736 kb
Host smart-61753ab5-7c05-4e4f-9b3c-c1b1abcdd452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872741567 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.2872741567
Directory /workspace/2.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke_hw.1122278363
Short name T71
Test name
Test status
Simulation time 26284900 ps
CPU time 25.69 seconds
Started Mar 26 01:23:30 PM PDT 24
Finished Mar 26 01:23:55 PM PDT 24
Peak memory 258168 kb
Host smart-2a98504b-509d-4761-93ac-52aad9444d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122278363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.1122278363
Directory /workspace/2.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/2.flash_ctrl_stress_all.243921630
Short name T640
Test name
Test status
Simulation time 100589900 ps
CPU time 87.04 seconds
Started Mar 26 01:23:50 PM PDT 24
Finished Mar 26 01:25:18 PM PDT 24
Peak memory 276868 kb
Host smart-de5a28c1-f773-47e0-bce6-7af97f1feb43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243921630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stress
_all.243921630
Directory /workspace/2.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.flash_ctrl_sw_op.3706006583
Short name T789
Test name
Test status
Simulation time 28312400 ps
CPU time 26.09 seconds
Started Mar 26 01:23:42 PM PDT 24
Finished Mar 26 01:24:08 PM PDT 24
Peak memory 260536 kb
Host smart-7ef35dca-4de1-4bfe-9008-be8b11aca2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706006583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.3706006583
Directory /workspace/2.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_wo.3584278991
Short name T565
Test name
Test status
Simulation time 1609781600 ps
CPU time 117.63 seconds
Started Mar 26 01:23:45 PM PDT 24
Finished Mar 26 01:25:43 PM PDT 24
Peak memory 258696 kb
Host smart-3a34365a-abcd-43c4-9e55-f1c8d894321b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584278991 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.flash_ctrl_wo.3584278991
Directory /workspace/2.flash_ctrl_wo/latest

Test location /workspace/coverage/default/2.flash_ctrl_wr_intg.3716810582
Short name T12
Test name
Test status
Simulation time 111190700 ps
CPU time 14.81 seconds
Started Mar 26 01:23:47 PM PDT 24
Finished Mar 26 01:24:03 PM PDT 24
Peak memory 259172 kb
Host smart-912f63a8-e84f-4c71-8453-f25247db9124
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716810582 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wr_intg.3716810582
Directory /workspace/2.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/20.flash_ctrl_alert_test.1151776249
Short name T895
Test name
Test status
Simulation time 71506700 ps
CPU time 13.99 seconds
Started Mar 26 01:26:50 PM PDT 24
Finished Mar 26 01:27:04 PM PDT 24
Peak memory 257352 kb
Host smart-f9faf194-121e-4455-a2a7-2550ba370404
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151776249 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.
1151776249
Directory /workspace/20.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.flash_ctrl_connect.2793271948
Short name T754
Test name
Test status
Simulation time 51137000 ps
CPU time 16.18 seconds
Started Mar 26 01:26:50 PM PDT 24
Finished Mar 26 01:27:07 PM PDT 24
Peak memory 274068 kb
Host smart-3e796dcd-b6c1-46cd-9c16-c055d39401b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793271948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.2793271948
Directory /workspace/20.flash_ctrl_connect/latest

Test location /workspace/coverage/default/20.flash_ctrl_disable.592492642
Short name T835
Test name
Test status
Simulation time 28922600 ps
CPU time 20.43 seconds
Started Mar 26 01:26:51 PM PDT 24
Finished Mar 26 01:27:12 PM PDT 24
Peak memory 272664 kb
Host smart-952d5e61-96c2-4a23-bf54-949b7bd240d9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592492642 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_disable.592492642
Directory /workspace/20.flash_ctrl_disable/latest

Test location /workspace/coverage/default/20.flash_ctrl_hw_sec_otp.3101993159
Short name T426
Test name
Test status
Simulation time 15667546900 ps
CPU time 122.54 seconds
Started Mar 26 01:26:49 PM PDT 24
Finished Mar 26 01:28:52 PM PDT 24
Peak memory 261660 kb
Host smart-9e3b8db0-0834-4f33-90b5-37fe312f6835
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101993159 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_
hw_sec_otp.3101993159
Directory /workspace/20.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd_slow_flash.4105535239
Short name T650
Test name
Test status
Simulation time 24420362000 ps
CPU time 253.42 seconds
Started Mar 26 01:26:50 PM PDT 24
Finished Mar 26 01:31:04 PM PDT 24
Peak memory 283776 kb
Host smart-a8cc610f-02a7-42bc-b877-8df57b728877
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105535239 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd_slow_flash.4105535239
Directory /workspace/20.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/20.flash_ctrl_otp_reset.3370602514
Short name T454
Test name
Test status
Simulation time 35152600 ps
CPU time 129.22 seconds
Started Mar 26 01:26:51 PM PDT 24
Finished Mar 26 01:29:01 PM PDT 24
Peak memory 259128 kb
Host smart-3d77da31-4a70-4854-998c-2d2b9de5f877
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370602514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_o
tp_reset.3370602514
Directory /workspace/20.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_prog_reset.179774715
Short name T850
Test name
Test status
Simulation time 43416300 ps
CPU time 13.9 seconds
Started Mar 26 01:26:53 PM PDT 24
Finished Mar 26 01:27:07 PM PDT 24
Peak memory 264252 kb
Host smart-e0bc90c9-3609-4d6b-84d8-c7e9ead70ce2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179774715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_prog_res
et.179774715
Directory /workspace/20.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict.3652091858
Short name T864
Test name
Test status
Simulation time 54668600 ps
CPU time 30.56 seconds
Started Mar 26 01:26:51 PM PDT 24
Finished Mar 26 01:27:22 PM PDT 24
Peak memory 272536 kb
Host smart-bee06700-4cbb-43d0-ac54-98b4e18ad5a7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652091858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fl
ash_ctrl_rw_evict.3652091858
Directory /workspace/20.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/20.flash_ctrl_sec_info_access.1391386564
Short name T564
Test name
Test status
Simulation time 1111918800 ps
CPU time 60.37 seconds
Started Mar 26 01:27:12 PM PDT 24
Finished Mar 26 01:28:13 PM PDT 24
Peak memory 262692 kb
Host smart-f37bceb1-246d-4654-adaf-04f26aa929d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391386564 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.1391386564
Directory /workspace/20.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/20.flash_ctrl_smoke.3679392199
Short name T756
Test name
Test status
Simulation time 49278800 ps
CPU time 193.89 seconds
Started Mar 26 01:26:52 PM PDT 24
Finished Mar 26 01:30:06 PM PDT 24
Peak memory 275940 kb
Host smart-f926323d-d326-4f6b-887c-35dded6a5e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679392199 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.3679392199
Directory /workspace/20.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/21.flash_ctrl_connect.3228243398
Short name T724
Test name
Test status
Simulation time 81469000 ps
CPU time 15.91 seconds
Started Mar 26 01:26:52 PM PDT 24
Finished Mar 26 01:27:08 PM PDT 24
Peak memory 274924 kb
Host smart-90100b99-0d7a-461e-aabd-ba1309741ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228243398 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.3228243398
Directory /workspace/21.flash_ctrl_connect/latest

Test location /workspace/coverage/default/21.flash_ctrl_disable.1944408260
Short name T107
Test name
Test status
Simulation time 21787600 ps
CPU time 22.01 seconds
Started Mar 26 01:26:51 PM PDT 24
Finished Mar 26 01:27:13 PM PDT 24
Peak memory 272712 kb
Host smart-3b596f4c-411a-4d2b-abcd-559842882ca2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944408260 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.flash_ctrl_disable.1944408260
Directory /workspace/21.flash_ctrl_disable/latest

Test location /workspace/coverage/default/21.flash_ctrl_hw_sec_otp.695634041
Short name T444
Test name
Test status
Simulation time 7660532100 ps
CPU time 138.71 seconds
Started Mar 26 01:26:52 PM PDT 24
Finished Mar 26 01:29:11 PM PDT 24
Peak memory 261680 kb
Host smart-e30df735-465c-4a3a-bb9b-b8ab67c44530
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695634041 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_h
w_sec_otp.695634041
Directory /workspace/21.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd_slow_flash.3070610351
Short name T237
Test name
Test status
Simulation time 17519003200 ps
CPU time 217.84 seconds
Started Mar 26 01:26:54 PM PDT 24
Finished Mar 26 01:30:32 PM PDT 24
Peak memory 283680 kb
Host smart-b7319bef-61ee-4044-a921-0fb2e50cab47
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070610351 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd_slow_flash.3070610351
Directory /workspace/21.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/21.flash_ctrl_otp_reset.1063351637
Short name T740
Test name
Test status
Simulation time 266851700 ps
CPU time 127.68 seconds
Started Mar 26 01:26:50 PM PDT 24
Finished Mar 26 01:28:57 PM PDT 24
Peak memory 259996 kb
Host smart-41003119-a5be-4da9-b3fa-44fae17f4f44
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063351637 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_o
tp_reset.1063351637
Directory /workspace/21.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict.450039499
Short name T549
Test name
Test status
Simulation time 81096100 ps
CPU time 33.71 seconds
Started Mar 26 01:26:54 PM PDT 24
Finished Mar 26 01:27:28 PM PDT 24
Peak memory 273588 kb
Host smart-f0e05778-7a26-4530-9854-aec0df99ad24
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450039499 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fla
sh_ctrl_rw_evict.450039499
Directory /workspace/21.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict_all_en.303163510
Short name T77
Test name
Test status
Simulation time 197622300 ps
CPU time 34.41 seconds
Started Mar 26 01:26:55 PM PDT 24
Finished Mar 26 01:27:29 PM PDT 24
Peak memory 265392 kb
Host smart-32a509fb-9a36-441e-94a4-c26c35fcd598
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303163510 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict_all_en.303163510
Directory /workspace/21.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/21.flash_ctrl_sec_info_access.2619313383
Short name T386
Test name
Test status
Simulation time 2587202200 ps
CPU time 67.16 seconds
Started Mar 26 01:26:51 PM PDT 24
Finished Mar 26 01:27:59 PM PDT 24
Peak memory 262264 kb
Host smart-6d036716-42f0-4986-a265-aeb088f0ae17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619313383 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.2619313383
Directory /workspace/21.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/21.flash_ctrl_smoke.1641983031
Short name T480
Test name
Test status
Simulation time 19836600 ps
CPU time 121.38 seconds
Started Mar 26 01:26:51 PM PDT 24
Finished Mar 26 01:28:53 PM PDT 24
Peak memory 276120 kb
Host smart-089bf8be-edbe-4621-a45f-e293c6d65019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641983031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.1641983031
Directory /workspace/21.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/22.flash_ctrl_alert_test.2802844763
Short name T592
Test name
Test status
Simulation time 36714000 ps
CPU time 13.18 seconds
Started Mar 26 01:27:02 PM PDT 24
Finished Mar 26 01:27:16 PM PDT 24
Peak memory 257268 kb
Host smart-d63d425c-e542-478d-a8a5-e00b5cef1b72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802844763 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.
2802844763
Directory /workspace/22.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.flash_ctrl_connect.3172111293
Short name T505
Test name
Test status
Simulation time 16055900 ps
CPU time 15.57 seconds
Started Mar 26 01:27:04 PM PDT 24
Finished Mar 26 01:27:20 PM PDT 24
Peak memory 275188 kb
Host smart-ea7a7e42-e075-4b34-8d8f-e8f00cafe4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172111293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.3172111293
Directory /workspace/22.flash_ctrl_connect/latest

Test location /workspace/coverage/default/22.flash_ctrl_hw_sec_otp.2269610855
Short name T447
Test name
Test status
Simulation time 10308428900 ps
CPU time 80.8 seconds
Started Mar 26 01:27:04 PM PDT 24
Finished Mar 26 01:28:25 PM PDT 24
Peak memory 261560 kb
Host smart-de98bcb2-0e9c-4f9a-bd44-3c303f622c03
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269610855 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_
hw_sec_otp.2269610855
Directory /workspace/22.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd_slow_flash.2307939320
Short name T591
Test name
Test status
Simulation time 8412448300 ps
CPU time 223.39 seconds
Started Mar 26 01:27:03 PM PDT 24
Finished Mar 26 01:30:46 PM PDT 24
Peak memory 283928 kb
Host smart-2c2b0835-57c5-4b0f-90f0-64f4bc99fb06
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307939320 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd_slow_flash.2307939320
Directory /workspace/22.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/22.flash_ctrl_otp_reset.199366784
Short name T886
Test name
Test status
Simulation time 75480600 ps
CPU time 109 seconds
Started Mar 26 01:27:02 PM PDT 24
Finished Mar 26 01:28:52 PM PDT 24
Peak memory 259364 kb
Host smart-c3488dd6-bd60-49d6-8b1b-2aede82a8391
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199366784 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_ot
p_reset.199366784
Directory /workspace/22.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_prog_reset.1778779883
Short name T257
Test name
Test status
Simulation time 45055300 ps
CPU time 14 seconds
Started Mar 26 01:27:06 PM PDT 24
Finished Mar 26 01:27:20 PM PDT 24
Peak memory 259240 kb
Host smart-44ee93cf-4e1a-4637-b0ba-9a390a740fa5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778779883 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_prog_re
set.1778779883
Directory /workspace/22.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict.2950607844
Short name T720
Test name
Test status
Simulation time 320528800 ps
CPU time 31.05 seconds
Started Mar 26 01:27:03 PM PDT 24
Finished Mar 26 01:27:35 PM PDT 24
Peak memory 272568 kb
Host smart-4e6422dc-8370-4df5-b6b6-6b65f3322b80
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950607844 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fl
ash_ctrl_rw_evict.2950607844
Directory /workspace/22.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict_all_en.2899769801
Short name T859
Test name
Test status
Simulation time 134189400 ps
CPU time 31.19 seconds
Started Mar 26 01:27:05 PM PDT 24
Finished Mar 26 01:27:36 PM PDT 24
Peak memory 272788 kb
Host smart-905743f9-8360-45da-a7bc-9d35acf01ce2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899769801 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.flash_ctrl_rw_evict_all_en.2899769801
Directory /workspace/22.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/22.flash_ctrl_sec_info_access.315491373
Short name T746
Test name
Test status
Simulation time 1957871000 ps
CPU time 52.54 seconds
Started Mar 26 01:27:03 PM PDT 24
Finished Mar 26 01:27:55 PM PDT 24
Peak memory 263244 kb
Host smart-f85065ce-2d92-4c03-9774-8d2a4ffcd71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315491373 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.315491373
Directory /workspace/22.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/22.flash_ctrl_smoke.4133773371
Short name T541
Test name
Test status
Simulation time 265501000 ps
CPU time 169.11 seconds
Started Mar 26 01:26:49 PM PDT 24
Finished Mar 26 01:29:38 PM PDT 24
Peak memory 275988 kb
Host smart-0ad78dba-39aa-4e2d-8ddd-cd394d12ff9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133773371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.4133773371
Directory /workspace/22.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/23.flash_ctrl_alert_test.767658967
Short name T485
Test name
Test status
Simulation time 335207900 ps
CPU time 13.64 seconds
Started Mar 26 01:27:16 PM PDT 24
Finished Mar 26 01:27:30 PM PDT 24
Peak memory 264268 kb
Host smart-74a4c461-a41f-409e-b4b9-81a9143f1cd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767658967 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.767658967
Directory /workspace/23.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.flash_ctrl_connect.3261710722
Short name T529
Test name
Test status
Simulation time 80581600 ps
CPU time 15.59 seconds
Started Mar 26 01:27:19 PM PDT 24
Finished Mar 26 01:27:35 PM PDT 24
Peak memory 274832 kb
Host smart-2fcbf192-63c5-477f-9bf0-9623314e228a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261710722 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.3261710722
Directory /workspace/23.flash_ctrl_connect/latest

Test location /workspace/coverage/default/23.flash_ctrl_hw_sec_otp.2614509235
Short name T325
Test name
Test status
Simulation time 4904436600 ps
CPU time 134.94 seconds
Started Mar 26 01:27:05 PM PDT 24
Finished Mar 26 01:29:20 PM PDT 24
Peak memory 261816 kb
Host smart-b0d28b37-33c4-48bd-b09c-6d3403937c21
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614509235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_
hw_sec_otp.2614509235
Directory /workspace/23.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.2331402327
Short name T34
Test name
Test status
Simulation time 8742772800 ps
CPU time 203.5 seconds
Started Mar 26 01:27:03 PM PDT 24
Finished Mar 26 01:30:27 PM PDT 24
Peak memory 291920 kb
Host smart-6efc06f6-d961-49be-9f70-ca94569a983e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331402327 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd_slow_flash.2331402327
Directory /workspace/23.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/23.flash_ctrl_otp_reset.793704611
Short name T551
Test name
Test status
Simulation time 238728900 ps
CPU time 128.11 seconds
Started Mar 26 01:27:04 PM PDT 24
Finished Mar 26 01:29:12 PM PDT 24
Peak memory 259184 kb
Host smart-6d15e3c1-148b-4a46-8c95-6455a76b0fb3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793704611 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_ot
p_reset.793704611
Directory /workspace/23.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_prog_reset.1427849808
Short name T543
Test name
Test status
Simulation time 59239000 ps
CPU time 13.32 seconds
Started Mar 26 01:27:03 PM PDT 24
Finished Mar 26 01:27:17 PM PDT 24
Peak memory 264128 kb
Host smart-d5b75b01-d6f5-49f9-a922-d084921a3fc4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427849808 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_prog_re
set.1427849808
Directory /workspace/23.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_rw_evict.207025310
Short name T328
Test name
Test status
Simulation time 330524700 ps
CPU time 33.56 seconds
Started Mar 26 01:27:04 PM PDT 24
Finished Mar 26 01:27:38 PM PDT 24
Peak memory 272584 kb
Host smart-a85dc51b-b29a-43b3-8f66-fd29670b5980
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207025310 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fla
sh_ctrl_rw_evict.207025310
Directory /workspace/23.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/23.flash_ctrl_rw_evict_all_en.488832957
Short name T788
Test name
Test status
Simulation time 34048600 ps
CPU time 30.83 seconds
Started Mar 26 01:27:06 PM PDT 24
Finished Mar 26 01:27:37 PM PDT 24
Peak memory 273616 kb
Host smart-bcd11817-10e1-4a5d-a0a4-e753b3f45b2c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488832957 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict_all_en.488832957
Directory /workspace/23.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/23.flash_ctrl_sec_info_access.3949158822
Short name T1049
Test name
Test status
Simulation time 5446976800 ps
CPU time 64.45 seconds
Started Mar 26 01:27:16 PM PDT 24
Finished Mar 26 01:28:21 PM PDT 24
Peak memory 262280 kb
Host smart-1f98ca18-c3ab-4218-bd9d-0c6c13c651e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949158822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.3949158822
Directory /workspace/23.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/23.flash_ctrl_smoke.3629972118
Short name T389
Test name
Test status
Simulation time 181012300 ps
CPU time 123.47 seconds
Started Mar 26 01:27:02 PM PDT 24
Finished Mar 26 01:29:06 PM PDT 24
Peak memory 274872 kb
Host smart-f78d7f17-9edf-4262-8e96-1f95375a24a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629972118 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.3629972118
Directory /workspace/23.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/24.flash_ctrl_alert_test.1264509398
Short name T762
Test name
Test status
Simulation time 110575500 ps
CPU time 13.47 seconds
Started Mar 26 01:27:16 PM PDT 24
Finished Mar 26 01:27:30 PM PDT 24
Peak memory 257356 kb
Host smart-62c31383-b1fc-4fbd-9109-11167c4764cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264509398 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.
1264509398
Directory /workspace/24.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.flash_ctrl_connect.856897977
Short name T941
Test name
Test status
Simulation time 50165600 ps
CPU time 13.16 seconds
Started Mar 26 01:27:16 PM PDT 24
Finished Mar 26 01:27:30 PM PDT 24
Peak memory 274960 kb
Host smart-38c82197-4660-4482-9967-69bab961ef36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856897977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.856897977
Directory /workspace/24.flash_ctrl_connect/latest

Test location /workspace/coverage/default/24.flash_ctrl_disable.3731914004
Short name T750
Test name
Test status
Simulation time 10908400 ps
CPU time 21.48 seconds
Started Mar 26 01:27:17 PM PDT 24
Finished Mar 26 01:27:39 PM PDT 24
Peak memory 272556 kb
Host smart-5fd86cfa-adad-4e68-962b-1ff38d352b61
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731914004 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_disable.3731914004
Directory /workspace/24.flash_ctrl_disable/latest

Test location /workspace/coverage/default/24.flash_ctrl_hw_sec_otp.3102522154
Short name T459
Test name
Test status
Simulation time 4046581800 ps
CPU time 48.72 seconds
Started Mar 26 01:27:15 PM PDT 24
Finished Mar 26 01:28:04 PM PDT 24
Peak memory 261596 kb
Host smart-8bc20958-fac2-4176-a3dc-0b1e67e46630
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102522154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_
hw_sec_otp.3102522154
Directory /workspace/24.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd_slow_flash.1303604774
Short name T353
Test name
Test status
Simulation time 8694395900 ps
CPU time 197.91 seconds
Started Mar 26 01:27:17 PM PDT 24
Finished Mar 26 01:30:35 PM PDT 24
Peak memory 288816 kb
Host smart-a28d2e7b-5fb3-4c96-a560-acffcd05cccc
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303604774 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd_slow_flash.1303604774
Directory /workspace/24.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/24.flash_ctrl_otp_reset.1038850174
Short name T869
Test name
Test status
Simulation time 65220800 ps
CPU time 108.94 seconds
Started Mar 26 01:27:15 PM PDT 24
Finished Mar 26 01:29:04 PM PDT 24
Peak memory 258920 kb
Host smart-fddf0b20-c394-4d5e-bb2d-0c0732bfd2ba
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038850174 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_o
tp_reset.1038850174
Directory /workspace/24.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_prog_reset.2280329470
Short name T978
Test name
Test status
Simulation time 39620600 ps
CPU time 13.28 seconds
Started Mar 26 01:27:18 PM PDT 24
Finished Mar 26 01:27:31 PM PDT 24
Peak memory 259132 kb
Host smart-3766cf6d-4e2c-4f62-949e-0f96a9d2303f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280329470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_prog_re
set.2280329470
Directory /workspace/24.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict.1006684712
Short name T687
Test name
Test status
Simulation time 79316600 ps
CPU time 30.65 seconds
Started Mar 26 01:27:15 PM PDT 24
Finished Mar 26 01:27:46 PM PDT 24
Peak memory 273572 kb
Host smart-14809ffb-7537-4f58-9552-9f2b476cf374
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006684712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fl
ash_ctrl_rw_evict.1006684712
Directory /workspace/24.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict_all_en.912253032
Short name T231
Test name
Test status
Simulation time 56025100 ps
CPU time 31.08 seconds
Started Mar 26 01:27:16 PM PDT 24
Finished Mar 26 01:27:48 PM PDT 24
Peak memory 272560 kb
Host smart-0182236b-f7d9-4ec3-9a82-8d91d206f0b7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912253032 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict_all_en.912253032
Directory /workspace/24.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/24.flash_ctrl_sec_info_access.2824619738
Short name T380
Test name
Test status
Simulation time 18444839000 ps
CPU time 86.93 seconds
Started Mar 26 01:27:16 PM PDT 24
Finished Mar 26 01:28:44 PM PDT 24
Peak memory 262568 kb
Host smart-6006c441-0204-4b66-80fb-eef8245d70b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824619738 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.2824619738
Directory /workspace/24.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/24.flash_ctrl_smoke.4045248116
Short name T544
Test name
Test status
Simulation time 27396900 ps
CPU time 97.07 seconds
Started Mar 26 01:27:14 PM PDT 24
Finished Mar 26 01:28:51 PM PDT 24
Peak memory 275476 kb
Host smart-c08e2c69-c4c8-4c0c-8e47-29812a06f9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045248116 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.4045248116
Directory /workspace/24.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/25.flash_ctrl_alert_test.812408476
Short name T924
Test name
Test status
Simulation time 44019600 ps
CPU time 14.33 seconds
Started Mar 26 01:27:28 PM PDT 24
Finished Mar 26 01:27:43 PM PDT 24
Peak memory 264268 kb
Host smart-cce0a22e-5de4-40a4-bd31-ce6f7c575bc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812408476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test.812408476
Directory /workspace/25.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.flash_ctrl_connect.677181974
Short name T558
Test name
Test status
Simulation time 14584300 ps
CPU time 15.54 seconds
Started Mar 26 01:27:29 PM PDT 24
Finished Mar 26 01:27:44 PM PDT 24
Peak memory 274768 kb
Host smart-3ebdb9ee-7c4a-462c-9e3c-a8b8b2773196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677181974 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.677181974
Directory /workspace/25.flash_ctrl_connect/latest

Test location /workspace/coverage/default/25.flash_ctrl_disable.3519552093
Short name T1047
Test name
Test status
Simulation time 44990000 ps
CPU time 21.1 seconds
Started Mar 26 01:27:15 PM PDT 24
Finished Mar 26 01:27:37 PM PDT 24
Peak memory 279552 kb
Host smart-2ae5af4b-b21e-46dd-a0bd-237f2f3198bd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519552093 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.flash_ctrl_disable.3519552093
Directory /workspace/25.flash_ctrl_disable/latest

Test location /workspace/coverage/default/25.flash_ctrl_hw_sec_otp.1961255687
Short name T727
Test name
Test status
Simulation time 4604071300 ps
CPU time 141.47 seconds
Started Mar 26 01:27:19 PM PDT 24
Finished Mar 26 01:29:40 PM PDT 24
Peak memory 261356 kb
Host smart-2b34b659-57be-4425-8cf1-56c450749c26
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961255687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_
hw_sec_otp.1961255687
Directory /workspace/25.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd_slow_flash.134682192
Short name T347
Test name
Test status
Simulation time 16210891400 ps
CPU time 218.74 seconds
Started Mar 26 01:27:17 PM PDT 24
Finished Mar 26 01:30:56 PM PDT 24
Peak memory 291988 kb
Host smart-f3b7007e-1992-472d-8db1-4ba42f50102e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134682192 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd_slow_flash.134682192
Directory /workspace/25.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/25.flash_ctrl_otp_reset.2731741655
Short name T619
Test name
Test status
Simulation time 41759600 ps
CPU time 111.38 seconds
Started Mar 26 01:27:19 PM PDT 24
Finished Mar 26 01:29:11 PM PDT 24
Peak memory 260028 kb
Host smart-3014c3ca-6e07-435a-8edf-1ce587d30d92
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731741655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_o
tp_reset.2731741655
Directory /workspace/25.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_prog_reset.2131809756
Short name T460
Test name
Test status
Simulation time 69455100 ps
CPU time 13.44 seconds
Started Mar 26 01:27:15 PM PDT 24
Finished Mar 26 01:27:29 PM PDT 24
Peak memory 264296 kb
Host smart-94a93749-41ed-4a96-a8e7-d1e5ec52372b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131809756 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_prog_re
set.2131809756
Directory /workspace/25.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_rw_evict.3717787477
Short name T593
Test name
Test status
Simulation time 324595000 ps
CPU time 34.71 seconds
Started Mar 26 01:27:15 PM PDT 24
Finished Mar 26 01:27:50 PM PDT 24
Peak memory 272620 kb
Host smart-8ac2f199-2fd4-4395-897a-054faa65e464
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717787477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fl
ash_ctrl_rw_evict.3717787477
Directory /workspace/25.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/25.flash_ctrl_rw_evict_all_en.3988540234
Short name T611
Test name
Test status
Simulation time 29575500 ps
CPU time 31.38 seconds
Started Mar 26 01:27:18 PM PDT 24
Finished Mar 26 01:27:50 PM PDT 24
Peak memory 272528 kb
Host smart-fbc17bbf-8b3e-40d8-852a-ec967cf65570
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988540234 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict_all_en.3988540234
Directory /workspace/25.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/25.flash_ctrl_sec_info_access.1109603849
Short name T944
Test name
Test status
Simulation time 797422500 ps
CPU time 78.53 seconds
Started Mar 26 01:27:31 PM PDT 24
Finished Mar 26 01:28:50 PM PDT 24
Peak memory 262240 kb
Host smart-1999003f-7997-4e71-81e2-e7f0cbe91e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109603849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.1109603849
Directory /workspace/25.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/25.flash_ctrl_smoke.2352622804
Short name T514
Test name
Test status
Simulation time 73064900 ps
CPU time 146.7 seconds
Started Mar 26 01:27:17 PM PDT 24
Finished Mar 26 01:29:44 PM PDT 24
Peak memory 276108 kb
Host smart-25926470-5dcc-413d-b03d-e33fbaa18b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352622804 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.2352622804
Directory /workspace/25.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/26.flash_ctrl_alert_test.1786046233
Short name T975
Test name
Test status
Simulation time 71151700 ps
CPU time 13.79 seconds
Started Mar 26 01:27:31 PM PDT 24
Finished Mar 26 01:27:45 PM PDT 24
Peak memory 257356 kb
Host smart-7cff7553-441e-487c-863f-ee917930d546
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786046233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.
1786046233
Directory /workspace/26.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.flash_ctrl_connect.4143404632
Short name T326
Test name
Test status
Simulation time 41161800 ps
CPU time 15.97 seconds
Started Mar 26 01:27:32 PM PDT 24
Finished Mar 26 01:27:48 PM PDT 24
Peak memory 275152 kb
Host smart-e115c0a3-0361-47cd-be91-d5d4659b14ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143404632 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.4143404632
Directory /workspace/26.flash_ctrl_connect/latest

Test location /workspace/coverage/default/26.flash_ctrl_disable.3496960033
Short name T588
Test name
Test status
Simulation time 16774700 ps
CPU time 21.54 seconds
Started Mar 26 01:27:33 PM PDT 24
Finished Mar 26 01:27:54 PM PDT 24
Peak memory 264400 kb
Host smart-bd2b0b46-a045-4e66-831d-d5d62c0897cd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496960033 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_disable.3496960033
Directory /workspace/26.flash_ctrl_disable/latest

Test location /workspace/coverage/default/26.flash_ctrl_hw_sec_otp.3930594790
Short name T523
Test name
Test status
Simulation time 931356600 ps
CPU time 50.6 seconds
Started Mar 26 01:27:31 PM PDT 24
Finished Mar 26 01:28:22 PM PDT 24
Peak memory 261632 kb
Host smart-0b16bef1-1887-4a36-a6ed-12b71696730e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930594790 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_
hw_sec_otp.3930594790
Directory /workspace/26.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd_slow_flash.2131267351
Short name T575
Test name
Test status
Simulation time 102193245600 ps
CPU time 248.97 seconds
Started Mar 26 01:27:28 PM PDT 24
Finished Mar 26 01:31:38 PM PDT 24
Peak memory 288804 kb
Host smart-17b398d7-19a2-46f5-b5a4-1654bbe35ec4
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131267351 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd_slow_flash.2131267351
Directory /workspace/26.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/26.flash_ctrl_otp_reset.347223534
Short name T581
Test name
Test status
Simulation time 181617100 ps
CPU time 108.44 seconds
Started Mar 26 01:27:31 PM PDT 24
Finished Mar 26 01:29:20 PM PDT 24
Peak memory 260180 kb
Host smart-3c6ddb7c-e29d-4852-a51f-a3dbec1143ea
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347223534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_ot
p_reset.347223534
Directory /workspace/26.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_prog_reset.4087398583
Short name T892
Test name
Test status
Simulation time 169146200 ps
CPU time 13.61 seconds
Started Mar 26 01:27:29 PM PDT 24
Finished Mar 26 01:27:42 PM PDT 24
Peak memory 259308 kb
Host smart-d08e1d27-9279-4c0c-b647-743c977cf2da
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087398583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_prog_re
set.4087398583
Directory /workspace/26.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict.1111709666
Short name T215
Test name
Test status
Simulation time 35351000 ps
CPU time 30.63 seconds
Started Mar 26 01:27:30 PM PDT 24
Finished Mar 26 01:28:01 PM PDT 24
Peak memory 273668 kb
Host smart-e4f42903-4e7d-4bc4-90a6-3b088ccf8dcb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111709666 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fl
ash_ctrl_rw_evict.1111709666
Directory /workspace/26.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/26.flash_ctrl_smoke.33360162
Short name T462
Test name
Test status
Simulation time 109167200 ps
CPU time 122.78 seconds
Started Mar 26 01:27:30 PM PDT 24
Finished Mar 26 01:29:33 PM PDT 24
Peak memory 274716 kb
Host smart-c877b185-6b0b-43f4-aeae-02cbe27b57f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33360162 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.33360162
Directory /workspace/26.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/27.flash_ctrl_alert_test.527804147
Short name T465
Test name
Test status
Simulation time 94352400 ps
CPU time 13.95 seconds
Started Mar 26 01:27:39 PM PDT 24
Finished Mar 26 01:27:54 PM PDT 24
Peak memory 257296 kb
Host smart-3462d17d-3908-479f-895d-be169ddabc55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527804147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.527804147
Directory /workspace/27.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.flash_ctrl_connect.2205510892
Short name T963
Test name
Test status
Simulation time 49726600 ps
CPU time 13.12 seconds
Started Mar 26 01:27:38 PM PDT 24
Finished Mar 26 01:27:51 PM PDT 24
Peak memory 275232 kb
Host smart-5b9840bb-e3e1-4673-b24e-7e7250231f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205510892 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.2205510892
Directory /workspace/27.flash_ctrl_connect/latest

Test location /workspace/coverage/default/27.flash_ctrl_disable.2694933915
Short name T857
Test name
Test status
Simulation time 21120600 ps
CPU time 19.93 seconds
Started Mar 26 01:27:34 PM PDT 24
Finished Mar 26 01:27:54 PM PDT 24
Peak memory 264424 kb
Host smart-1d737de0-96a3-4ac9-894e-a2418fe237e8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694933915 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_disable.2694933915
Directory /workspace/27.flash_ctrl_disable/latest

Test location /workspace/coverage/default/27.flash_ctrl_hw_sec_otp.3479122622
Short name T1003
Test name
Test status
Simulation time 8006368600 ps
CPU time 120.55 seconds
Started Mar 26 01:27:31 PM PDT 24
Finished Mar 26 01:29:32 PM PDT 24
Peak memory 261560 kb
Host smart-69c6926f-3a85-4660-bc9f-c4758fa1c501
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479122622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_
hw_sec_otp.3479122622
Directory /workspace/27.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd.3236232624
Short name T794
Test name
Test status
Simulation time 1130941300 ps
CPU time 139.6 seconds
Started Mar 26 01:27:34 PM PDT 24
Finished Mar 26 01:29:53 PM PDT 24
Peak memory 294092 kb
Host smart-62f8ec9d-97be-4248-bdcb-b77cc94d3300
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236232624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fla
sh_ctrl_intr_rd.3236232624
Directory /workspace/27.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.3969146884
Short name T637
Test name
Test status
Simulation time 17264486300 ps
CPU time 197.59 seconds
Started Mar 26 01:27:32 PM PDT 24
Finished Mar 26 01:30:49 PM PDT 24
Peak memory 283864 kb
Host smart-f1d123ea-63e7-424b-8a6a-46a931d9aac0
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969146884 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd_slow_flash.3969146884
Directory /workspace/27.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/27.flash_ctrl_otp_reset.136796922
Short name T929
Test name
Test status
Simulation time 37132400 ps
CPU time 131.13 seconds
Started Mar 26 01:27:33 PM PDT 24
Finished Mar 26 01:29:45 PM PDT 24
Peak memory 263252 kb
Host smart-2b2748f0-5a20-4e94-8d2a-349a0ec6a0d7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136796922 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_ot
p_reset.136796922
Directory /workspace/27.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_prog_reset.2183020053
Short name T392
Test name
Test status
Simulation time 17628700 ps
CPU time 13.37 seconds
Started Mar 26 01:27:34 PM PDT 24
Finished Mar 26 01:27:48 PM PDT 24
Peak memory 263712 kb
Host smart-68689e5f-d2c5-4caa-abf2-679a4cd3090a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183020053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_prog_re
set.2183020053
Directory /workspace/27.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict.3070400901
Short name T473
Test name
Test status
Simulation time 56628200 ps
CPU time 34.12 seconds
Started Mar 26 01:27:38 PM PDT 24
Finished Mar 26 01:28:12 PM PDT 24
Peak memory 273684 kb
Host smart-7757424d-4efe-4d5f-9eb8-5cb32ce08986
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070400901 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fl
ash_ctrl_rw_evict.3070400901
Directory /workspace/27.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict_all_en.4263464324
Short name T422
Test name
Test status
Simulation time 30897300 ps
CPU time 28.44 seconds
Started Mar 26 01:27:37 PM PDT 24
Finished Mar 26 01:28:06 PM PDT 24
Peak memory 272668 kb
Host smart-54773e5d-095a-48de-ba38-83cbcb2f5136
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263464324 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict_all_en.4263464324
Directory /workspace/27.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/27.flash_ctrl_sec_info_access.1742646953
Short name T385
Test name
Test status
Simulation time 1532467200 ps
CPU time 64.45 seconds
Started Mar 26 01:27:33 PM PDT 24
Finished Mar 26 01:28:37 PM PDT 24
Peak memory 261716 kb
Host smart-d4d17095-197f-4edd-8072-f9581a52dde6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742646953 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.1742646953
Directory /workspace/27.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/27.flash_ctrl_smoke.2061496268
Short name T516
Test name
Test status
Simulation time 1371043500 ps
CPU time 178.82 seconds
Started Mar 26 01:27:34 PM PDT 24
Finished Mar 26 01:30:33 PM PDT 24
Peak memory 280532 kb
Host smart-df326ebc-e0a5-48b6-a206-27e208924fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061496268 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.2061496268
Directory /workspace/27.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/28.flash_ctrl_alert_test.143865082
Short name T566
Test name
Test status
Simulation time 54661500 ps
CPU time 13.72 seconds
Started Mar 26 01:27:39 PM PDT 24
Finished Mar 26 01:27:53 PM PDT 24
Peak memory 264228 kb
Host smart-ef0f7682-b925-48e7-b58a-37f405a32bd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143865082 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.143865082
Directory /workspace/28.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.flash_ctrl_connect.1498779256
Short name T796
Test name
Test status
Simulation time 35898800 ps
CPU time 15.54 seconds
Started Mar 26 01:27:41 PM PDT 24
Finished Mar 26 01:27:57 PM PDT 24
Peak memory 274176 kb
Host smart-85ae2e9c-a1ed-4a7d-bb45-8df999c57f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498779256 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.1498779256
Directory /workspace/28.flash_ctrl_connect/latest

Test location /workspace/coverage/default/28.flash_ctrl_disable.3804776098
Short name T156
Test name
Test status
Simulation time 74200200 ps
CPU time 20.58 seconds
Started Mar 26 01:27:38 PM PDT 24
Finished Mar 26 01:27:59 PM PDT 24
Peak memory 272432 kb
Host smart-d41a4356-d6be-4e84-b667-9db63d22d7e0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804776098 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_disable.3804776098
Directory /workspace/28.flash_ctrl_disable/latest

Test location /workspace/coverage/default/28.flash_ctrl_hw_sec_otp.1274283448
Short name T262
Test name
Test status
Simulation time 4113747700 ps
CPU time 91.08 seconds
Started Mar 26 01:27:38 PM PDT 24
Finished Mar 26 01:29:09 PM PDT 24
Peak memory 261744 kb
Host smart-720e05c4-5f4f-4235-92fa-7ca1f3746c4b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274283448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_
hw_sec_otp.1274283448
Directory /workspace/28.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd_slow_flash.2319008130
Short name T348
Test name
Test status
Simulation time 12306786600 ps
CPU time 209.28 seconds
Started Mar 26 01:27:39 PM PDT 24
Finished Mar 26 01:31:08 PM PDT 24
Peak memory 283912 kb
Host smart-e16e0ed7-136a-48f9-a527-aa542bf32149
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319008130 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd_slow_flash.2319008130
Directory /workspace/28.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/28.flash_ctrl_otp_reset.4130307193
Short name T492
Test name
Test status
Simulation time 77174800 ps
CPU time 108.99 seconds
Started Mar 26 01:27:39 PM PDT 24
Finished Mar 26 01:29:28 PM PDT 24
Peak memory 259028 kb
Host smart-ce365b46-1e39-4d07-bda9-3f091ed3d474
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130307193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_o
tp_reset.4130307193
Directory /workspace/28.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_prog_reset.13762945
Short name T530
Test name
Test status
Simulation time 18148700 ps
CPU time 13.73 seconds
Started Mar 26 01:27:40 PM PDT 24
Finished Mar 26 01:27:54 PM PDT 24
Peak memory 259212 kb
Host smart-c71d0c06-d935-4b45-aa0f-d11518265d3f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13762945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_prog_rese
t.13762945
Directory /workspace/28.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict.1835885007
Short name T922
Test name
Test status
Simulation time 395008500 ps
CPU time 30.18 seconds
Started Mar 26 01:27:40 PM PDT 24
Finished Mar 26 01:28:10 PM PDT 24
Peak memory 273616 kb
Host smart-69fa6e0c-1828-4d89-898f-e098ce94bf62
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835885007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fl
ash_ctrl_rw_evict.1835885007
Directory /workspace/28.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.3331030651
Short name T885
Test name
Test status
Simulation time 30158500 ps
CPU time 31.52 seconds
Started Mar 26 01:27:38 PM PDT 24
Finished Mar 26 01:28:10 PM PDT 24
Peak memory 265580 kb
Host smart-0cdd39ac-4a9f-439f-a027-22b8da0a28ac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331030651 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict_all_en.3331030651
Directory /workspace/28.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/28.flash_ctrl_sec_info_access.482036124
Short name T603
Test name
Test status
Simulation time 1731876500 ps
CPU time 65.87 seconds
Started Mar 26 01:27:41 PM PDT 24
Finished Mar 26 01:28:47 PM PDT 24
Peak memory 262268 kb
Host smart-609bf520-8a6c-4c9c-99df-ccf5421310f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482036124 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.482036124
Directory /workspace/28.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/28.flash_ctrl_smoke.971424349
Short name T860
Test name
Test status
Simulation time 78692200 ps
CPU time 171.41 seconds
Started Mar 26 01:27:41 PM PDT 24
Finished Mar 26 01:30:33 PM PDT 24
Peak memory 278156 kb
Host smart-456a37ec-1de8-40c0-8007-0e300c1d0220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971424349 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.971424349
Directory /workspace/28.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/29.flash_ctrl_alert_test.517501024
Short name T542
Test name
Test status
Simulation time 42218200 ps
CPU time 13.9 seconds
Started Mar 26 01:27:53 PM PDT 24
Finished Mar 26 01:28:07 PM PDT 24
Peak memory 257168 kb
Host smart-d98d1aa7-850b-4416-94a4-da262a09bf8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517501024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test.517501024
Directory /workspace/29.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.flash_ctrl_connect.2192893282
Short name T698
Test name
Test status
Simulation time 23050200 ps
CPU time 15.79 seconds
Started Mar 26 01:27:50 PM PDT 24
Finished Mar 26 01:28:06 PM PDT 24
Peak memory 274132 kb
Host smart-12c720f7-08ae-44a5-8452-ac6b08dddbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192893282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.2192893282
Directory /workspace/29.flash_ctrl_connect/latest

Test location /workspace/coverage/default/29.flash_ctrl_disable.647252871
Short name T400
Test name
Test status
Simulation time 12151600 ps
CPU time 21.27 seconds
Started Mar 26 01:27:50 PM PDT 24
Finished Mar 26 01:28:11 PM PDT 24
Peak memory 264420 kb
Host smart-cf79c6a0-ffcb-478f-8522-c6c19e53e220
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647252871 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_disable.647252871
Directory /workspace/29.flash_ctrl_disable/latest

Test location /workspace/coverage/default/29.flash_ctrl_hw_sec_otp.1394256976
Short name T695
Test name
Test status
Simulation time 848536300 ps
CPU time 37.19 seconds
Started Mar 26 01:27:38 PM PDT 24
Finished Mar 26 01:28:16 PM PDT 24
Peak memory 261700 kb
Host smart-0e3f447e-5fb2-4f36-a32f-8fa2ccaa1347
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394256976 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_
hw_sec_otp.1394256976
Directory /workspace/29.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.1556495186
Short name T699
Test name
Test status
Simulation time 9653659900 ps
CPU time 201.14 seconds
Started Mar 26 01:27:51 PM PDT 24
Finished Mar 26 01:31:12 PM PDT 24
Peak memory 283804 kb
Host smart-721d6abc-0fdd-4677-9ab6-0d5a5d40714c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556495186 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd_slow_flash.1556495186
Directory /workspace/29.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/29.flash_ctrl_otp_reset.930503314
Short name T606
Test name
Test status
Simulation time 39244000 ps
CPU time 130.38 seconds
Started Mar 26 01:27:39 PM PDT 24
Finished Mar 26 01:29:50 PM PDT 24
Peak memory 260216 kb
Host smart-39978b2f-ed7d-4d08-82d0-b8e8130e4525
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930503314 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_ot
p_reset.930503314
Directory /workspace/29.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_prog_reset.3258026365
Short name T55
Test name
Test status
Simulation time 97706500 ps
CPU time 13.5 seconds
Started Mar 26 01:27:50 PM PDT 24
Finished Mar 26 01:28:04 PM PDT 24
Peak memory 259320 kb
Host smart-910841dc-aa44-4eaa-98a3-6117753e1503
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258026365 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_prog_re
set.3258026365
Directory /workspace/29.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict.3208689469
Short name T795
Test name
Test status
Simulation time 72338800 ps
CPU time 30.57 seconds
Started Mar 26 01:27:52 PM PDT 24
Finished Mar 26 01:28:23 PM PDT 24
Peak memory 273636 kb
Host smart-cb7b3870-d019-4879-bf2c-c60d8b057d5d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208689469 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fl
ash_ctrl_rw_evict.3208689469
Directory /workspace/29.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict_all_en.4147519612
Short name T53
Test name
Test status
Simulation time 38157500 ps
CPU time 31.29 seconds
Started Mar 26 01:27:52 PM PDT 24
Finished Mar 26 01:28:24 PM PDT 24
Peak memory 272524 kb
Host smart-b5287315-2f49-4b8e-83b5-96638773e94d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147519612 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict_all_en.4147519612
Directory /workspace/29.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/29.flash_ctrl_sec_info_access.740109416
Short name T382
Test name
Test status
Simulation time 1393300900 ps
CPU time 57.07 seconds
Started Mar 26 01:27:49 PM PDT 24
Finished Mar 26 01:28:46 PM PDT 24
Peak memory 262352 kb
Host smart-36bcc221-5336-43e1-8cf1-fb0c1f905e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740109416 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.740109416
Directory /workspace/29.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/29.flash_ctrl_smoke.1950693546
Short name T618
Test name
Test status
Simulation time 68492600 ps
CPU time 51.26 seconds
Started Mar 26 01:27:39 PM PDT 24
Finished Mar 26 01:28:31 PM PDT 24
Peak memory 269572 kb
Host smart-45b41ecb-4b16-4e38-a58a-e12f93367ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950693546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.1950693546
Directory /workspace/29.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_alert_test.1093283045
Short name T174
Test name
Test status
Simulation time 42539000 ps
CPU time 13.45 seconds
Started Mar 26 01:24:07 PM PDT 24
Finished Mar 26 01:24:21 PM PDT 24
Peak memory 264308 kb
Host smart-4b5a1ab3-b3ce-4ab3-9f12-a96754ea9af6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093283045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.1
093283045
Directory /workspace/3.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.flash_ctrl_config_regwen.885238882
Short name T272
Test name
Test status
Simulation time 25318900 ps
CPU time 13.52 seconds
Started Mar 26 01:24:04 PM PDT 24
Finished Mar 26 01:24:18 PM PDT 24
Peak memory 260944 kb
Host smart-04961917-74bb-40f0-936a-d72a4b2925cf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885238882 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
flash_ctrl_config_regwen.885238882
Directory /workspace/3.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/3.flash_ctrl_connect.3247601759
Short name T190
Test name
Test status
Simulation time 49747000 ps
CPU time 15.87 seconds
Started Mar 26 01:23:49 PM PDT 24
Finished Mar 26 01:24:05 PM PDT 24
Peak memory 274084 kb
Host smart-a9ba03aa-a046-45d5-a6ab-c290f0f8fc23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247601759 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.3247601759
Directory /workspace/3.flash_ctrl_connect/latest

Test location /workspace/coverage/default/3.flash_ctrl_derr_detect.2384768823
Short name T820
Test name
Test status
Simulation time 128621100 ps
CPU time 101.77 seconds
Started Mar 26 01:23:51 PM PDT 24
Finished Mar 26 01:25:32 PM PDT 24
Peak memory 272600 kb
Host smart-a36e1ae2-4a4f-40cd-90dc-915b4cba83f0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384768823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.flash_ctrl_derr_detect.2384768823
Directory /workspace/3.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/3.flash_ctrl_disable.546057047
Short name T56
Test name
Test status
Simulation time 10357600 ps
CPU time 21.37 seconds
Started Mar 26 01:23:50 PM PDT 24
Finished Mar 26 01:24:11 PM PDT 24
Peak memory 272544 kb
Host smart-1a60fec1-2416-4357-a724-cf58295690e8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546057047 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_disable.546057047
Directory /workspace/3.flash_ctrl_disable/latest

Test location /workspace/coverage/default/3.flash_ctrl_erase_suspend.3509683363
Short name T131
Test name
Test status
Simulation time 10787304800 ps
CPU time 450.84 seconds
Started Mar 26 01:23:50 PM PDT 24
Finished Mar 26 01:31:21 PM PDT 24
Peak memory 262036 kb
Host smart-3783bc37-499f-4d6c-b469-a18d1ef48159
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3509683363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.3509683363
Directory /workspace/3.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_mp.60506891
Short name T35
Test name
Test status
Simulation time 6642210500 ps
CPU time 2220.46 seconds
Started Mar 26 01:23:48 PM PDT 24
Finished Mar 26 02:00:49 PM PDT 24
Peak memory 263608 kb
Host smart-b101a188-8807-412c-bb49-a6977002e175
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60506891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error
_mp.60506891
Directory /workspace/3.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_type.3318016450
Short name T1024
Test name
Test status
Simulation time 1870227300 ps
CPU time 2810.99 seconds
Started Mar 26 01:23:48 PM PDT 24
Finished Mar 26 02:10:39 PM PDT 24
Peak memory 264204 kb
Host smart-fa51f2cf-bf7e-4cb8-b935-b38988fe3e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318016450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_type.3318016450
Directory /workspace/3.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_win.86180694
Short name T171
Test name
Test status
Simulation time 1400936700 ps
CPU time 945.33 seconds
Started Mar 26 01:23:51 PM PDT 24
Finished Mar 26 01:39:36 PM PDT 24
Peak memory 272364 kb
Host smart-b016651b-c174-4a09-bde4-6f988284e425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86180694 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.86180694
Directory /workspace/3.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/3.flash_ctrl_fetch_code.2260065671
Short name T21
Test name
Test status
Simulation time 242083700 ps
CPU time 22.32 seconds
Started Mar 26 01:23:51 PM PDT 24
Finished Mar 26 01:24:14 PM PDT 24
Peak memory 264184 kb
Host smart-37feae0d-929f-479e-a90d-2e0eff897867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260065671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetch_code.2260065671
Directory /workspace/3.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/3.flash_ctrl_fs_sup.883991969
Short name T172
Test name
Test status
Simulation time 299083900 ps
CPU time 34.59 seconds
Started Mar 26 01:23:52 PM PDT 24
Finished Mar 26 01:24:27 PM PDT 24
Peak memory 272480 kb
Host smart-b9cbb761-67b2-45da-b409-3f2bbfb1b978
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883991969 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_fs_sup.883991969
Directory /workspace/3.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/3.flash_ctrl_full_mem_access.4042792600
Short name T721
Test name
Test status
Simulation time 240266866400 ps
CPU time 2571.06 seconds
Started Mar 26 01:23:48 PM PDT 24
Finished Mar 26 02:06:39 PM PDT 24
Peak memory 263228 kb
Host smart-c2996d2d-0fd5-4124-a52b-4b3e0494df7c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042792600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_c
trl_full_mem_access.4042792600
Directory /workspace/3.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_dir_rd.1141220825
Short name T293
Test name
Test status
Simulation time 169268900 ps
CPU time 117.87 seconds
Started Mar 26 01:23:47 PM PDT 24
Finished Mar 26 01:25:46 PM PDT 24
Peak memory 264192 kb
Host smart-f73a23fe-5527-4af2-bcc7-d080d5e75e26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1141220825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.1141220825
Directory /workspace/3.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.3776821044
Short name T145
Test name
Test status
Simulation time 10036701500 ps
CPU time 99.09 seconds
Started Mar 26 01:24:05 PM PDT 24
Finished Mar 26 01:25:45 PM PDT 24
Peak memory 273228 kb
Host smart-e9994e64-8141-4d96-95ae-b4baeaaca460
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776821044 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.3776821044
Directory /workspace/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_read_seed_err.1509241748
Short name T744
Test name
Test status
Simulation time 155733300 ps
CPU time 13.31 seconds
Started Mar 26 01:24:08 PM PDT 24
Finished Mar 26 01:24:21 PM PDT 24
Peak memory 257464 kb
Host smart-3447e40a-1594-4ef7-81e6-bbfaeb4f5460
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509241748 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_read_seed_err.1509241748
Directory /workspace/3.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_rma_reset.256228204
Short name T768
Test name
Test status
Simulation time 150191562400 ps
CPU time 941.86 seconds
Started Mar 26 01:23:49 PM PDT 24
Finished Mar 26 01:39:31 PM PDT 24
Peak memory 258956 kb
Host smart-146fa9d4-22a5-402c-bc54-c095e9604e09
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256228204 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_hw_rma_reset.256228204
Directory /workspace/3.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_sec_otp.3479303273
Short name T810
Test name
Test status
Simulation time 8664503600 ps
CPU time 83.43 seconds
Started Mar 26 01:23:47 PM PDT 24
Finished Mar 26 01:25:11 PM PDT 24
Peak memory 261652 kb
Host smart-73a67973-c8cc-438f-bd2b-0a99f6ac40e4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479303273 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_h
w_sec_otp.3479303273
Directory /workspace/3.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.3596341972
Short name T831
Test name
Test status
Simulation time 109020778200 ps
CPU time 270.14 seconds
Started Mar 26 01:23:53 PM PDT 24
Finished Mar 26 01:28:23 PM PDT 24
Peak memory 290092 kb
Host smart-1323adf5-2430-4a14-b665-8e7b2ffdbbb8
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596341972 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd_slow_flash.3596341972
Directory /workspace/3.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr.76061082
Short name T816
Test name
Test status
Simulation time 4062453700 ps
CPU time 88.85 seconds
Started Mar 26 01:23:48 PM PDT 24
Finished Mar 26 01:25:18 PM PDT 24
Peak memory 264296 kb
Host smart-14c1fd53-7d75-44fd-bb82-b2387bd5769e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76061082 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +U
VM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.flash_ctrl_intr_wr.76061082
Directory /workspace/3.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr_slow_flash.3070560718
Short name T506
Test name
Test status
Simulation time 150358550400 ps
CPU time 328.23 seconds
Started Mar 26 01:23:52 PM PDT 24
Finished Mar 26 01:29:21 PM PDT 24
Peak memory 264264 kb
Host smart-a9a5096a-d403-444c-8046-6eb7019a6a38
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307
0560718 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.3070560718
Directory /workspace/3.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_invalid_op.2397850652
Short name T675
Test name
Test status
Simulation time 3810131600 ps
CPU time 92.79 seconds
Started Mar 26 01:23:47 PM PDT 24
Finished Mar 26 01:25:21 PM PDT 24
Peak memory 259712 kb
Host smart-5988880d-b46a-43bd-9974-ee7d8d84b171
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397850652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.2397850652
Directory /workspace/3.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_lcmgr_intg.334820311
Short name T306
Test name
Test status
Simulation time 35525800 ps
CPU time 13.32 seconds
Started Mar 26 01:24:04 PM PDT 24
Finished Mar 26 01:24:18 PM PDT 24
Peak memory 258672 kb
Host smart-4041abd4-f3f6-467a-affe-4968539ceaf6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334820311 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.flash_ctrl_lcmgr_intg.334820311
Directory /workspace/3.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/3.flash_ctrl_mp_regions.1592438365
Short name T92
Test name
Test status
Simulation time 10213031800 ps
CPU time 345.07 seconds
Started Mar 26 01:24:26 PM PDT 24
Finished Mar 26 01:30:11 PM PDT 24
Peak memory 273660 kb
Host smart-87eea318-0d22-4e96-881e-336cf5debe80
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592438365 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_mp_regions.1592438365
Directory /workspace/3.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/3.flash_ctrl_otp_reset.1582291097
Short name T917
Test name
Test status
Simulation time 143217900 ps
CPU time 130.54 seconds
Started Mar 26 01:23:53 PM PDT 24
Finished Mar 26 01:26:04 PM PDT 24
Peak memory 260380 kb
Host smart-fd084c66-6bf0-4b4f-aacc-a90f0aebc641
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582291097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ot
p_reset.1582291097
Directory /workspace/3.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.993929458
Short name T72
Test name
Test status
Simulation time 25311600 ps
CPU time 13.98 seconds
Started Mar 26 01:24:07 PM PDT 24
Finished Mar 26 01:24:21 PM PDT 24
Peak memory 276100 kb
Host smart-e6385d58-3a32-4374-98f4-a04548217abb
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=993929458 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.993929458
Directory /workspace/3.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb.105700274
Short name T889
Test name
Test status
Simulation time 89817100 ps
CPU time 192.69 seconds
Started Mar 26 01:23:47 PM PDT 24
Finished Mar 26 01:27:01 PM PDT 24
Peak memory 260768 kb
Host smart-ac1b262a-fb2d-48b5-a559-a84603b230e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=105700274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.105700274
Directory /workspace/3.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb_redun.2341966556
Short name T81
Test name
Test status
Simulation time 675764800 ps
CPU time 25.36 seconds
Started Mar 26 01:23:49 PM PDT 24
Finished Mar 26 01:24:15 PM PDT 24
Peak memory 264652 kb
Host smart-7ec4d479-b434-4dc7-b079-0fd3043aaaff
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341966556 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.2341966556
Directory /workspace/3.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.2267437462
Short name T976
Test name
Test status
Simulation time 46728800 ps
CPU time 13.48 seconds
Started Mar 26 01:23:52 PM PDT 24
Finished Mar 26 01:24:06 PM PDT 24
Peak memory 264020 kb
Host smart-8794a47c-a9e8-4f49-9395-2fa4c4c673c6
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267437462 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.2267437462
Directory /workspace/3.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_prog_reset.1662921409
Short name T884
Test name
Test status
Simulation time 27009700 ps
CPU time 13.6 seconds
Started Mar 26 01:23:51 PM PDT 24
Finished Mar 26 01:24:04 PM PDT 24
Peak memory 264204 kb
Host smart-f4d8d3e3-e1ea-4e8b-9c3a-a1f65d74595f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662921409 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_prog_res
et.1662921409
Directory /workspace/3.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_rand_ops.1988913670
Short name T47
Test name
Test status
Simulation time 95874000 ps
CPU time 154.79 seconds
Started Mar 26 01:23:49 PM PDT 24
Finished Mar 26 01:26:24 PM PDT 24
Peak memory 271216 kb
Host smart-ecc76453-3b19-4c09-925c-a0033763bec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988913670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.1988913670
Directory /workspace/3.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/3.flash_ctrl_rd_buff_evict.120126903
Short name T292
Test name
Test status
Simulation time 144856500 ps
CPU time 101.53 seconds
Started Mar 26 01:23:50 PM PDT 24
Finished Mar 26 01:25:32 PM PDT 24
Peak memory 264140 kb
Host smart-8eedeb6d-7309-476c-bc29-7e2a59014628
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=120126903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.120126903
Directory /workspace/3.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_re_evict.31151457
Short name T106
Test name
Test status
Simulation time 68864600 ps
CPU time 31.27 seconds
Started Mar 26 01:23:53 PM PDT 24
Finished Mar 26 01:24:24 PM PDT 24
Peak memory 272636 kb
Host smart-4eea3949-d57a-4aa1-a661-ba42ceff1e22
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31151457 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash
_ctrl_re_evict.31151457
Directory /workspace/3.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_derr.2908357595
Short name T220
Test name
Test status
Simulation time 119167800 ps
CPU time 22.38 seconds
Started Mar 26 01:23:49 PM PDT 24
Finished Mar 26 01:24:11 PM PDT 24
Peak memory 264532 kb
Host smart-8a10f8b4-1c66-4f6a-b84e-012ac8ea19e3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908357595 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_derr.2908357595
Directory /workspace/3.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_serr.1106957521
Short name T487
Test name
Test status
Simulation time 124482500 ps
CPU time 21.14 seconds
Started Mar 26 01:23:50 PM PDT 24
Finished Mar 26 01:24:12 PM PDT 24
Peak memory 263560 kb
Host smart-c8de54ee-7363-4fd0-a6db-e89c1bdc1885
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106957521 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fl
ash_ctrl_read_word_sweep_serr.1106957521
Directory /workspace/3.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro.1734481503
Short name T217
Test name
Test status
Simulation time 330264700 ps
CPU time 100.04 seconds
Started Mar 26 01:23:49 PM PDT 24
Finished Mar 26 01:25:30 PM PDT 24
Peak memory 279912 kb
Host smart-176db70e-bcf1-4694-8ad4-7b983e57ebc4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734481503 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.flash_ctrl_ro.1734481503
Directory /workspace/3.flash_ctrl_ro/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw.490107411
Short name T629
Test name
Test status
Simulation time 3309218700 ps
CPU time 504 seconds
Started Mar 26 01:23:47 PM PDT 24
Finished Mar 26 01:32:12 PM PDT 24
Peak memory 313044 kb
Host smart-50967324-7716-4db7-a6e6-c23ecea3cf10
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490107411 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctr
l_rw.490107411
Directory /workspace/3.flash_ctrl_rw/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict.3448282238
Short name T1020
Test name
Test status
Simulation time 51955700 ps
CPU time 30.87 seconds
Started Mar 26 01:23:52 PM PDT 24
Finished Mar 26 01:24:23 PM PDT 24
Peak memory 272660 kb
Host smart-c60f80ad-3497-4387-9cd7-a92fae62cc6a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448282238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_rw_evict.3448282238
Directory /workspace/3.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_info_access.2320078790
Short name T626
Test name
Test status
Simulation time 1464733000 ps
CPU time 65.67 seconds
Started Mar 26 01:23:50 PM PDT 24
Finished Mar 26 01:24:56 PM PDT 24
Peak memory 262080 kb
Host smart-e164c6ea-3509-4e27-893d-dc2ce67bc796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320078790 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.2320078790
Directory /workspace/3.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_address.444798148
Short name T910
Test name
Test status
Simulation time 3621328600 ps
CPU time 69.86 seconds
Started Mar 26 01:23:45 PM PDT 24
Finished Mar 26 01:24:55 PM PDT 24
Peak memory 264360 kb
Host smart-09e5caab-cf4f-4547-b679-db8b3bb68070
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444798148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.flash_ctrl_serr_address.444798148
Directory /workspace/3.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_counter.423709852
Short name T958
Test name
Test status
Simulation time 351733700 ps
CPU time 47.09 seconds
Started Mar 26 01:23:52 PM PDT 24
Finished Mar 26 01:24:39 PM PDT 24
Peak memory 272596 kb
Host smart-63f492a3-281d-4d9d-bd37-944ea0115c59
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423709852 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_serr_counter.423709852
Directory /workspace/3.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke.143433123
Short name T388
Test name
Test status
Simulation time 21588300 ps
CPU time 98.54 seconds
Started Mar 26 01:23:51 PM PDT 24
Finished Mar 26 01:25:30 PM PDT 24
Peak memory 275736 kb
Host smart-9b091acf-9173-4869-b050-566b9c64b916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143433123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.143433123
Directory /workspace/3.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke_hw.3389551475
Short name T433
Test name
Test status
Simulation time 48220900 ps
CPU time 26.02 seconds
Started Mar 26 01:23:51 PM PDT 24
Finished Mar 26 01:24:17 PM PDT 24
Peak memory 258060 kb
Host smart-346729b0-eced-47bc-b5d9-654ceaac4a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389551475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.3389551475
Directory /workspace/3.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/3.flash_ctrl_stress_all.400275545
Short name T967
Test name
Test status
Simulation time 1604431600 ps
CPU time 1157.6 seconds
Started Mar 26 01:23:53 PM PDT 24
Finished Mar 26 01:43:11 PM PDT 24
Peak memory 284332 kb
Host smart-839d3902-08a8-40a9-8108-a825748a5e6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400275545 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stress
_all.400275545
Directory /workspace/3.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.flash_ctrl_sw_op.262547098
Short name T483
Test name
Test status
Simulation time 291667200 ps
CPU time 26.01 seconds
Started Mar 26 01:23:48 PM PDT 24
Finished Mar 26 01:24:15 PM PDT 24
Peak memory 260400 kb
Host smart-0eb621db-33c8-493e-9b38-935cd9e84e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262547098 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.262547098
Directory /workspace/3.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_wo.1902307538
Short name T676
Test name
Test status
Simulation time 1814930400 ps
CPU time 149.85 seconds
Started Mar 26 01:23:53 PM PDT 24
Finished Mar 26 01:26:23 PM PDT 24
Peak memory 258092 kb
Host smart-a5da2826-996f-4ee5-86d3-85fdf760abc0
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902307538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.flash_ctrl_wo.1902307538
Directory /workspace/3.flash_ctrl_wo/latest

Test location /workspace/coverage/default/30.flash_ctrl_alert_test.3092257534
Short name T893
Test name
Test status
Simulation time 126836200 ps
CPU time 14.28 seconds
Started Mar 26 01:27:51 PM PDT 24
Finished Mar 26 01:28:05 PM PDT 24
Peak memory 257400 kb
Host smart-24ede7c5-6d3a-4527-8697-7ba5bb2b08fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092257534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.
3092257534
Directory /workspace/30.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.flash_ctrl_connect.215450945
Short name T477
Test name
Test status
Simulation time 17019700 ps
CPU time 16.19 seconds
Started Mar 26 01:27:52 PM PDT 24
Finished Mar 26 01:28:09 PM PDT 24
Peak memory 275004 kb
Host smart-2f4301cb-2920-4614-a91b-421aed85d1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215450945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.215450945
Directory /workspace/30.flash_ctrl_connect/latest

Test location /workspace/coverage/default/30.flash_ctrl_disable.2253901820
Short name T161
Test name
Test status
Simulation time 30219600 ps
CPU time 21.86 seconds
Started Mar 26 01:27:51 PM PDT 24
Finished Mar 26 01:28:13 PM PDT 24
Peak memory 272924 kb
Host smart-50bf1028-f2ce-41f6-8675-c52d6fd410c3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253901820 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_disable.2253901820
Directory /workspace/30.flash_ctrl_disable/latest

Test location /workspace/coverage/default/30.flash_ctrl_hw_sec_otp.3712248307
Short name T321
Test name
Test status
Simulation time 7391677700 ps
CPU time 139.55 seconds
Started Mar 26 01:27:51 PM PDT 24
Finished Mar 26 01:30:11 PM PDT 24
Peak memory 261272 kb
Host smart-e57abd9c-30da-4b41-a213-d8df8da759b4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712248307 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_
hw_sec_otp.3712248307
Directory /workspace/30.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd_slow_flash.2826557655
Short name T807
Test name
Test status
Simulation time 45388696200 ps
CPU time 217.07 seconds
Started Mar 26 01:27:49 PM PDT 24
Finished Mar 26 01:31:26 PM PDT 24
Peak memory 290232 kb
Host smart-201995f2-2dcd-4e3f-8a98-d8226cd4104c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826557655 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd_slow_flash.2826557655
Directory /workspace/30.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/30.flash_ctrl_otp_reset.4066069895
Short name T911
Test name
Test status
Simulation time 258802500 ps
CPU time 130.87 seconds
Started Mar 26 01:27:50 PM PDT 24
Finished Mar 26 01:30:01 PM PDT 24
Peak memory 260100 kb
Host smart-044ba880-04a9-49e5-a661-a3d4cc59d2a5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066069895 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_o
tp_reset.4066069895
Directory /workspace/30.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict.1257843272
Short name T747
Test name
Test status
Simulation time 65320300 ps
CPU time 28.63 seconds
Started Mar 26 01:27:53 PM PDT 24
Finished Mar 26 01:28:22 PM PDT 24
Peak memory 273596 kb
Host smart-3893685e-7239-4445-8977-a347364ecb0e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257843272 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fl
ash_ctrl_rw_evict.1257843272
Directory /workspace/30.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict_all_en.886983854
Short name T1027
Test name
Test status
Simulation time 61061300 ps
CPU time 31.15 seconds
Started Mar 26 01:27:50 PM PDT 24
Finished Mar 26 01:28:21 PM PDT 24
Peak memory 272560 kb
Host smart-1f88befd-4193-4f85-b9fa-570fb8cc3511
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886983854 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict_all_en.886983854
Directory /workspace/30.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/30.flash_ctrl_sec_info_access.2767217680
Short name T404
Test name
Test status
Simulation time 1172853700 ps
CPU time 60.05 seconds
Started Mar 26 01:27:51 PM PDT 24
Finished Mar 26 01:28:52 PM PDT 24
Peak memory 262252 kb
Host smart-ae394380-eb80-4d8f-ab8c-3e5af4bb1afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767217680 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.2767217680
Directory /workspace/30.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/30.flash_ctrl_smoke.2896155893
Short name T1044
Test name
Test status
Simulation time 31264200 ps
CPU time 97.07 seconds
Started Mar 26 01:27:51 PM PDT 24
Finished Mar 26 01:29:29 PM PDT 24
Peak memory 274436 kb
Host smart-80e1e6be-2a80-4e71-9985-5ca1cb2acc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896155893 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.2896155893
Directory /workspace/30.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/31.flash_ctrl_alert_test.1689765227
Short name T679
Test name
Test status
Simulation time 26439400 ps
CPU time 13.44 seconds
Started Mar 26 01:27:53 PM PDT 24
Finished Mar 26 01:28:06 PM PDT 24
Peak memory 257360 kb
Host smart-26658c9f-6052-4cb5-bb4a-41961027ef76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689765227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test.
1689765227
Directory /workspace/31.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.flash_ctrl_connect.276368138
Short name T702
Test name
Test status
Simulation time 87800600 ps
CPU time 15.62 seconds
Started Mar 26 01:27:52 PM PDT 24
Finished Mar 26 01:28:08 PM PDT 24
Peak memory 274780 kb
Host smart-99a2b038-4ab1-45fd-8f8f-5c9ad57c07dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276368138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.276368138
Directory /workspace/31.flash_ctrl_connect/latest

Test location /workspace/coverage/default/31.flash_ctrl_disable.1988390789
Short name T158
Test name
Test status
Simulation time 13792300 ps
CPU time 21.66 seconds
Started Mar 26 01:27:52 PM PDT 24
Finished Mar 26 01:28:13 PM PDT 24
Peak memory 272508 kb
Host smart-3983190a-b297-4ded-aef8-13bf1b25d385
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988390789 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_disable.1988390789
Directory /workspace/31.flash_ctrl_disable/latest

Test location /workspace/coverage/default/31.flash_ctrl_hw_sec_otp.1381348495
Short name T688
Test name
Test status
Simulation time 22235468000 ps
CPU time 129.65 seconds
Started Mar 26 01:27:51 PM PDT 24
Finished Mar 26 01:30:01 PM PDT 24
Peak memory 261564 kb
Host smart-4c45f674-deff-473a-8a67-738325a231dd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381348495 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_
hw_sec_otp.1381348495
Directory /workspace/31.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd_slow_flash.3456447399
Short name T1015
Test name
Test status
Simulation time 17014445700 ps
CPU time 196.69 seconds
Started Mar 26 01:27:53 PM PDT 24
Finished Mar 26 01:31:09 PM PDT 24
Peak memory 288876 kb
Host smart-10ddabec-8868-479c-8992-f0e543de2e5c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456447399 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd_slow_flash.3456447399
Directory /workspace/31.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/31.flash_ctrl_otp_reset.2032446230
Short name T538
Test name
Test status
Simulation time 35464500 ps
CPU time 108.94 seconds
Started Mar 26 01:27:55 PM PDT 24
Finished Mar 26 01:29:44 PM PDT 24
Peak memory 258856 kb
Host smart-d6b3dfc7-26d0-4aeb-b304-422b1ad8104e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032446230 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_o
tp_reset.2032446230
Directory /workspace/31.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict.1905537744
Short name T42
Test name
Test status
Simulation time 82453500 ps
CPU time 28.57 seconds
Started Mar 26 01:27:50 PM PDT 24
Finished Mar 26 01:28:19 PM PDT 24
Peak memory 266584 kb
Host smart-dbd31594-e8b9-4d13-bd0e-3162a758d797
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905537744 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fl
ash_ctrl_rw_evict.1905537744
Directory /workspace/31.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict_all_en.2078944716
Short name T337
Test name
Test status
Simulation time 151983900 ps
CPU time 30.59 seconds
Started Mar 26 01:27:53 PM PDT 24
Finished Mar 26 01:28:23 PM PDT 24
Peak memory 272608 kb
Host smart-f9802dad-9bfd-49dd-add2-f8724237a5ec
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078944716 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict_all_en.2078944716
Directory /workspace/31.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/31.flash_ctrl_sec_info_access.4211035185
Short name T639
Test name
Test status
Simulation time 878989700 ps
CPU time 72.69 seconds
Started Mar 26 01:27:51 PM PDT 24
Finished Mar 26 01:29:04 PM PDT 24
Peak memory 262664 kb
Host smart-ebbe4394-fc03-4d8f-bfaf-8a9dc6f08919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211035185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.4211035185
Directory /workspace/31.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/31.flash_ctrl_smoke.1486237222
Short name T836
Test name
Test status
Simulation time 71031900 ps
CPU time 51.91 seconds
Started Mar 26 01:27:51 PM PDT 24
Finished Mar 26 01:28:43 PM PDT 24
Peak memory 269476 kb
Host smart-6606791f-98a1-433f-af53-e81ba022a5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486237222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.1486237222
Directory /workspace/31.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/32.flash_ctrl_alert_test.698540635
Short name T1040
Test name
Test status
Simulation time 76259600 ps
CPU time 13.36 seconds
Started Mar 26 01:28:04 PM PDT 24
Finished Mar 26 01:28:18 PM PDT 24
Peak memory 257344 kb
Host smart-a751206a-08ad-4cf9-898a-61e7cfa941d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698540635 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.698540635
Directory /workspace/32.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.flash_ctrl_connect.4141946121
Short name T1042
Test name
Test status
Simulation time 51544200 ps
CPU time 15.69 seconds
Started Mar 26 01:28:04 PM PDT 24
Finished Mar 26 01:28:20 PM PDT 24
Peak memory 275164 kb
Host smart-2db3d3f9-c6e1-4d45-a555-d3345df9e502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141946121 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.4141946121
Directory /workspace/32.flash_ctrl_connect/latest

Test location /workspace/coverage/default/32.flash_ctrl_disable.1078368770
Short name T632
Test name
Test status
Simulation time 29032100 ps
CPU time 21.44 seconds
Started Mar 26 01:28:03 PM PDT 24
Finished Mar 26 01:28:26 PM PDT 24
Peak memory 272612 kb
Host smart-535a46f6-0f87-473d-8b9a-a740497960ba
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078368770 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.flash_ctrl_disable.1078368770
Directory /workspace/32.flash_ctrl_disable/latest

Test location /workspace/coverage/default/32.flash_ctrl_hw_sec_otp.1612333829
Short name T848
Test name
Test status
Simulation time 2298950100 ps
CPU time 102.35 seconds
Started Mar 26 01:27:50 PM PDT 24
Finished Mar 26 01:29:33 PM PDT 24
Peak memory 261528 kb
Host smart-e93642bc-057f-4702-942b-2015e87ef1d7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612333829 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_
hw_sec_otp.1612333829
Directory /workspace/32.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd_slow_flash.3608233788
Short name T238
Test name
Test status
Simulation time 16713809300 ps
CPU time 183.58 seconds
Started Mar 26 01:27:51 PM PDT 24
Finished Mar 26 01:30:54 PM PDT 24
Peak memory 283844 kb
Host smart-2263e398-c4d7-4355-ab5d-aec1fccfdfc3
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608233788 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd_slow_flash.3608233788
Directory /workspace/32.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/32.flash_ctrl_otp_reset.3070710046
Short name T658
Test name
Test status
Simulation time 213095600 ps
CPU time 109.18 seconds
Started Mar 26 01:27:51 PM PDT 24
Finished Mar 26 01:29:40 PM PDT 24
Peak memory 258964 kb
Host smart-6425afbe-2747-4acb-8388-fd3238caf1e4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070710046 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_o
tp_reset.3070710046
Directory /workspace/32.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict.1585749599
Short name T1043
Test name
Test status
Simulation time 881406100 ps
CPU time 34.68 seconds
Started Mar 26 01:27:53 PM PDT 24
Finished Mar 26 01:28:27 PM PDT 24
Peak memory 272500 kb
Host smart-66d3c516-3c3d-4e2f-b70b-659aaca5c8b2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585749599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fl
ash_ctrl_rw_evict.1585749599
Directory /workspace/32.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict_all_en.762902869
Short name T993
Test name
Test status
Simulation time 30516800 ps
CPU time 31.38 seconds
Started Mar 26 01:27:53 PM PDT 24
Finished Mar 26 01:28:24 PM PDT 24
Peak memory 272584 kb
Host smart-aecf2ee4-6ffb-44eb-a0cc-2230d46f3c07
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762902869 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict_all_en.762902869
Directory /workspace/32.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/32.flash_ctrl_sec_info_access.3169495
Short name T568
Test name
Test status
Simulation time 4488031300 ps
CPU time 72.65 seconds
Started Mar 26 01:28:05 PM PDT 24
Finished Mar 26 01:29:18 PM PDT 24
Peak memory 262656 kb
Host smart-28672a19-b376-4957-b8cf-65a13e8e9a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169495 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.3169495
Directory /workspace/32.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/32.flash_ctrl_smoke.4007315913
Short name T751
Test name
Test status
Simulation time 23705600 ps
CPU time 51.27 seconds
Started Mar 26 01:27:51 PM PDT 24
Finished Mar 26 01:28:43 PM PDT 24
Peak memory 269676 kb
Host smart-ceed00f1-1c7f-4992-95a4-2309186a7bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007315913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.4007315913
Directory /workspace/32.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/33.flash_ctrl_alert_test.4145654181
Short name T431
Test name
Test status
Simulation time 67828500 ps
CPU time 13.33 seconds
Started Mar 26 01:28:06 PM PDT 24
Finished Mar 26 01:28:20 PM PDT 24
Peak memory 264276 kb
Host smart-9a821673-f1a0-4829-83f8-08be5974c005
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145654181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test.
4145654181
Directory /workspace/33.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.flash_ctrl_connect.1232498833
Short name T937
Test name
Test status
Simulation time 15312600 ps
CPU time 15.95 seconds
Started Mar 26 01:28:03 PM PDT 24
Finished Mar 26 01:28:19 PM PDT 24
Peak memory 274872 kb
Host smart-6d0c5069-845e-421a-9600-6aa61f00d501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232498833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.1232498833
Directory /workspace/33.flash_ctrl_connect/latest

Test location /workspace/coverage/default/33.flash_ctrl_disable.502521165
Short name T157
Test name
Test status
Simulation time 14635600 ps
CPU time 21.41 seconds
Started Mar 26 01:28:08 PM PDT 24
Finished Mar 26 01:28:30 PM PDT 24
Peak memory 264440 kb
Host smart-f70f153e-f372-4d2d-a20a-4b9acfb07604
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502521165 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.flash_ctrl_disable.502521165
Directory /workspace/33.flash_ctrl_disable/latest

Test location /workspace/coverage/default/33.flash_ctrl_hw_sec_otp.3431945423
Short name T995
Test name
Test status
Simulation time 4713395600 ps
CPU time 100.53 seconds
Started Mar 26 01:28:03 PM PDT 24
Finished Mar 26 01:29:43 PM PDT 24
Peak memory 261660 kb
Host smart-f03e7b08-d9c2-4be9-a970-239ad6d62926
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431945423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_
hw_sec_otp.3431945423
Directory /workspace/33.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd_slow_flash.3830592120
Short name T350
Test name
Test status
Simulation time 7857366300 ps
CPU time 195.2 seconds
Started Mar 26 01:28:09 PM PDT 24
Finished Mar 26 01:31:24 PM PDT 24
Peak memory 288940 kb
Host smart-0bdf1ac1-21bb-40e7-a827-c3098a4a476b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830592120 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd_slow_flash.3830592120
Directory /workspace/33.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict.1390843172
Short name T988
Test name
Test status
Simulation time 32002000 ps
CPU time 31.55 seconds
Started Mar 26 01:28:03 PM PDT 24
Finished Mar 26 01:28:36 PM PDT 24
Peak memory 272568 kb
Host smart-5a714552-713d-4750-92d7-206efe9011e1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390843172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fl
ash_ctrl_rw_evict.1390843172
Directory /workspace/33.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict_all_en.96006274
Short name T1037
Test name
Test status
Simulation time 35148300 ps
CPU time 30.79 seconds
Started Mar 26 01:28:04 PM PDT 24
Finished Mar 26 01:28:35 PM PDT 24
Peak memory 273632 kb
Host smart-029e7055-6349-49fc-9220-4cd107e86826
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96006274 -assert nopostproc +UVM_TESTNAME=fl
ash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 33.flash_ctrl_rw_evict_all_en.96006274
Directory /workspace/33.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/33.flash_ctrl_sec_info_access.1991637037
Short name T384
Test name
Test status
Simulation time 13243085500 ps
CPU time 77.12 seconds
Started Mar 26 01:28:05 PM PDT 24
Finished Mar 26 01:29:22 PM PDT 24
Peak memory 262040 kb
Host smart-17f9819d-8a6c-4137-98a3-4026cc2e6cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991637037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.1991637037
Directory /workspace/33.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/33.flash_ctrl_smoke.4139828576
Short name T641
Test name
Test status
Simulation time 20285900 ps
CPU time 50.83 seconds
Started Mar 26 01:28:06 PM PDT 24
Finished Mar 26 01:28:57 PM PDT 24
Peak memory 269700 kb
Host smart-c6ac939b-b6ff-4940-b0c3-37c14179bd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139828576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.4139828576
Directory /workspace/33.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/34.flash_ctrl_alert_test.25711799
Short name T663
Test name
Test status
Simulation time 23765100 ps
CPU time 13.6 seconds
Started Mar 26 01:28:02 PM PDT 24
Finished Mar 26 01:28:16 PM PDT 24
Peak memory 264204 kb
Host smart-475bd0d7-ca0c-45bc-acf4-93f71e32ad7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25711799 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.25711799
Directory /workspace/34.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.flash_ctrl_connect.3680932386
Short name T817
Test name
Test status
Simulation time 38609800 ps
CPU time 15.26 seconds
Started Mar 26 01:28:04 PM PDT 24
Finished Mar 26 01:28:20 PM PDT 24
Peak memory 275132 kb
Host smart-90f015f8-38c9-406a-a80b-1edb5e3abc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680932386 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.3680932386
Directory /workspace/34.flash_ctrl_connect/latest

Test location /workspace/coverage/default/34.flash_ctrl_disable.84654378
Short name T780
Test name
Test status
Simulation time 12574100 ps
CPU time 20.14 seconds
Started Mar 26 01:28:04 PM PDT 24
Finished Mar 26 01:28:24 PM PDT 24
Peak memory 264328 kb
Host smart-c320f922-dc92-48ec-8ee3-5c2ba9e9d700
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84654378 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 34.flash_ctrl_disable.84654378
Directory /workspace/34.flash_ctrl_disable/latest

Test location /workspace/coverage/default/34.flash_ctrl_hw_sec_otp.3045198712
Short name T539
Test name
Test status
Simulation time 20721105600 ps
CPU time 133.38 seconds
Started Mar 26 01:28:05 PM PDT 24
Finished Mar 26 01:30:18 PM PDT 24
Peak memory 261672 kb
Host smart-50d305f1-f292-4b55-ab87-de1b31c3c9c7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045198712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_
hw_sec_otp.3045198712
Directory /workspace/34.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd_slow_flash.1606136874
Short name T838
Test name
Test status
Simulation time 8933906700 ps
CPU time 195.97 seconds
Started Mar 26 01:28:02 PM PDT 24
Finished Mar 26 01:31:18 PM PDT 24
Peak memory 288876 kb
Host smart-1e8640dc-851e-4bf3-be3c-636f78bef96e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606136874 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd_slow_flash.1606136874
Directory /workspace/34.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/34.flash_ctrl_otp_reset.4143110319
Short name T598
Test name
Test status
Simulation time 50646000 ps
CPU time 132.31 seconds
Started Mar 26 01:28:04 PM PDT 24
Finished Mar 26 01:30:16 PM PDT 24
Peak memory 259208 kb
Host smart-bfb5e5cd-da73-4573-be75-1561f2631080
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143110319 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_o
tp_reset.4143110319
Directory /workspace/34.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict.573162959
Short name T749
Test name
Test status
Simulation time 50299100 ps
CPU time 31.1 seconds
Started Mar 26 01:28:04 PM PDT 24
Finished Mar 26 01:28:36 PM PDT 24
Peak memory 273684 kb
Host smart-a2bd874c-25ee-493f-b209-767578edb4f9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573162959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fla
sh_ctrl_rw_evict.573162959
Directory /workspace/34.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict_all_en.2423903348
Short name T829
Test name
Test status
Simulation time 379550100 ps
CPU time 33.57 seconds
Started Mar 26 01:28:05 PM PDT 24
Finished Mar 26 01:28:39 PM PDT 24
Peak memory 272544 kb
Host smart-75888061-d370-4347-8aa7-137f7e5fc383
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423903348 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict_all_en.2423903348
Directory /workspace/34.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/34.flash_ctrl_sec_info_access.156226437
Short name T330
Test name
Test status
Simulation time 3702414100 ps
CPU time 79.76 seconds
Started Mar 26 01:28:04 PM PDT 24
Finished Mar 26 01:29:24 PM PDT 24
Peak memory 262048 kb
Host smart-bb6ec146-e742-4423-85fc-baaf4827c0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156226437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.156226437
Directory /workspace/34.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/34.flash_ctrl_smoke.1945745541
Short name T1005
Test name
Test status
Simulation time 81172800 ps
CPU time 195.18 seconds
Started Mar 26 01:28:02 PM PDT 24
Finished Mar 26 01:31:17 PM PDT 24
Peak memory 277616 kb
Host smart-d80022d9-5cd7-46c0-b127-019308caaeb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945745541 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.1945745541
Directory /workspace/34.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/35.flash_ctrl_alert_test.3264147310
Short name T645
Test name
Test status
Simulation time 71521500 ps
CPU time 13.89 seconds
Started Mar 26 01:28:02 PM PDT 24
Finished Mar 26 01:28:16 PM PDT 24
Peak memory 257236 kb
Host smart-33d4a69f-ec5d-48e5-81ca-7080be2a4af1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264147310 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test.
3264147310
Directory /workspace/35.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.flash_ctrl_disable.2151345021
Short name T86
Test name
Test status
Simulation time 13215500 ps
CPU time 21.51 seconds
Started Mar 26 01:28:06 PM PDT 24
Finished Mar 26 01:28:28 PM PDT 24
Peak memory 264396 kb
Host smart-7e78751a-1015-4bcd-99f7-6eff7f078df9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151345021 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.flash_ctrl_disable.2151345021
Directory /workspace/35.flash_ctrl_disable/latest

Test location /workspace/coverage/default/35.flash_ctrl_hw_sec_otp.272667030
Short name T500
Test name
Test status
Simulation time 5196934500 ps
CPU time 145.57 seconds
Started Mar 26 01:28:09 PM PDT 24
Finished Mar 26 01:30:35 PM PDT 24
Peak memory 261572 kb
Host smart-8c789139-496d-4f27-a8d6-e258934a8635
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272667030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_h
w_sec_otp.272667030
Directory /workspace/35.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd_slow_flash.311286768
Short name T819
Test name
Test status
Simulation time 33038063900 ps
CPU time 184.34 seconds
Started Mar 26 01:28:06 PM PDT 24
Finished Mar 26 01:31:10 PM PDT 24
Peak memory 288776 kb
Host smart-3da41dbd-c019-4435-9c10-35d7b81fcfde
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311286768 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd_slow_flash.311286768
Directory /workspace/35.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/35.flash_ctrl_otp_reset.649726856
Short name T785
Test name
Test status
Simulation time 141685100 ps
CPU time 129.71 seconds
Started Mar 26 01:28:05 PM PDT 24
Finished Mar 26 01:30:15 PM PDT 24
Peak memory 260140 kb
Host smart-51c7be6c-c15b-4319-969d-5abf559f7dd8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649726856 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_ot
p_reset.649726856
Directory /workspace/35.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict.4233160595
Short name T625
Test name
Test status
Simulation time 43588000 ps
CPU time 30.67 seconds
Started Mar 26 01:28:06 PM PDT 24
Finished Mar 26 01:28:37 PM PDT 24
Peak memory 265324 kb
Host smart-f33d8a50-80d4-4c0d-9e02-6e12026a556a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233160595 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fl
ash_ctrl_rw_evict.4233160595
Directory /workspace/35.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict_all_en.1746930794
Short name T390
Test name
Test status
Simulation time 83345200 ps
CPU time 28.27 seconds
Started Mar 26 01:28:06 PM PDT 24
Finished Mar 26 01:28:34 PM PDT 24
Peak memory 273628 kb
Host smart-4de6a8b8-cf23-4392-83a2-c601147639f3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746930794 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.flash_ctrl_rw_evict_all_en.1746930794
Directory /workspace/35.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/35.flash_ctrl_sec_info_access.4180672859
Short name T403
Test name
Test status
Simulation time 2036301400 ps
CPU time 61.96 seconds
Started Mar 26 01:28:06 PM PDT 24
Finished Mar 26 01:29:08 PM PDT 24
Peak memory 263092 kb
Host smart-2a40921e-86ca-4e76-a498-2b06ff3fb00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180672859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.4180672859
Directory /workspace/35.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/35.flash_ctrl_smoke.1439504130
Short name T387
Test name
Test status
Simulation time 38331500 ps
CPU time 117.93 seconds
Started Mar 26 01:28:03 PM PDT 24
Finished Mar 26 01:30:01 PM PDT 24
Peak memory 276180 kb
Host smart-80894431-0eca-42df-9969-b061839c4e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439504130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.1439504130
Directory /workspace/35.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/36.flash_ctrl_alert_test.942846694
Short name T685
Test name
Test status
Simulation time 31231500 ps
CPU time 13.66 seconds
Started Mar 26 01:28:18 PM PDT 24
Finished Mar 26 01:28:32 PM PDT 24
Peak memory 257340 kb
Host smart-63d9699e-917e-4681-8138-6fe8fbc5726c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942846694 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.942846694
Directory /workspace/36.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.flash_ctrl_connect.1935892540
Short name T320
Test name
Test status
Simulation time 26248700 ps
CPU time 15.92 seconds
Started Mar 26 01:28:18 PM PDT 24
Finished Mar 26 01:28:34 PM PDT 24
Peak memory 275088 kb
Host smart-4c2a7221-bdcc-444a-bbcb-f8a5185d8707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935892540 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.1935892540
Directory /workspace/36.flash_ctrl_connect/latest

Test location /workspace/coverage/default/36.flash_ctrl_disable.1604951989
Short name T813
Test name
Test status
Simulation time 25770200 ps
CPU time 21.73 seconds
Started Mar 26 01:28:16 PM PDT 24
Finished Mar 26 01:28:38 PM PDT 24
Peak memory 264412 kb
Host smart-6e680695-e90e-4d5b-8589-8d0251cf305c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604951989 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_disable.1604951989
Directory /workspace/36.flash_ctrl_disable/latest

Test location /workspace/coverage/default/36.flash_ctrl_hw_sec_otp.1756964012
Short name T870
Test name
Test status
Simulation time 6286388400 ps
CPU time 166.1 seconds
Started Mar 26 01:28:18 PM PDT 24
Finished Mar 26 01:31:04 PM PDT 24
Peak memory 261708 kb
Host smart-0a853c88-9e3b-494c-abb8-737452a1711f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756964012 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_
hw_sec_otp.1756964012
Directory /workspace/36.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.1786108135
Short name T352
Test name
Test status
Simulation time 33867237500 ps
CPU time 228.15 seconds
Started Mar 26 01:28:18 PM PDT 24
Finished Mar 26 01:32:07 PM PDT 24
Peak memory 283928 kb
Host smart-4a67fb5c-3c8d-449b-a93d-e9c31920a0c8
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786108135 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd_slow_flash.1786108135
Directory /workspace/36.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/36.flash_ctrl_otp_reset.20679903
Short name T604
Test name
Test status
Simulation time 76248800 ps
CPU time 130.62 seconds
Started Mar 26 01:28:17 PM PDT 24
Finished Mar 26 01:30:27 PM PDT 24
Peak memory 259212 kb
Host smart-7921f2e1-76eb-4ed8-80d4-96a4b201125a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20679903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_otp
_reset.20679903
Directory /workspace/36.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict.329775980
Short name T176
Test name
Test status
Simulation time 85215800 ps
CPU time 31.2 seconds
Started Mar 26 01:28:18 PM PDT 24
Finished Mar 26 01:28:49 PM PDT 24
Peak memory 272568 kb
Host smart-ca5fabd7-0e96-40f0-a916-f5977602c24d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329775980 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fla
sh_ctrl_rw_evict.329775980
Directory /workspace/36.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict_all_en.2980315814
Short name T419
Test name
Test status
Simulation time 73598700 ps
CPU time 27.71 seconds
Started Mar 26 01:28:16 PM PDT 24
Finished Mar 26 01:28:44 PM PDT 24
Peak memory 271752 kb
Host smart-4cbf209b-7497-45cc-8ce9-4215b4196c15
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980315814 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict_all_en.2980315814
Directory /workspace/36.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/36.flash_ctrl_sec_info_access.1461099785
Short name T406
Test name
Test status
Simulation time 1928753400 ps
CPU time 69.1 seconds
Started Mar 26 01:28:18 PM PDT 24
Finished Mar 26 01:29:27 PM PDT 24
Peak memory 262388 kb
Host smart-a7cf7110-971a-43b0-a35d-4a8c06c2889a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461099785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.1461099785
Directory /workspace/36.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/36.flash_ctrl_smoke.1338026189
Short name T940
Test name
Test status
Simulation time 24625100 ps
CPU time 122.34 seconds
Started Mar 26 01:28:04 PM PDT 24
Finished Mar 26 01:30:06 PM PDT 24
Peak memory 276024 kb
Host smart-a875f7a7-01af-4d17-a3c5-a4b8420fb135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338026189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.1338026189
Directory /workspace/36.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/37.flash_ctrl_alert_test.1373761703
Short name T949
Test name
Test status
Simulation time 86292200 ps
CPU time 14.18 seconds
Started Mar 26 01:28:16 PM PDT 24
Finished Mar 26 01:28:31 PM PDT 24
Peak memory 257300 kb
Host smart-a54bd6d1-5728-4e6e-96cf-2a9ffb650626
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373761703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test.
1373761703
Directory /workspace/37.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.flash_ctrl_connect.2212296591
Short name T494
Test name
Test status
Simulation time 38631400 ps
CPU time 15.52 seconds
Started Mar 26 01:28:17 PM PDT 24
Finished Mar 26 01:28:33 PM PDT 24
Peak memory 274748 kb
Host smart-abeb46e1-5464-4e13-9d9d-5a22d92f2c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212296591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.2212296591
Directory /workspace/37.flash_ctrl_connect/latest

Test location /workspace/coverage/default/37.flash_ctrl_disable.2483660740
Short name T666
Test name
Test status
Simulation time 16217500 ps
CPU time 21.93 seconds
Started Mar 26 01:28:18 PM PDT 24
Finished Mar 26 01:28:40 PM PDT 24
Peak memory 272516 kb
Host smart-3e1a725a-0a89-48f1-9617-8ac75568a6a1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483660740 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_disable.2483660740
Directory /workspace/37.flash_ctrl_disable/latest

Test location /workspace/coverage/default/37.flash_ctrl_hw_sec_otp.2192236042
Short name T714
Test name
Test status
Simulation time 3106305000 ps
CPU time 277.85 seconds
Started Mar 26 01:28:16 PM PDT 24
Finished Mar 26 01:32:54 PM PDT 24
Peak memory 261648 kb
Host smart-04272d29-1242-4d7b-9622-bbdfce6513a1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192236042 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_
hw_sec_otp.2192236042
Directory /workspace/37.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd_slow_flash.3569467560
Short name T856
Test name
Test status
Simulation time 8442148000 ps
CPU time 190.11 seconds
Started Mar 26 01:28:19 PM PDT 24
Finished Mar 26 01:31:29 PM PDT 24
Peak memory 288848 kb
Host smart-b2619c33-6c6d-4ee9-be4b-f042bdc55243
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569467560 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd_slow_flash.3569467560
Directory /workspace/37.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/37.flash_ctrl_otp_reset.2016566482
Short name T647
Test name
Test status
Simulation time 76245600 ps
CPU time 130.08 seconds
Started Mar 26 01:28:17 PM PDT 24
Finished Mar 26 01:30:27 PM PDT 24
Peak memory 259112 kb
Host smart-00c7f01f-b298-49df-ac4b-3173c05aee7f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016566482 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_o
tp_reset.2016566482
Directory /workspace/37.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict.3817306511
Short name T295
Test name
Test status
Simulation time 285778700 ps
CPU time 33.71 seconds
Started Mar 26 01:28:17 PM PDT 24
Finished Mar 26 01:28:51 PM PDT 24
Peak memory 265380 kb
Host smart-06412f10-396d-40a3-8079-b02d91991b42
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817306511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fl
ash_ctrl_rw_evict.3817306511
Directory /workspace/37.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict_all_en.3177611210
Short name T234
Test name
Test status
Simulation time 55678000 ps
CPU time 31.07 seconds
Started Mar 26 01:28:15 PM PDT 24
Finished Mar 26 01:28:47 PM PDT 24
Peak memory 275032 kb
Host smart-fdfa1a1f-13dd-4839-afb1-d200c70db01c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177611210 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict_all_en.3177611210
Directory /workspace/37.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/37.flash_ctrl_smoke.4011513573
Short name T586
Test name
Test status
Simulation time 26981700 ps
CPU time 100.31 seconds
Started Mar 26 01:28:20 PM PDT 24
Finished Mar 26 01:30:00 PM PDT 24
Peak memory 274432 kb
Host smart-38ddc51f-e2d5-41fa-baa6-3b21a6a17e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011513573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.4011513573
Directory /workspace/37.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/38.flash_ctrl_alert_test.357049190
Short name T773
Test name
Test status
Simulation time 31879900 ps
CPU time 13.41 seconds
Started Mar 26 01:28:30 PM PDT 24
Finished Mar 26 01:28:44 PM PDT 24
Peak memory 257384 kb
Host smart-dcf6945f-b3cd-4e0b-885f-6a062fc3a023
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357049190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test.357049190
Directory /workspace/38.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.flash_ctrl_connect.3109999109
Short name T533
Test name
Test status
Simulation time 28682900 ps
CPU time 15.68 seconds
Started Mar 26 01:28:30 PM PDT 24
Finished Mar 26 01:28:45 PM PDT 24
Peak memory 275120 kb
Host smart-6d8803f5-080e-4dcc-9536-8aeb7a0f5637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109999109 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.3109999109
Directory /workspace/38.flash_ctrl_connect/latest

Test location /workspace/coverage/default/38.flash_ctrl_disable.1095523529
Short name T690
Test name
Test status
Simulation time 19552200 ps
CPU time 20.56 seconds
Started Mar 26 01:28:32 PM PDT 24
Finished Mar 26 01:28:52 PM PDT 24
Peak memory 272536 kb
Host smart-40ddeb20-2108-40c0-8d47-f421e2e12ca8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095523529 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.flash_ctrl_disable.1095523529
Directory /workspace/38.flash_ctrl_disable/latest

Test location /workspace/coverage/default/38.flash_ctrl_hw_sec_otp.16739337
Short name T338
Test name
Test status
Simulation time 3242574500 ps
CPU time 158.97 seconds
Started Mar 26 01:28:16 PM PDT 24
Finished Mar 26 01:30:55 PM PDT 24
Peak memory 261712 kb
Host smart-86130ddc-2907-4e10-a55d-fba9b9573fba
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16739337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_hw
_sec_otp.16739337
Directory /workspace/38.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd_slow_flash.2354604522
Short name T569
Test name
Test status
Simulation time 18685120100 ps
CPU time 227.61 seconds
Started Mar 26 01:28:31 PM PDT 24
Finished Mar 26 01:32:19 PM PDT 24
Peak memory 288924 kb
Host smart-e22d923f-73ed-473b-954e-9e4e379a020f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354604522 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd_slow_flash.2354604522
Directory /workspace/38.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/38.flash_ctrl_otp_reset.342295590
Short name T149
Test name
Test status
Simulation time 139699400 ps
CPU time 109.28 seconds
Started Mar 26 01:28:18 PM PDT 24
Finished Mar 26 01:30:07 PM PDT 24
Peak memory 258992 kb
Host smart-e55d85df-ec55-42b2-a568-72e6f4827aa8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342295590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_ot
p_reset.342295590
Directory /workspace/38.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict_all_en.638242827
Short name T923
Test name
Test status
Simulation time 100166000 ps
CPU time 35.1 seconds
Started Mar 26 01:28:29 PM PDT 24
Finished Mar 26 01:29:04 PM PDT 24
Peak memory 273640 kb
Host smart-3565295d-4e3c-4120-adbc-4bff114047a7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638242827 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict_all_en.638242827
Directory /workspace/38.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/38.flash_ctrl_sec_info_access.486280666
Short name T31
Test name
Test status
Simulation time 1876830200 ps
CPU time 68.27 seconds
Started Mar 26 01:28:31 PM PDT 24
Finished Mar 26 01:29:39 PM PDT 24
Peak memory 262728 kb
Host smart-3f3c6d84-4a2d-4c85-8520-6260c887bf8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486280666 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.486280666
Directory /workspace/38.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/38.flash_ctrl_smoke.1763448121
Short name T206
Test name
Test status
Simulation time 201580100 ps
CPU time 74.72 seconds
Started Mar 26 01:28:16 PM PDT 24
Finished Mar 26 01:29:31 PM PDT 24
Peak memory 273164 kb
Host smart-3a14c523-4039-47c5-810f-c150441996fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763448121 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.1763448121
Directory /workspace/38.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/39.flash_ctrl_alert_test.3962247413
Short name T665
Test name
Test status
Simulation time 71832100 ps
CPU time 13.33 seconds
Started Mar 26 01:28:32 PM PDT 24
Finished Mar 26 01:28:46 PM PDT 24
Peak memory 257364 kb
Host smart-8d00411f-0abb-44a0-9f6f-0f480de2b75a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962247413 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test.
3962247413
Directory /workspace/39.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.flash_ctrl_connect.461437570
Short name T737
Test name
Test status
Simulation time 54185600 ps
CPU time 15.86 seconds
Started Mar 26 01:28:32 PM PDT 24
Finished Mar 26 01:28:48 PM PDT 24
Peak memory 275276 kb
Host smart-8ddb7d2c-d6dd-48aa-8dc4-3557aa3babb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461437570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.461437570
Directory /workspace/39.flash_ctrl_connect/latest

Test location /workspace/coverage/default/39.flash_ctrl_disable.1201563195
Short name T374
Test name
Test status
Simulation time 25477200 ps
CPU time 21.72 seconds
Started Mar 26 01:28:31 PM PDT 24
Finished Mar 26 01:28:53 PM PDT 24
Peak memory 272576 kb
Host smart-ff3319ee-fa88-42f3-b85f-c2596988e55a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201563195 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_disable.1201563195
Directory /workspace/39.flash_ctrl_disable/latest

Test location /workspace/coverage/default/39.flash_ctrl_hw_sec_otp.629442364
Short name T436
Test name
Test status
Simulation time 1779534400 ps
CPU time 121.42 seconds
Started Mar 26 01:28:34 PM PDT 24
Finished Mar 26 01:30:35 PM PDT 24
Peak memory 261920 kb
Host smart-01f2a99e-5ade-4ca2-bfee-ca69a6030056
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629442364 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_h
w_sec_otp.629442364
Directory /workspace/39.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd_slow_flash.1212167061
Short name T346
Test name
Test status
Simulation time 8167103800 ps
CPU time 274.9 seconds
Started Mar 26 01:28:30 PM PDT 24
Finished Mar 26 01:33:05 PM PDT 24
Peak memory 288844 kb
Host smart-2eed095c-78ea-477c-bdbf-1774c9c32420
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212167061 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd_slow_flash.1212167061
Directory /workspace/39.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/39.flash_ctrl_otp_reset.1526491376
Short name T1
Test name
Test status
Simulation time 314333400 ps
CPU time 130.96 seconds
Started Mar 26 01:28:32 PM PDT 24
Finished Mar 26 01:30:43 PM PDT 24
Peak memory 259088 kb
Host smart-a7fac45a-c198-4140-9778-910e65576cbd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526491376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_o
tp_reset.1526491376
Directory /workspace/39.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict.4033371746
Short name T421
Test name
Test status
Simulation time 111818700 ps
CPU time 36.94 seconds
Started Mar 26 01:28:33 PM PDT 24
Finished Mar 26 01:29:10 PM PDT 24
Peak memory 271696 kb
Host smart-d4ce84b4-b012-4416-acb7-a1fc6ba1e03a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033371746 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fl
ash_ctrl_rw_evict.4033371746
Directory /workspace/39.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict_all_en.513842260
Short name T825
Test name
Test status
Simulation time 217144100 ps
CPU time 30.34 seconds
Started Mar 26 01:28:32 PM PDT 24
Finished Mar 26 01:29:03 PM PDT 24
Peak memory 272672 kb
Host smart-21ac65c3-430e-4d62-b6d6-a70e71b1db82
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513842260 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict_all_en.513842260
Directory /workspace/39.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/39.flash_ctrl_sec_info_access.2904973196
Short name T30
Test name
Test status
Simulation time 1419009200 ps
CPU time 72.67 seconds
Started Mar 26 01:28:32 PM PDT 24
Finished Mar 26 01:29:45 PM PDT 24
Peak memory 262244 kb
Host smart-128abb12-e8bb-48b4-8b1d-952d6fb06a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904973196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.2904973196
Directory /workspace/39.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/39.flash_ctrl_smoke.1241025121
Short name T745
Test name
Test status
Simulation time 19949100 ps
CPU time 124.22 seconds
Started Mar 26 01:28:32 PM PDT 24
Finished Mar 26 01:30:36 PM PDT 24
Peak memory 275840 kb
Host smart-41d6182a-eb4d-49b3-8c72-7e438a611930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241025121 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.1241025121
Directory /workspace/39.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_alert_test.3374332430
Short name T605
Test name
Test status
Simulation time 36202800 ps
CPU time 13.54 seconds
Started Mar 26 01:24:03 PM PDT 24
Finished Mar 26 01:24:16 PM PDT 24
Peak memory 264292 kb
Host smart-6c74789e-be4a-42e8-a332-05de25a97c04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374332430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.3
374332430
Directory /workspace/4.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.flash_ctrl_config_regwen.1268691342
Short name T979
Test name
Test status
Simulation time 57272200 ps
CPU time 13.77 seconds
Started Mar 26 01:24:07 PM PDT 24
Finished Mar 26 01:24:21 PM PDT 24
Peak memory 264172 kb
Host smart-2ff7a53f-e186-4abc-9b23-61bf8ed955dd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268691342 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.flash_ctrl_config_regwen.1268691342
Directory /workspace/4.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.flash_ctrl_connect.320830532
Short name T519
Test name
Test status
Simulation time 115370900 ps
CPU time 13.15 seconds
Started Mar 26 01:24:08 PM PDT 24
Finished Mar 26 01:24:21 PM PDT 24
Peak memory 274208 kb
Host smart-3c06b23c-1c0a-4138-9e39-0f6c5626a4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320830532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.320830532
Directory /workspace/4.flash_ctrl_connect/latest

Test location /workspace/coverage/default/4.flash_ctrl_derr_detect.1940314171
Short name T197
Test name
Test status
Simulation time 136837600 ps
CPU time 101.88 seconds
Started Mar 26 01:24:11 PM PDT 24
Finished Mar 26 01:25:53 PM PDT 24
Peak memory 271480 kb
Host smart-75cde8a5-4592-4d20-bddb-0aac70568bfd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940314171 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.flash_ctrl_derr_detect.1940314171
Directory /workspace/4.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/4.flash_ctrl_disable.1071342916
Short name T531
Test name
Test status
Simulation time 35563500 ps
CPU time 22.05 seconds
Started Mar 26 01:24:15 PM PDT 24
Finished Mar 26 01:24:37 PM PDT 24
Peak memory 264428 kb
Host smart-01fca545-18cb-44e7-abd9-ad4b653dd6b9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071342916 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_disable.1071342916
Directory /workspace/4.flash_ctrl_disable/latest

Test location /workspace/coverage/default/4.flash_ctrl_erase_suspend.3623047585
Short name T798
Test name
Test status
Simulation time 756738300 ps
CPU time 293.71 seconds
Started Mar 26 01:24:07 PM PDT 24
Finished Mar 26 01:29:00 PM PDT 24
Peak memory 262044 kb
Host smart-ba78dee7-ccda-4956-be3f-022552605e59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3623047585 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.3623047585
Directory /workspace/4.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_mp.1902978377
Short name T36
Test name
Test status
Simulation time 9495810100 ps
CPU time 2230.1 seconds
Started Mar 26 01:24:11 PM PDT 24
Finished Mar 26 02:01:22 PM PDT 24
Peak memory 263816 kb
Host smart-29c67458-2bc5-4b7a-83ff-4c502c6d9269
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902978377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_err
or_mp.1902978377
Directory /workspace/4.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_type.1883912734
Short name T904
Test name
Test status
Simulation time 991110000 ps
CPU time 2581.03 seconds
Started Mar 26 01:24:11 PM PDT 24
Finished Mar 26 02:07:12 PM PDT 24
Peak memory 264104 kb
Host smart-3fa74ed3-c44a-45bb-b4b8-6836fdf29030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883912734 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_type.1883912734
Directory /workspace/4.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_win.1404900183
Short name T308
Test name
Test status
Simulation time 2084702800 ps
CPU time 714.4 seconds
Started Mar 26 01:24:08 PM PDT 24
Finished Mar 26 01:36:03 PM PDT 24
Peak memory 264248 kb
Host smart-2ed540be-22c7-4ac5-8783-55a32eb66d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404900183 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.1404900183
Directory /workspace/4.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/4.flash_ctrl_fetch_code.4208812241
Short name T446
Test name
Test status
Simulation time 136506500 ps
CPU time 25.24 seconds
Started Mar 26 01:24:08 PM PDT 24
Finished Mar 26 01:24:33 PM PDT 24
Peak memory 261112 kb
Host smart-ea14e03d-41bc-4c6b-bebc-a86d914cef00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208812241 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetch_code.4208812241
Directory /workspace/4.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/4.flash_ctrl_fs_sup.1919665870
Short name T423
Test name
Test status
Simulation time 296631500 ps
CPU time 36.27 seconds
Started Mar 26 01:24:08 PM PDT 24
Finished Mar 26 01:24:44 PM PDT 24
Peak memory 272372 kb
Host smart-4752d949-b90e-4d4e-a3bc-744dbda7b1ba
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919665870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.flash_ctrl_fs_sup.1919665870
Directory /workspace/4.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/4.flash_ctrl_full_mem_access.3931653837
Short name T1000
Test name
Test status
Simulation time 125212043900 ps
CPU time 3668.2 seconds
Started Mar 26 01:24:06 PM PDT 24
Finished Mar 26 02:25:15 PM PDT 24
Peak memory 264184 kb
Host smart-1dc6e01e-6f52-42f2-885d-a1c6371a2b58
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931653837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_c
trl_full_mem_access.3931653837
Directory /workspace/4.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.775951839
Short name T132
Test name
Test status
Simulation time 10034083500 ps
CPU time 109.03 seconds
Started Mar 26 01:24:09 PM PDT 24
Finished Mar 26 01:25:58 PM PDT 24
Peak memory 274424 kb
Host smart-b75d6e5a-dad7-42f8-97c6-20b6a8705627
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775951839 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.775951839
Directory /workspace/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_read_seed_err.2526326464
Short name T225
Test name
Test status
Simulation time 15692900 ps
CPU time 13.57 seconds
Started Mar 26 01:24:08 PM PDT 24
Finished Mar 26 01:24:21 PM PDT 24
Peak memory 258376 kb
Host smart-1a5de853-567a-4a8a-82d7-18741f9c4fd6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526326464 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_seed_err.2526326464
Directory /workspace/4.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_rma_reset.3731008873
Short name T732
Test name
Test status
Simulation time 80150064900 ps
CPU time 920.87 seconds
Started Mar 26 01:24:06 PM PDT 24
Finished Mar 26 01:39:27 PM PDT 24
Peak memory 259288 kb
Host smart-b018c238-a0fb-4799-8337-218a6ec40d6b
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731008873 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.flash_ctrl_hw_rma_reset.3731008873
Directory /workspace/4.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_sec_otp.1720450455
Short name T1046
Test name
Test status
Simulation time 3698481500 ps
CPU time 118.51 seconds
Started Mar 26 01:24:06 PM PDT 24
Finished Mar 26 01:26:05 PM PDT 24
Peak memory 261696 kb
Host smart-09688835-104d-42a7-9582-bf9963881aa2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720450455 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_h
w_sec_otp.1720450455
Directory /workspace/4.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd_slow_flash.1241639332
Short name T912
Test name
Test status
Simulation time 8958271500 ps
CPU time 210.81 seconds
Started Mar 26 01:24:16 PM PDT 24
Finished Mar 26 01:27:47 PM PDT 24
Peak memory 290432 kb
Host smart-39c4dc2d-c45c-4839-95c9-b726bdbb7af2
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241639332 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd_slow_flash.1241639332
Directory /workspace/4.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr.4022715574
Short name T554
Test name
Test status
Simulation time 7523045000 ps
CPU time 90.7 seconds
Started Mar 26 01:24:10 PM PDT 24
Finished Mar 26 01:25:40 PM PDT 24
Peak memory 261104 kb
Host smart-037ffccc-79c7-415e-870a-b6a7d0146613
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022715574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.flash_ctrl_intr_wr.4022715574
Directory /workspace/4.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr_slow_flash.3725094096
Short name T602
Test name
Test status
Simulation time 46787627600 ps
CPU time 372.46 seconds
Started Mar 26 01:24:17 PM PDT 24
Finished Mar 26 01:30:29 PM PDT 24
Peak memory 260480 kb
Host smart-90a2cbe6-62b3-4ad3-ba2b-ac89f1ac0feb
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372
5094096 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.3725094096
Directory /workspace/4.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_invalid_op.914454351
Short name T413
Test name
Test status
Simulation time 8331178700 ps
CPU time 78.99 seconds
Started Mar 26 01:24:13 PM PDT 24
Finished Mar 26 01:25:32 PM PDT 24
Peak memory 259704 kb
Host smart-8856475e-5cfd-4f6f-a9ec-8be615557ede
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914454351 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.914454351
Directory /workspace/4.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_lcmgr_intg.3508198475
Short name T989
Test name
Test status
Simulation time 15380300 ps
CPU time 13.32 seconds
Started Mar 26 01:24:05 PM PDT 24
Finished Mar 26 01:24:19 PM PDT 24
Peak memory 258808 kb
Host smart-a952215d-bb6d-4f63-bb5b-e29fb7ebce22
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508198475 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.flash_ctrl_lcmgr_intg.3508198475
Directory /workspace/4.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/4.flash_ctrl_mp_regions.485957805
Short name T96
Test name
Test status
Simulation time 37017482500 ps
CPU time 973.37 seconds
Started Mar 26 01:24:07 PM PDT 24
Finished Mar 26 01:40:21 PM PDT 24
Peak memory 273252 kb
Host smart-ff48c04d-adb1-4170-9d7a-f23827d21fbc
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485957805 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_mp_regions.485957805
Directory /workspace/4.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/4.flash_ctrl_otp_reset.2777854244
Short name T812
Test name
Test status
Simulation time 76204200 ps
CPU time 129.95 seconds
Started Mar 26 01:24:05 PM PDT 24
Finished Mar 26 01:26:16 PM PDT 24
Peak memory 259004 kb
Host smart-cf4d67fa-0554-4ffb-9818-6899142cc8cc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777854244 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ot
p_reset.2777854244
Directory /workspace/4.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_ack_consistency.2839546870
Short name T235
Test name
Test status
Simulation time 25490700 ps
CPU time 13.84 seconds
Started Mar 26 01:24:05 PM PDT 24
Finished Mar 26 01:24:19 PM PDT 24
Peak memory 264564 kb
Host smart-db697b94-871c-444f-8be9-6841962dec45
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2839546870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.2839546870
Directory /workspace/4.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb.2909259354
Short name T921
Test name
Test status
Simulation time 103482900 ps
CPU time 68.41 seconds
Started Mar 26 01:24:04 PM PDT 24
Finished Mar 26 01:25:13 PM PDT 24
Peak memory 261360 kb
Host smart-b5f25d0c-aff6-4043-aa3d-6ea71869e30c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2909259354 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.2909259354
Directory /workspace/4.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb_redun.2890714574
Short name T82
Test name
Test status
Simulation time 885222000 ps
CPU time 32.25 seconds
Started Mar 26 01:24:07 PM PDT 24
Finished Mar 26 01:24:40 PM PDT 24
Peak memory 263768 kb
Host smart-29be4219-43ff-4b1a-9c52-ebb068d97b79
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890714574 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.2890714574
Directory /workspace/4.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/4.flash_ctrl_prog_reset.1991673441
Short name T931
Test name
Test status
Simulation time 174276800 ps
CPU time 13.69 seconds
Started Mar 26 01:24:08 PM PDT 24
Finished Mar 26 01:24:22 PM PDT 24
Peak memory 264204 kb
Host smart-55df58fb-f7b8-4dd8-a23b-3eb1e1767160
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991673441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_prog_res
et.1991673441
Directory /workspace/4.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_rand_ops.560038
Short name T113
Test name
Test status
Simulation time 113163300 ps
CPU time 317.98 seconds
Started Mar 26 01:24:06 PM PDT 24
Finished Mar 26 01:29:24 PM PDT 24
Peak memory 280612 kb
Host smart-12dfb480-36d4-4375-ac66-f65fb8bef160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560038 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.560038
Directory /workspace/4.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/4.flash_ctrl_rd_buff_evict.2470666176
Short name T849
Test name
Test status
Simulation time 1787019300 ps
CPU time 114.79 seconds
Started Mar 26 01:24:07 PM PDT 24
Finished Mar 26 01:26:02 PM PDT 24
Peak memory 264256 kb
Host smart-1ce161bb-87e2-4079-8228-f6dcd646b402
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2470666176 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.2470666176
Directory /workspace/4.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_re_evict.3145122998
Short name T984
Test name
Test status
Simulation time 143884700 ps
CPU time 40.16 seconds
Started Mar 26 01:24:17 PM PDT 24
Finished Mar 26 01:24:57 PM PDT 24
Peak memory 272568 kb
Host smart-e6080d0e-9731-4245-a09e-635e8e046342
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145122998 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_re_evict.3145122998
Directory /workspace/4.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.742841088
Short name T214
Test name
Test status
Simulation time 18922000 ps
CPU time 22.54 seconds
Started Mar 26 01:24:10 PM PDT 24
Finished Mar 26 01:24:33 PM PDT 24
Peak memory 264312 kb
Host smart-414f6ab6-52ad-40a9-8582-bddaec4a8c32
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742841088 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_derr.742841088
Directory /workspace/4.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_serr.3282863137
Short name T40
Test name
Test status
Simulation time 85040800 ps
CPU time 21.31 seconds
Started Mar 26 01:24:13 PM PDT 24
Finished Mar 26 01:24:35 PM PDT 24
Peak memory 263656 kb
Host smart-3f099146-1b5d-42ba-ab5d-388c85a7bfac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282863137 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fl
ash_ctrl_read_word_sweep_serr.3282863137
Directory /workspace/4.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro.3793836550
Short name T265
Test name
Test status
Simulation time 924480200 ps
CPU time 98.29 seconds
Started Mar 26 01:24:11 PM PDT 24
Finished Mar 26 01:25:50 PM PDT 24
Peak memory 280048 kb
Host smart-49b300a9-99d5-4b56-ae37-41b425484341
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793836550 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.flash_ctrl_ro.3793836550
Directory /workspace/4.flash_ctrl_ro/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict.1347625058
Short name T25
Test name
Test status
Simulation time 39255100 ps
CPU time 29.33 seconds
Started Mar 26 01:24:11 PM PDT 24
Finished Mar 26 01:24:40 PM PDT 24
Peak memory 272612 kb
Host smart-750e7932-038d-444e-850c-45e2e81ee361
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347625058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_rw_evict.1347625058
Directory /workspace/4.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict_all_en.627568761
Short name T571
Test name
Test status
Simulation time 125269300 ps
CPU time 30.35 seconds
Started Mar 26 01:24:12 PM PDT 24
Finished Mar 26 01:24:43 PM PDT 24
Peak memory 272532 kb
Host smart-9b7174db-c63c-491f-ab08-a280cf61a95c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627568761 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict_all_en.627568761
Directory /workspace/4.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_cm.3953597175
Short name T191
Test name
Test status
Simulation time 15869987700 ps
CPU time 4661.69 seconds
Started Mar 26 01:24:08 PM PDT 24
Finished Mar 26 02:41:51 PM PDT 24
Peak memory 282888 kb
Host smart-8233bbaf-d5e6-461f-86a4-1bed8f0518dd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953597175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.3953597175
Directory /workspace/4.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_info_access.142789473
Short name T977
Test name
Test status
Simulation time 20722670000 ps
CPU time 66.29 seconds
Started Mar 26 01:24:08 PM PDT 24
Finished Mar 26 01:25:14 PM PDT 24
Peak memory 262172 kb
Host smart-87233c67-cde9-49a0-9948-0efccf10b7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142789473 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.142789473
Directory /workspace/4.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_address.2339596335
Short name T716
Test name
Test status
Simulation time 1142783000 ps
CPU time 60.77 seconds
Started Mar 26 01:24:11 PM PDT 24
Finished Mar 26 01:25:12 PM PDT 24
Peak memory 264324 kb
Host smart-3bb48eae-880e-4c8a-b89d-92c4d75bf3a9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339596335 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_serr_address.2339596335
Directory /workspace/4.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke.3726011476
Short name T495
Test name
Test status
Simulation time 26829700 ps
CPU time 74.85 seconds
Started Mar 26 01:24:09 PM PDT 24
Finished Mar 26 01:25:24 PM PDT 24
Peak memory 275224 kb
Host smart-ba7e12ec-a06f-4af2-86e4-a4da3fe4f6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726011476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.3726011476
Directory /workspace/4.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke_hw.585022885
Short name T331
Test name
Test status
Simulation time 45588200 ps
CPU time 25.8 seconds
Started Mar 26 01:24:11 PM PDT 24
Finished Mar 26 01:24:37 PM PDT 24
Peak memory 258080 kb
Host smart-d918b1f2-8a8a-462f-8982-9e1c0281304a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585022885 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.585022885
Directory /workspace/4.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/4.flash_ctrl_sw_op.2843327476
Short name T100
Test name
Test status
Simulation time 82995900 ps
CPU time 24.11 seconds
Started Mar 26 01:24:08 PM PDT 24
Finished Mar 26 01:24:32 PM PDT 24
Peak memory 258100 kb
Host smart-8c059843-c408-4cc4-ba13-45ad134606cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843327476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.2843327476
Directory /workspace/4.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_wo.1577669882
Short name T818
Test name
Test status
Simulation time 4698996400 ps
CPU time 208.11 seconds
Started Mar 26 01:24:14 PM PDT 24
Finished Mar 26 01:27:42 PM PDT 24
Peak memory 258640 kb
Host smart-d761ffeb-102d-4a75-9ab0-122e41d93327
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577669882 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.flash_ctrl_wo.1577669882
Directory /workspace/4.flash_ctrl_wo/latest

Test location /workspace/coverage/default/40.flash_ctrl_alert_test.4049242929
Short name T584
Test name
Test status
Simulation time 159507000 ps
CPU time 13.66 seconds
Started Mar 26 01:28:31 PM PDT 24
Finished Mar 26 01:28:45 PM PDT 24
Peak memory 257336 kb
Host smart-4c0911f1-ce29-4ad9-90cc-0ba5d5f849d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049242929 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test.
4049242929
Directory /workspace/40.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.flash_ctrl_connect.3447085918
Short name T439
Test name
Test status
Simulation time 41212300 ps
CPU time 15.65 seconds
Started Mar 26 01:28:29 PM PDT 24
Finished Mar 26 01:28:45 PM PDT 24
Peak memory 274812 kb
Host smart-0f87180d-c03c-4296-8ad7-69ba5e2b0b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447085918 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.3447085918
Directory /workspace/40.flash_ctrl_connect/latest

Test location /workspace/coverage/default/40.flash_ctrl_hw_sec_otp.2312683197
Short name T705
Test name
Test status
Simulation time 2180039400 ps
CPU time 87.48 seconds
Started Mar 26 01:28:31 PM PDT 24
Finished Mar 26 01:29:59 PM PDT 24
Peak memory 261604 kb
Host smart-8b1665fb-d724-4705-a7bb-dbb3f1cd47d6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312683197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_
hw_sec_otp.2312683197
Directory /workspace/40.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/40.flash_ctrl_otp_reset.2124115725
Short name T651
Test name
Test status
Simulation time 422478300 ps
CPU time 110.55 seconds
Started Mar 26 01:28:31 PM PDT 24
Finished Mar 26 01:30:22 PM PDT 24
Peak memory 263484 kb
Host smart-ebf33366-fbfd-42bc-b50b-0c53884d11fc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124115725 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_o
tp_reset.2124115725
Directory /workspace/40.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/40.flash_ctrl_sec_info_access.1191481367
Short name T241
Test name
Test status
Simulation time 804501100 ps
CPU time 55.89 seconds
Started Mar 26 01:28:29 PM PDT 24
Finished Mar 26 01:29:25 PM PDT 24
Peak memory 261892 kb
Host smart-31501e40-8726-430a-9675-d6ed8e9a89ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191481367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.1191481367
Directory /workspace/40.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/40.flash_ctrl_smoke.3439460706
Short name T251
Test name
Test status
Simulation time 72135300 ps
CPU time 141 seconds
Started Mar 26 01:28:31 PM PDT 24
Finished Mar 26 01:30:52 PM PDT 24
Peak memory 276588 kb
Host smart-45f931d3-a0fe-438b-a323-b3c04c26d842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439460706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.3439460706
Directory /workspace/40.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/41.flash_ctrl_alert_test.2045273343
Short name T429
Test name
Test status
Simulation time 36377100 ps
CPU time 13.3 seconds
Started Mar 26 01:28:40 PM PDT 24
Finished Mar 26 01:28:53 PM PDT 24
Peak memory 257368 kb
Host smart-4c1d402a-7b2a-4f76-ac98-ec4dd980b7ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045273343 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test.
2045273343
Directory /workspace/41.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.flash_ctrl_connect.2772953229
Short name T781
Test name
Test status
Simulation time 103118500 ps
CPU time 13.31 seconds
Started Mar 26 01:28:31 PM PDT 24
Finished Mar 26 01:28:44 PM PDT 24
Peak memory 275072 kb
Host smart-74a13fae-64a5-4f83-9c02-93439e1b45b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772953229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.2772953229
Directory /workspace/41.flash_ctrl_connect/latest

Test location /workspace/coverage/default/41.flash_ctrl_disable.1577700758
Short name T671
Test name
Test status
Simulation time 12808200 ps
CPU time 22.17 seconds
Started Mar 26 01:28:34 PM PDT 24
Finished Mar 26 01:28:56 PM PDT 24
Peak memory 272584 kb
Host smart-3a337529-e450-4b9d-9a03-76c2986a7a01
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577700758 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.flash_ctrl_disable.1577700758
Directory /workspace/41.flash_ctrl_disable/latest

Test location /workspace/coverage/default/41.flash_ctrl_hw_sec_otp.409388006
Short name T596
Test name
Test status
Simulation time 17085700800 ps
CPU time 137.09 seconds
Started Mar 26 01:28:30 PM PDT 24
Finished Mar 26 01:30:47 PM PDT 24
Peak memory 260956 kb
Host smart-dfa78407-b8a7-430e-9f73-31fa7df74f71
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409388006 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_h
w_sec_otp.409388006
Directory /workspace/41.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/41.flash_ctrl_otp_reset.4038449069
Short name T102
Test name
Test status
Simulation time 73390500 ps
CPU time 129.9 seconds
Started Mar 26 01:28:31 PM PDT 24
Finished Mar 26 01:30:41 PM PDT 24
Peak memory 259356 kb
Host smart-057d6ed4-9bab-448b-bf6d-57194fedd71a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038449069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_o
tp_reset.4038449069
Directory /workspace/41.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/41.flash_ctrl_sec_info_access.812415574
Short name T991
Test name
Test status
Simulation time 3120856900 ps
CPU time 78.2 seconds
Started Mar 26 01:28:32 PM PDT 24
Finished Mar 26 01:29:50 PM PDT 24
Peak memory 261896 kb
Host smart-ef2d8769-81e5-4093-9728-ab958ae7c714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812415574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.812415574
Directory /workspace/41.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/41.flash_ctrl_smoke.4154029791
Short name T834
Test name
Test status
Simulation time 195434600 ps
CPU time 98.95 seconds
Started Mar 26 01:28:30 PM PDT 24
Finished Mar 26 01:30:09 PM PDT 24
Peak memory 274216 kb
Host smart-6c5d55fa-1f36-49b4-9d7c-8c32480ac166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154029791 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.4154029791
Directory /workspace/41.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/42.flash_ctrl_alert_test.2433279125
Short name T722
Test name
Test status
Simulation time 42340100 ps
CPU time 13.83 seconds
Started Mar 26 01:28:44 PM PDT 24
Finished Mar 26 01:28:58 PM PDT 24
Peak memory 257312 kb
Host smart-b3f93d27-a48d-4d9b-9c1c-a067768d4601
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433279125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test.
2433279125
Directory /workspace/42.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.flash_ctrl_connect.1971189291
Short name T1019
Test name
Test status
Simulation time 53759700 ps
CPU time 13.23 seconds
Started Mar 26 01:28:42 PM PDT 24
Finished Mar 26 01:28:57 PM PDT 24
Peak memory 274800 kb
Host smart-43e52a76-5e29-46ba-bad1-ee2aaff17b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971189291 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.1971189291
Directory /workspace/42.flash_ctrl_connect/latest

Test location /workspace/coverage/default/42.flash_ctrl_disable.3564007509
Short name T767
Test name
Test status
Simulation time 20555000 ps
CPU time 21.71 seconds
Started Mar 26 01:28:30 PM PDT 24
Finished Mar 26 01:28:52 PM PDT 24
Peak memory 272640 kb
Host smart-da59840c-59dc-49f1-bf27-e193f8e5aadc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564007509 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.flash_ctrl_disable.3564007509
Directory /workspace/42.flash_ctrl_disable/latest

Test location /workspace/coverage/default/42.flash_ctrl_hw_sec_otp.1310798612
Short name T461
Test name
Test status
Simulation time 24928663400 ps
CPU time 127.92 seconds
Started Mar 26 01:28:33 PM PDT 24
Finished Mar 26 01:30:41 PM PDT 24
Peak memory 261208 kb
Host smart-8574c532-916b-46e7-a12f-5885a6a2f9d5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310798612 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_
hw_sec_otp.1310798612
Directory /workspace/42.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/42.flash_ctrl_otp_reset.1336123704
Short name T535
Test name
Test status
Simulation time 151773900 ps
CPU time 133.27 seconds
Started Mar 26 01:28:33 PM PDT 24
Finished Mar 26 01:30:47 PM PDT 24
Peak memory 263488 kb
Host smart-8939f864-7654-4e92-8948-fe205578c476
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336123704 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_o
tp_reset.1336123704
Directory /workspace/42.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/42.flash_ctrl_sec_info_access.3587554435
Short name T634
Test name
Test status
Simulation time 947347300 ps
CPU time 56.81 seconds
Started Mar 26 01:28:41 PM PDT 24
Finished Mar 26 01:29:38 PM PDT 24
Peak memory 262248 kb
Host smart-9599c289-0c54-4d5e-bae8-4cbcbffad69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587554435 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.3587554435
Directory /workspace/42.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/42.flash_ctrl_smoke.2103286800
Short name T590
Test name
Test status
Simulation time 43168500 ps
CPU time 147.5 seconds
Started Mar 26 01:28:30 PM PDT 24
Finished Mar 26 01:30:58 PM PDT 24
Peak memory 276616 kb
Host smart-69a30d03-9d16-4aae-8156-17309c41db4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103286800 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.2103286800
Directory /workspace/42.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/43.flash_ctrl_alert_test.3533581207
Short name T207
Test name
Test status
Simulation time 158538600 ps
CPU time 13.24 seconds
Started Mar 26 01:28:41 PM PDT 24
Finished Mar 26 01:28:55 PM PDT 24
Peak memory 264208 kb
Host smart-8953b6ee-c73f-4ee2-9520-c6ddb315198a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533581207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test.
3533581207
Directory /workspace/43.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.flash_ctrl_connect.1286252708
Short name T464
Test name
Test status
Simulation time 24800600 ps
CPU time 13.14 seconds
Started Mar 26 01:28:42 PM PDT 24
Finished Mar 26 01:28:55 PM PDT 24
Peak memory 274808 kb
Host smart-6f14addf-80f3-4329-8581-557109ae9ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286252708 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.1286252708
Directory /workspace/43.flash_ctrl_connect/latest

Test location /workspace/coverage/default/43.flash_ctrl_disable.3795334276
Short name T57
Test name
Test status
Simulation time 13152600 ps
CPU time 21.79 seconds
Started Mar 26 01:28:45 PM PDT 24
Finished Mar 26 01:29:07 PM PDT 24
Peak memory 272680 kb
Host smart-431fb879-4fa7-4cae-9c46-4e29ed228a01
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795334276 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.flash_ctrl_disable.3795334276
Directory /workspace/43.flash_ctrl_disable/latest

Test location /workspace/coverage/default/43.flash_ctrl_hw_sec_otp.1559789762
Short name T508
Test name
Test status
Simulation time 927552700 ps
CPU time 43.95 seconds
Started Mar 26 01:28:46 PM PDT 24
Finished Mar 26 01:29:30 PM PDT 24
Peak memory 261512 kb
Host smart-0f5997b4-7cfb-478e-b978-c495c6dd3a8c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559789762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_
hw_sec_otp.1559789762
Directory /workspace/43.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/43.flash_ctrl_otp_reset.198018991
Short name T966
Test name
Test status
Simulation time 41013700 ps
CPU time 129.99 seconds
Started Mar 26 01:28:43 PM PDT 24
Finished Mar 26 01:30:53 PM PDT 24
Peak memory 259104 kb
Host smart-a6325cc7-97af-4bfd-9890-dfa48e4f2735
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198018991 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_ot
p_reset.198018991
Directory /workspace/43.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/43.flash_ctrl_sec_info_access.1020951275
Short name T407
Test name
Test status
Simulation time 6358003300 ps
CPU time 72.24 seconds
Started Mar 26 01:28:44 PM PDT 24
Finished Mar 26 01:29:57 PM PDT 24
Peak memory 263188 kb
Host smart-ee639a78-ef41-4b74-ad76-c57cab70de89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020951275 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.1020951275
Directory /workspace/43.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/43.flash_ctrl_smoke.1020377174
Short name T953
Test name
Test status
Simulation time 48468100 ps
CPU time 74.81 seconds
Started Mar 26 01:28:42 PM PDT 24
Finished Mar 26 01:29:57 PM PDT 24
Peak memory 274196 kb
Host smart-f2a4503f-8041-49c3-9c4f-f841be4250ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020377174 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.1020377174
Directory /workspace/43.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/44.flash_ctrl_alert_test.4286883753
Short name T710
Test name
Test status
Simulation time 90492400 ps
CPU time 13.83 seconds
Started Mar 26 01:28:42 PM PDT 24
Finished Mar 26 01:28:56 PM PDT 24
Peak memory 257404 kb
Host smart-4f7773d8-663d-4d46-b93e-3ae1f046aae2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286883753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.
4286883753
Directory /workspace/44.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.flash_ctrl_connect.1783062244
Short name T654
Test name
Test status
Simulation time 53344600 ps
CPU time 13.55 seconds
Started Mar 26 01:28:46 PM PDT 24
Finished Mar 26 01:29:00 PM PDT 24
Peak memory 274824 kb
Host smart-7364bd7b-8893-49cc-8f82-2468f09e332f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783062244 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.1783062244
Directory /workspace/44.flash_ctrl_connect/latest

Test location /workspace/coverage/default/44.flash_ctrl_disable.4006201894
Short name T560
Test name
Test status
Simulation time 49238100 ps
CPU time 22.1 seconds
Started Mar 26 01:28:42 PM PDT 24
Finished Mar 26 01:29:04 PM PDT 24
Peak memory 279864 kb
Host smart-da49e0ed-34e1-423b-b731-01e87196fec2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006201894 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.flash_ctrl_disable.4006201894
Directory /workspace/44.flash_ctrl_disable/latest

Test location /workspace/coverage/default/44.flash_ctrl_hw_sec_otp.1661374839
Short name T799
Test name
Test status
Simulation time 10903342400 ps
CPU time 156.88 seconds
Started Mar 26 01:28:46 PM PDT 24
Finished Mar 26 01:31:23 PM PDT 24
Peak memory 261440 kb
Host smart-330bb55a-e2be-4098-9899-aacda8f98c94
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661374839 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_
hw_sec_otp.1661374839
Directory /workspace/44.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/44.flash_ctrl_otp_reset.729075174
Short name T536
Test name
Test status
Simulation time 266196100 ps
CPU time 128.95 seconds
Started Mar 26 01:28:41 PM PDT 24
Finished Mar 26 01:30:50 PM PDT 24
Peak memory 263920 kb
Host smart-47138c30-0bd5-40de-8346-3ab0a82d789c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729075174 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_ot
p_reset.729075174
Directory /workspace/44.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/44.flash_ctrl_sec_info_access.1067066970
Short name T448
Test name
Test status
Simulation time 5245076200 ps
CPU time 72.44 seconds
Started Mar 26 01:28:41 PM PDT 24
Finished Mar 26 01:29:55 PM PDT 24
Peak memory 261980 kb
Host smart-02d7c466-b4a8-4114-8f81-6f6698af2363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067066970 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.1067066970
Directory /workspace/44.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/44.flash_ctrl_smoke.647015584
Short name T615
Test name
Test status
Simulation time 41575300 ps
CPU time 122.17 seconds
Started Mar 26 01:28:41 PM PDT 24
Finished Mar 26 01:30:44 PM PDT 24
Peak memory 275960 kb
Host smart-3415a348-2b71-4a8e-bdff-98f33ea10ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647015584 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.647015584
Directory /workspace/44.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/45.flash_ctrl_alert_test.2775576017
Short name T466
Test name
Test status
Simulation time 51390800 ps
CPU time 13.41 seconds
Started Mar 26 01:28:43 PM PDT 24
Finished Mar 26 01:28:57 PM PDT 24
Peak memory 257328 kb
Host smart-8235676f-7b09-462a-9653-3369ce6ecebd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775576017 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.
2775576017
Directory /workspace/45.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.flash_ctrl_connect.2329921079
Short name T694
Test name
Test status
Simulation time 21487700 ps
CPU time 15.9 seconds
Started Mar 26 01:28:46 PM PDT 24
Finished Mar 26 01:29:02 PM PDT 24
Peak memory 274712 kb
Host smart-c215fa6e-0b15-4ac0-886f-a982e7ea0d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329921079 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.2329921079
Directory /workspace/45.flash_ctrl_connect/latest

Test location /workspace/coverage/default/45.flash_ctrl_disable.1197175210
Short name T830
Test name
Test status
Simulation time 28553700 ps
CPU time 21.89 seconds
Started Mar 26 01:28:41 PM PDT 24
Finished Mar 26 01:29:03 PM PDT 24
Peak memory 264372 kb
Host smart-2c28e3f6-6132-4225-87e7-2e4bc603dab7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197175210 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.flash_ctrl_disable.1197175210
Directory /workspace/45.flash_ctrl_disable/latest

Test location /workspace/coverage/default/45.flash_ctrl_hw_sec_otp.77293479
Short name T70
Test name
Test status
Simulation time 1380478800 ps
CPU time 59.58 seconds
Started Mar 26 01:28:43 PM PDT 24
Finished Mar 26 01:29:43 PM PDT 24
Peak memory 261552 kb
Host smart-18dd692f-673f-4773-8344-3b7c0fdd15cf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77293479 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_hw
_sec_otp.77293479
Directory /workspace/45.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/45.flash_ctrl_otp_reset.934692473
Short name T624
Test name
Test status
Simulation time 69057900 ps
CPU time 129.95 seconds
Started Mar 26 01:28:42 PM PDT 24
Finished Mar 26 01:30:52 PM PDT 24
Peak memory 263596 kb
Host smart-139ef846-2e40-4564-b21e-4e90adc4faff
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934692473 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_ot
p_reset.934692473
Directory /workspace/45.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/45.flash_ctrl_sec_info_access.3746299612
Short name T643
Test name
Test status
Simulation time 5024217200 ps
CPU time 61.29 seconds
Started Mar 26 01:28:41 PM PDT 24
Finished Mar 26 01:29:43 PM PDT 24
Peak memory 262360 kb
Host smart-08f40364-7d0f-4713-bd64-9c1d03a09924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746299612 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.3746299612
Directory /workspace/45.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/45.flash_ctrl_smoke.1978102698
Short name T692
Test name
Test status
Simulation time 40601000 ps
CPU time 77.36 seconds
Started Mar 26 01:28:44 PM PDT 24
Finished Mar 26 01:30:02 PM PDT 24
Peak memory 273396 kb
Host smart-6a82554c-8dcb-4116-b5d2-ee65ce08250d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978102698 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.1978102698
Directory /workspace/45.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/46.flash_ctrl_alert_test.1193065235
Short name T521
Test name
Test status
Simulation time 63258300 ps
CPU time 13.68 seconds
Started Mar 26 01:28:44 PM PDT 24
Finished Mar 26 01:28:58 PM PDT 24
Peak memory 257308 kb
Host smart-ae255ed8-8ccd-455f-afa0-e698883deb0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193065235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.
1193065235
Directory /workspace/46.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.flash_ctrl_connect.1442727895
Short name T438
Test name
Test status
Simulation time 14286300 ps
CPU time 13.22 seconds
Started Mar 26 01:28:43 PM PDT 24
Finished Mar 26 01:28:57 PM PDT 24
Peak memory 274892 kb
Host smart-202f3054-6b7e-4bdd-8cf3-e770bd8a1acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442727895 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.1442727895
Directory /workspace/46.flash_ctrl_connect/latest

Test location /workspace/coverage/default/46.flash_ctrl_disable.3189812712
Short name T614
Test name
Test status
Simulation time 27726100 ps
CPU time 21.97 seconds
Started Mar 26 01:28:42 PM PDT 24
Finished Mar 26 01:29:05 PM PDT 24
Peak memory 272676 kb
Host smart-2a9dce21-d8e4-4d5f-9186-fe226fa6b700
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189812712 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.flash_ctrl_disable.3189812712
Directory /workspace/46.flash_ctrl_disable/latest

Test location /workspace/coverage/default/46.flash_ctrl_hw_sec_otp.182990011
Short name T573
Test name
Test status
Simulation time 988122000 ps
CPU time 63.26 seconds
Started Mar 26 01:28:45 PM PDT 24
Finished Mar 26 01:29:49 PM PDT 24
Peak memory 261688 kb
Host smart-36aad42a-f67a-4247-a5c1-6974fba38de6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182990011 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_h
w_sec_otp.182990011
Directory /workspace/46.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/46.flash_ctrl_sec_info_access.762510066
Short name T1007
Test name
Test status
Simulation time 5804921700 ps
CPU time 72.49 seconds
Started Mar 26 01:28:42 PM PDT 24
Finished Mar 26 01:29:55 PM PDT 24
Peak memory 263048 kb
Host smart-db5429b9-7900-4a81-b91d-8a66a57add43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762510066 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.762510066
Directory /workspace/46.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/46.flash_ctrl_smoke.2047491866
Short name T517
Test name
Test status
Simulation time 26850500 ps
CPU time 101.65 seconds
Started Mar 26 01:28:42 PM PDT 24
Finished Mar 26 01:30:24 PM PDT 24
Peak memory 275376 kb
Host smart-e46ab674-f977-4f18-a87c-10c749dfa786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047491866 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.2047491866
Directory /workspace/46.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/47.flash_ctrl_alert_test.3872915907
Short name T502
Test name
Test status
Simulation time 65956400 ps
CPU time 13.81 seconds
Started Mar 26 01:28:55 PM PDT 24
Finished Mar 26 01:29:10 PM PDT 24
Peak memory 264232 kb
Host smart-85b30fa7-4129-4b4d-9195-faa8e654f3c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872915907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test.
3872915907
Directory /workspace/47.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.flash_ctrl_connect.2392646081
Short name T983
Test name
Test status
Simulation time 51568000 ps
CPU time 13.24 seconds
Started Mar 26 01:28:55 PM PDT 24
Finished Mar 26 01:29:09 PM PDT 24
Peak memory 275200 kb
Host smart-8263194a-5b4b-4e4b-bde9-c38e5543fd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392646081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.2392646081
Directory /workspace/47.flash_ctrl_connect/latest

Test location /workspace/coverage/default/47.flash_ctrl_disable.3023365201
Short name T890
Test name
Test status
Simulation time 21188500 ps
CPU time 21.98 seconds
Started Mar 26 01:28:56 PM PDT 24
Finished Mar 26 01:29:19 PM PDT 24
Peak memory 272476 kb
Host smart-c7b19984-c790-4c77-aa2f-bee21e34e013
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023365201 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.flash_ctrl_disable.3023365201
Directory /workspace/47.flash_ctrl_disable/latest

Test location /workspace/coverage/default/47.flash_ctrl_hw_sec_otp.2504064794
Short name T862
Test name
Test status
Simulation time 2701933200 ps
CPU time 105.38 seconds
Started Mar 26 01:29:01 PM PDT 24
Finished Mar 26 01:30:46 PM PDT 24
Peak memory 261744 kb
Host smart-030b88e6-5ba5-4309-bf5c-eea35c1f45fd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504064794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_
hw_sec_otp.2504064794
Directory /workspace/47.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/47.flash_ctrl_otp_reset.1403518913
Short name T398
Test name
Test status
Simulation time 106262000 ps
CPU time 133.66 seconds
Started Mar 26 01:28:54 PM PDT 24
Finished Mar 26 01:31:08 PM PDT 24
Peak memory 260372 kb
Host smart-0a109100-024e-4644-a3ea-9b7935315b29
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403518913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_o
tp_reset.1403518913
Directory /workspace/47.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/47.flash_ctrl_smoke.2101488726
Short name T1030
Test name
Test status
Simulation time 33652000 ps
CPU time 124.39 seconds
Started Mar 26 01:28:53 PM PDT 24
Finished Mar 26 01:30:58 PM PDT 24
Peak memory 274716 kb
Host smart-1b25999f-e149-4597-9975-e20fbaad18cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101488726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.2101488726
Directory /workspace/47.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/48.flash_ctrl_alert_test.227363752
Short name T452
Test name
Test status
Simulation time 32943900 ps
CPU time 13.13 seconds
Started Mar 26 01:28:54 PM PDT 24
Finished Mar 26 01:29:07 PM PDT 24
Peak memory 257408 kb
Host smart-f17b357d-8d47-4773-ad63-463f596a118f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227363752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.227363752
Directory /workspace/48.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.flash_ctrl_connect.508885774
Short name T840
Test name
Test status
Simulation time 75902900 ps
CPU time 13.36 seconds
Started Mar 26 01:28:54 PM PDT 24
Finished Mar 26 01:29:07 PM PDT 24
Peak memory 275076 kb
Host smart-e17c2805-e481-410f-96c7-0d7a8bdc06bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508885774 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.508885774
Directory /workspace/48.flash_ctrl_connect/latest

Test location /workspace/coverage/default/48.flash_ctrl_disable.3938025955
Short name T258
Test name
Test status
Simulation time 13297900 ps
CPU time 20.34 seconds
Started Mar 26 01:29:01 PM PDT 24
Finished Mar 26 01:29:21 PM PDT 24
Peak memory 272604 kb
Host smart-f690c4ac-93b0-427b-b4aa-cde81b5351c6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938025955 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.flash_ctrl_disable.3938025955
Directory /workspace/48.flash_ctrl_disable/latest

Test location /workspace/coverage/default/48.flash_ctrl_hw_sec_otp.122158876
Short name T599
Test name
Test status
Simulation time 3171060100 ps
CPU time 264.66 seconds
Started Mar 26 01:28:54 PM PDT 24
Finished Mar 26 01:33:19 PM PDT 24
Peak memory 261592 kb
Host smart-787ca60f-7a8e-4419-868f-83a0f0b2b3eb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122158876 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_h
w_sec_otp.122158876
Directory /workspace/48.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/48.flash_ctrl_otp_reset.1734054686
Short name T730
Test name
Test status
Simulation time 37168100 ps
CPU time 107.65 seconds
Started Mar 26 01:28:54 PM PDT 24
Finished Mar 26 01:30:42 PM PDT 24
Peak memory 259012 kb
Host smart-d7f62335-a5c3-4cdb-8e87-3661f783d19d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734054686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_o
tp_reset.1734054686
Directory /workspace/48.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/48.flash_ctrl_sec_info_access.2963862689
Short name T450
Test name
Test status
Simulation time 15773764900 ps
CPU time 74.63 seconds
Started Mar 26 01:28:55 PM PDT 24
Finished Mar 26 01:30:10 PM PDT 24
Peak memory 264272 kb
Host smart-f8f5ea39-f790-4bfb-be93-e13128d77610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963862689 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.2963862689
Directory /workspace/48.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/48.flash_ctrl_smoke.1492801826
Short name T887
Test name
Test status
Simulation time 21787300 ps
CPU time 146.34 seconds
Started Mar 26 01:28:57 PM PDT 24
Finished Mar 26 01:31:23 PM PDT 24
Peak memory 276452 kb
Host smart-9799b8e8-6b92-470f-8193-1669243dca88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492801826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.1492801826
Directory /workspace/48.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/49.flash_ctrl_alert_test.1968347083
Short name T806
Test name
Test status
Simulation time 101740400 ps
CPU time 13.32 seconds
Started Mar 26 01:28:54 PM PDT 24
Finished Mar 26 01:29:07 PM PDT 24
Peak memory 264232 kb
Host smart-e32f4ecb-6b63-4ee7-8bbd-1dbca6901265
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968347083 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.
1968347083
Directory /workspace/49.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.flash_ctrl_connect.4052397912
Short name T957
Test name
Test status
Simulation time 15940600 ps
CPU time 15.49 seconds
Started Mar 26 01:29:00 PM PDT 24
Finished Mar 26 01:29:16 PM PDT 24
Peak memory 274756 kb
Host smart-eb34cbd1-d25b-4203-8677-6cca79049d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052397912 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.4052397912
Directory /workspace/49.flash_ctrl_connect/latest

Test location /workspace/coverage/default/49.flash_ctrl_disable.1691886849
Short name T852
Test name
Test status
Simulation time 35289000 ps
CPU time 21.9 seconds
Started Mar 26 01:28:56 PM PDT 24
Finished Mar 26 01:29:18 PM PDT 24
Peak memory 272632 kb
Host smart-4b18b6a1-5525-4732-9d98-06cb3cbec21f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691886849 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.flash_ctrl_disable.1691886849
Directory /workspace/49.flash_ctrl_disable/latest

Test location /workspace/coverage/default/49.flash_ctrl_hw_sec_otp.3637738071
Short name T572
Test name
Test status
Simulation time 15441157000 ps
CPU time 65.61 seconds
Started Mar 26 01:28:55 PM PDT 24
Finished Mar 26 01:30:00 PM PDT 24
Peak memory 261528 kb
Host smart-285f7f98-bc5e-4415-80bc-636a0b7e872d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637738071 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_
hw_sec_otp.3637738071
Directory /workspace/49.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/49.flash_ctrl_otp_reset.1076064609
Short name T1051
Test name
Test status
Simulation time 123139700 ps
CPU time 130.55 seconds
Started Mar 26 01:28:55 PM PDT 24
Finished Mar 26 01:31:06 PM PDT 24
Peak memory 261616 kb
Host smart-3e4938c8-7494-41fa-8de3-148d8ac20ca3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076064609 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_o
tp_reset.1076064609
Directory /workspace/49.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/49.flash_ctrl_sec_info_access.3315345883
Short name T1036
Test name
Test status
Simulation time 1539616400 ps
CPU time 79.65 seconds
Started Mar 26 01:28:55 PM PDT 24
Finished Mar 26 01:30:15 PM PDT 24
Peak memory 262392 kb
Host smart-ac26805e-6cb3-46e0-add6-0913773e8273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315345883 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.3315345883
Directory /workspace/49.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/49.flash_ctrl_smoke.2901983762
Short name T920
Test name
Test status
Simulation time 47625700 ps
CPU time 52.66 seconds
Started Mar 26 01:28:55 PM PDT 24
Finished Mar 26 01:29:48 PM PDT 24
Peak memory 269716 kb
Host smart-25111a46-ab1c-4dd1-8d97-095d753790be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901983762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.2901983762
Directory /workspace/49.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_alert_test.16976851
Short name T261
Test name
Test status
Simulation time 39503300 ps
CPU time 13.53 seconds
Started Mar 26 01:24:19 PM PDT 24
Finished Mar 26 01:24:32 PM PDT 24
Peak memory 257300 kb
Host smart-60626799-6981-447e-a320-950f57b3cf34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16976851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.16976851
Directory /workspace/5.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.flash_ctrl_connect.1769397005
Short name T430
Test name
Test status
Simulation time 74079100 ps
CPU time 13.09 seconds
Started Mar 26 01:24:29 PM PDT 24
Finished Mar 26 01:24:42 PM PDT 24
Peak memory 274956 kb
Host smart-3bb91b93-673e-49b7-a8a7-2615e95421a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769397005 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.1769397005
Directory /workspace/5.flash_ctrl_connect/latest

Test location /workspace/coverage/default/5.flash_ctrl_disable.671929143
Short name T243
Test name
Test status
Simulation time 38297700 ps
CPU time 21.43 seconds
Started Mar 26 01:24:14 PM PDT 24
Finished Mar 26 01:24:36 PM PDT 24
Peak memory 272608 kb
Host smart-d68cd07c-13c8-4f72-a4e2-31d00d0e339d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671929143 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_disable.671929143
Directory /workspace/5.flash_ctrl_disable/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_prog_win.759057578
Short name T906
Test name
Test status
Simulation time 1133051000 ps
CPU time 731.93 seconds
Started Mar 26 01:24:16 PM PDT 24
Finished Mar 26 01:36:28 PM PDT 24
Peak memory 264224 kb
Host smart-0078889c-10be-4633-94b4-ce1d8400eadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759057578 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.759057578
Directory /workspace/5.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/5.flash_ctrl_fetch_code.4014907459
Short name T339
Test name
Test status
Simulation time 496238600 ps
CPU time 27.51 seconds
Started Mar 26 01:24:13 PM PDT 24
Finished Mar 26 01:24:41 PM PDT 24
Peak memory 264044 kb
Host smart-bf89899b-415f-46c9-a6a6-3d5ed22f5773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014907459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetch_code.4014907459
Directory /workspace/5.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.409843179
Short name T1023
Test name
Test status
Simulation time 10018616400 ps
CPU time 178.13 seconds
Started Mar 26 01:24:17 PM PDT 24
Finished Mar 26 01:27:16 PM PDT 24
Peak memory 289676 kb
Host smart-1d0f96cf-9892-4664-8b46-dfdc512d9622
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409843179 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.409843179
Directory /workspace/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_read_seed_err.21276911
Short name T791
Test name
Test status
Simulation time 36442800 ps
CPU time 13.34 seconds
Started Mar 26 01:24:17 PM PDT 24
Finished Mar 26 01:24:31 PM PDT 24
Peak memory 257656 kb
Host smart-0e59643a-78d2-4399-b684-198d7fd865ff
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21276911 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_seed_err.21276911
Directory /workspace/5.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_rma_reset.2823810813
Short name T164
Test name
Test status
Simulation time 260224015500 ps
CPU time 965.03 seconds
Started Mar 26 01:24:15 PM PDT 24
Finished Mar 26 01:40:20 PM PDT 24
Peak memory 259292 kb
Host smart-f2f97d65-e07a-409f-bafd-962877a68fd1
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823810813 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 5.flash_ctrl_hw_rma_reset.2823810813
Directory /workspace/5.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_sec_otp.4094089438
Short name T336
Test name
Test status
Simulation time 2366417000 ps
CPU time 188.91 seconds
Started Mar 26 01:24:13 PM PDT 24
Finished Mar 26 01:27:22 PM PDT 24
Peak memory 261688 kb
Host smart-e560362b-9834-48a7-adcd-016e46cb6c1b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094089438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_h
w_sec_otp.4094089438
Directory /workspace/5.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd_slow_flash.3005700035
Short name T997
Test name
Test status
Simulation time 34985106400 ps
CPU time 215.75 seconds
Started Mar 26 01:24:16 PM PDT 24
Finished Mar 26 01:27:51 PM PDT 24
Peak memory 290436 kb
Host smart-d0f6114c-3efa-4270-9296-77c9ba3f4b1c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005700035 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd_slow_flash.3005700035
Directory /workspace/5.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr.31973397
Short name T683
Test name
Test status
Simulation time 14569146100 ps
CPU time 84.21 seconds
Started Mar 26 01:24:15 PM PDT 24
Finished Mar 26 01:25:40 PM PDT 24
Peak memory 260520 kb
Host smart-6909d9fb-cf42-484e-82c1-4551d25fce49
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31973397 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +U
VM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.flash_ctrl_intr_wr.31973397
Directory /workspace/5.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr_slow_flash.1100791367
Short name T28
Test name
Test status
Simulation time 208139076800 ps
CPU time 446.1 seconds
Started Mar 26 01:24:19 PM PDT 24
Finished Mar 26 01:31:45 PM PDT 24
Peak memory 264260 kb
Host smart-b529e27a-ea22-4b8b-9876-4b58d2a6a4d5
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110
0791367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.1100791367
Directory /workspace/5.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_invalid_op.1634923823
Short name T1014
Test name
Test status
Simulation time 13842988900 ps
CPU time 90.42 seconds
Started Mar 26 01:24:31 PM PDT 24
Finished Mar 26 01:26:02 PM PDT 24
Peak memory 260008 kb
Host smart-da1a2465-a1f5-46a2-aac5-4b0a2a56dca0
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634923823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.1634923823
Directory /workspace/5.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/5.flash_ctrl_lcmgr_intg.2866175496
Short name T839
Test name
Test status
Simulation time 15537900 ps
CPU time 13.33 seconds
Started Mar 26 01:24:24 PM PDT 24
Finished Mar 26 01:24:38 PM PDT 24
Peak memory 258796 kb
Host smart-0fb7d186-1417-4557-8582-cdf60a6566de
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866175496 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.flash_ctrl_lcmgr_intg.2866175496
Directory /workspace/5.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/5.flash_ctrl_mp_regions.2379622782
Short name T97
Test name
Test status
Simulation time 124728716700 ps
CPU time 430.99 seconds
Started Mar 26 01:24:13 PM PDT 24
Finished Mar 26 01:31:25 PM PDT 24
Peak memory 273240 kb
Host smart-a85a9f7c-eee7-4f5e-90bb-af8f46bade36
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379622782 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 5.flash_ctrl_mp_regions.2379622782
Directory /workspace/5.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/5.flash_ctrl_otp_reset.2915871053
Short name T896
Test name
Test status
Simulation time 274005300 ps
CPU time 128.32 seconds
Started Mar 26 01:24:16 PM PDT 24
Finished Mar 26 01:26:25 PM PDT 24
Peak memory 259196 kb
Host smart-439d4014-d0f9-4098-8a95-eeb8862e97e7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915871053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ot
p_reset.2915871053
Directory /workspace/5.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_phy_arb.1046027864
Short name T742
Test name
Test status
Simulation time 65402100 ps
CPU time 315.15 seconds
Started Mar 26 01:24:15 PM PDT 24
Finished Mar 26 01:29:30 PM PDT 24
Peak memory 261496 kb
Host smart-22f6769b-25ac-4f70-805a-61676fde5851
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1046027864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.1046027864
Directory /workspace/5.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/5.flash_ctrl_prog_reset.1511870428
Short name T763
Test name
Test status
Simulation time 183354900 ps
CPU time 13.51 seconds
Started Mar 26 01:24:18 PM PDT 24
Finished Mar 26 01:24:31 PM PDT 24
Peak memory 264252 kb
Host smart-99aea524-50b4-4cce-bf45-a029cef7e780
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511870428 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_prog_res
et.1511870428
Directory /workspace/5.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_rand_ops.3370256237
Short name T652
Test name
Test status
Simulation time 174075500 ps
CPU time 130.48 seconds
Started Mar 26 01:24:05 PM PDT 24
Finished Mar 26 01:26:16 PM PDT 24
Peak memory 280508 kb
Host smart-6a0ec9ff-2fce-4fba-96b2-7ceee14da589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370256237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.3370256237
Directory /workspace/5.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/5.flash_ctrl_re_evict.3158301332
Short name T417
Test name
Test status
Simulation time 128222900 ps
CPU time 37.79 seconds
Started Mar 26 01:24:15 PM PDT 24
Finished Mar 26 01:24:53 PM PDT 24
Peak memory 272836 kb
Host smart-9950e064-bb9a-4774-8685-e6b57d613520
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158301332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla
sh_ctrl_re_evict.3158301332
Directory /workspace/5.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro.1775251544
Short name T876
Test name
Test status
Simulation time 911851900 ps
CPU time 95.56 seconds
Started Mar 26 01:24:24 PM PDT 24
Finished Mar 26 01:26:00 PM PDT 24
Peak memory 280064 kb
Host smart-9d9bc7a3-8c95-4dc6-b01c-3769271b9283
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775251544 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.flash_ctrl_ro.1775251544
Directory /workspace/5.flash_ctrl_ro/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw.684978
Short name T563
Test name
Test status
Simulation time 4420429500 ps
CPU time 588.68 seconds
Started Mar 26 01:24:29 PM PDT 24
Finished Mar 26 01:34:18 PM PDT 24
Peak memory 313304 kb
Host smart-97e2ef58-6605-42dc-8e1c-caca6f03b779
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684978 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=
flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw.684978
Directory /workspace/5.flash_ctrl_rw/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict.391501239
Short name T24
Test name
Test status
Simulation time 95709200 ps
CPU time 30.59 seconds
Started Mar 26 01:24:17 PM PDT 24
Finished Mar 26 01:24:47 PM PDT 24
Peak memory 265384 kb
Host smart-6a743d15-fc6c-4221-b078-b664094fbe59
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391501239 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas
h_ctrl_rw_evict.391501239
Directory /workspace/5.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict_all_en.341545137
Short name T985
Test name
Test status
Simulation time 49051500 ps
CPU time 30.36 seconds
Started Mar 26 01:24:29 PM PDT 24
Finished Mar 26 01:24:59 PM PDT 24
Peak memory 265476 kb
Host smart-ac767deb-4519-4819-addc-bf08bedd14e6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341545137 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict_all_en.341545137
Directory /workspace/5.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/5.flash_ctrl_sec_info_access.350976387
Short name T914
Test name
Test status
Simulation time 5724432400 ps
CPU time 66.52 seconds
Started Mar 26 01:24:18 PM PDT 24
Finished Mar 26 01:25:24 PM PDT 24
Peak memory 261856 kb
Host smart-6c40bec3-71e5-4e99-a79e-897a0972dde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350976387 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.350976387
Directory /workspace/5.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/5.flash_ctrl_smoke.2228072672
Short name T638
Test name
Test status
Simulation time 21276800 ps
CPU time 48.74 seconds
Started Mar 26 01:23:57 PM PDT 24
Finished Mar 26 01:24:46 PM PDT 24
Peak memory 269680 kb
Host smart-3e7d3150-5d08-4c89-bec2-4fda35cf87d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228072672 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.2228072672
Directory /workspace/5.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_wo.1498536375
Short name T469
Test name
Test status
Simulation time 27642535800 ps
CPU time 172.51 seconds
Started Mar 26 01:24:14 PM PDT 24
Finished Mar 26 01:27:07 PM PDT 24
Peak memory 264576 kb
Host smart-8c5a43b2-0207-4f50-94fc-076a55526b0f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498536375 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.flash_ctrl_wo.1498536375
Directory /workspace/5.flash_ctrl_wo/latest

Test location /workspace/coverage/default/50.flash_ctrl_connect.534259224
Short name T814
Test name
Test status
Simulation time 20103800 ps
CPU time 15.97 seconds
Started Mar 26 01:28:55 PM PDT 24
Finished Mar 26 01:29:11 PM PDT 24
Peak memory 274880 kb
Host smart-9adea3ab-2ef8-4f8a-a2cd-aa97f3329528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534259224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.534259224
Directory /workspace/50.flash_ctrl_connect/latest

Test location /workspace/coverage/default/50.flash_ctrl_otp_reset.861443726
Short name T617
Test name
Test status
Simulation time 150993100 ps
CPU time 129.59 seconds
Started Mar 26 01:28:53 PM PDT 24
Finished Mar 26 01:31:03 PM PDT 24
Peak memory 259372 kb
Host smart-ddb08eb9-2dfc-4c35-8a7e-77b00f541fe9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861443726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_ot
p_reset.861443726
Directory /workspace/50.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/51.flash_ctrl_connect.915037745
Short name T69
Test name
Test status
Simulation time 28701700 ps
CPU time 15.87 seconds
Started Mar 26 01:28:57 PM PDT 24
Finished Mar 26 01:29:13 PM PDT 24
Peak memory 275236 kb
Host smart-ea84c58a-2c48-411a-b1d1-406f4e880d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915037745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.915037745
Directory /workspace/51.flash_ctrl_connect/latest

Test location /workspace/coverage/default/51.flash_ctrl_otp_reset.2077023125
Short name T771
Test name
Test status
Simulation time 156958200 ps
CPU time 110.87 seconds
Started Mar 26 01:28:55 PM PDT 24
Finished Mar 26 01:30:46 PM PDT 24
Peak memory 263748 kb
Host smart-91f808a0-38d6-492e-a7b1-f6dc84fe5a2d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077023125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_o
tp_reset.2077023125
Directory /workspace/51.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/52.flash_ctrl_connect.2197747222
Short name T524
Test name
Test status
Simulation time 13592700 ps
CPU time 15.91 seconds
Started Mar 26 01:28:55 PM PDT 24
Finished Mar 26 01:29:11 PM PDT 24
Peak memory 275184 kb
Host smart-4d0d9aa3-b475-449f-a5bc-c30f23287838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197747222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.2197747222
Directory /workspace/52.flash_ctrl_connect/latest

Test location /workspace/coverage/default/52.flash_ctrl_otp_reset.2848017437
Short name T509
Test name
Test status
Simulation time 119260700 ps
CPU time 130.55 seconds
Started Mar 26 01:28:57 PM PDT 24
Finished Mar 26 01:31:08 PM PDT 24
Peak memory 258900 kb
Host smart-8b0dca97-c0d2-42e4-8d90-691af53f777b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848017437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_o
tp_reset.2848017437
Directory /workspace/52.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/53.flash_ctrl_connect.2635890139
Short name T765
Test name
Test status
Simulation time 20204900 ps
CPU time 13.2 seconds
Started Mar 26 01:29:04 PM PDT 24
Finished Mar 26 01:29:17 PM PDT 24
Peak memory 274152 kb
Host smart-a0274ac6-b38a-4f24-952a-c6e17dae5974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635890139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.2635890139
Directory /workspace/53.flash_ctrl_connect/latest

Test location /workspace/coverage/default/53.flash_ctrl_otp_reset.816817500
Short name T475
Test name
Test status
Simulation time 77401900 ps
CPU time 131.47 seconds
Started Mar 26 01:29:05 PM PDT 24
Finished Mar 26 01:31:16 PM PDT 24
Peak memory 259092 kb
Host smart-f28f3e11-72f5-497f-8130-929bdcce102a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816817500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_ot
p_reset.816817500
Directory /workspace/53.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/54.flash_ctrl_connect.1245621736
Short name T609
Test name
Test status
Simulation time 24400300 ps
CPU time 13.54 seconds
Started Mar 26 01:29:04 PM PDT 24
Finished Mar 26 01:29:18 PM PDT 24
Peak memory 274080 kb
Host smart-5a3186a5-9a10-4583-8f47-c825a76c16eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245621736 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.1245621736
Directory /workspace/54.flash_ctrl_connect/latest

Test location /workspace/coverage/default/54.flash_ctrl_otp_reset.3049628775
Short name T1012
Test name
Test status
Simulation time 499138200 ps
CPU time 132.01 seconds
Started Mar 26 01:29:08 PM PDT 24
Finished Mar 26 01:31:20 PM PDT 24
Peak memory 258880 kb
Host smart-41f88920-9d5b-4b5e-b982-b44f6f6df5cd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049628775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_o
tp_reset.3049628775
Directory /workspace/54.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/55.flash_ctrl_connect.527761254
Short name T59
Test name
Test status
Simulation time 60269100 ps
CPU time 15.77 seconds
Started Mar 26 01:29:07 PM PDT 24
Finished Mar 26 01:29:22 PM PDT 24
Peak memory 275152 kb
Host smart-ed57cd69-46c1-4500-9e3a-7db9f15d6ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527761254 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.527761254
Directory /workspace/55.flash_ctrl_connect/latest

Test location /workspace/coverage/default/55.flash_ctrl_otp_reset.2166343557
Short name T656
Test name
Test status
Simulation time 38222800 ps
CPU time 135.5 seconds
Started Mar 26 01:29:06 PM PDT 24
Finished Mar 26 01:31:21 PM PDT 24
Peak memory 263648 kb
Host smart-4ee0b6f9-c204-461c-bef2-3d3bd8fbe87d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166343557 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_o
tp_reset.2166343557
Directory /workspace/55.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/56.flash_ctrl_connect.1331284687
Short name T437
Test name
Test status
Simulation time 34544300 ps
CPU time 15.36 seconds
Started Mar 26 01:29:06 PM PDT 24
Finished Mar 26 01:29:21 PM PDT 24
Peak memory 274720 kb
Host smart-f16a04e6-04e2-4120-b319-ceb0e0a849ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331284687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.1331284687
Directory /workspace/56.flash_ctrl_connect/latest

Test location /workspace/coverage/default/56.flash_ctrl_otp_reset.355143518
Short name T481
Test name
Test status
Simulation time 102636900 ps
CPU time 130.98 seconds
Started Mar 26 01:29:04 PM PDT 24
Finished Mar 26 01:31:15 PM PDT 24
Peak memory 260112 kb
Host smart-21a5028d-f6ca-440f-ad63-52be7ed5da25
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355143518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_ot
p_reset.355143518
Directory /workspace/56.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/57.flash_ctrl_connect.1660022720
Short name T526
Test name
Test status
Simulation time 24695100 ps
CPU time 15.71 seconds
Started Mar 26 01:29:07 PM PDT 24
Finished Mar 26 01:29:23 PM PDT 24
Peak memory 275024 kb
Host smart-44714580-2ecb-4114-98e3-8603bfd0f5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660022720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.1660022720
Directory /workspace/57.flash_ctrl_connect/latest

Test location /workspace/coverage/default/57.flash_ctrl_otp_reset.2954569713
Short name T540
Test name
Test status
Simulation time 36402500 ps
CPU time 107.32 seconds
Started Mar 26 01:29:05 PM PDT 24
Finished Mar 26 01:30:53 PM PDT 24
Peak memory 259152 kb
Host smart-1289c198-2ffa-4724-b4d1-f066dd9487de
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954569713 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_o
tp_reset.2954569713
Directory /workspace/57.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/58.flash_ctrl_connect.3348146833
Short name T653
Test name
Test status
Simulation time 43623700 ps
CPU time 13.18 seconds
Started Mar 26 01:29:05 PM PDT 24
Finished Mar 26 01:29:18 PM PDT 24
Peak memory 275160 kb
Host smart-c6d8639c-d9dc-4304-afde-6f738da8f287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348146833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.3348146833
Directory /workspace/58.flash_ctrl_connect/latest

Test location /workspace/coverage/default/58.flash_ctrl_otp_reset.3322275622
Short name T946
Test name
Test status
Simulation time 590223000 ps
CPU time 109.96 seconds
Started Mar 26 01:29:04 PM PDT 24
Finished Mar 26 01:30:54 PM PDT 24
Peak memory 263744 kb
Host smart-df00a4cf-acb4-405c-a94a-61fda68ec667
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322275622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_o
tp_reset.3322275622
Directory /workspace/58.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/59.flash_ctrl_connect.866055605
Short name T1041
Test name
Test status
Simulation time 15521900 ps
CPU time 15.67 seconds
Started Mar 26 01:29:07 PM PDT 24
Finished Mar 26 01:29:23 PM PDT 24
Peak memory 275016 kb
Host smart-50e40f7f-a49e-4506-b6a6-e5702379220d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866055605 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.866055605
Directory /workspace/59.flash_ctrl_connect/latest

Test location /workspace/coverage/default/59.flash_ctrl_otp_reset.3552416188
Short name T738
Test name
Test status
Simulation time 40035800 ps
CPU time 109.31 seconds
Started Mar 26 01:29:12 PM PDT 24
Finished Mar 26 01:31:01 PM PDT 24
Peak memory 263624 kb
Host smart-2cac26e5-c31a-4851-97cf-d9e1badb24a4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552416188 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_o
tp_reset.3552416188
Directory /workspace/59.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_alert_test.3839987620
Short name T803
Test name
Test status
Simulation time 22393500 ps
CPU time 13.64 seconds
Started Mar 26 01:24:41 PM PDT 24
Finished Mar 26 01:24:54 PM PDT 24
Peak memory 264312 kb
Host smart-35577cf4-e17b-4a2e-9bb0-16b63c1847a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839987620 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.3
839987620
Directory /workspace/6.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.flash_ctrl_connect.1479008685
Short name T635
Test name
Test status
Simulation time 40344100 ps
CPU time 15.47 seconds
Started Mar 26 01:24:41 PM PDT 24
Finished Mar 26 01:24:57 PM PDT 24
Peak memory 274788 kb
Host smart-21dcffbf-b9de-4605-87e7-f52bf70a587d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479008685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.1479008685
Directory /workspace/6.flash_ctrl_connect/latest

Test location /workspace/coverage/default/6.flash_ctrl_disable.3936799452
Short name T323
Test name
Test status
Simulation time 20093200 ps
CPU time 21.64 seconds
Started Mar 26 01:24:26 PM PDT 24
Finished Mar 26 01:24:48 PM PDT 24
Peak memory 272648 kb
Host smart-71c85700-a357-4fea-9f50-9e5281f8676d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936799452 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_disable.3936799452
Directory /workspace/6.flash_ctrl_disable/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_mp.3257161761
Short name T741
Test name
Test status
Simulation time 32205919000 ps
CPU time 2112.37 seconds
Started Mar 26 01:24:26 PM PDT 24
Finished Mar 26 01:59:39 PM PDT 24
Peak memory 264100 kb
Host smart-71d98952-0add-49f7-a60f-5c1e639e8794
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257161761 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_err
or_mp.3257161761
Directory /workspace/6.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_prog_win.3498616022
Short name T550
Test name
Test status
Simulation time 1854252700 ps
CPU time 987.04 seconds
Started Mar 26 01:24:25 PM PDT 24
Finished Mar 26 01:40:52 PM PDT 24
Peak memory 272472 kb
Host smart-899190f6-f9e2-4970-b8df-9f2e48e5d82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498616022 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.3498616022
Directory /workspace/6.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/6.flash_ctrl_fetch_code.347864427
Short name T54
Test name
Test status
Simulation time 970100800 ps
CPU time 27.12 seconds
Started Mar 26 01:24:24 PM PDT 24
Finished Mar 26 01:24:52 PM PDT 24
Peak memory 264148 kb
Host smart-34e48d02-d8ed-4a77-aa3d-5cb3ca434529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347864427 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetch_code.347864427
Directory /workspace/6.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.1128737510
Short name T303
Test name
Test status
Simulation time 10035739200 ps
CPU time 54.59 seconds
Started Mar 26 01:24:40 PM PDT 24
Finished Mar 26 01:25:35 PM PDT 24
Peak memory 268544 kb
Host smart-bf10936a-3767-4093-ba5f-4708950eecca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128737510 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.1128737510
Directory /workspace/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_read_seed_err.729849935
Short name T58
Test name
Test status
Simulation time 16240300 ps
CPU time 13.19 seconds
Started Mar 26 01:24:39 PM PDT 24
Finished Mar 26 01:24:52 PM PDT 24
Peak memory 257140 kb
Host smart-b7cad718-28e0-4c72-8c31-abf0722d9913
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729849935 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_seed_err.729849935
Directory /workspace/6.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_rma_reset.3274707400
Short name T76
Test name
Test status
Simulation time 80135433400 ps
CPU time 769.48 seconds
Started Mar 26 01:24:24 PM PDT 24
Finished Mar 26 01:37:14 PM PDT 24
Peak memory 262600 kb
Host smart-af9f72bb-c110-401c-806e-05d91c334994
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274707400 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.flash_ctrl_hw_rma_reset.3274707400
Directory /workspace/6.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_sec_otp.841903079
Short name T442
Test name
Test status
Simulation time 9931559000 ps
CPU time 97.14 seconds
Started Mar 26 01:24:23 PM PDT 24
Finished Mar 26 01:26:01 PM PDT 24
Peak memory 261460 kb
Host smart-c9c46caa-3e25-440d-ba0f-de23ed5de73f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841903079 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw
_sec_otp.841903079
Directory /workspace/6.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd_slow_flash.3730894714
Short name T351
Test name
Test status
Simulation time 14791430500 ps
CPU time 181 seconds
Started Mar 26 01:24:25 PM PDT 24
Finished Mar 26 01:27:26 PM PDT 24
Peak memory 290208 kb
Host smart-c689108b-4b07-4030-96af-eef0e1ea4bf5
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730894714 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd_slow_flash.3730894714
Directory /workspace/6.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr.3925997999
Short name T673
Test name
Test status
Simulation time 3972686200 ps
CPU time 93.49 seconds
Started Mar 26 01:24:27 PM PDT 24
Finished Mar 26 01:26:00 PM PDT 24
Peak memory 261032 kb
Host smart-7c2c0d32-6104-42a7-a250-a1f6004b9040
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925997999 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.flash_ctrl_intr_wr.3925997999
Directory /workspace/6.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.3779155379
Short name T27
Test name
Test status
Simulation time 48129834900 ps
CPU time 366.72 seconds
Started Mar 26 01:24:26 PM PDT 24
Finished Mar 26 01:30:33 PM PDT 24
Peak memory 260188 kb
Host smart-589ebb14-cba6-46cb-8385-e19c50b13058
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377
9155379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.3779155379
Directory /workspace/6.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_invalid_op.2766717333
Short name T409
Test name
Test status
Simulation time 6532399100 ps
CPU time 73.07 seconds
Started Mar 26 01:24:25 PM PDT 24
Finished Mar 26 01:25:38 PM PDT 24
Peak memory 259556 kb
Host smart-cea9f798-a4b6-4ce0-92f8-39c109697a05
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766717333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.2766717333
Directory /workspace/6.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/6.flash_ctrl_lcmgr_intg.410185865
Short name T759
Test name
Test status
Simulation time 15398800 ps
CPU time 13.29 seconds
Started Mar 26 01:24:41 PM PDT 24
Finished Mar 26 01:24:54 PM PDT 24
Peak memory 259736 kb
Host smart-b5547ba1-4402-4c18-a66c-2c77d22d02be
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410185865 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.flash_ctrl_lcmgr_intg.410185865
Directory /workspace/6.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/6.flash_ctrl_mp_regions.4153161090
Short name T719
Test name
Test status
Simulation time 14015374800 ps
CPU time 511.74 seconds
Started Mar 26 01:24:24 PM PDT 24
Finished Mar 26 01:32:56 PM PDT 24
Peak memory 273256 kb
Host smart-bc044395-ef7f-49d4-a858-43cfade1d775
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153161090 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 6.flash_ctrl_mp_regions.4153161090
Directory /workspace/6.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/6.flash_ctrl_otp_reset.4013252898
Short name T636
Test name
Test status
Simulation time 152257600 ps
CPU time 108.96 seconds
Started Mar 26 01:24:23 PM PDT 24
Finished Mar 26 01:26:13 PM PDT 24
Peak memory 263776 kb
Host smart-5a479e60-9cf6-497a-b295-62c2d28ce7bd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013252898 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ot
p_reset.4013252898
Directory /workspace/6.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_phy_arb.1381593815
Short name T865
Test name
Test status
Simulation time 230933000 ps
CPU time 235.88 seconds
Started Mar 26 01:24:15 PM PDT 24
Finished Mar 26 01:28:11 PM PDT 24
Peak memory 260768 kb
Host smart-5915f1b2-300a-4ec5-a69e-babb15e78cc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1381593815 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.1381593815
Directory /workspace/6.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/6.flash_ctrl_prog_reset.996005791
Short name T613
Test name
Test status
Simulation time 55833900 ps
CPU time 14.11 seconds
Started Mar 26 01:24:27 PM PDT 24
Finished Mar 26 01:24:41 PM PDT 24
Peak memory 259480 kb
Host smart-93129bbf-67e0-453b-bd6e-c8fa82fc85cc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996005791 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_prog_rese
t.996005791
Directory /workspace/6.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_rand_ops.710688403
Short name T787
Test name
Test status
Simulation time 67091500 ps
CPU time 361.61 seconds
Started Mar 26 01:24:31 PM PDT 24
Finished Mar 26 01:30:33 PM PDT 24
Peak memory 280612 kb
Host smart-b5598c7c-f951-442d-ab92-4581872b3b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710688403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.710688403
Directory /workspace/6.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/6.flash_ctrl_re_evict.1597692277
Short name T418
Test name
Test status
Simulation time 1172240100 ps
CPU time 38.22 seconds
Started Mar 26 01:24:24 PM PDT 24
Finished Mar 26 01:25:02 PM PDT 24
Peak memory 272576 kb
Host smart-5c434bf8-5c28-4b97-ae21-a79be5467c07
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597692277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla
sh_ctrl_re_evict.1597692277
Directory /workspace/6.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro.3053538346
Short name T847
Test name
Test status
Simulation time 418621300 ps
CPU time 91.8 seconds
Started Mar 26 01:24:25 PM PDT 24
Finished Mar 26 01:25:57 PM PDT 24
Peak memory 279976 kb
Host smart-44934266-4519-454e-812a-89133641f108
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053538346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.flash_ctrl_ro.3053538346
Directory /workspace/6.flash_ctrl_ro/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw.1702307584
Short name T729
Test name
Test status
Simulation time 4318456400 ps
CPU time 594.22 seconds
Started Mar 26 01:24:26 PM PDT 24
Finished Mar 26 01:34:20 PM PDT 24
Peak memory 313608 kb
Host smart-d713f4cb-c8cb-4ab1-a9e9-e94f0622417e
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702307584 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ct
rl_rw.1702307584
Directory /workspace/6.flash_ctrl_rw/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict.3819620707
Short name T948
Test name
Test status
Simulation time 256112500 ps
CPU time 34.64 seconds
Started Mar 26 01:24:25 PM PDT 24
Finished Mar 26 01:25:00 PM PDT 24
Peak memory 273560 kb
Host smart-7e8ee718-a847-40cb-afe4-ec08668ef8f9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819620707 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla
sh_ctrl_rw_evict.3819620707
Directory /workspace/6.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict_all_en.1292738919
Short name T1009
Test name
Test status
Simulation time 28148000 ps
CPU time 31.48 seconds
Started Mar 26 01:24:24 PM PDT 24
Finished Mar 26 01:24:56 PM PDT 24
Peak memory 271796 kb
Host smart-baadedaa-222f-4f92-ae93-d63ee036f9b0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292738919 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict_all_en.1292738919
Directory /workspace/6.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/6.flash_ctrl_sec_info_access.2148717435
Short name T378
Test name
Test status
Simulation time 350861300 ps
CPU time 51.4 seconds
Started Mar 26 01:24:32 PM PDT 24
Finished Mar 26 01:25:24 PM PDT 24
Peak memory 262212 kb
Host smart-d8125dd2-2f88-4b1a-833e-4f0031ddfc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148717435 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.2148717435
Directory /workspace/6.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/6.flash_ctrl_smoke.3812885484
Short name T804
Test name
Test status
Simulation time 307830700 ps
CPU time 194.19 seconds
Started Mar 26 01:24:25 PM PDT 24
Finished Mar 26 01:27:39 PM PDT 24
Peak memory 279224 kb
Host smart-21d22b7f-5219-4132-9759-a46969519811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812885484 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.3812885484
Directory /workspace/6.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/6.flash_ctrl_wo.3170274239
Short name T686
Test name
Test status
Simulation time 17010838800 ps
CPU time 160.79 seconds
Started Mar 26 01:24:26 PM PDT 24
Finished Mar 26 01:27:07 PM PDT 24
Peak memory 258740 kb
Host smart-6c3ce0b4-e915-4c18-9058-2f3f07833158
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170274239 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.flash_ctrl_wo.3170274239
Directory /workspace/6.flash_ctrl_wo/latest

Test location /workspace/coverage/default/60.flash_ctrl_connect.978280992
Short name T868
Test name
Test status
Simulation time 28799900 ps
CPU time 13.34 seconds
Started Mar 26 01:29:08 PM PDT 24
Finished Mar 26 01:29:21 PM PDT 24
Peak memory 274752 kb
Host smart-5080f32a-a3ac-436b-9ba9-dc999a84b08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978280992 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.978280992
Directory /workspace/60.flash_ctrl_connect/latest

Test location /workspace/coverage/default/60.flash_ctrl_otp_reset.2107229337
Short name T334
Test name
Test status
Simulation time 43914400 ps
CPU time 133.36 seconds
Started Mar 26 01:29:05 PM PDT 24
Finished Mar 26 01:31:18 PM PDT 24
Peak memory 260132 kb
Host smart-5191a76e-682f-4f89-a5ac-dd52b25b52c1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107229337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_o
tp_reset.2107229337
Directory /workspace/60.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/61.flash_ctrl_connect.3327828876
Short name T649
Test name
Test status
Simulation time 23561000 ps
CPU time 15.63 seconds
Started Mar 26 01:29:07 PM PDT 24
Finished Mar 26 01:29:23 PM PDT 24
Peak memory 274080 kb
Host smart-baa381c3-bbc5-4927-9278-f7d0769bd4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327828876 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.3327828876
Directory /workspace/61.flash_ctrl_connect/latest

Test location /workspace/coverage/default/61.flash_ctrl_otp_reset.3411128054
Short name T146
Test name
Test status
Simulation time 368374600 ps
CPU time 128.11 seconds
Started Mar 26 01:29:06 PM PDT 24
Finished Mar 26 01:31:14 PM PDT 24
Peak memory 259160 kb
Host smart-9c6f1a9f-aac7-4747-b3e6-ca72c1a0d04d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411128054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_o
tp_reset.3411128054
Directory /workspace/61.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/62.flash_ctrl_connect.2643549666
Short name T527
Test name
Test status
Simulation time 82315900 ps
CPU time 15.61 seconds
Started Mar 26 01:29:04 PM PDT 24
Finished Mar 26 01:29:20 PM PDT 24
Peak memory 275212 kb
Host smart-4e0fa52f-40bc-481f-a038-ab8dc4a30978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643549666 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.2643549666
Directory /workspace/62.flash_ctrl_connect/latest

Test location /workspace/coverage/default/62.flash_ctrl_otp_reset.1796663750
Short name T151
Test name
Test status
Simulation time 133223300 ps
CPU time 129.05 seconds
Started Mar 26 01:29:07 PM PDT 24
Finished Mar 26 01:31:17 PM PDT 24
Peak memory 259216 kb
Host smart-6b08ab87-d754-41f3-8708-b55052e161e6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796663750 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_o
tp_reset.1796663750
Directory /workspace/62.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/63.flash_ctrl_connect.366834211
Short name T377
Test name
Test status
Simulation time 15724800 ps
CPU time 13.33 seconds
Started Mar 26 01:29:11 PM PDT 24
Finished Mar 26 01:29:24 PM PDT 24
Peak memory 274756 kb
Host smart-df582e5d-ca43-4241-95a8-563c59bfee48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366834211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.366834211
Directory /workspace/63.flash_ctrl_connect/latest

Test location /workspace/coverage/default/63.flash_ctrl_otp_reset.2728314160
Short name T537
Test name
Test status
Simulation time 38377800 ps
CPU time 132.38 seconds
Started Mar 26 01:29:06 PM PDT 24
Finished Mar 26 01:31:19 PM PDT 24
Peak memory 258908 kb
Host smart-b0bbe63a-3713-47e5-8fdb-c9bb27f54209
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728314160 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_o
tp_reset.2728314160
Directory /workspace/63.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/64.flash_ctrl_connect.3906544874
Short name T66
Test name
Test status
Simulation time 25180600 ps
CPU time 15.72 seconds
Started Mar 26 01:29:11 PM PDT 24
Finished Mar 26 01:29:27 PM PDT 24
Peak memory 274920 kb
Host smart-2b6b8b64-457e-4b00-934d-0a361c3a900b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906544874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.3906544874
Directory /workspace/64.flash_ctrl_connect/latest

Test location /workspace/coverage/default/65.flash_ctrl_connect.2608845723
Short name T209
Test name
Test status
Simulation time 46266300 ps
CPU time 15.38 seconds
Started Mar 26 01:29:11 PM PDT 24
Finished Mar 26 01:29:27 PM PDT 24
Peak memory 274908 kb
Host smart-9fbdcfd5-dba9-4ae8-9344-f9e2f239d112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608845723 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.2608845723
Directory /workspace/65.flash_ctrl_connect/latest

Test location /workspace/coverage/default/65.flash_ctrl_otp_reset.2211752663
Short name T140
Test name
Test status
Simulation time 38257700 ps
CPU time 110.17 seconds
Started Mar 26 01:29:06 PM PDT 24
Finished Mar 26 01:30:56 PM PDT 24
Peak memory 263448 kb
Host smart-d8938926-53ac-48a6-a09b-2e805a51797f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211752663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_o
tp_reset.2211752663
Directory /workspace/65.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/66.flash_ctrl_connect.2725918063
Short name T881
Test name
Test status
Simulation time 15287100 ps
CPU time 15.38 seconds
Started Mar 26 01:29:04 PM PDT 24
Finished Mar 26 01:29:20 PM PDT 24
Peak memory 274780 kb
Host smart-a6a35fd4-bd7e-492d-82e4-9d773961dcf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725918063 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.2725918063
Directory /workspace/66.flash_ctrl_connect/latest

Test location /workspace/coverage/default/66.flash_ctrl_otp_reset.3025138807
Short name T546
Test name
Test status
Simulation time 90191400 ps
CPU time 130.53 seconds
Started Mar 26 01:29:08 PM PDT 24
Finished Mar 26 01:31:18 PM PDT 24
Peak memory 262028 kb
Host smart-ee188c9b-57e7-49cb-8599-753936cea304
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025138807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_o
tp_reset.3025138807
Directory /workspace/66.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/67.flash_ctrl_connect.1033652523
Short name T783
Test name
Test status
Simulation time 21635200 ps
CPU time 15.44 seconds
Started Mar 26 01:29:07 PM PDT 24
Finished Mar 26 01:29:23 PM PDT 24
Peak memory 275224 kb
Host smart-a005fac6-9ff6-432a-a525-ea82b9342702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033652523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.1033652523
Directory /workspace/67.flash_ctrl_connect/latest

Test location /workspace/coverage/default/67.flash_ctrl_otp_reset.38319393
Short name T488
Test name
Test status
Simulation time 41677300 ps
CPU time 128.06 seconds
Started Mar 26 01:29:05 PM PDT 24
Finished Mar 26 01:31:13 PM PDT 24
Peak memory 259048 kb
Host smart-53bb1260-7736-40c9-9475-ff8ede581818
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38319393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_otp
_reset.38319393
Directory /workspace/67.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/68.flash_ctrl_connect.2744300310
Short name T646
Test name
Test status
Simulation time 65665400 ps
CPU time 13.44 seconds
Started Mar 26 01:29:15 PM PDT 24
Finished Mar 26 01:29:29 PM PDT 24
Peak memory 275232 kb
Host smart-07bce468-cdc7-4f8f-ac49-75feb3b2640a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744300310 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.2744300310
Directory /workspace/68.flash_ctrl_connect/latest

Test location /workspace/coverage/default/68.flash_ctrl_otp_reset.3702524714
Short name T456
Test name
Test status
Simulation time 41421000 ps
CPU time 108.82 seconds
Started Mar 26 01:29:08 PM PDT 24
Finished Mar 26 01:30:57 PM PDT 24
Peak memory 259132 kb
Host smart-dbe015b9-5e47-4859-b44a-c942180c922b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702524714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_o
tp_reset.3702524714
Directory /workspace/68.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/69.flash_ctrl_connect.2912498619
Short name T595
Test name
Test status
Simulation time 25863500 ps
CPU time 15.64 seconds
Started Mar 26 01:29:17 PM PDT 24
Finished Mar 26 01:29:33 PM PDT 24
Peak memory 275132 kb
Host smart-26eaa762-613d-4064-9cdc-29430d9f3d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912498619 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.2912498619
Directory /workspace/69.flash_ctrl_connect/latest

Test location /workspace/coverage/default/69.flash_ctrl_otp_reset.1993966142
Short name T18
Test name
Test status
Simulation time 309062900 ps
CPU time 132.07 seconds
Started Mar 26 01:29:16 PM PDT 24
Finished Mar 26 01:31:28 PM PDT 24
Peak memory 260000 kb
Host smart-6e9c3bd9-f370-489c-8888-041fbee1675b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993966142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_o
tp_reset.1993966142
Directory /workspace/69.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_alert_test.3342366963
Short name T445
Test name
Test status
Simulation time 105186800 ps
CPU time 14.05 seconds
Started Mar 26 01:24:54 PM PDT 24
Finished Mar 26 01:25:08 PM PDT 24
Peak memory 264212 kb
Host smart-07a97cc5-8609-4dcf-afd7-5df5efc1e308
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342366963 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.3
342366963
Directory /workspace/7.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.flash_ctrl_connect.179087565
Short name T68
Test name
Test status
Simulation time 48007500 ps
CPU time 15.47 seconds
Started Mar 26 01:24:50 PM PDT 24
Finished Mar 26 01:25:06 PM PDT 24
Peak memory 275000 kb
Host smart-1fd63a32-1a37-418f-bdf2-5abeff865166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179087565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.179087565
Directory /workspace/7.flash_ctrl_connect/latest

Test location /workspace/coverage/default/7.flash_ctrl_disable.3774814509
Short name T160
Test name
Test status
Simulation time 25106600 ps
CPU time 20.12 seconds
Started Mar 26 01:24:51 PM PDT 24
Finished Mar 26 01:25:11 PM PDT 24
Peak memory 264412 kb
Host smart-3f2d4e0e-f648-4b94-805b-5f921c7e075f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774814509 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_disable.3774814509
Directory /workspace/7.flash_ctrl_disable/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_mp.666909911
Short name T974
Test name
Test status
Simulation time 3893293400 ps
CPU time 2162.57 seconds
Started Mar 26 01:24:40 PM PDT 24
Finished Mar 26 02:00:43 PM PDT 24
Peak memory 264012 kb
Host smart-b93d5f67-27e6-4341-835d-61120e6afb1f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666909911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_erro
r_mp.666909911
Directory /workspace/7.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_prog_win.3712297685
Short name T555
Test name
Test status
Simulation time 702971300 ps
CPU time 851.54 seconds
Started Mar 26 01:24:38 PM PDT 24
Finished Mar 26 01:38:50 PM PDT 24
Peak memory 270120 kb
Host smart-1fcb66f6-21d2-46c5-bdb3-f2a6bc9d8010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712297685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.3712297685
Directory /workspace/7.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.3098890399
Short name T662
Test name
Test status
Simulation time 10034943900 ps
CPU time 53.39 seconds
Started Mar 26 01:24:54 PM PDT 24
Finished Mar 26 01:25:47 PM PDT 24
Peak memory 270888 kb
Host smart-f4e8f5c1-4646-4759-90e1-aa5211dfb8d3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098890399 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.3098890399
Directory /workspace/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_read_seed_err.1832954006
Short name T552
Test name
Test status
Simulation time 146887400 ps
CPU time 13.31 seconds
Started Mar 26 01:24:52 PM PDT 24
Finished Mar 26 01:25:06 PM PDT 24
Peak memory 257292 kb
Host smart-b7ea4ecf-04f7-4333-8b5d-ed6c77220085
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832954006 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_read_seed_err.1832954006
Directory /workspace/7.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_rma_reset.1691215357
Short name T990
Test name
Test status
Simulation time 50127770200 ps
CPU time 870.26 seconds
Started Mar 26 01:24:41 PM PDT 24
Finished Mar 26 01:39:11 PM PDT 24
Peak memory 262008 kb
Host smart-2138b44e-a267-4574-9795-d32b1e5944df
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691215357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.flash_ctrl_hw_rma_reset.1691215357
Directory /workspace/7.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_sec_otp.1664215221
Short name T826
Test name
Test status
Simulation time 929111200 ps
CPU time 77.05 seconds
Started Mar 26 01:24:39 PM PDT 24
Finished Mar 26 01:25:56 PM PDT 24
Peak memory 261680 kb
Host smart-4198367b-6ae2-4147-b639-f479621833cd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664215221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_h
w_sec_otp.1664215221
Directory /workspace/7.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd_slow_flash.3620719479
Short name T854
Test name
Test status
Simulation time 23125808100 ps
CPU time 198.38 seconds
Started Mar 26 01:24:39 PM PDT 24
Finished Mar 26 01:27:57 PM PDT 24
Peak memory 288808 kb
Host smart-98a7f200-079a-4402-8429-ebe79a0a10f9
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620719479 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd_slow_flash.3620719479
Directory /workspace/7.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr.906480617
Short name T498
Test name
Test status
Simulation time 6786884500 ps
CPU time 100.2 seconds
Started Mar 26 01:24:39 PM PDT 24
Finished Mar 26 01:26:20 PM PDT 24
Peak memory 260384 kb
Host smart-b4f764ed-fbf7-41e5-9cbc-a7bd058ef5d7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906480617 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 7.flash_ctrl_intr_wr.906480617
Directory /workspace/7.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr_slow_flash.40869540
Short name T574
Test name
Test status
Simulation time 44621368900 ps
CPU time 313.33 seconds
Started Mar 26 01:24:41 PM PDT 24
Finished Mar 26 01:29:54 PM PDT 24
Peak memory 260104 kb
Host smart-86e041fe-223a-40f1-a655-bd684a392332
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408
69540 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.40869540
Directory /workspace/7.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_invalid_op.2614658428
Short name T879
Test name
Test status
Simulation time 5802466800 ps
CPU time 96.2 seconds
Started Mar 26 01:24:39 PM PDT 24
Finished Mar 26 01:26:15 PM PDT 24
Peak memory 258920 kb
Host smart-96bf7fd3-7e26-4332-a725-077b85339e93
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614658428 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.2614658428
Directory /workspace/7.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/7.flash_ctrl_lcmgr_intg.386073454
Short name T307
Test name
Test status
Simulation time 26476400 ps
CPU time 13.64 seconds
Started Mar 26 01:25:01 PM PDT 24
Finished Mar 26 01:25:15 PM PDT 24
Peak memory 264356 kb
Host smart-93a5392f-ed80-42f1-9263-4d7d58e7db28
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386073454 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.flash_ctrl_lcmgr_intg.386073454
Directory /workspace/7.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/7.flash_ctrl_mp_regions.651122362
Short name T748
Test name
Test status
Simulation time 8710985200 ps
CPU time 548.25 seconds
Started Mar 26 01:24:41 PM PDT 24
Finished Mar 26 01:33:50 PM PDT 24
Peak memory 272492 kb
Host smart-4bd3dabb-8ecb-44db-a9f1-b997ff46d515
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651122362 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 7.flash_ctrl_mp_regions.651122362
Directory /workspace/7.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/7.flash_ctrl_otp_reset.3304994818
Short name T770
Test name
Test status
Simulation time 111266900 ps
CPU time 129.67 seconds
Started Mar 26 01:24:38 PM PDT 24
Finished Mar 26 01:26:48 PM PDT 24
Peak memory 260124 kb
Host smart-38521024-ce65-4c92-b186-3a3a469400b8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304994818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ot
p_reset.3304994818
Directory /workspace/7.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_phy_arb.267768581
Short name T532
Test name
Test status
Simulation time 1419303000 ps
CPU time 160.6 seconds
Started Mar 26 01:24:38 PM PDT 24
Finished Mar 26 01:27:18 PM PDT 24
Peak memory 260816 kb
Host smart-b317fb12-bf83-452a-99b1-fcdf334a6f39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=267768581 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.267768581
Directory /workspace/7.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/7.flash_ctrl_prog_reset.2787413726
Short name T534
Test name
Test status
Simulation time 21277800 ps
CPU time 13.72 seconds
Started Mar 26 01:24:40 PM PDT 24
Finished Mar 26 01:24:54 PM PDT 24
Peak memory 259264 kb
Host smart-bae37834-95dc-44d1-bc37-bdacda4228fb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787413726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_prog_res
et.2787413726
Directory /workspace/7.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_rand_ops.3190532560
Short name T1022
Test name
Test status
Simulation time 1420217700 ps
CPU time 456.26 seconds
Started Mar 26 01:24:38 PM PDT 24
Finished Mar 26 01:32:15 PM PDT 24
Peak memory 282524 kb
Host smart-8d2fbef3-542c-416c-a989-44fab9e2a0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190532560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.3190532560
Directory /workspace/7.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/7.flash_ctrl_re_evict.474470745
Short name T548
Test name
Test status
Simulation time 683725900 ps
CPU time 40.68 seconds
Started Mar 26 01:24:50 PM PDT 24
Finished Mar 26 01:25:31 PM PDT 24
Peak memory 265316 kb
Host smart-6061bb17-1d22-4bd0-9300-c8af7899f56b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474470745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas
h_ctrl_re_evict.474470745
Directory /workspace/7.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro.4261971720
Short name T601
Test name
Test status
Simulation time 1979646900 ps
CPU time 97.56 seconds
Started Mar 26 01:24:40 PM PDT 24
Finished Mar 26 01:26:17 PM PDT 24
Peak memory 280396 kb
Host smart-af3f1086-8b98-4c1d-b30b-e65e72351c50
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261971720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.flash_ctrl_ro.4261971720
Directory /workspace/7.flash_ctrl_ro/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw.159129067
Short name T956
Test name
Test status
Simulation time 3189647400 ps
CPU time 504.5 seconds
Started Mar 26 01:24:37 PM PDT 24
Finished Mar 26 01:33:02 PM PDT 24
Peak memory 313444 kb
Host smart-7a2177a2-04f9-40f3-81a0-a7880d36381b
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159129067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctr
l_rw.159129067
Directory /workspace/7.flash_ctrl_rw/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict.3387664595
Short name T915
Test name
Test status
Simulation time 192044700 ps
CPU time 30.86 seconds
Started Mar 26 01:24:38 PM PDT 24
Finished Mar 26 01:25:10 PM PDT 24
Peak memory 265372 kb
Host smart-d735abee-bf54-4182-89fb-e2cc21c004df
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387664595 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla
sh_ctrl_rw_evict.3387664595
Directory /workspace/7.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict_all_en.3413256956
Short name T121
Test name
Test status
Simulation time 33247800 ps
CPU time 31.77 seconds
Started Mar 26 01:24:49 PM PDT 24
Finished Mar 26 01:25:21 PM PDT 24
Peak memory 272616 kb
Host smart-842eafbe-b2c1-4c2f-9d9c-a7fa9daaad48
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413256956 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict_all_en.3413256956
Directory /workspace/7.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/7.flash_ctrl_sec_info_access.116459288
Short name T482
Test name
Test status
Simulation time 1303744500 ps
CPU time 79.03 seconds
Started Mar 26 01:24:51 PM PDT 24
Finished Mar 26 01:26:11 PM PDT 24
Peak memory 262340 kb
Host smart-b7930149-1b92-4381-8b1c-a5c46348b395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116459288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.116459288
Directory /workspace/7.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/7.flash_ctrl_smoke.1587336392
Short name T210
Test name
Test status
Simulation time 22151400 ps
CPU time 73.95 seconds
Started Mar 26 01:24:39 PM PDT 24
Finished Mar 26 01:25:53 PM PDT 24
Peak memory 274192 kb
Host smart-8ac1e3b1-2e49-444a-930c-696b53d25399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587336392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.1587336392
Directory /workspace/7.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/7.flash_ctrl_wo.335722819
Short name T1001
Test name
Test status
Simulation time 2130446900 ps
CPU time 171.13 seconds
Started Mar 26 01:24:41 PM PDT 24
Finished Mar 26 01:27:33 PM PDT 24
Peak memory 264208 kb
Host smart-9ab6ab2e-2371-4ff3-b79b-9609a5f3def1
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335722819 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.flash_ctrl_wo.335722819
Directory /workspace/7.flash_ctrl_wo/latest

Test location /workspace/coverage/default/70.flash_ctrl_connect.3586847453
Short name T843
Test name
Test status
Simulation time 17971400 ps
CPU time 15.89 seconds
Started Mar 26 01:29:19 PM PDT 24
Finished Mar 26 01:29:35 PM PDT 24
Peak memory 275224 kb
Host smart-0aeafae8-d1ec-48a3-add9-a27d93d14e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586847453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.3586847453
Directory /workspace/70.flash_ctrl_connect/latest

Test location /workspace/coverage/default/70.flash_ctrl_otp_reset.654096519
Short name T101
Test name
Test status
Simulation time 74820000 ps
CPU time 129.5 seconds
Started Mar 26 01:29:17 PM PDT 24
Finished Mar 26 01:31:26 PM PDT 24
Peak memory 260400 kb
Host smart-ddc2affd-a68a-4a29-adc4-a964d8bd7c63
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654096519 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_ot
p_reset.654096519
Directory /workspace/70.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/71.flash_ctrl_connect.4246880851
Short name T954
Test name
Test status
Simulation time 45977300 ps
CPU time 15.67 seconds
Started Mar 26 01:29:14 PM PDT 24
Finished Mar 26 01:29:30 PM PDT 24
Peak memory 275036 kb
Host smart-1e1dace8-ee3b-4733-a8a5-da3c2752fce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246880851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.4246880851
Directory /workspace/71.flash_ctrl_connect/latest

Test location /workspace/coverage/default/71.flash_ctrl_otp_reset.3329708589
Short name T85
Test name
Test status
Simulation time 64120400 ps
CPU time 133.38 seconds
Started Mar 26 01:29:17 PM PDT 24
Finished Mar 26 01:31:31 PM PDT 24
Peak memory 263424 kb
Host smart-d7d73e49-c23e-4f46-8761-e7014490fef9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329708589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_o
tp_reset.3329708589
Directory /workspace/71.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/72.flash_ctrl_connect.646235197
Short name T489
Test name
Test status
Simulation time 28908800 ps
CPU time 16.08 seconds
Started Mar 26 01:29:15 PM PDT 24
Finished Mar 26 01:29:31 PM PDT 24
Peak memory 274864 kb
Host smart-24b605a4-b9ce-4698-b880-24596ec2400d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646235197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.646235197
Directory /workspace/72.flash_ctrl_connect/latest

Test location /workspace/coverage/default/72.flash_ctrl_otp_reset.2645506985
Short name T503
Test name
Test status
Simulation time 74718900 ps
CPU time 133.07 seconds
Started Mar 26 01:29:16 PM PDT 24
Finished Mar 26 01:31:29 PM PDT 24
Peak memory 260332 kb
Host smart-6c9a2a8f-940b-459c-9aca-f532dc68aeb3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645506985 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_o
tp_reset.2645506985
Directory /workspace/72.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/73.flash_ctrl_connect.177206589
Short name T851
Test name
Test status
Simulation time 23687600 ps
CPU time 15.67 seconds
Started Mar 26 01:29:16 PM PDT 24
Finished Mar 26 01:29:32 PM PDT 24
Peak memory 274892 kb
Host smart-c9cf1435-f839-4040-8936-f495e0543048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177206589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.177206589
Directory /workspace/73.flash_ctrl_connect/latest

Test location /workspace/coverage/default/73.flash_ctrl_otp_reset.3292798964
Short name T684
Test name
Test status
Simulation time 69710800 ps
CPU time 129.45 seconds
Started Mar 26 01:29:15 PM PDT 24
Finished Mar 26 01:31:24 PM PDT 24
Peak memory 263668 kb
Host smart-79907fba-5105-429f-b1c6-cd6fbdfbb73d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292798964 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_o
tp_reset.3292798964
Directory /workspace/73.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/74.flash_ctrl_connect.1959123519
Short name T491
Test name
Test status
Simulation time 13098600 ps
CPU time 15.42 seconds
Started Mar 26 01:29:17 PM PDT 24
Finished Mar 26 01:29:33 PM PDT 24
Peak memory 275096 kb
Host smart-577bc01a-f7b8-4336-aa05-b7e9e04911c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959123519 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.1959123519
Directory /workspace/74.flash_ctrl_connect/latest

Test location /workspace/coverage/default/74.flash_ctrl_otp_reset.305730542
Short name T1031
Test name
Test status
Simulation time 56110200 ps
CPU time 128.88 seconds
Started Mar 26 01:29:15 PM PDT 24
Finished Mar 26 01:31:25 PM PDT 24
Peak memory 259356 kb
Host smart-ab74a9fe-263b-4b8f-99ca-47cc0dcd4b49
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305730542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_ot
p_reset.305730542
Directory /workspace/74.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/75.flash_ctrl_connect.108253150
Short name T828
Test name
Test status
Simulation time 47798800 ps
CPU time 13.29 seconds
Started Mar 26 01:29:16 PM PDT 24
Finished Mar 26 01:29:30 PM PDT 24
Peak memory 275144 kb
Host smart-a7bb4704-c75a-4575-b2be-308d5a687ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108253150 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.108253150
Directory /workspace/75.flash_ctrl_connect/latest

Test location /workspace/coverage/default/75.flash_ctrl_otp_reset.2962753448
Short name T878
Test name
Test status
Simulation time 52705000 ps
CPU time 110.83 seconds
Started Mar 26 01:29:16 PM PDT 24
Finished Mar 26 01:31:07 PM PDT 24
Peak memory 258968 kb
Host smart-bfb71812-ddef-4f86-8a64-7804c92c1e1a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962753448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_o
tp_reset.2962753448
Directory /workspace/75.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/76.flash_ctrl_connect.39920916
Short name T471
Test name
Test status
Simulation time 47803800 ps
CPU time 15.68 seconds
Started Mar 26 01:29:19 PM PDT 24
Finished Mar 26 01:29:35 PM PDT 24
Peak memory 275280 kb
Host smart-21c0a135-d877-472c-87fa-21c871e981c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39920916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.39920916
Directory /workspace/76.flash_ctrl_connect/latest

Test location /workspace/coverage/default/76.flash_ctrl_otp_reset.1294896488
Short name T913
Test name
Test status
Simulation time 141115100 ps
CPU time 129.65 seconds
Started Mar 26 01:29:16 PM PDT 24
Finished Mar 26 01:31:25 PM PDT 24
Peak memory 258968 kb
Host smart-75ec5978-63f4-419f-ba27-5a1d150d7aae
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294896488 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_o
tp_reset.1294896488
Directory /workspace/76.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/77.flash_ctrl_connect.934188271
Short name T853
Test name
Test status
Simulation time 45453700 ps
CPU time 13.46 seconds
Started Mar 26 01:29:16 PM PDT 24
Finished Mar 26 01:29:29 PM PDT 24
Peak memory 275052 kb
Host smart-8d3c1d4e-2164-4c4d-b39e-7db3d3c6e5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934188271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.934188271
Directory /workspace/77.flash_ctrl_connect/latest

Test location /workspace/coverage/default/77.flash_ctrl_otp_reset.3519519366
Short name T484
Test name
Test status
Simulation time 71273900 ps
CPU time 130.69 seconds
Started Mar 26 01:29:19 PM PDT 24
Finished Mar 26 01:31:30 PM PDT 24
Peak memory 259320 kb
Host smart-5262a835-c3b0-413e-a231-fa4dac67e637
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519519366 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_o
tp_reset.3519519366
Directory /workspace/77.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/78.flash_ctrl_connect.1038810945
Short name T443
Test name
Test status
Simulation time 23646300 ps
CPU time 15.4 seconds
Started Mar 26 01:29:15 PM PDT 24
Finished Mar 26 01:29:30 PM PDT 24
Peak memory 274672 kb
Host smart-499e205b-4216-42a0-9b1d-bf938716bbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038810945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.1038810945
Directory /workspace/78.flash_ctrl_connect/latest

Test location /workspace/coverage/default/78.flash_ctrl_otp_reset.2374516836
Short name T327
Test name
Test status
Simulation time 346157100 ps
CPU time 131.06 seconds
Started Mar 26 01:29:19 PM PDT 24
Finished Mar 26 01:31:31 PM PDT 24
Peak memory 259172 kb
Host smart-ca1ae94a-35bf-4a13-bbcb-25b8d52d8d1e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374516836 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_o
tp_reset.2374516836
Directory /workspace/78.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/79.flash_ctrl_connect.4250710538
Short name T486
Test name
Test status
Simulation time 43449500 ps
CPU time 13.12 seconds
Started Mar 26 01:29:28 PM PDT 24
Finished Mar 26 01:29:41 PM PDT 24
Peak memory 275236 kb
Host smart-f1b101ca-d72e-4db1-9265-9691b3d5186c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250710538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.4250710538
Directory /workspace/79.flash_ctrl_connect/latest

Test location /workspace/coverage/default/79.flash_ctrl_otp_reset.1381070823
Short name T329
Test name
Test status
Simulation time 56922400 ps
CPU time 132.08 seconds
Started Mar 26 01:29:15 PM PDT 24
Finished Mar 26 01:31:28 PM PDT 24
Peak memory 260340 kb
Host smart-bac616ce-3725-423d-b208-496f3f5342f5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381070823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_o
tp_reset.1381070823
Directory /workspace/79.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_alert_test.2941308261
Short name T723
Test name
Test status
Simulation time 27512900 ps
CPU time 13.47 seconds
Started Mar 26 01:25:08 PM PDT 24
Finished Mar 26 01:25:22 PM PDT 24
Peak memory 257344 kb
Host smart-fecdf739-dd36-4e84-a42b-b0a8f643a29e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941308261 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.2
941308261
Directory /workspace/8.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.flash_ctrl_connect.894689291
Short name T457
Test name
Test status
Simulation time 21118600 ps
CPU time 15.59 seconds
Started Mar 26 01:24:49 PM PDT 24
Finished Mar 26 01:25:04 PM PDT 24
Peak memory 275180 kb
Host smart-25daf34e-a8b1-4a4b-8e17-c9ed84ec0162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894689291 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.894689291
Directory /workspace/8.flash_ctrl_connect/latest

Test location /workspace/coverage/default/8.flash_ctrl_disable.1471633489
Short name T179
Test name
Test status
Simulation time 11033600 ps
CPU time 22.03 seconds
Started Mar 26 01:24:50 PM PDT 24
Finished Mar 26 01:25:12 PM PDT 24
Peak memory 272556 kb
Host smart-84145251-d8e6-487d-b20b-bd6db9aacae4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471633489 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_disable.1471633489
Directory /workspace/8.flash_ctrl_disable/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_mp.3240453479
Short name T577
Test name
Test status
Simulation time 20727608300 ps
CPU time 2429.91 seconds
Started Mar 26 01:24:51 PM PDT 24
Finished Mar 26 02:05:21 PM PDT 24
Peak memory 263248 kb
Host smart-c9be254b-d2b1-4470-af8e-7b4ed66048df
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240453479 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_err
or_mp.3240453479
Directory /workspace/8.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_prog_win.2733612337
Short name T715
Test name
Test status
Simulation time 1771808700 ps
CPU time 899.7 seconds
Started Mar 26 01:24:51 PM PDT 24
Finished Mar 26 01:39:51 PM PDT 24
Peak memory 269644 kb
Host smart-aa615ec2-8a74-4361-8f4a-dca55dd11619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733612337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.2733612337
Directory /workspace/8.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/8.flash_ctrl_fetch_code.3061260811
Short name T1039
Test name
Test status
Simulation time 125851000 ps
CPU time 21.62 seconds
Started Mar 26 01:24:49 PM PDT 24
Finished Mar 26 01:25:11 PM PDT 24
Peak memory 264108 kb
Host smart-61eeb3ea-4263-4013-b18e-b25db175532a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061260811 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetch_code.3061260811
Directory /workspace/8.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.1744468523
Short name T987
Test name
Test status
Simulation time 10019996700 ps
CPU time 68.56 seconds
Started Mar 26 01:24:51 PM PDT 24
Finished Mar 26 01:25:59 PM PDT 24
Peak memory 276476 kb
Host smart-7aa6bc22-39bf-4d3c-b55b-0cc0f5b39014
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744468523 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.1744468523
Directory /workspace/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.2986790467
Short name T264
Test name
Test status
Simulation time 25308900 ps
CPU time 13.47 seconds
Started Mar 26 01:24:50 PM PDT 24
Finished Mar 26 01:25:04 PM PDT 24
Peak memory 258292 kb
Host smart-14c5c30b-bf35-4f68-8a53-83eb6137f497
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986790467 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_seed_err.2986790467
Directory /workspace/8.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_rma_reset.980785703
Short name T961
Test name
Test status
Simulation time 40122639200 ps
CPU time 832.16 seconds
Started Mar 26 01:24:50 PM PDT 24
Finished Mar 26 01:38:42 PM PDT 24
Peak memory 262820 kb
Host smart-c90990e0-f42d-4855-bff0-d176d1df13fe
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980785703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.flash_ctrl_hw_rma_reset.980785703
Directory /workspace/8.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.2670420562
Short name T358
Test name
Test status
Simulation time 8750714200 ps
CPU time 187.64 seconds
Started Mar 26 01:24:52 PM PDT 24
Finished Mar 26 01:28:00 PM PDT 24
Peak memory 291964 kb
Host smart-42e009b8-1fe6-478b-a636-c4618ffe7c2e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670420562 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd_slow_flash.2670420562
Directory /workspace/8.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr.1685860573
Short name T579
Test name
Test status
Simulation time 11159389900 ps
CPU time 105.7 seconds
Started Mar 26 01:24:53 PM PDT 24
Finished Mar 26 01:26:38 PM PDT 24
Peak memory 260080 kb
Host smart-d754c9f3-f582-4825-b3d9-df531751a4a3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685860573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.flash_ctrl_intr_wr.1685860573
Directory /workspace/8.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/8.flash_ctrl_invalid_op.642184645
Short name T232
Test name
Test status
Simulation time 2544137200 ps
CPU time 83.77 seconds
Started Mar 26 01:24:49 PM PDT 24
Finished Mar 26 01:26:13 PM PDT 24
Peak memory 259800 kb
Host smart-93a3c253-ece3-4839-b775-1a58490d5d50
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642184645 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.642184645
Directory /workspace/8.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/8.flash_ctrl_lcmgr_intg.3538983647
Short name T821
Test name
Test status
Simulation time 137890000 ps
CPU time 13.43 seconds
Started Mar 26 01:24:49 PM PDT 24
Finished Mar 26 01:25:03 PM PDT 24
Peak memory 258780 kb
Host smart-4425940c-5b37-456d-8964-1be564d0a0ef
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538983647 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.flash_ctrl_lcmgr_intg.3538983647
Directory /workspace/8.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/8.flash_ctrl_mp_regions.3536633905
Short name T815
Test name
Test status
Simulation time 3856142800 ps
CPU time 124.13 seconds
Started Mar 26 01:25:02 PM PDT 24
Finished Mar 26 01:27:07 PM PDT 24
Peak memory 261400 kb
Host smart-186d2f44-8907-4454-a89e-105b529bf8a1
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536633905 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 8.flash_ctrl_mp_regions.3536633905
Directory /workspace/8.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/8.flash_ctrl_otp_reset.2680398282
Short name T139
Test name
Test status
Simulation time 70626000 ps
CPU time 130.85 seconds
Started Mar 26 01:24:51 PM PDT 24
Finished Mar 26 01:27:02 PM PDT 24
Peak memory 263456 kb
Host smart-3244c6e2-9c25-4515-8f7d-ba481d1bfb9c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680398282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ot
p_reset.2680398282
Directory /workspace/8.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_phy_arb.1672464631
Short name T203
Test name
Test status
Simulation time 3138108900 ps
CPU time 351.22 seconds
Started Mar 26 01:24:49 PM PDT 24
Finished Mar 26 01:30:41 PM PDT 24
Peak memory 260832 kb
Host smart-e861ba54-0bf4-42a2-a000-9c77074f80f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1672464631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.1672464631
Directory /workspace/8.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/8.flash_ctrl_prog_reset.2390977858
Short name T784
Test name
Test status
Simulation time 77332000 ps
CPU time 13.43 seconds
Started Mar 26 01:24:51 PM PDT 24
Finished Mar 26 01:25:04 PM PDT 24
Peak memory 264164 kb
Host smart-1deba793-1209-4729-9445-c5837783a331
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390977858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_prog_res
et.2390977858
Directory /workspace/8.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_rand_ops.1709623420
Short name T110
Test name
Test status
Simulation time 652114000 ps
CPU time 1052.97 seconds
Started Mar 26 01:24:54 PM PDT 24
Finished Mar 26 01:42:27 PM PDT 24
Peak memory 285136 kb
Host smart-d67ba79b-f224-4eb9-b710-421ba8cb85f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709623420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.1709623420
Directory /workspace/8.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/8.flash_ctrl_re_evict.1656725792
Short name T428
Test name
Test status
Simulation time 82604200 ps
CPU time 34.85 seconds
Started Mar 26 01:24:50 PM PDT 24
Finished Mar 26 01:25:25 PM PDT 24
Peak memory 272524 kb
Host smart-0a4d3bc4-4202-4c0c-8862-f6963f789e92
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656725792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla
sh_ctrl_re_evict.1656725792
Directory /workspace/8.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro.385018888
Short name T793
Test name
Test status
Simulation time 434155900 ps
CPU time 95.22 seconds
Started Mar 26 01:24:50 PM PDT 24
Finished Mar 26 01:26:26 PM PDT 24
Peak memory 280076 kb
Host smart-1916a7f9-6a36-436a-aaf3-38d1c3d257be
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385018888 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.flash_ctrl_ro.385018888
Directory /workspace/8.flash_ctrl_ro/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_serr.136601553
Short name T972
Test name
Test status
Simulation time 2194305500 ps
CPU time 117.49 seconds
Started Mar 26 01:24:49 PM PDT 24
Finished Mar 26 01:26:47 PM PDT 24
Peak memory 293332 kb
Host smart-efdafc56-4061-49da-ae13-c21af959f6f3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136601553 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 8.flash_ctrl_ro_serr.136601553
Directory /workspace/8.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw.1520767729
Short name T883
Test name
Test status
Simulation time 12408341400 ps
CPU time 554.81 seconds
Started Mar 26 01:24:51 PM PDT 24
Finished Mar 26 01:34:06 PM PDT 24
Peak memory 318328 kb
Host smart-4146a056-51e5-4d2e-857d-1af75de8d14f
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520767729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ct
rl_rw.1520767729
Directory /workspace/8.flash_ctrl_rw/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict.400816198
Short name T823
Test name
Test status
Simulation time 71321500 ps
CPU time 31.07 seconds
Started Mar 26 01:24:48 PM PDT 24
Finished Mar 26 01:25:19 PM PDT 24
Peak memory 272540 kb
Host smart-5a1598ea-4b9a-4569-b870-2e6d45d3e13c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400816198 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas
h_ctrl_rw_evict.400816198
Directory /workspace/8.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict_all_en.230181065
Short name T874
Test name
Test status
Simulation time 39281000 ps
CPU time 27.58 seconds
Started Mar 26 01:24:50 PM PDT 24
Finished Mar 26 01:25:18 PM PDT 24
Peak memory 273832 kb
Host smart-8b880d22-b26e-434b-b81a-fd8f99a1fc1f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230181065 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict_all_en.230181065
Directory /workspace/8.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/8.flash_ctrl_sec_info_access.3774720540
Short name T866
Test name
Test status
Simulation time 3609506400 ps
CPU time 67.96 seconds
Started Mar 26 01:24:49 PM PDT 24
Finished Mar 26 01:25:57 PM PDT 24
Peak memory 263676 kb
Host smart-a87cfcde-7c03-4963-aaa2-cd90c447a24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774720540 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.3774720540
Directory /workspace/8.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/8.flash_ctrl_smoke.1474808223
Short name T451
Test name
Test status
Simulation time 74902100 ps
CPU time 48.98 seconds
Started Mar 26 01:24:50 PM PDT 24
Finished Mar 26 01:25:39 PM PDT 24
Peak memory 269704 kb
Host smart-f9c07f8c-01fd-4c70-a228-61b3b8eb7c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474808223 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.1474808223
Directory /workspace/8.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/8.flash_ctrl_wo.3779165674
Short name T587
Test name
Test status
Simulation time 12907271900 ps
CPU time 228.9 seconds
Started Mar 26 01:24:49 PM PDT 24
Finished Mar 26 01:28:38 PM PDT 24
Peak memory 258696 kb
Host smart-217f8c2c-44ea-453e-8d9c-52386f6a25f9
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779165674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.flash_ctrl_wo.3779165674
Directory /workspace/8.flash_ctrl_wo/latest

Test location /workspace/coverage/default/9.flash_ctrl_alert_test.3051985050
Short name T3
Test name
Test status
Simulation time 303534000 ps
CPU time 13.93 seconds
Started Mar 26 01:25:05 PM PDT 24
Finished Mar 26 01:25:19 PM PDT 24
Peak memory 257220 kb
Host smart-8529b7a8-bdbe-419a-abc2-11986ed7f20e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051985050 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.3
051985050
Directory /workspace/9.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.flash_ctrl_connect.1437052565
Short name T669
Test name
Test status
Simulation time 107045300 ps
CPU time 13.14 seconds
Started Mar 26 01:25:02 PM PDT 24
Finished Mar 26 01:25:16 PM PDT 24
Peak memory 275096 kb
Host smart-e229aad6-ba34-478e-a44c-f8c7f14cdfdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437052565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.1437052565
Directory /workspace/9.flash_ctrl_connect/latest

Test location /workspace/coverage/default/9.flash_ctrl_disable.3099696994
Short name T712
Test name
Test status
Simulation time 14575400 ps
CPU time 20.46 seconds
Started Mar 26 01:25:03 PM PDT 24
Finished Mar 26 01:25:24 PM PDT 24
Peak memory 264360 kb
Host smart-e9d6493e-16d6-4a98-bd23-b97eb8d25754
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099696994 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_disable.3099696994
Directory /workspace/9.flash_ctrl_disable/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_mp.3440124325
Short name T623
Test name
Test status
Simulation time 5302478600 ps
CPU time 2109.47 seconds
Started Mar 26 01:25:05 PM PDT 24
Finished Mar 26 02:00:15 PM PDT 24
Peak memory 263340 kb
Host smart-36d14ec4-5442-4c1c-b7c2-b06c8d7854c4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440124325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_err
or_mp.3440124325
Directory /workspace/9.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_prog_win.2044794609
Short name T681
Test name
Test status
Simulation time 2640488000 ps
CPU time 814.71 seconds
Started Mar 26 01:25:10 PM PDT 24
Finished Mar 26 01:38:45 PM PDT 24
Peak memory 270068 kb
Host smart-22d51fb0-f93d-4d40-94b2-d420654e8917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044794609 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.2044794609
Directory /workspace/9.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/9.flash_ctrl_fetch_code.1174651703
Short name T761
Test name
Test status
Simulation time 1452787500 ps
CPU time 21.44 seconds
Started Mar 26 01:25:03 PM PDT 24
Finished Mar 26 01:25:25 PM PDT 24
Peak memory 264180 kb
Host smart-80938fbb-d882-4f71-8efe-a3c3bb2e3d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174651703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetch_code.1174651703
Directory /workspace/9.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.4173709943
Short name T897
Test name
Test status
Simulation time 10020033000 ps
CPU time 169.02 seconds
Started Mar 26 01:25:01 PM PDT 24
Finished Mar 26 01:27:51 PM PDT 24
Peak memory 267836 kb
Host smart-6661f54c-f555-4c4c-905a-20b6f065fc87
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173709943 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.4173709943
Directory /workspace/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.1240870067
Short name T777
Test name
Test status
Simulation time 89734000 ps
CPU time 13.15 seconds
Started Mar 26 01:25:02 PM PDT 24
Finished Mar 26 01:25:16 PM PDT 24
Peak memory 264148 kb
Host smart-527405c9-08ef-4fb0-b740-1f374bb1326b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240870067 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_seed_err.1240870067
Directory /workspace/9.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_rma_reset.2974886015
Short name T142
Test name
Test status
Simulation time 40124339200 ps
CPU time 812.11 seconds
Started Mar 26 01:25:01 PM PDT 24
Finished Mar 26 01:38:33 PM PDT 24
Peak memory 263524 kb
Host smart-3df59039-123e-4227-a968-39b6a6881121
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974886015 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.flash_ctrl_hw_rma_reset.2974886015
Directory /workspace/9.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_sec_otp.25910511
Short name T689
Test name
Test status
Simulation time 14595073600 ps
CPU time 271.7 seconds
Started Mar 26 01:25:02 PM PDT 24
Finished Mar 26 01:29:35 PM PDT 24
Peak memory 261768 kb
Host smart-1f6358bb-9d7d-4de4-b152-507a12f611de
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25910511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_
sec_otp.25910511
Directory /workspace/9.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.1636902263
Short name T802
Test name
Test status
Simulation time 85113035200 ps
CPU time 271.52 seconds
Started Mar 26 01:25:08 PM PDT 24
Finished Mar 26 01:29:39 PM PDT 24
Peak memory 284000 kb
Host smart-5e3a2be1-c549-4a00-9424-70a89916c261
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636902263 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd_slow_flash.1636902263
Directory /workspace/9.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr.2642995875
Short name T880
Test name
Test status
Simulation time 18459973800 ps
CPU time 106.71 seconds
Started Mar 26 01:25:03 PM PDT 24
Finished Mar 26 01:26:50 PM PDT 24
Peak memory 264384 kb
Host smart-f29e2a5e-f50c-4d7e-8ed3-e91b33760701
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642995875 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.flash_ctrl_intr_wr.2642995875
Directory /workspace/9.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr_slow_flash.2456326289
Short name T458
Test name
Test status
Simulation time 192215432000 ps
CPU time 374.12 seconds
Started Mar 26 01:25:05 PM PDT 24
Finished Mar 26 01:31:20 PM PDT 24
Peak memory 260388 kb
Host smart-f39d22f2-39c9-4d48-bd6e-146beb66ad9e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245
6326289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.2456326289
Directory /workspace/9.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_invalid_op.556522197
Short name T80
Test name
Test status
Simulation time 2167844200 ps
CPU time 71.11 seconds
Started Mar 26 01:25:02 PM PDT 24
Finished Mar 26 01:26:14 PM PDT 24
Peak memory 259672 kb
Host smart-565e2ada-7771-4722-9441-3da82e4d533a
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556522197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.556522197
Directory /workspace/9.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/9.flash_ctrl_lcmgr_intg.3781500972
Short name T667
Test name
Test status
Simulation time 15382100 ps
CPU time 13.22 seconds
Started Mar 26 01:25:02 PM PDT 24
Finished Mar 26 01:25:16 PM PDT 24
Peak memory 258740 kb
Host smart-1d102109-2199-4657-8350-d2ed269913f5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781500972 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.flash_ctrl_lcmgr_intg.3781500972
Directory /workspace/9.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/9.flash_ctrl_mp_regions.3642891693
Short name T115
Test name
Test status
Simulation time 10492657400 ps
CPU time 228.97 seconds
Started Mar 26 01:25:06 PM PDT 24
Finished Mar 26 01:28:55 PM PDT 24
Peak memory 272800 kb
Host smart-2ae27af9-e9e7-4dfe-bbe2-d71239623075
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642891693 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.flash_ctrl_mp_regions.3642891693
Directory /workspace/9.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/9.flash_ctrl_otp_reset.1409160306
Short name T822
Test name
Test status
Simulation time 74408600 ps
CPU time 128.75 seconds
Started Mar 26 01:25:06 PM PDT 24
Finished Mar 26 01:27:15 PM PDT 24
Peak memory 259096 kb
Host smart-c2351f18-f039-4856-93c7-2dbf1191614e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409160306 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ot
p_reset.1409160306
Directory /workspace/9.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_phy_arb.3602944967
Short name T888
Test name
Test status
Simulation time 58273200 ps
CPU time 66.02 seconds
Started Mar 26 01:24:59 PM PDT 24
Finished Mar 26 01:26:06 PM PDT 24
Peak memory 260772 kb
Host smart-762ba063-c604-4d86-9c8a-23df1c4792ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3602944967 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.3602944967
Directory /workspace/9.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/9.flash_ctrl_prog_reset.657552906
Short name T833
Test name
Test status
Simulation time 20841400 ps
CPU time 13.5 seconds
Started Mar 26 01:25:02 PM PDT 24
Finished Mar 26 01:25:16 PM PDT 24
Peak memory 259288 kb
Host smart-741984a4-9c35-4160-96b4-e8cb5225800f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657552906 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_prog_rese
t.657552906
Directory /workspace/9.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_rand_ops.871705518
Short name T959
Test name
Test status
Simulation time 296794100 ps
CPU time 923.73 seconds
Started Mar 26 01:25:04 PM PDT 24
Finished Mar 26 01:40:28 PM PDT 24
Peak memory 282640 kb
Host smart-76507718-dd8a-4a93-bbac-c18acc85f771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871705518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.871705518
Directory /workspace/9.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/9.flash_ctrl_re_evict.3932359995
Short name T1045
Test name
Test status
Simulation time 178322300 ps
CPU time 30.97 seconds
Started Mar 26 01:25:02 PM PDT 24
Finished Mar 26 01:25:33 PM PDT 24
Peak memory 273648 kb
Host smart-fc546347-2545-401c-b146-25398d0646c0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932359995 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla
sh_ctrl_re_evict.3932359995
Directory /workspace/9.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro.3978966936
Short name T219
Test name
Test status
Simulation time 3619366500 ps
CPU time 102.17 seconds
Started Mar 26 01:25:02 PM PDT 24
Finished Mar 26 01:26:45 PM PDT 24
Peak memory 280168 kb
Host smart-7f7c8a83-0645-458b-974f-6c3e99bbe199
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978966936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.flash_ctrl_ro.3978966936
Directory /workspace/9.flash_ctrl_ro/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_serr.3533858210
Short name T178
Test name
Test status
Simulation time 947523000 ps
CPU time 132.05 seconds
Started Mar 26 01:25:10 PM PDT 24
Finished Mar 26 01:27:22 PM PDT 24
Peak memory 280724 kb
Host smart-26615379-8f7a-467f-90d6-4a903b36f3b6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533858210 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.flash_ctrl_ro_serr.3533858210
Directory /workspace/9.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw.3112802414
Short name T608
Test name
Test status
Simulation time 6544410600 ps
CPU time 561.87 seconds
Started Mar 26 01:25:01 PM PDT 24
Finished Mar 26 01:34:23 PM PDT 24
Peak memory 313096 kb
Host smart-d88e8a4f-2882-4732-a0c8-2122bdb52a42
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112802414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_
SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ct
rl_rw.3112802414
Directory /workspace/9.flash_ctrl_rw/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict.493559459
Short name T333
Test name
Test status
Simulation time 45536000 ps
CPU time 30.58 seconds
Started Mar 26 01:25:06 PM PDT 24
Finished Mar 26 01:25:37 PM PDT 24
Peak memory 272560 kb
Host smart-d45d0b98-2e2b-4322-ad9c-2d6747a23754
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493559459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas
h_ctrl_rw_evict.493559459
Directory /workspace/9.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict_all_en.3763065279
Short name T425
Test name
Test status
Simulation time 65446800 ps
CPU time 31.56 seconds
Started Mar 26 01:25:04 PM PDT 24
Finished Mar 26 01:25:36 PM PDT 24
Peak memory 265432 kb
Host smart-eb65c993-d1f4-4480-9a7e-25ecc8b1302e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763065279 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict_all_en.3763065279
Directory /workspace/9.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_serr.680232261
Short name T224
Test name
Test status
Simulation time 10907981300 ps
CPU time 476.73 seconds
Started Mar 26 01:25:01 PM PDT 24
Finished Mar 26 01:32:58 PM PDT 24
Peak memory 311404 kb
Host smart-6c3d43c4-ca87-4564-85ca-415cfd273602
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680232261 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_se
rr.680232261
Directory /workspace/9.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_sec_info_access.194822565
Short name T739
Test name
Test status
Simulation time 2409253600 ps
CPU time 67.69 seconds
Started Mar 26 01:25:01 PM PDT 24
Finished Mar 26 01:26:09 PM PDT 24
Peak memory 261996 kb
Host smart-9c16742c-b836-4f61-a6bd-5cf338a85e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194822565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.194822565
Directory /workspace/9.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/9.flash_ctrl_smoke.959303653
Short name T1021
Test name
Test status
Simulation time 95231000 ps
CPU time 120.57 seconds
Started Mar 26 01:25:01 PM PDT 24
Finished Mar 26 01:27:02 PM PDT 24
Peak memory 275276 kb
Host smart-61145884-0326-4541-b0cd-95828aa484c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959303653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.959303653
Directory /workspace/9.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/9.flash_ctrl_wo.3766598086
Short name T664
Test name
Test status
Simulation time 7443258300 ps
CPU time 137.09 seconds
Started Mar 26 01:25:02 PM PDT 24
Finished Mar 26 01:27:20 PM PDT 24
Peak memory 258252 kb
Host smart-513de3cb-c1b7-4c57-bde7-bccd89b92fde
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766598086 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.flash_ctrl_wo.3766598086
Directory /workspace/9.flash_ctrl_wo/latest
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