Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	352428	1		T1	1		T2	1		T3	1
all_values[1]	352428	1		T1	1		T2	1		T3	1
all_values[2]	352428	1		T1	1		T2	1		T3	1
all_values[3]	352428	1		T1	1		T2	1		T3	1
all_values[4]	352428	1		T1	1		T2	1		T3	1
all_values[5]	352428	1		T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	711337	1		T1	6		T2	6		T3	6
auto[1]	1403231	1		T7	8848		T9	15388		T25	4452

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1033136	1		T1	4		T2	4		T3	4
auto[1]	1081432	1		T1	2		T2	2		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	352281	1		T1	1		T2	1		T3	1
all_values[0]	auto[1]	auto[1]	147	1		T256	2		T257	2		T258	4
all_values[1]	auto[0]	auto[1]	352292	1		T1	1		T2	1		T3	1
all_values[1]	auto[1]	auto[1]	136	1		T256	2		T257	3		T258	4
all_values[2]	auto[0]	auto[0]	1622	1		T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	61	1		T256	2		T257	2		T258	1
all_values[2]	auto[1]	auto[0]	350685	1		T7	2212		T9	3847		T25	1113
all_values[2]	auto[1]	auto[1]	60	1		T256	1		T257	2		T258	1
all_values[3]	auto[0]	auto[0]	1646	1		T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	78	1		T256	1		T258	1		T320	3
all_values[3]	auto[1]	auto[0]	72666	1		T7	1106		T9	961		T25	1113
all_values[3]	auto[1]	auto[1]	278038	1		T7	1106		T9	2886		T34	1273
all_values[4]	auto[0]	auto[0]	1144	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	550	1		T4	1		T5	1		T20	1
all_values[4]	auto[1]	auto[0]	253156	1		T7	1106		T9	2885		T25	1
all_values[4]	auto[1]	auto[1]	97578	1		T7	1106		T9	962		T25	1112
all_values[5]	auto[0]	auto[0]	1528	1		T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	135	1		T4	1		T36	1		T37	1
all_values[5]	auto[1]	auto[0]	350689	1		T7	2212		T9	3847		T25	1113
all_values[5]	auto[1]	auto[1]	76	1		T257	1		T258	2		T320	2