Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
202 |
1 |
|
T5 |
8 |
|
T52 |
1 |
|
T382 |
1 |
| others[1] |
217 |
1 |
|
T4 |
1 |
|
T5 |
16 |
|
T25 |
1 |
| others[2] |
213 |
1 |
|
T5 |
7 |
|
T36 |
1 |
|
T131 |
1 |
| others[3] |
383 |
1 |
|
T5 |
16 |
|
T7 |
1 |
|
T182 |
1 |
| false |
112 |
1 |
|
T5 |
7 |
|
T391 |
1 |
|
T393 |
1 |
| true |
12583 |
1 |
|
T1 |
119 |
|
T5 |
47 |
|
T20 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T5 |
7 |
|
T181 |
1 |
|
T397 |
1 |
| others[1] |
208 |
1 |
|
T5 |
13 |
|
T131 |
1 |
|
T121 |
1 |
| others[2] |
214 |
1 |
|
T5 |
7 |
|
T228 |
1 |
|
T111 |
1 |
| others[3] |
387 |
1 |
|
T5 |
15 |
|
T29 |
1 |
|
T248 |
1 |
| false |
103 |
1 |
|
T5 |
2 |
|
T25 |
1 |
|
T393 |
1 |
| true |
12573 |
1 |
|
T1 |
119 |
|
T4 |
1 |
|
T5 |
57 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8187 |
1 |
|
T1 |
119 |
|
T5 |
28 |
|
T20 |
1 |
| others[1] |
1258 |
1 |
|
T5 |
13 |
|
T22 |
13 |
|
T69 |
20 |
| others[2] |
1218 |
1 |
|
T5 |
16 |
|
T20 |
1 |
|
T8 |
1 |
| others[3] |
1980 |
1 |
|
T5 |
37 |
|
T20 |
2 |
|
T8 |
1 |
| false |
633 |
1 |
|
T5 |
7 |
|
T20 |
1 |
|
T22 |
10 |
| true |
434 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8155 |
1 |
|
T1 |
119 |
|
T5 |
22 |
|
T6 |
40 |
| others[1] |
1183 |
1 |
|
T5 |
16 |
|
T20 |
2 |
|
T22 |
12 |
| others[2] |
1259 |
1 |
|
T5 |
21 |
|
T22 |
21 |
|
T69 |
14 |
| others[3] |
2037 |
1 |
|
T5 |
29 |
|
T20 |
2 |
|
T22 |
20 |
| false |
647 |
1 |
|
T5 |
13 |
|
T20 |
1 |
|
T8 |
1 |
| true |
429 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
117 |
1 |
|
T5 |
3 |
|
T383 |
1 |
|
T272 |
1 |
| others[1] |
106 |
1 |
|
T5 |
4 |
|
T105 |
1 |
|
T382 |
1 |
| others[2] |
103 |
1 |
|
T5 |
1 |
|
T131 |
1 |
|
T391 |
1 |
| others[3] |
186 |
1 |
|
T5 |
8 |
|
T210 |
1 |
|
T64 |
1 |
| false |
44 |
1 |
|
T5 |
1 |
|
T52 |
1 |
|
T396 |
1 |
| true |
13154 |
1 |
|
T1 |
119 |
|
T4 |
1 |
|
T5 |
84 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
236 |
1 |
|
T5 |
11 |
|
T36 |
1 |
|
T64 |
1 |
| others[1] |
239 |
1 |
|
T5 |
13 |
|
T105 |
1 |
|
T121 |
1 |
| others[2] |
217 |
1 |
|
T5 |
10 |
|
T34 |
1 |
|
T27 |
1 |
| others[3] |
381 |
1 |
|
T5 |
13 |
|
T29 |
1 |
|
T248 |
1 |
| false |
116 |
1 |
|
T5 |
4 |
|
T7 |
1 |
|
T131 |
1 |
| true |
12521 |
1 |
|
T1 |
119 |
|
T4 |
1 |
|
T5 |
50 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8014 |
1 |
|
T1 |
119 |
|
T5 |
13 |
|
T6 |
40 |
| others[1] |
983 |
1 |
|
T5 |
17 |
|
T20 |
1 |
|
T8 |
1 |
| others[2] |
1014 |
1 |
|
T5 |
21 |
|
T7 |
1 |
|
T8 |
1 |
| others[3] |
1774 |
1 |
|
T5 |
42 |
|
T20 |
2 |
|
T22 |
26 |
| false |
551 |
1 |
|
T5 |
8 |
|
T20 |
2 |
|
T22 |
7 |
| true |
1374 |
1 |
|
T4 |
1 |
|
T106 |
1 |
|
T36 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
235 |
1 |
|
T5 |
10 |
|
T24 |
1 |
|
T36 |
1 |
| others[1] |
226 |
1 |
|
T5 |
9 |
|
T228 |
1 |
|
T382 |
1 |
| others[2] |
209 |
1 |
|
T5 |
11 |
|
T52 |
1 |
|
T248 |
1 |
| others[3] |
370 |
1 |
|
T4 |
1 |
|
T5 |
20 |
|
T34 |
1 |
| false |
120 |
1 |
|
T5 |
6 |
|
T393 |
1 |
|
T400 |
1 |
| true |
12550 |
1 |
|
T1 |
119 |
|
T5 |
45 |
|
T20 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
215 |
1 |
|
T4 |
1 |
|
T5 |
4 |
|
T385 |
1 |
| others[1] |
208 |
1 |
|
T5 |
8 |
|
T76 |
1 |
|
T401 |
1 |
| others[2] |
206 |
1 |
|
T5 |
12 |
|
T382 |
1 |
|
T91 |
7 |
| others[3] |
343 |
1 |
|
T5 |
17 |
|
T105 |
1 |
|
T131 |
1 |
| false |
105 |
1 |
|
T5 |
1 |
|
T37 |
1 |
|
T398 |
1 |
| true |
12633 |
1 |
|
T1 |
119 |
|
T5 |
59 |
|
T20 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8212 |
1 |
|
T1 |
119 |
|
T5 |
19 |
|
T20 |
1 |
| others[1] |
1213 |
1 |
|
T5 |
23 |
|
T20 |
2 |
|
T22 |
13 |
| others[2] |
1242 |
1 |
|
T5 |
21 |
|
T20 |
2 |
|
T8 |
1 |
| others[3] |
2055 |
1 |
|
T5 |
28 |
|
T9 |
1 |
|
T22 |
23 |
| false |
566 |
1 |
|
T5 |
10 |
|
T22 |
4 |
|
T69 |
4 |
| true |
422 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1247 |
1 |
|
T5 |
18 |
|
T20 |
1 |
|
T22 |
12 |
| others[1] |
1163 |
1 |
|
T5 |
17 |
|
T20 |
1 |
|
T22 |
17 |
| others[2] |
1229 |
1 |
|
T5 |
11 |
|
T8 |
1 |
|
T22 |
10 |
| others[3] |
2044 |
1 |
|
T5 |
41 |
|
T20 |
3 |
|
T8 |
1 |
| false |
606 |
1 |
|
T5 |
14 |
|
T9 |
1 |
|
T22 |
10 |
| true |
433 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
108 |
1 |
|
T5 |
3 |
|
T382 |
2 |
|
T381 |
1 |
| others[1] |
81 |
1 |
|
T5 |
3 |
|
T393 |
1 |
|
T383 |
1 |
| others[2] |
109 |
1 |
|
T5 |
3 |
|
T210 |
1 |
|
T63 |
1 |
| others[3] |
169 |
1 |
|
T4 |
1 |
|
T5 |
6 |
|
T52 |
1 |
| false |
56 |
1 |
|
T5 |
2 |
|
T105 |
1 |
|
T91 |
3 |
| true |
6199 |
1 |
|
T5 |
84 |
|
T20 |
5 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
209 |
1 |
|
T5 |
9 |
|
T7 |
1 |
|
T338 |
1 |
| others[1] |
227 |
1 |
|
T4 |
1 |
|
T5 |
11 |
|
T105 |
1 |
| others[2] |
209 |
1 |
|
T5 |
7 |
|
T228 |
1 |
|
T26 |
1 |
| others[3] |
369 |
1 |
|
T5 |
13 |
|
T131 |
1 |
|
T248 |
1 |
| false |
118 |
1 |
|
T5 |
3 |
|
T208 |
1 |
|
T349 |
1 |
| true |
5590 |
1 |
|
T5 |
58 |
|
T20 |
5 |
|
T8 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1000 |
1 |
|
T5 |
15 |
|
T20 |
2 |
|
T22 |
12 |
| others[1] |
1057 |
1 |
|
T4 |
1 |
|
T5 |
18 |
|
T20 |
2 |
| others[2] |
1016 |
1 |
|
T5 |
14 |
|
T20 |
1 |
|
T8 |
1 |
| others[3] |
1669 |
1 |
|
T5 |
38 |
|
T9 |
1 |
|
T22 |
20 |
| false |
566 |
1 |
|
T5 |
16 |
|
T24 |
1 |
|
T22 |
8 |
| true |
1414 |
1 |
|
T10 |
1 |
|
T36 |
1 |
|
T135 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T5 |
6 |
|
T34 |
1 |
|
T76 |
1 |
| others[1] |
226 |
1 |
|
T5 |
14 |
|
T131 |
1 |
|
T402 |
1 |
| others[2] |
204 |
1 |
|
T5 |
13 |
|
T36 |
1 |
|
T28 |
1 |
| others[3] |
386 |
1 |
|
T5 |
17 |
|
T7 |
1 |
|
T52 |
1 |
| false |
139 |
1 |
|
T5 |
4 |
|
T349 |
2 |
|
T343 |
1 |
| true |
5549 |
1 |
|
T4 |
1 |
|
T5 |
47 |
|
T20 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
200 |
1 |
|
T5 |
7 |
|
T29 |
1 |
|
T248 |
1 |
| others[1] |
230 |
1 |
|
T5 |
8 |
|
T105 |
1 |
|
T398 |
1 |
| others[2] |
230 |
1 |
|
T5 |
24 |
|
T382 |
1 |
|
T75 |
1 |
| others[3] |
356 |
1 |
|
T5 |
11 |
|
T210 |
1 |
|
T37 |
1 |
| false |
139 |
1 |
|
T5 |
9 |
|
T25 |
1 |
|
T403 |
1 |
| true |
5567 |
1 |
|
T4 |
1 |
|
T5 |
42 |
|
T20 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1219 |
1 |
|
T5 |
21 |
|
T22 |
20 |
|
T69 |
11 |
| others[1] |
1218 |
1 |
|
T5 |
14 |
|
T20 |
2 |
|
T22 |
18 |
| others[2] |
1212 |
1 |
|
T5 |
14 |
|
T20 |
1 |
|
T8 |
1 |
| others[3] |
2051 |
1 |
|
T5 |
38 |
|
T8 |
1 |
|
T22 |
18 |
| false |
591 |
1 |
|
T5 |
14 |
|
T20 |
2 |
|
T9 |
1 |
| true |
431 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1216 |
1 |
|
T5 |
18 |
|
T22 |
17 |
|
T105 |
1 |
| others[1] |
1228 |
1 |
|
T5 |
20 |
|
T20 |
1 |
|
T8 |
1 |
| others[2] |
1207 |
1 |
|
T5 |
18 |
|
T20 |
2 |
|
T22 |
15 |
| others[3] |
1988 |
1 |
|
T5 |
38 |
|
T20 |
2 |
|
T9 |
1 |
| false |
651 |
1 |
|
T5 |
7 |
|
T8 |
1 |
|
T22 |
4 |
| true |
432 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
106 |
1 |
|
T5 |
7 |
|
T36 |
1 |
|
T404 |
1 |
| others[1] |
92 |
1 |
|
T5 |
6 |
|
T210 |
1 |
|
T29 |
1 |
| others[2] |
105 |
1 |
|
T5 |
6 |
|
T395 |
1 |
|
T391 |
1 |
| others[3] |
180 |
1 |
|
T4 |
1 |
|
T5 |
6 |
|
T105 |
1 |
| false |
46 |
1 |
|
T5 |
3 |
|
T52 |
1 |
|
T64 |
1 |
| true |
6193 |
1 |
|
T5 |
73 |
|
T20 |
5 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
230 |
1 |
|
T5 |
8 |
|
T228 |
1 |
|
T102 |
1 |
| others[1] |
242 |
1 |
|
T5 |
14 |
|
T25 |
1 |
|
T405 |
1 |
| others[2] |
224 |
1 |
|
T5 |
12 |
|
T398 |
1 |
|
T35 |
1 |
| others[3] |
384 |
1 |
|
T4 |
1 |
|
T5 |
19 |
|
T36 |
1 |
| false |
120 |
1 |
|
T5 |
6 |
|
T276 |
1 |
|
T91 |
3 |
| true |
5522 |
1 |
|
T5 |
42 |
|
T20 |
5 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1051 |
1 |
|
T5 |
22 |
|
T20 |
3 |
|
T22 |
13 |
| others[1] |
1031 |
1 |
|
T5 |
22 |
|
T20 |
2 |
|
T8 |
1 |
| others[2] |
1026 |
1 |
|
T5 |
19 |
|
T22 |
13 |
|
T52 |
1 |
| others[3] |
1677 |
1 |
|
T5 |
29 |
|
T8 |
1 |
|
T22 |
21 |
| false |
539 |
1 |
|
T5 |
9 |
|
T22 |
7 |
|
T105 |
1 |
| true |
1398 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
219 |
1 |
|
T5 |
5 |
|
T382 |
2 |
|
T102 |
1 |
| others[1] |
222 |
1 |
|
T5 |
8 |
|
T29 |
1 |
|
T34 |
1 |
| others[2] |
228 |
1 |
|
T5 |
13 |
|
T24 |
1 |
|
T63 |
1 |
| others[3] |
369 |
1 |
|
T4 |
1 |
|
T5 |
14 |
|
T36 |
1 |
| false |
117 |
1 |
|
T5 |
10 |
|
T52 |
1 |
|
T131 |
1 |
| true |
5567 |
1 |
|
T5 |
51 |
|
T20 |
5 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
208 |
1 |
|
T5 |
7 |
|
T52 |
1 |
|
T36 |
1 |
| others[1] |
230 |
1 |
|
T5 |
11 |
|
T228 |
1 |
|
T401 |
1 |
| others[2] |
195 |
1 |
|
T5 |
9 |
|
T131 |
1 |
|
T182 |
1 |
| others[3] |
384 |
1 |
|
T4 |
1 |
|
T5 |
16 |
|
T25 |
1 |
| false |
110 |
1 |
|
T5 |
4 |
|
T29 |
1 |
|
T385 |
1 |
| true |
5595 |
1 |
|
T5 |
54 |
|
T20 |
5 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1173 |
1 |
|
T5 |
22 |
|
T8 |
1 |
|
T22 |
13 |
| others[1] |
1215 |
1 |
|
T5 |
17 |
|
T20 |
1 |
|
T22 |
15 |
| others[2] |
1200 |
1 |
|
T5 |
22 |
|
T20 |
2 |
|
T8 |
1 |
| others[3] |
2070 |
1 |
|
T5 |
32 |
|
T20 |
1 |
|
T9 |
1 |
| false |
632 |
1 |
|
T5 |
8 |
|
T20 |
1 |
|
T22 |
14 |
| true |
432 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1205 |
1 |
|
T5 |
11 |
|
T20 |
1 |
|
T8 |
1 |
| others[1] |
1224 |
1 |
|
T5 |
33 |
|
T20 |
2 |
|
T22 |
14 |
| others[2] |
1216 |
1 |
|
T5 |
21 |
|
T20 |
1 |
|
T22 |
15 |
| others[3] |
1994 |
1 |
|
T5 |
23 |
|
T8 |
1 |
|
T9 |
1 |
| false |
659 |
1 |
|
T5 |
13 |
|
T20 |
1 |
|
T22 |
6 |
| true |
424 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
105 |
1 |
|
T5 |
5 |
|
T210 |
1 |
|
T63 |
1 |
| others[1] |
98 |
1 |
|
T4 |
1 |
|
T5 |
6 |
|
T52 |
1 |
| others[2] |
103 |
1 |
|
T5 |
3 |
|
T382 |
1 |
|
T227 |
1 |
| others[3] |
194 |
1 |
|
T5 |
6 |
|
T37 |
1 |
|
T181 |
1 |
| false |
43 |
1 |
|
T5 |
3 |
|
T105 |
1 |
|
T75 |
1 |
| true |
6179 |
1 |
|
T5 |
78 |
|
T20 |
5 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T5 |
8 |
|
T25 |
1 |
|
T27 |
1 |
| others[1] |
222 |
1 |
|
T5 |
14 |
|
T28 |
1 |
|
T382 |
1 |
| others[2] |
236 |
1 |
|
T5 |
12 |
|
T24 |
1 |
|
T131 |
1 |
| others[3] |
367 |
1 |
|
T4 |
1 |
|
T5 |
11 |
|
T52 |
1 |
| false |
142 |
1 |
|
T5 |
10 |
|
T181 |
1 |
|
T338 |
1 |
| true |
5527 |
1 |
|
T5 |
46 |
|
T20 |
5 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1034 |
1 |
|
T5 |
19 |
|
T20 |
4 |
|
T9 |
1 |
| others[1] |
1051 |
1 |
|
T4 |
1 |
|
T5 |
25 |
|
T22 |
7 |
| others[2] |
1082 |
1 |
|
T5 |
18 |
|
T20 |
1 |
|
T8 |
2 |
| others[3] |
1677 |
1 |
|
T5 |
28 |
|
T7 |
1 |
|
T24 |
1 |
| false |
527 |
1 |
|
T5 |
11 |
|
T22 |
5 |
|
T69 |
9 |
| true |
1351 |
1 |
|
T15 |
1 |
|
T106 |
1 |
|
T135 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T5 |
9 |
|
T28 |
1 |
|
T75 |
1 |
| others[1] |
224 |
1 |
|
T5 |
14 |
|
T102 |
1 |
|
T337 |
1 |
| others[2] |
226 |
1 |
|
T5 |
11 |
|
T121 |
1 |
|
T280 |
1 |
| others[3] |
361 |
1 |
|
T4 |
1 |
|
T5 |
16 |
|
T7 |
1 |
| false |
107 |
1 |
|
T5 |
3 |
|
T105 |
1 |
|
T281 |
1 |
| true |
5571 |
1 |
|
T5 |
48 |
|
T20 |
5 |
|
T8 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T5 |
12 |
|
T29 |
1 |
|
T248 |
1 |
| others[1] |
208 |
1 |
|
T5 |
8 |
|
T398 |
1 |
|
T223 |
1 |
| others[2] |
191 |
1 |
|
T5 |
14 |
|
T111 |
1 |
|
T383 |
1 |
| others[3] |
364 |
1 |
|
T5 |
13 |
|
T52 |
1 |
|
T105 |
1 |
| false |
111 |
1 |
|
T382 |
1 |
|
T272 |
1 |
|
T91 |
2 |
| true |
5628 |
1 |
|
T4 |
1 |
|
T5 |
54 |
|
T20 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1263 |
1 |
|
T5 |
17 |
|
T20 |
1 |
|
T22 |
12 |
| others[1] |
1186 |
1 |
|
T5 |
17 |
|
T20 |
4 |
|
T9 |
1 |
| others[2] |
1209 |
1 |
|
T5 |
22 |
|
T22 |
13 |
|
T51 |
1 |
| others[3] |
1950 |
1 |
|
T5 |
35 |
|
T8 |
1 |
|
T22 |
30 |
| false |
686 |
1 |
|
T5 |
10 |
|
T8 |
1 |
|
T22 |
10 |
| true |
428 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T24 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |