Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1186 |
1 |
|
T5 |
22 |
|
T22 |
13 |
|
T16 |
1 |
| others[1] |
1175 |
1 |
|
T5 |
17 |
|
T22 |
15 |
|
T51 |
1 |
| others[2] |
1210 |
1 |
|
T5 |
21 |
|
T20 |
4 |
|
T22 |
15 |
| others[3] |
2098 |
1 |
|
T5 |
30 |
|
T20 |
1 |
|
T8 |
1 |
| false |
632 |
1 |
|
T5 |
11 |
|
T8 |
1 |
|
T22 |
6 |
| true |
421 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
98 |
1 |
|
T5 |
4 |
|
T406 |
1 |
|
T388 |
2 |
| others[1] |
95 |
1 |
|
T5 |
4 |
|
T383 |
1 |
|
T381 |
1 |
| others[2] |
100 |
1 |
|
T5 |
3 |
|
T210 |
1 |
|
T382 |
2 |
| others[3] |
179 |
1 |
|
T5 |
9 |
|
T52 |
1 |
|
T105 |
1 |
| false |
52 |
1 |
|
T5 |
3 |
|
T76 |
1 |
|
T91 |
3 |
| true |
6198 |
1 |
|
T4 |
1 |
|
T5 |
78 |
|
T20 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
230 |
1 |
|
T5 |
2 |
|
T26 |
1 |
|
T199 |
1 |
| others[1] |
217 |
1 |
|
T5 |
8 |
|
T24 |
1 |
|
T36 |
1 |
| others[2] |
221 |
1 |
|
T5 |
12 |
|
T228 |
1 |
|
T248 |
1 |
| others[3] |
374 |
1 |
|
T4 |
1 |
|
T5 |
18 |
|
T210 |
1 |
| false |
114 |
1 |
|
T5 |
6 |
|
T64 |
1 |
|
T382 |
1 |
| true |
5566 |
1 |
|
T5 |
55 |
|
T20 |
5 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
992 |
1 |
|
T5 |
18 |
|
T20 |
1 |
|
T22 |
20 |
| others[1] |
1082 |
1 |
|
T5 |
12 |
|
T20 |
2 |
|
T8 |
1 |
| others[2] |
1044 |
1 |
|
T5 |
17 |
|
T8 |
1 |
|
T22 |
14 |
| others[3] |
1672 |
1 |
|
T5 |
44 |
|
T20 |
2 |
|
T22 |
24 |
| false |
534 |
1 |
|
T5 |
10 |
|
T9 |
1 |
|
T22 |
4 |
| true |
1398 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T4 |
1 |
|
T5 |
16 |
|
T131 |
1 |
| others[1] |
233 |
1 |
|
T5 |
9 |
|
T34 |
1 |
|
T382 |
1 |
| others[2] |
240 |
1 |
|
T5 |
7 |
|
T25 |
1 |
|
T248 |
1 |
| others[3] |
367 |
1 |
|
T5 |
9 |
|
T105 |
1 |
|
T210 |
1 |
| false |
92 |
1 |
|
T5 |
2 |
|
T384 |
1 |
|
T407 |
1 |
| true |
5572 |
1 |
|
T5 |
58 |
|
T20 |
5 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T5 |
11 |
|
T105 |
1 |
|
T131 |
1 |
| others[1] |
210 |
1 |
|
T5 |
13 |
|
T52 |
1 |
|
T25 |
1 |
| others[2] |
216 |
1 |
|
T5 |
12 |
|
T210 |
1 |
|
T382 |
1 |
| others[3] |
361 |
1 |
|
T5 |
18 |
|
T248 |
1 |
|
T121 |
1 |
| false |
115 |
1 |
|
T5 |
3 |
|
T396 |
1 |
|
T404 |
1 |
| true |
5588 |
1 |
|
T4 |
1 |
|
T5 |
44 |
|
T20 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1220 |
1 |
|
T5 |
18 |
|
T20 |
1 |
|
T8 |
1 |
| others[1] |
1251 |
1 |
|
T5 |
18 |
|
T8 |
1 |
|
T22 |
19 |
| others[2] |
1224 |
1 |
|
T5 |
22 |
|
T20 |
2 |
|
T22 |
12 |
| others[3] |
1937 |
1 |
|
T5 |
29 |
|
T20 |
2 |
|
T9 |
1 |
| false |
653 |
1 |
|
T5 |
14 |
|
T22 |
6 |
|
T69 |
8 |
| true |
437 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1236 |
1 |
|
T5 |
23 |
|
T20 |
1 |
|
T22 |
16 |
| others[1] |
1181 |
1 |
|
T5 |
12 |
|
T8 |
1 |
|
T22 |
15 |
| others[2] |
1226 |
1 |
|
T5 |
20 |
|
T20 |
1 |
|
T8 |
1 |
| others[3] |
2007 |
1 |
|
T5 |
34 |
|
T20 |
3 |
|
T22 |
24 |
| false |
648 |
1 |
|
T5 |
12 |
|
T9 |
1 |
|
T22 |
9 |
| true |
424 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
87 |
1 |
|
T5 |
2 |
|
T228 |
1 |
|
T63 |
1 |
| others[1] |
85 |
1 |
|
T5 |
2 |
|
T383 |
2 |
|
T381 |
1 |
| others[2] |
112 |
1 |
|
T5 |
8 |
|
T382 |
1 |
|
T184 |
1 |
| others[3] |
165 |
1 |
|
T5 |
5 |
|
T52 |
1 |
|
T105 |
1 |
| false |
63 |
1 |
|
T5 |
4 |
|
T382 |
1 |
|
T385 |
1 |
| true |
6210 |
1 |
|
T4 |
1 |
|
T5 |
80 |
|
T20 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
211 |
1 |
|
T5 |
10 |
|
T248 |
1 |
|
T28 |
1 |
| others[1] |
242 |
1 |
|
T5 |
8 |
|
T105 |
1 |
|
T25 |
1 |
| others[2] |
244 |
1 |
|
T5 |
13 |
|
T24 |
1 |
|
T36 |
1 |
| others[3] |
391 |
1 |
|
T5 |
15 |
|
T52 |
1 |
|
T63 |
1 |
| false |
123 |
1 |
|
T5 |
3 |
|
T64 |
1 |
|
T349 |
1 |
| true |
5511 |
1 |
|
T4 |
1 |
|
T5 |
52 |
|
T20 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
999 |
1 |
|
T5 |
19 |
|
T20 |
2 |
|
T22 |
17 |
| others[1] |
1018 |
1 |
|
T5 |
13 |
|
T8 |
1 |
|
T22 |
15 |
| others[2] |
1022 |
1 |
|
T4 |
1 |
|
T5 |
23 |
|
T20 |
1 |
| others[3] |
1756 |
1 |
|
T5 |
39 |
|
T20 |
1 |
|
T9 |
1 |
| false |
551 |
1 |
|
T5 |
7 |
|
T20 |
1 |
|
T22 |
11 |
| true |
1376 |
1 |
|
T7 |
1 |
|
T24 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T5 |
10 |
|
T248 |
1 |
|
T181 |
1 |
| others[1] |
218 |
1 |
|
T5 |
8 |
|
T52 |
1 |
|
T105 |
1 |
| others[2] |
228 |
1 |
|
T5 |
13 |
|
T28 |
1 |
|
T382 |
1 |
| others[3] |
337 |
1 |
|
T4 |
1 |
|
T5 |
16 |
|
T64 |
1 |
| false |
120 |
1 |
|
T5 |
3 |
|
T98 |
1 |
|
T381 |
1 |
| true |
5590 |
1 |
|
T5 |
51 |
|
T20 |
5 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
206 |
1 |
|
T5 |
1 |
|
T223 |
1 |
|
T393 |
1 |
| others[1] |
208 |
1 |
|
T4 |
1 |
|
T5 |
9 |
|
T36 |
1 |
| others[2] |
233 |
1 |
|
T5 |
12 |
|
T248 |
1 |
|
T64 |
1 |
| others[3] |
355 |
1 |
|
T5 |
16 |
|
T105 |
1 |
|
T25 |
1 |
| false |
97 |
1 |
|
T5 |
7 |
|
T76 |
1 |
|
T401 |
1 |
| true |
5623 |
1 |
|
T5 |
56 |
|
T20 |
5 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1237 |
1 |
|
T5 |
18 |
|
T20 |
1 |
|
T8 |
1 |
| others[1] |
1205 |
1 |
|
T5 |
12 |
|
T20 |
2 |
|
T22 |
18 |
| others[2] |
1201 |
1 |
|
T5 |
16 |
|
T20 |
1 |
|
T22 |
14 |
| others[3] |
1999 |
1 |
|
T5 |
46 |
|
T20 |
1 |
|
T9 |
1 |
| false |
634 |
1 |
|
T5 |
9 |
|
T8 |
1 |
|
T22 |
5 |
| true |
446 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1236 |
1 |
|
T5 |
23 |
|
T20 |
1 |
|
T22 |
14 |
| others[1] |
1219 |
1 |
|
T5 |
22 |
|
T20 |
1 |
|
T8 |
2 |
| others[2] |
1232 |
1 |
|
T5 |
24 |
|
T20 |
2 |
|
T22 |
12 |
| others[3] |
2026 |
1 |
|
T5 |
28 |
|
T20 |
1 |
|
T22 |
31 |
| false |
587 |
1 |
|
T5 |
4 |
|
T22 |
6 |
|
T69 |
11 |
| true |
422 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
103 |
1 |
|
T5 |
5 |
|
T52 |
1 |
|
T391 |
1 |
| others[1] |
93 |
1 |
|
T5 |
4 |
|
T210 |
1 |
|
T382 |
1 |
| others[2] |
106 |
1 |
|
T5 |
1 |
|
T227 |
1 |
|
T383 |
3 |
| others[3] |
178 |
1 |
|
T5 |
2 |
|
T105 |
1 |
|
T36 |
1 |
| false |
58 |
1 |
|
T5 |
5 |
|
T91 |
3 |
|
T113 |
1 |
| true |
6184 |
1 |
|
T4 |
1 |
|
T5 |
84 |
|
T20 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
215 |
1 |
|
T5 |
9 |
|
T131 |
1 |
|
T63 |
1 |
| others[1] |
224 |
1 |
|
T5 |
11 |
|
T24 |
1 |
|
T52 |
1 |
| others[2] |
187 |
1 |
|
T5 |
9 |
|
T208 |
1 |
|
T223 |
1 |
| others[3] |
387 |
1 |
|
T4 |
1 |
|
T5 |
18 |
|
T36 |
1 |
| false |
125 |
1 |
|
T5 |
4 |
|
T105 |
1 |
|
T28 |
1 |
| true |
5584 |
1 |
|
T5 |
50 |
|
T20 |
5 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1036 |
1 |
|
T5 |
24 |
|
T8 |
1 |
|
T22 |
17 |
| others[1] |
1047 |
1 |
|
T5 |
24 |
|
T20 |
1 |
|
T7 |
1 |
| others[2] |
1046 |
1 |
|
T5 |
16 |
|
T20 |
2 |
|
T22 |
12 |
| others[3] |
1648 |
1 |
|
T5 |
31 |
|
T20 |
1 |
|
T22 |
28 |
| false |
548 |
1 |
|
T4 |
1 |
|
T5 |
6 |
|
T20 |
1 |
| true |
1397 |
1 |
|
T24 |
1 |
|
T15 |
1 |
|
T36 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
212 |
1 |
|
T5 |
9 |
|
T75 |
1 |
|
T394 |
1 |
| others[1] |
223 |
1 |
|
T5 |
5 |
|
T24 |
1 |
|
T131 |
1 |
| others[2] |
220 |
1 |
|
T5 |
7 |
|
T105 |
1 |
|
T382 |
1 |
| others[3] |
410 |
1 |
|
T5 |
16 |
|
T7 |
1 |
|
T36 |
1 |
| false |
97 |
1 |
|
T5 |
3 |
|
T29 |
1 |
|
T181 |
1 |
| true |
5560 |
1 |
|
T4 |
1 |
|
T5 |
61 |
|
T20 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
209 |
1 |
|
T5 |
10 |
|
T210 |
1 |
|
T29 |
1 |
| others[1] |
193 |
1 |
|
T5 |
12 |
|
T111 |
1 |
|
T408 |
1 |
| others[2] |
210 |
1 |
|
T5 |
5 |
|
T219 |
1 |
|
T396 |
1 |
| others[3] |
353 |
1 |
|
T5 |
13 |
|
T105 |
1 |
|
T181 |
1 |
| false |
117 |
1 |
|
T5 |
3 |
|
T36 |
1 |
|
T37 |
1 |
| true |
5640 |
1 |
|
T4 |
1 |
|
T5 |
58 |
|
T20 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1250 |
1 |
|
T5 |
16 |
|
T8 |
1 |
|
T22 |
17 |
| others[1] |
1222 |
1 |
|
T5 |
20 |
|
T20 |
2 |
|
T8 |
1 |
| others[2] |
1220 |
1 |
|
T5 |
18 |
|
T22 |
17 |
|
T69 |
13 |
| others[3] |
1968 |
1 |
|
T5 |
39 |
|
T20 |
3 |
|
T22 |
21 |
| false |
637 |
1 |
|
T5 |
8 |
|
T22 |
10 |
|
T69 |
6 |
| true |
425 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1216 |
1 |
|
T5 |
20 |
|
T20 |
1 |
|
T22 |
15 |
| others[1] |
1222 |
1 |
|
T5 |
20 |
|
T20 |
1 |
|
T8 |
2 |
| others[2] |
1220 |
1 |
|
T5 |
22 |
|
T20 |
1 |
|
T22 |
14 |
| others[3] |
1970 |
1 |
|
T5 |
28 |
|
T20 |
2 |
|
T22 |
22 |
| false |
679 |
1 |
|
T5 |
11 |
|
T22 |
7 |
|
T69 |
6 |
| true |
415 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
99 |
1 |
|
T382 |
1 |
|
T383 |
1 |
|
T381 |
1 |
| others[1] |
101 |
1 |
|
T5 |
7 |
|
T105 |
1 |
|
T75 |
1 |
| others[2] |
101 |
1 |
|
T5 |
4 |
|
T210 |
1 |
|
T395 |
1 |
| others[3] |
184 |
1 |
|
T5 |
5 |
|
T398 |
1 |
|
T382 |
1 |
| false |
62 |
1 |
|
T5 |
1 |
|
T52 |
1 |
|
T383 |
1 |
| true |
6175 |
1 |
|
T4 |
1 |
|
T5 |
84 |
|
T20 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
219 |
1 |
|
T4 |
1 |
|
T5 |
10 |
|
T29 |
1 |
| others[1] |
232 |
1 |
|
T5 |
9 |
|
T24 |
1 |
|
T27 |
1 |
| others[2] |
220 |
1 |
|
T5 |
7 |
|
T210 |
1 |
|
T34 |
1 |
| others[3] |
331 |
1 |
|
T5 |
12 |
|
T52 |
1 |
|
T181 |
1 |
| false |
135 |
1 |
|
T5 |
2 |
|
T349 |
1 |
|
T388 |
1 |
| true |
5585 |
1 |
|
T5 |
61 |
|
T20 |
5 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1026 |
1 |
|
T5 |
17 |
|
T20 |
2 |
|
T22 |
14 |
| others[1] |
1037 |
1 |
|
T5 |
26 |
|
T20 |
2 |
|
T8 |
1 |
| others[2] |
1062 |
1 |
|
T5 |
18 |
|
T8 |
1 |
|
T22 |
12 |
| others[3] |
1675 |
1 |
|
T5 |
29 |
|
T24 |
1 |
|
T22 |
25 |
| false |
527 |
1 |
|
T4 |
1 |
|
T5 |
11 |
|
T20 |
1 |
| true |
1395 |
1 |
|
T7 |
1 |
|
T15 |
1 |
|
T106 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
210 |
1 |
|
T5 |
8 |
|
T7 |
1 |
|
T210 |
1 |
| others[1] |
221 |
1 |
|
T5 |
9 |
|
T105 |
1 |
|
T25 |
1 |
| others[2] |
228 |
1 |
|
T5 |
12 |
|
T24 |
1 |
|
T394 |
1 |
| others[3] |
353 |
1 |
|
T5 |
18 |
|
T36 |
1 |
|
T111 |
1 |
| false |
106 |
1 |
|
T5 |
2 |
|
T181 |
1 |
|
T34 |
1 |
| true |
5604 |
1 |
|
T4 |
1 |
|
T5 |
52 |
|
T20 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
215 |
1 |
|
T5 |
15 |
|
T29 |
1 |
|
T403 |
1 |
| others[1] |
199 |
1 |
|
T5 |
4 |
|
T63 |
1 |
|
T182 |
1 |
| others[2] |
218 |
1 |
|
T5 |
9 |
|
T52 |
1 |
|
T25 |
1 |
| others[3] |
330 |
1 |
|
T5 |
13 |
|
T382 |
1 |
|
T395 |
1 |
| false |
108 |
1 |
|
T5 |
2 |
|
T91 |
6 |
|
T386 |
1 |
| true |
5652 |
1 |
|
T4 |
1 |
|
T5 |
58 |
|
T20 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1177 |
1 |
|
T5 |
21 |
|
T22 |
17 |
|
T69 |
13 |
| others[1] |
1213 |
1 |
|
T5 |
16 |
|
T20 |
4 |
|
T8 |
1 |
| others[2] |
1268 |
1 |
|
T5 |
13 |
|
T22 |
15 |
|
T52 |
1 |
| others[3] |
1980 |
1 |
|
T5 |
39 |
|
T20 |
1 |
|
T8 |
1 |
| false |
652 |
1 |
|
T5 |
12 |
|
T22 |
6 |
|
T69 |
9 |
| true |
432 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1279 |
1 |
|
T5 |
16 |
|
T20 |
2 |
|
T22 |
21 |
| others[1] |
1190 |
1 |
|
T5 |
26 |
|
T20 |
1 |
|
T9 |
1 |
| others[2] |
1191 |
1 |
|
T5 |
17 |
|
T22 |
14 |
|
T69 |
14 |
| others[3] |
2013 |
1 |
|
T5 |
30 |
|
T20 |
2 |
|
T8 |
2 |
| false |
631 |
1 |
|
T5 |
12 |
|
T22 |
9 |
|
T105 |
1 |
| true |
418 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
124 |
1 |
|
T5 |
6 |
|
T105 |
1 |
|
T385 |
1 |
| others[1] |
94 |
1 |
|
T5 |
5 |
|
T210 |
1 |
|
T388 |
1 |
| others[2] |
99 |
1 |
|
T52 |
1 |
|
T391 |
1 |
|
T393 |
1 |
| others[3] |
173 |
1 |
|
T5 |
9 |
|
T382 |
2 |
|
T395 |
1 |
| false |
60 |
1 |
|
T5 |
3 |
|
T228 |
1 |
|
T383 |
3 |
| true |
6172 |
1 |
|
T4 |
1 |
|
T5 |
78 |
|
T20 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
244 |
1 |
|
T5 |
11 |
|
T36 |
1 |
|
T64 |
1 |
| others[1] |
230 |
1 |
|
T5 |
7 |
|
T228 |
1 |
|
T382 |
1 |
| others[2] |
203 |
1 |
|
T5 |
7 |
|
T7 |
1 |
|
T210 |
1 |
| others[3] |
383 |
1 |
|
T5 |
21 |
|
T52 |
1 |
|
T25 |
1 |
| false |
132 |
1 |
|
T5 |
10 |
|
T394 |
1 |
|
T409 |
1 |
| true |
5530 |
1 |
|
T4 |
1 |
|
T5 |
45 |
|
T20 |
5 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |