Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
997 |
1 |
|
T5 |
21 |
|
T20 |
2 |
|
T8 |
1 |
| others[1] |
1053 |
1 |
|
T5 |
19 |
|
T22 |
16 |
|
T69 |
18 |
| others[2] |
1015 |
1 |
|
T4 |
1 |
|
T5 |
19 |
|
T8 |
1 |
| others[3] |
1712 |
1 |
|
T5 |
32 |
|
T20 |
3 |
|
T22 |
26 |
| false |
554 |
1 |
|
T5 |
10 |
|
T22 |
6 |
|
T105 |
1 |
| true |
1391 |
1 |
|
T7 |
1 |
|
T24 |
1 |
|
T106 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
246 |
1 |
|
T5 |
8 |
|
T37 |
1 |
|
T397 |
1 |
| others[1] |
235 |
1 |
|
T5 |
17 |
|
T24 |
1 |
|
T52 |
1 |
| others[2] |
238 |
1 |
|
T5 |
11 |
|
T105 |
1 |
|
T29 |
1 |
| others[3] |
358 |
1 |
|
T5 |
14 |
|
T36 |
1 |
|
T210 |
1 |
| false |
120 |
1 |
|
T4 |
1 |
|
T5 |
6 |
|
T401 |
1 |
| true |
5525 |
1 |
|
T5 |
45 |
|
T20 |
5 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
206 |
1 |
|
T5 |
10 |
|
T181 |
1 |
|
T385 |
1 |
| others[1] |
217 |
1 |
|
T5 |
15 |
|
T76 |
1 |
|
T383 |
2 |
| others[2] |
234 |
1 |
|
T5 |
7 |
|
T248 |
1 |
|
T397 |
1 |
| others[3] |
382 |
1 |
|
T5 |
13 |
|
T382 |
1 |
|
T111 |
1 |
| false |
118 |
1 |
|
T5 |
6 |
|
T25 |
1 |
|
T399 |
1 |
| true |
5565 |
1 |
|
T4 |
1 |
|
T5 |
50 |
|
T20 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1227 |
1 |
|
T5 |
20 |
|
T20 |
2 |
|
T22 |
13 |
| others[1] |
1147 |
1 |
|
T5 |
16 |
|
T8 |
1 |
|
T22 |
11 |
| others[2] |
1218 |
1 |
|
T5 |
21 |
|
T20 |
1 |
|
T8 |
1 |
| others[3] |
2045 |
1 |
|
T5 |
31 |
|
T20 |
1 |
|
T22 |
23 |
| false |
656 |
1 |
|
T5 |
13 |
|
T20 |
1 |
|
T9 |
1 |
| true |
429 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1308 |
1 |
|
T5 |
18 |
|
T20 |
2 |
|
T8 |
1 |
| others[1] |
1214 |
1 |
|
T5 |
18 |
|
T9 |
1 |
|
T22 |
10 |
| others[2] |
1156 |
1 |
|
T5 |
29 |
|
T20 |
2 |
|
T22 |
9 |
| others[3] |
1999 |
1 |
|
T5 |
25 |
|
T20 |
1 |
|
T8 |
1 |
| false |
626 |
1 |
|
T5 |
11 |
|
T22 |
8 |
|
T69 |
6 |
| true |
419 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
89 |
1 |
|
T5 |
5 |
|
T36 |
1 |
|
T210 |
1 |
| others[1] |
109 |
1 |
|
T5 |
2 |
|
T105 |
1 |
|
T382 |
2 |
| others[2] |
102 |
1 |
|
T5 |
3 |
|
T52 |
1 |
|
T391 |
1 |
| others[3] |
165 |
1 |
|
T5 |
5 |
|
T383 |
3 |
|
T381 |
1 |
| false |
44 |
1 |
|
T383 |
1 |
|
T388 |
1 |
|
T91 |
1 |
| true |
6213 |
1 |
|
T4 |
1 |
|
T5 |
86 |
|
T20 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
237 |
1 |
|
T4 |
1 |
|
T5 |
10 |
|
T29 |
1 |
| others[1] |
201 |
1 |
|
T5 |
4 |
|
T35 |
1 |
|
T184 |
1 |
| others[2] |
210 |
1 |
|
T5 |
8 |
|
T105 |
1 |
|
T228 |
1 |
| others[3] |
408 |
1 |
|
T5 |
19 |
|
T7 |
1 |
|
T36 |
1 |
| false |
120 |
1 |
|
T5 |
5 |
|
T24 |
1 |
|
T337 |
1 |
| true |
5546 |
1 |
|
T5 |
55 |
|
T20 |
5 |
|
T8 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1022 |
1 |
|
T5 |
22 |
|
T20 |
1 |
|
T8 |
1 |
| others[1] |
1037 |
1 |
|
T5 |
21 |
|
T22 |
17 |
|
T69 |
15 |
| others[2] |
1049 |
1 |
|
T5 |
16 |
|
T20 |
2 |
|
T7 |
1 |
| others[3] |
1681 |
1 |
|
T5 |
35 |
|
T20 |
2 |
|
T22 |
24 |
| false |
530 |
1 |
|
T5 |
7 |
|
T22 |
8 |
|
T69 |
8 |
| true |
1403 |
1 |
|
T4 |
1 |
|
T15 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
208 |
1 |
|
T4 |
1 |
|
T5 |
10 |
|
T35 |
1 |
| others[1] |
208 |
1 |
|
T5 |
11 |
|
T105 |
1 |
|
T25 |
1 |
| others[2] |
239 |
1 |
|
T5 |
7 |
|
T24 |
1 |
|
T52 |
1 |
| others[3] |
366 |
1 |
|
T5 |
23 |
|
T36 |
1 |
|
T28 |
1 |
| false |
124 |
1 |
|
T5 |
9 |
|
T131 |
1 |
|
T98 |
1 |
| true |
5577 |
1 |
|
T5 |
41 |
|
T20 |
5 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T5 |
11 |
|
T121 |
1 |
|
T223 |
1 |
| others[1] |
199 |
1 |
|
T4 |
1 |
|
T5 |
11 |
|
T248 |
1 |
| others[2] |
216 |
1 |
|
T5 |
16 |
|
T52 |
1 |
|
T25 |
1 |
| others[3] |
349 |
1 |
|
T5 |
12 |
|
T29 |
1 |
|
T37 |
1 |
| false |
114 |
1 |
|
T5 |
3 |
|
T382 |
1 |
|
T397 |
1 |
| true |
5615 |
1 |
|
T5 |
48 |
|
T20 |
5 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1184 |
1 |
|
T5 |
12 |
|
T20 |
1 |
|
T8 |
1 |
| others[1] |
1219 |
1 |
|
T5 |
22 |
|
T20 |
3 |
|
T22 |
10 |
| others[2] |
1172 |
1 |
|
T5 |
19 |
|
T8 |
1 |
|
T9 |
1 |
| others[3] |
2065 |
1 |
|
T5 |
40 |
|
T20 |
1 |
|
T22 |
31 |
| false |
635 |
1 |
|
T5 |
8 |
|
T22 |
7 |
|
T52 |
1 |
| true |
447 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1213 |
1 |
|
T5 |
20 |
|
T20 |
1 |
|
T8 |
1 |
| others[1] |
1237 |
1 |
|
T5 |
18 |
|
T20 |
1 |
|
T22 |
17 |
| others[2] |
1218 |
1 |
|
T5 |
15 |
|
T22 |
16 |
|
T69 |
13 |
| others[3] |
2018 |
1 |
|
T5 |
35 |
|
T20 |
3 |
|
T8 |
1 |
| false |
616 |
1 |
|
T5 |
13 |
|
T9 |
1 |
|
T22 |
8 |
| true |
420 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
96 |
1 |
|
T5 |
2 |
|
T52 |
1 |
|
T381 |
1 |
| others[1] |
108 |
1 |
|
T5 |
4 |
|
T121 |
1 |
|
T406 |
1 |
| others[2] |
104 |
1 |
|
T5 |
3 |
|
T382 |
1 |
|
T385 |
1 |
| others[3] |
185 |
1 |
|
T5 |
3 |
|
T210 |
1 |
|
T37 |
1 |
| false |
56 |
1 |
|
T5 |
5 |
|
T105 |
1 |
|
T228 |
1 |
| true |
6173 |
1 |
|
T4 |
1 |
|
T5 |
84 |
|
T20 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
214 |
1 |
|
T5 |
9 |
|
T228 |
1 |
|
T26 |
1 |
| others[1] |
233 |
1 |
|
T5 |
10 |
|
T210 |
1 |
|
T29 |
1 |
| others[2] |
218 |
1 |
|
T5 |
14 |
|
T25 |
1 |
|
T75 |
1 |
| others[3] |
389 |
1 |
|
T4 |
1 |
|
T5 |
16 |
|
T24 |
1 |
| false |
112 |
1 |
|
T5 |
9 |
|
T98 |
1 |
|
T397 |
1 |
| true |
5556 |
1 |
|
T5 |
43 |
|
T20 |
5 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1020 |
1 |
|
T5 |
15 |
|
T20 |
1 |
|
T8 |
1 |
| others[1] |
1076 |
1 |
|
T5 |
16 |
|
T22 |
14 |
|
T52 |
1 |
| others[2] |
1013 |
1 |
|
T5 |
17 |
|
T20 |
1 |
|
T22 |
17 |
| others[3] |
1718 |
1 |
|
T4 |
1 |
|
T5 |
36 |
|
T20 |
2 |
| false |
526 |
1 |
|
T5 |
17 |
|
T20 |
1 |
|
T8 |
1 |
| true |
1369 |
1 |
|
T7 |
1 |
|
T24 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
213 |
1 |
|
T5 |
11 |
|
T35 |
1 |
|
T98 |
1 |
| others[1] |
215 |
1 |
|
T5 |
7 |
|
T76 |
1 |
|
T223 |
1 |
| others[2] |
218 |
1 |
|
T5 |
10 |
|
T248 |
1 |
|
T37 |
1 |
| others[3] |
358 |
1 |
|
T5 |
25 |
|
T52 |
1 |
|
T105 |
1 |
| false |
139 |
1 |
|
T5 |
5 |
|
T131 |
1 |
|
T228 |
1 |
| true |
5579 |
1 |
|
T4 |
1 |
|
T5 |
43 |
|
T20 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
204 |
1 |
|
T5 |
13 |
|
T383 |
2 |
|
T91 |
5 |
| others[1] |
211 |
1 |
|
T4 |
1 |
|
T5 |
11 |
|
T228 |
1 |
| others[2] |
210 |
1 |
|
T5 |
8 |
|
T181 |
1 |
|
T64 |
1 |
| others[3] |
355 |
1 |
|
T5 |
15 |
|
T105 |
1 |
|
T131 |
1 |
| false |
110 |
1 |
|
T5 |
5 |
|
T25 |
1 |
|
T383 |
1 |
| true |
5632 |
1 |
|
T5 |
49 |
|
T20 |
5 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1230 |
1 |
|
T5 |
18 |
|
T20 |
1 |
|
T22 |
11 |
| others[1] |
1232 |
1 |
|
T5 |
20 |
|
T20 |
2 |
|
T22 |
12 |
| others[2] |
1210 |
1 |
|
T5 |
23 |
|
T8 |
1 |
|
T22 |
20 |
| others[3] |
2016 |
1 |
|
T5 |
32 |
|
T8 |
1 |
|
T9 |
1 |
| false |
599 |
1 |
|
T5 |
8 |
|
T20 |
2 |
|
T22 |
8 |
| true |
435 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1211 |
1 |
|
T5 |
11 |
|
T20 |
1 |
|
T22 |
22 |
| others[1] |
1226 |
1 |
|
T5 |
20 |
|
T9 |
1 |
|
T22 |
12 |
| others[2] |
1228 |
1 |
|
T5 |
24 |
|
T8 |
1 |
|
T22 |
20 |
| others[3] |
2016 |
1 |
|
T5 |
38 |
|
T20 |
4 |
|
T8 |
1 |
| false |
617 |
1 |
|
T5 |
8 |
|
T22 |
5 |
|
T69 |
11 |
| true |
424 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
93 |
1 |
|
T5 |
2 |
|
T382 |
1 |
|
T76 |
1 |
| others[1] |
88 |
1 |
|
T5 |
3 |
|
T382 |
1 |
|
T393 |
1 |
| others[2] |
100 |
1 |
|
T5 |
3 |
|
T105 |
1 |
|
T248 |
1 |
| others[3] |
179 |
1 |
|
T5 |
10 |
|
T52 |
1 |
|
T37 |
1 |
| false |
59 |
1 |
|
T5 |
2 |
|
T210 |
1 |
|
T63 |
1 |
| true |
6203 |
1 |
|
T4 |
1 |
|
T5 |
81 |
|
T20 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T5 |
12 |
|
T26 |
1 |
|
T208 |
1 |
| others[1] |
193 |
1 |
|
T5 |
8 |
|
T34 |
1 |
|
T405 |
1 |
| others[2] |
220 |
1 |
|
T5 |
7 |
|
T121 |
1 |
|
T382 |
1 |
| others[3] |
398 |
1 |
|
T5 |
17 |
|
T24 |
1 |
|
T105 |
1 |
| false |
117 |
1 |
|
T5 |
5 |
|
T63 |
1 |
|
T91 |
6 |
| true |
5567 |
1 |
|
T4 |
1 |
|
T5 |
52 |
|
T20 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1066 |
1 |
|
T5 |
29 |
|
T8 |
1 |
|
T22 |
14 |
| others[1] |
1005 |
1 |
|
T5 |
11 |
|
T20 |
1 |
|
T22 |
13 |
| others[2] |
1022 |
1 |
|
T5 |
20 |
|
T20 |
1 |
|
T7 |
1 |
| others[3] |
1681 |
1 |
|
T5 |
32 |
|
T20 |
3 |
|
T8 |
1 |
| false |
552 |
1 |
|
T5 |
9 |
|
T22 |
4 |
|
T105 |
1 |
| true |
1396 |
1 |
|
T4 |
1 |
|
T24 |
1 |
|
T106 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T5 |
8 |
|
T131 |
1 |
|
T210 |
1 |
| others[1] |
228 |
1 |
|
T5 |
11 |
|
T24 |
1 |
|
T382 |
1 |
| others[2] |
214 |
1 |
|
T5 |
12 |
|
T181 |
1 |
|
T34 |
1 |
| others[3] |
361 |
1 |
|
T5 |
11 |
|
T7 |
1 |
|
T28 |
1 |
| false |
108 |
1 |
|
T5 |
3 |
|
T52 |
1 |
|
T280 |
1 |
| true |
5586 |
1 |
|
T4 |
1 |
|
T5 |
56 |
|
T20 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T5 |
11 |
|
T37 |
1 |
|
T75 |
1 |
| others[1] |
234 |
1 |
|
T5 |
9 |
|
T181 |
1 |
|
T76 |
1 |
| others[2] |
201 |
1 |
|
T5 |
14 |
|
T52 |
1 |
|
T131 |
1 |
| others[3] |
319 |
1 |
|
T5 |
11 |
|
T248 |
1 |
|
T121 |
1 |
| false |
107 |
1 |
|
T5 |
2 |
|
T91 |
4 |
|
T386 |
1 |
| true |
5632 |
1 |
|
T4 |
1 |
|
T5 |
54 |
|
T20 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1190 |
1 |
|
T5 |
12 |
|
T20 |
2 |
|
T8 |
1 |
| others[1] |
1215 |
1 |
|
T5 |
21 |
|
T20 |
2 |
|
T8 |
1 |
| others[2] |
1201 |
1 |
|
T5 |
22 |
|
T20 |
1 |
|
T22 |
10 |
| others[3] |
2058 |
1 |
|
T5 |
35 |
|
T22 |
33 |
|
T16 |
1 |
| false |
623 |
1 |
|
T5 |
11 |
|
T22 |
3 |
|
T69 |
9 |
| true |
435 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1235 |
1 |
|
T5 |
26 |
|
T22 |
22 |
|
T69 |
20 |
| others[1] |
1253 |
1 |
|
T5 |
9 |
|
T8 |
1 |
|
T22 |
13 |
| others[2] |
1213 |
1 |
|
T5 |
19 |
|
T20 |
1 |
|
T8 |
1 |
| others[3] |
1998 |
1 |
|
T5 |
36 |
|
T20 |
3 |
|
T9 |
1 |
| false |
610 |
1 |
|
T5 |
11 |
|
T20 |
1 |
|
T22 |
7 |
| true |
413 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
107 |
1 |
|
T5 |
3 |
|
T210 |
1 |
|
T248 |
1 |
| others[1] |
99 |
1 |
|
T5 |
3 |
|
T398 |
1 |
|
T383 |
1 |
| others[2] |
112 |
1 |
|
T5 |
3 |
|
T131 |
1 |
|
T228 |
1 |
| others[3] |
150 |
1 |
|
T5 |
2 |
|
T52 |
1 |
|
T105 |
1 |
| false |
58 |
1 |
|
T388 |
1 |
|
T91 |
6 |
|
T410 |
1 |
| true |
6196 |
1 |
|
T4 |
1 |
|
T5 |
90 |
|
T20 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
222 |
1 |
|
T5 |
8 |
|
T36 |
1 |
|
T26 |
1 |
| others[1] |
216 |
1 |
|
T5 |
6 |
|
T394 |
1 |
|
T281 |
1 |
| others[2] |
206 |
1 |
|
T5 |
9 |
|
T63 |
1 |
|
T27 |
1 |
| others[3] |
361 |
1 |
|
T5 |
21 |
|
T131 |
1 |
|
T228 |
1 |
| false |
117 |
1 |
|
T5 |
4 |
|
T64 |
1 |
|
T34 |
1 |
| true |
5600 |
1 |
|
T4 |
1 |
|
T5 |
53 |
|
T20 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
979 |
1 |
|
T5 |
15 |
|
T8 |
1 |
|
T22 |
15 |
| others[1] |
1010 |
1 |
|
T5 |
13 |
|
T22 |
13 |
|
T15 |
1 |
| others[2] |
1024 |
1 |
|
T5 |
28 |
|
T20 |
2 |
|
T8 |
1 |
| others[3] |
1770 |
1 |
|
T4 |
1 |
|
T5 |
32 |
|
T20 |
3 |
| false |
542 |
1 |
|
T5 |
13 |
|
T9 |
1 |
|
T22 |
8 |
| true |
1397 |
1 |
|
T7 |
1 |
|
T10 |
1 |
|
T136 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
213 |
1 |
|
T5 |
10 |
|
T52 |
1 |
|
T64 |
1 |
| others[1] |
231 |
1 |
|
T5 |
7 |
|
T210 |
1 |
|
T248 |
1 |
| others[2] |
236 |
1 |
|
T4 |
1 |
|
T5 |
13 |
|
T182 |
1 |
| others[3] |
364 |
1 |
|
T5 |
12 |
|
T131 |
1 |
|
T29 |
1 |
| false |
110 |
1 |
|
T5 |
5 |
|
T7 |
1 |
|
T36 |
1 |
| true |
5568 |
1 |
|
T5 |
54 |
|
T20 |
5 |
|
T8 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
217 |
1 |
|
T5 |
8 |
|
T248 |
1 |
|
T382 |
1 |
| others[1] |
220 |
1 |
|
T5 |
11 |
|
T52 |
1 |
|
T25 |
1 |
| others[2] |
217 |
1 |
|
T5 |
12 |
|
T91 |
12 |
|
T411 |
1 |
| others[3] |
345 |
1 |
|
T5 |
23 |
|
T393 |
1 |
|
T227 |
1 |
| false |
115 |
1 |
|
T4 |
1 |
|
T181 |
1 |
|
T401 |
1 |
| true |
5608 |
1 |
|
T5 |
47 |
|
T20 |
5 |
|
T7 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |