Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1244 |
1 |
|
T5 |
25 |
|
T20 |
1 |
|
T8 |
1 |
| others[1] |
1224 |
1 |
|
T5 |
15 |
|
T20 |
1 |
|
T8 |
1 |
| others[2] |
1217 |
1 |
|
T5 |
17 |
|
T20 |
1 |
|
T9 |
1 |
| others[3] |
1992 |
1 |
|
T5 |
33 |
|
T20 |
2 |
|
T22 |
21 |
| false |
603 |
1 |
|
T5 |
11 |
|
T22 |
8 |
|
T51 |
1 |
| true |
442 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1194 |
1 |
|
T5 |
18 |
|
T20 |
1 |
|
T22 |
10 |
| others[1] |
1261 |
1 |
|
T5 |
22 |
|
T20 |
1 |
|
T8 |
1 |
| others[2] |
1161 |
1 |
|
T5 |
23 |
|
T20 |
1 |
|
T22 |
21 |
| others[3] |
2058 |
1 |
|
T5 |
23 |
|
T20 |
1 |
|
T9 |
1 |
| false |
630 |
1 |
|
T5 |
15 |
|
T20 |
1 |
|
T8 |
1 |
| true |
418 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
82 |
1 |
|
T5 |
5 |
|
T121 |
1 |
|
T382 |
1 |
| others[1] |
107 |
1 |
|
T5 |
6 |
|
T383 |
1 |
|
T381 |
1 |
| others[2] |
90 |
1 |
|
T5 |
3 |
|
T210 |
1 |
|
T381 |
1 |
| others[3] |
215 |
1 |
|
T5 |
12 |
|
T52 |
1 |
|
T105 |
1 |
| false |
47 |
1 |
|
T91 |
1 |
|
T389 |
2 |
|
T412 |
1 |
| true |
6181 |
1 |
|
T4 |
1 |
|
T5 |
75 |
|
T20 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T4 |
1 |
|
T5 |
12 |
|
T7 |
1 |
| others[1] |
223 |
1 |
|
T5 |
9 |
|
T29 |
1 |
|
T248 |
1 |
| others[2] |
212 |
1 |
|
T5 |
8 |
|
T98 |
1 |
|
T384 |
1 |
| others[3] |
385 |
1 |
|
T5 |
19 |
|
T24 |
1 |
|
T228 |
1 |
| false |
125 |
1 |
|
T5 |
1 |
|
T27 |
1 |
|
T405 |
1 |
| true |
5552 |
1 |
|
T5 |
52 |
|
T20 |
5 |
|
T8 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1029 |
1 |
|
T5 |
17 |
|
T20 |
1 |
|
T22 |
18 |
| others[1] |
1073 |
1 |
|
T5 |
19 |
|
T20 |
2 |
|
T8 |
1 |
| others[2] |
1044 |
1 |
|
T5 |
29 |
|
T9 |
1 |
|
T22 |
11 |
| others[3] |
1638 |
1 |
|
T5 |
26 |
|
T20 |
2 |
|
T22 |
23 |
| false |
546 |
1 |
|
T5 |
10 |
|
T8 |
1 |
|
T22 |
8 |
| true |
1392 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T5 |
12 |
|
T36 |
1 |
|
T35 |
1 |
| others[1] |
220 |
1 |
|
T5 |
10 |
|
T25 |
1 |
|
T34 |
1 |
| others[2] |
221 |
1 |
|
T5 |
11 |
|
T210 |
1 |
|
T28 |
1 |
| others[3] |
357 |
1 |
|
T5 |
16 |
|
T131 |
1 |
|
T37 |
1 |
| false |
122 |
1 |
|
T5 |
10 |
|
T24 |
1 |
|
T384 |
1 |
| true |
5586 |
1 |
|
T4 |
1 |
|
T5 |
42 |
|
T20 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
206 |
1 |
|
T5 |
10 |
|
T111 |
1 |
|
T91 |
11 |
| others[1] |
192 |
1 |
|
T5 |
4 |
|
T105 |
1 |
|
T29 |
1 |
| others[2] |
235 |
1 |
|
T5 |
15 |
|
T393 |
1 |
|
T406 |
1 |
| others[3] |
380 |
1 |
|
T4 |
1 |
|
T5 |
21 |
|
T52 |
1 |
| false |
109 |
1 |
|
T5 |
2 |
|
T36 |
1 |
|
T383 |
2 |
| true |
5600 |
1 |
|
T5 |
49 |
|
T20 |
5 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1229 |
1 |
|
T5 |
19 |
|
T20 |
1 |
|
T8 |
1 |
| others[1] |
1211 |
1 |
|
T5 |
14 |
|
T22 |
10 |
|
T105 |
1 |
| others[2] |
1214 |
1 |
|
T5 |
18 |
|
T20 |
1 |
|
T8 |
1 |
| others[3] |
2013 |
1 |
|
T5 |
44 |
|
T20 |
2 |
|
T22 |
22 |
| false |
626 |
1 |
|
T5 |
6 |
|
T20 |
1 |
|
T22 |
11 |
| true |
429 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1211 |
1 |
|
T5 |
19 |
|
T20 |
1 |
|
T8 |
1 |
| others[1] |
1232 |
1 |
|
T5 |
22 |
|
T20 |
1 |
|
T22 |
14 |
| others[2] |
1176 |
1 |
|
T5 |
17 |
|
T8 |
1 |
|
T22 |
13 |
| others[3] |
2035 |
1 |
|
T5 |
34 |
|
T20 |
3 |
|
T22 |
25 |
| false |
653 |
1 |
|
T5 |
9 |
|
T9 |
1 |
|
T22 |
11 |
| true |
415 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
91 |
1 |
|
T5 |
2 |
|
T105 |
1 |
|
T64 |
1 |
| others[1] |
104 |
1 |
|
T5 |
1 |
|
T52 |
1 |
|
T37 |
1 |
| others[2] |
106 |
1 |
|
T5 |
4 |
|
T210 |
1 |
|
T29 |
1 |
| others[3] |
189 |
1 |
|
T5 |
5 |
|
T382 |
1 |
|
T385 |
1 |
| false |
46 |
1 |
|
T5 |
1 |
|
T382 |
1 |
|
T184 |
1 |
| true |
6186 |
1 |
|
T4 |
1 |
|
T5 |
88 |
|
T20 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T5 |
9 |
|
T327 |
1 |
|
T391 |
1 |
| others[1] |
227 |
1 |
|
T5 |
5 |
|
T24 |
1 |
|
T29 |
1 |
| others[2] |
215 |
1 |
|
T5 |
14 |
|
T36 |
1 |
|
T131 |
1 |
| others[3] |
406 |
1 |
|
T5 |
18 |
|
T105 |
1 |
|
T228 |
1 |
| false |
123 |
1 |
|
T5 |
4 |
|
T25 |
1 |
|
T382 |
1 |
| true |
5510 |
1 |
|
T4 |
1 |
|
T5 |
51 |
|
T20 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1037 |
1 |
|
T4 |
1 |
|
T5 |
19 |
|
T20 |
1 |
| others[1] |
1030 |
1 |
|
T5 |
20 |
|
T20 |
2 |
|
T22 |
11 |
| others[2] |
989 |
1 |
|
T5 |
20 |
|
T22 |
18 |
|
T51 |
1 |
| others[3] |
1700 |
1 |
|
T5 |
33 |
|
T20 |
1 |
|
T8 |
1 |
| false |
535 |
1 |
|
T5 |
9 |
|
T20 |
1 |
|
T8 |
1 |
| true |
1431 |
1 |
|
T7 |
1 |
|
T24 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T5 |
15 |
|
T248 |
1 |
|
T382 |
1 |
| others[1] |
217 |
1 |
|
T5 |
8 |
|
T52 |
1 |
|
T36 |
1 |
| others[2] |
224 |
1 |
|
T5 |
8 |
|
T121 |
1 |
|
T394 |
1 |
| others[3] |
358 |
1 |
|
T4 |
1 |
|
T5 |
7 |
|
T29 |
1 |
| false |
121 |
1 |
|
T5 |
9 |
|
T24 |
1 |
|
T397 |
1 |
| true |
5578 |
1 |
|
T5 |
54 |
|
T20 |
5 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
203 |
1 |
|
T5 |
8 |
|
T228 |
1 |
|
T398 |
1 |
| others[1] |
203 |
1 |
|
T5 |
11 |
|
T52 |
1 |
|
T383 |
1 |
| others[2] |
216 |
1 |
|
T5 |
12 |
|
T64 |
1 |
|
T75 |
1 |
| others[3] |
355 |
1 |
|
T5 |
18 |
|
T121 |
1 |
|
T397 |
1 |
| false |
122 |
1 |
|
T5 |
5 |
|
T405 |
1 |
|
T395 |
1 |
| true |
5623 |
1 |
|
T4 |
1 |
|
T5 |
47 |
|
T20 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1180 |
1 |
|
T5 |
19 |
|
T8 |
2 |
|
T22 |
13 |
| others[1] |
1202 |
1 |
|
T5 |
18 |
|
T20 |
3 |
|
T22 |
12 |
| others[2] |
1246 |
1 |
|
T5 |
19 |
|
T9 |
1 |
|
T22 |
15 |
| others[3] |
1994 |
1 |
|
T5 |
34 |
|
T20 |
1 |
|
T22 |
24 |
| false |
657 |
1 |
|
T5 |
11 |
|
T20 |
1 |
|
T22 |
11 |
| true |
443 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1233 |
1 |
|
T5 |
19 |
|
T20 |
2 |
|
T22 |
21 |
| others[1] |
1234 |
1 |
|
T5 |
21 |
|
T20 |
1 |
|
T22 |
13 |
| others[2] |
1169 |
1 |
|
T5 |
24 |
|
T20 |
1 |
|
T22 |
12 |
| others[3] |
2054 |
1 |
|
T5 |
26 |
|
T20 |
1 |
|
T8 |
2 |
| false |
607 |
1 |
|
T5 |
11 |
|
T22 |
4 |
|
T69 |
5 |
| true |
425 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
89 |
1 |
|
T5 |
5 |
|
T105 |
1 |
|
T210 |
1 |
| others[1] |
98 |
1 |
|
T5 |
3 |
|
T52 |
1 |
|
T63 |
1 |
| others[2] |
102 |
1 |
|
T5 |
3 |
|
T382 |
1 |
|
T391 |
1 |
| others[3] |
173 |
1 |
|
T5 |
7 |
|
T64 |
1 |
|
T385 |
1 |
| false |
52 |
1 |
|
T5 |
1 |
|
T382 |
1 |
|
T383 |
1 |
| true |
6208 |
1 |
|
T4 |
1 |
|
T5 |
82 |
|
T20 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T5 |
6 |
|
T228 |
1 |
|
T26 |
1 |
| others[1] |
262 |
1 |
|
T5 |
15 |
|
T398 |
1 |
|
T75 |
1 |
| others[2] |
239 |
1 |
|
T5 |
7 |
|
T24 |
1 |
|
T105 |
1 |
| others[3] |
376 |
1 |
|
T4 |
1 |
|
T5 |
9 |
|
T248 |
1 |
| false |
90 |
1 |
|
T5 |
4 |
|
T34 |
1 |
|
T184 |
1 |
| true |
5539 |
1 |
|
T5 |
60 |
|
T20 |
5 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
972 |
1 |
|
T5 |
25 |
|
T22 |
10 |
|
T52 |
1 |
| others[1] |
1068 |
1 |
|
T5 |
9 |
|
T20 |
2 |
|
T22 |
13 |
| others[2] |
1085 |
1 |
|
T5 |
20 |
|
T20 |
1 |
|
T8 |
2 |
| others[3] |
1654 |
1 |
|
T4 |
1 |
|
T5 |
42 |
|
T20 |
2 |
| false |
546 |
1 |
|
T5 |
5 |
|
T7 |
1 |
|
T22 |
6 |
| true |
1397 |
1 |
|
T15 |
1 |
|
T106 |
1 |
|
T36 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
215 |
1 |
|
T5 |
5 |
|
T36 |
1 |
|
T35 |
1 |
| others[1] |
231 |
1 |
|
T5 |
11 |
|
T228 |
1 |
|
T28 |
1 |
| others[2] |
219 |
1 |
|
T5 |
9 |
|
T38 |
1 |
|
T223 |
1 |
| others[3] |
362 |
1 |
|
T5 |
21 |
|
T52 |
1 |
|
T29 |
1 |
| false |
132 |
1 |
|
T5 |
4 |
|
T7 |
1 |
|
T64 |
1 |
| true |
5563 |
1 |
|
T4 |
1 |
|
T5 |
51 |
|
T20 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T5 |
13 |
|
T228 |
1 |
|
T37 |
1 |
| others[1] |
208 |
1 |
|
T5 |
10 |
|
T36 |
1 |
|
T29 |
1 |
| others[2] |
236 |
1 |
|
T5 |
9 |
|
T382 |
1 |
|
T187 |
1 |
| others[3] |
347 |
1 |
|
T5 |
21 |
|
T105 |
1 |
|
T63 |
1 |
| false |
98 |
1 |
|
T5 |
3 |
|
T385 |
1 |
|
T76 |
1 |
| true |
5606 |
1 |
|
T4 |
1 |
|
T5 |
45 |
|
T20 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1158 |
1 |
|
T5 |
18 |
|
T20 |
1 |
|
T8 |
1 |
| others[1] |
1206 |
1 |
|
T5 |
20 |
|
T22 |
11 |
|
T52 |
1 |
| others[2] |
1216 |
1 |
|
T5 |
25 |
|
T20 |
3 |
|
T9 |
1 |
| others[3] |
2071 |
1 |
|
T5 |
26 |
|
T20 |
1 |
|
T8 |
1 |
| false |
625 |
1 |
|
T5 |
12 |
|
T22 |
11 |
|
T16 |
1 |
| true |
446 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1208 |
1 |
|
T5 |
20 |
|
T20 |
1 |
|
T22 |
15 |
| others[1] |
1279 |
1 |
|
T5 |
20 |
|
T20 |
2 |
|
T8 |
1 |
| others[2] |
1204 |
1 |
|
T5 |
18 |
|
T9 |
1 |
|
T22 |
11 |
| others[3] |
1995 |
1 |
|
T5 |
33 |
|
T8 |
1 |
|
T22 |
21 |
| false |
620 |
1 |
|
T5 |
10 |
|
T20 |
2 |
|
T22 |
12 |
| true |
416 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
101 |
1 |
|
T5 |
5 |
|
T105 |
1 |
|
T91 |
8 |
| others[1] |
113 |
1 |
|
T5 |
2 |
|
T385 |
1 |
|
T383 |
1 |
| others[2] |
99 |
1 |
|
T5 |
2 |
|
T382 |
1 |
|
T383 |
1 |
| others[3] |
181 |
1 |
|
T5 |
10 |
|
T52 |
1 |
|
T210 |
1 |
| false |
42 |
1 |
|
T5 |
3 |
|
T403 |
1 |
|
T383 |
2 |
| true |
6186 |
1 |
|
T4 |
1 |
|
T5 |
79 |
|
T20 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T5 |
8 |
|
T25 |
1 |
|
T228 |
1 |
| others[1] |
232 |
1 |
|
T5 |
8 |
|
T24 |
1 |
|
T64 |
1 |
| others[2] |
218 |
1 |
|
T5 |
8 |
|
T131 |
1 |
|
T26 |
1 |
| others[3] |
371 |
1 |
|
T5 |
13 |
|
T7 |
1 |
|
T210 |
1 |
| false |
134 |
1 |
|
T5 |
5 |
|
T34 |
1 |
|
T75 |
1 |
| true |
5540 |
1 |
|
T4 |
1 |
|
T5 |
59 |
|
T20 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
985 |
1 |
|
T5 |
24 |
|
T20 |
1 |
|
T22 |
9 |
| others[1] |
971 |
1 |
|
T5 |
21 |
|
T20 |
1 |
|
T22 |
14 |
| others[2] |
1053 |
1 |
|
T5 |
13 |
|
T20 |
1 |
|
T8 |
1 |
| others[3] |
1790 |
1 |
|
T5 |
27 |
|
T20 |
1 |
|
T8 |
1 |
| false |
547 |
1 |
|
T5 |
16 |
|
T20 |
1 |
|
T22 |
10 |
| true |
1376 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
213 |
1 |
|
T5 |
17 |
|
T7 |
1 |
|
T36 |
1 |
| others[1] |
246 |
1 |
|
T5 |
9 |
|
T25 |
1 |
|
T37 |
1 |
| others[2] |
216 |
1 |
|
T5 |
9 |
|
T228 |
1 |
|
T102 |
1 |
| others[3] |
375 |
1 |
|
T5 |
10 |
|
T24 |
1 |
|
T105 |
1 |
| false |
106 |
1 |
|
T5 |
7 |
|
T181 |
1 |
|
T211 |
1 |
| true |
5566 |
1 |
|
T4 |
1 |
|
T5 |
49 |
|
T20 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
196 |
1 |
|
T5 |
11 |
|
T25 |
1 |
|
T248 |
1 |
| others[1] |
220 |
1 |
|
T4 |
1 |
|
T5 |
10 |
|
T131 |
1 |
| others[2] |
221 |
1 |
|
T5 |
8 |
|
T105 |
1 |
|
T36 |
1 |
| others[3] |
346 |
1 |
|
T5 |
13 |
|
T29 |
1 |
|
T228 |
1 |
| false |
101 |
1 |
|
T5 |
3 |
|
T52 |
1 |
|
T182 |
1 |
| true |
5638 |
1 |
|
T5 |
56 |
|
T20 |
5 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1157 |
1 |
|
T5 |
19 |
|
T20 |
1 |
|
T9 |
1 |
| others[1] |
1243 |
1 |
|
T5 |
19 |
|
T20 |
1 |
|
T22 |
15 |
| others[2] |
1265 |
1 |
|
T5 |
19 |
|
T22 |
12 |
|
T52 |
1 |
| others[3] |
1957 |
1 |
|
T5 |
35 |
|
T20 |
3 |
|
T8 |
1 |
| false |
656 |
1 |
|
T5 |
9 |
|
T8 |
1 |
|
T22 |
9 |
| true |
444 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
15 |
1 |
|
T61 |
1 |
|
T160 |
1 |
|
T226 |
1 |
| others[1] |
14 |
1 |
|
T157 |
1 |
|
T104 |
1 |
|
T140 |
1 |
| others[2] |
6 |
1 |
|
T158 |
1 |
|
T153 |
1 |
|
T413 |
1 |
| others[3] |
8 |
1 |
|
T80 |
1 |
|
T90 |
1 |
|
T414 |
1 |
| false |
2 |
1 |
|
T415 |
1 |
|
T416 |
1 |
|
- |
- |
| true |
44 |
1 |
|
T14 |
1 |
|
T129 |
1 |
|
T148 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1 |
1 |
|
T375 |
1 |
|
- |
- |
|
- |
- |
| others[1] |
2 |
1 |
|
T376 |
1 |
|
T417 |
1 |
|
- |
- |
| others[2] |
3 |
1 |
|
T418 |
1 |
|
T419 |
1 |
|
T420 |
1 |
| others[3] |
8 |
1 |
|
T166 |
1 |
|
T374 |
1 |
|
T421 |
1 |
| false |
10 |
1 |
|
T379 |
1 |
|
T380 |
1 |
|
T422 |
1 |
| true |
24 |
1 |
|
T31 |
1 |
|
T32 |
1 |
|
T33 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |