Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10069 |
1 |
|
T1 |
119 |
|
T5 |
17 |
|
T6 |
40 |
| others[1] |
767 |
1 |
|
T5 |
17 |
|
T22 |
14 |
|
T52 |
1 |
| others[2] |
783 |
1 |
|
T5 |
14 |
|
T22 |
14 |
|
T16 |
1 |
| others[3] |
1238 |
1 |
|
T5 |
43 |
|
T20 |
1 |
|
T22 |
24 |
| false |
414 |
1 |
|
T5 |
10 |
|
T20 |
2 |
|
T22 |
9 |
| true |
522 |
1 |
|
T4 |
1 |
|
T20 |
2 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2374 |
1 |
|
T1 |
17 |
|
T5 |
13 |
|
T20 |
2 |
| others[1] |
2357 |
1 |
|
T1 |
32 |
|
T5 |
8 |
|
T20 |
1 |
| others[2] |
2374 |
1 |
|
T1 |
23 |
|
T5 |
13 |
|
T20 |
1 |
| others[3] |
3911 |
1 |
|
T1 |
37 |
|
T4 |
1 |
|
T5 |
20 |
| false |
1249 |
1 |
|
T1 |
10 |
|
T5 |
5 |
|
T6 |
6 |
| true |
1528 |
1 |
|
T5 |
42 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9569 |
1 |
|
T1 |
119 |
|
T5 |
14 |
|
T6 |
40 |
| others[1] |
259 |
1 |
|
T5 |
4 |
|
T9 |
1 |
|
T58 |
1 |
| others[2] |
282 |
1 |
|
T5 |
8 |
|
T20 |
1 |
|
T62 |
3 |
| others[3] |
425 |
1 |
|
T5 |
12 |
|
T8 |
1 |
|
T58 |
2 |
| false |
141 |
1 |
|
T5 |
1 |
|
T20 |
2 |
|
T51 |
1 |
| true |
3117 |
1 |
|
T4 |
1 |
|
T5 |
62 |
|
T20 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9816 |
1 |
|
T1 |
119 |
|
T5 |
14 |
|
T20 |
1 |
| others[1] |
471 |
1 |
|
T5 |
10 |
|
T20 |
2 |
|
T8 |
1 |
| others[2] |
440 |
1 |
|
T4 |
1 |
|
T5 |
5 |
|
T22 |
6 |
| others[3] |
732 |
1 |
|
T5 |
17 |
|
T20 |
2 |
|
T22 |
10 |
| false |
238 |
1 |
|
T5 |
5 |
|
T24 |
1 |
|
T22 |
6 |
| true |
2096 |
1 |
|
T5 |
50 |
|
T7 |
1 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9576 |
1 |
|
T1 |
119 |
|
T5 |
12 |
|
T20 |
2 |
| others[1] |
250 |
1 |
|
T5 |
5 |
|
T52 |
1 |
|
T58 |
1 |
| others[2] |
232 |
1 |
|
T5 |
7 |
|
T171 |
1 |
|
T172 |
1 |
| others[3] |
433 |
1 |
|
T5 |
20 |
|
T58 |
1 |
|
T30 |
1 |
| false |
121 |
1 |
|
T5 |
2 |
|
T58 |
2 |
|
T62 |
1 |
| true |
3181 |
1 |
|
T4 |
1 |
|
T5 |
55 |
|
T20 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9538 |
1 |
|
T1 |
119 |
|
T5 |
17 |
|
T20 |
1 |
| others[1] |
240 |
1 |
|
T5 |
12 |
|
T8 |
1 |
|
T58 |
1 |
| others[2] |
258 |
1 |
|
T5 |
5 |
|
T20 |
1 |
|
T171 |
1 |
| others[3] |
413 |
1 |
|
T5 |
14 |
|
T51 |
1 |
|
T52 |
1 |
| false |
114 |
1 |
|
T5 |
5 |
|
T20 |
1 |
|
T8 |
1 |
| true |
3230 |
1 |
|
T4 |
1 |
|
T5 |
48 |
|
T20 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10158 |
1 |
|
T1 |
119 |
|
T5 |
25 |
|
T6 |
40 |
| others[1] |
743 |
1 |
|
T5 |
20 |
|
T22 |
9 |
|
T16 |
1 |
| others[2] |
769 |
1 |
|
T5 |
17 |
|
T20 |
1 |
|
T22 |
11 |
| others[3] |
1231 |
1 |
|
T5 |
31 |
|
T20 |
3 |
|
T9 |
1 |
| false |
401 |
1 |
|
T5 |
8 |
|
T22 |
7 |
|
T69 |
7 |
| true |
491 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10060 |
1 |
|
T1 |
119 |
|
T5 |
15 |
|
T20 |
1 |
| others[1] |
763 |
1 |
|
T5 |
28 |
|
T20 |
1 |
|
T22 |
18 |
| others[2] |
736 |
1 |
|
T5 |
11 |
|
T20 |
1 |
|
T9 |
1 |
| others[3] |
1255 |
1 |
|
T5 |
30 |
|
T8 |
1 |
|
T22 |
17 |
| false |
423 |
1 |
|
T5 |
17 |
|
T22 |
9 |
|
T51 |
1 |
| true |
525 |
1 |
|
T4 |
1 |
|
T20 |
2 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2389 |
1 |
|
T1 |
32 |
|
T5 |
13 |
|
T6 |
11 |
| others[1] |
2342 |
1 |
|
T1 |
17 |
|
T4 |
1 |
|
T5 |
8 |
| others[2] |
2383 |
1 |
|
T1 |
24 |
|
T5 |
7 |
|
T6 |
7 |
| others[3] |
3929 |
1 |
|
T1 |
32 |
|
T5 |
19 |
|
T20 |
2 |
| false |
1247 |
1 |
|
T1 |
14 |
|
T5 |
3 |
|
T20 |
1 |
| true |
1472 |
1 |
|
T5 |
51 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9536 |
1 |
|
T1 |
119 |
|
T5 |
7 |
|
T6 |
40 |
| others[1] |
261 |
1 |
|
T5 |
6 |
|
T20 |
1 |
|
T8 |
1 |
| others[2] |
270 |
1 |
|
T5 |
10 |
|
T58 |
1 |
|
T131 |
1 |
| others[3] |
439 |
1 |
|
T5 |
15 |
|
T20 |
1 |
|
T58 |
3 |
| false |
148 |
1 |
|
T5 |
5 |
|
T7 |
1 |
|
T25 |
1 |
| true |
3108 |
1 |
|
T4 |
1 |
|
T5 |
58 |
|
T20 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9786 |
1 |
|
T1 |
119 |
|
T5 |
12 |
|
T20 |
3 |
| others[1] |
444 |
1 |
|
T5 |
10 |
|
T20 |
1 |
|
T8 |
1 |
| others[2] |
411 |
1 |
|
T5 |
13 |
|
T22 |
12 |
|
T15 |
1 |
| others[3] |
790 |
1 |
|
T5 |
16 |
|
T20 |
1 |
|
T8 |
1 |
| false |
245 |
1 |
|
T5 |
6 |
|
T22 |
7 |
|
T69 |
3 |
| true |
2086 |
1 |
|
T4 |
1 |
|
T5 |
44 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9546 |
1 |
|
T1 |
119 |
|
T4 |
1 |
|
T5 |
7 |
| others[1] |
287 |
1 |
|
T5 |
9 |
|
T20 |
1 |
|
T51 |
1 |
| others[2] |
248 |
1 |
|
T5 |
10 |
|
T52 |
1 |
|
T58 |
3 |
| others[3] |
469 |
1 |
|
T5 |
16 |
|
T8 |
1 |
|
T58 |
2 |
| false |
116 |
1 |
|
T5 |
5 |
|
T20 |
1 |
|
T47 |
1 |
| true |
3096 |
1 |
|
T5 |
54 |
|
T20 |
3 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9551 |
1 |
|
T1 |
119 |
|
T5 |
16 |
|
T20 |
4 |
| others[1] |
230 |
1 |
|
T5 |
7 |
|
T8 |
1 |
|
T58 |
1 |
| others[2] |
226 |
1 |
|
T5 |
9 |
|
T29 |
1 |
|
T107 |
1 |
| others[3] |
406 |
1 |
|
T5 |
11 |
|
T58 |
2 |
|
T62 |
3 |
| false |
137 |
1 |
|
T4 |
1 |
|
T5 |
7 |
|
T8 |
1 |
| true |
3212 |
1 |
|
T5 |
51 |
|
T20 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10071 |
1 |
|
T1 |
119 |
|
T5 |
18 |
|
T6 |
40 |
| others[1] |
748 |
1 |
|
T5 |
17 |
|
T22 |
7 |
|
T105 |
1 |
| others[2] |
767 |
1 |
|
T5 |
18 |
|
T22 |
14 |
|
T69 |
18 |
| others[3] |
1267 |
1 |
|
T5 |
37 |
|
T9 |
1 |
|
T22 |
26 |
| false |
401 |
1 |
|
T5 |
11 |
|
T20 |
2 |
|
T22 |
10 |
| true |
508 |
1 |
|
T4 |
1 |
|
T20 |
3 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10076 |
1 |
|
T1 |
119 |
|
T5 |
22 |
|
T20 |
1 |
| others[1] |
794 |
1 |
|
T5 |
25 |
|
T20 |
1 |
|
T9 |
1 |
| others[2] |
769 |
1 |
|
T5 |
24 |
|
T22 |
19 |
|
T51 |
1 |
| others[3] |
1211 |
1 |
|
T5 |
25 |
|
T22 |
14 |
|
T69 |
28 |
| false |
387 |
1 |
|
T5 |
5 |
|
T22 |
7 |
|
T69 |
7 |
| true |
525 |
1 |
|
T4 |
1 |
|
T20 |
3 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2367 |
1 |
|
T1 |
23 |
|
T4 |
1 |
|
T5 |
13 |
| others[1] |
2376 |
1 |
|
T1 |
20 |
|
T5 |
7 |
|
T6 |
9 |
| others[2] |
2371 |
1 |
|
T1 |
23 |
|
T5 |
10 |
|
T20 |
2 |
| others[3] |
3939 |
1 |
|
T1 |
37 |
|
T5 |
23 |
|
T20 |
1 |
| false |
1201 |
1 |
|
T1 |
16 |
|
T5 |
5 |
|
T20 |
1 |
| true |
1508 |
1 |
|
T5 |
43 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9565 |
1 |
|
T1 |
119 |
|
T4 |
1 |
|
T5 |
14 |
| others[1] |
260 |
1 |
|
T5 |
10 |
|
T20 |
1 |
|
T58 |
1 |
| others[2] |
295 |
1 |
|
T5 |
13 |
|
T58 |
1 |
|
T29 |
1 |
| others[3] |
447 |
1 |
|
T5 |
15 |
|
T7 |
1 |
|
T25 |
1 |
| false |
132 |
1 |
|
T5 |
3 |
|
T8 |
1 |
|
T52 |
1 |
| true |
3063 |
1 |
|
T5 |
46 |
|
T20 |
3 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9764 |
1 |
|
T1 |
119 |
|
T5 |
9 |
|
T20 |
1 |
| others[1] |
435 |
1 |
|
T5 |
6 |
|
T8 |
1 |
|
T22 |
6 |
| others[2] |
434 |
1 |
|
T4 |
1 |
|
T5 |
13 |
|
T20 |
2 |
| others[3] |
756 |
1 |
|
T5 |
16 |
|
T20 |
2 |
|
T22 |
13 |
| false |
234 |
1 |
|
T5 |
5 |
|
T22 |
2 |
|
T69 |
4 |
| true |
2139 |
1 |
|
T5 |
52 |
|
T24 |
1 |
|
T22 |
37 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9550 |
1 |
|
T1 |
119 |
|
T5 |
12 |
|
T20 |
1 |
| others[1] |
265 |
1 |
|
T5 |
10 |
|
T58 |
1 |
|
T63 |
1 |
| others[2] |
262 |
1 |
|
T5 |
13 |
|
T7 |
1 |
|
T210 |
1 |
| others[3] |
431 |
1 |
|
T5 |
17 |
|
T20 |
1 |
|
T8 |
1 |
| false |
136 |
1 |
|
T5 |
4 |
|
T9 |
1 |
|
T58 |
1 |
| true |
3118 |
1 |
|
T4 |
1 |
|
T5 |
45 |
|
T20 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9532 |
1 |
|
T1 |
119 |
|
T4 |
1 |
|
T5 |
18 |
| others[1] |
238 |
1 |
|
T5 |
4 |
|
T58 |
1 |
|
T62 |
1 |
| others[2] |
222 |
1 |
|
T5 |
10 |
|
T20 |
1 |
|
T51 |
1 |
| others[3] |
417 |
1 |
|
T5 |
17 |
|
T20 |
1 |
|
T58 |
1 |
| false |
122 |
1 |
|
T5 |
2 |
|
T8 |
1 |
|
T105 |
1 |
| true |
3231 |
1 |
|
T5 |
50 |
|
T20 |
2 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10071 |
1 |
|
T1 |
119 |
|
T5 |
16 |
|
T6 |
40 |
| others[1] |
774 |
1 |
|
T5 |
26 |
|
T8 |
1 |
|
T22 |
14 |
| others[2] |
773 |
1 |
|
T5 |
21 |
|
T9 |
1 |
|
T22 |
19 |
| others[3] |
1252 |
1 |
|
T5 |
27 |
|
T20 |
1 |
|
T8 |
1 |
| false |
398 |
1 |
|
T5 |
11 |
|
T22 |
13 |
|
T52 |
1 |
| true |
494 |
1 |
|
T4 |
1 |
|
T20 |
4 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10083 |
1 |
|
T1 |
119 |
|
T5 |
25 |
|
T20 |
1 |
| others[1] |
758 |
1 |
|
T5 |
20 |
|
T20 |
4 |
|
T8 |
1 |
| others[2] |
747 |
1 |
|
T5 |
15 |
|
T8 |
1 |
|
T22 |
14 |
| others[3] |
1266 |
1 |
|
T5 |
29 |
|
T22 |
22 |
|
T51 |
1 |
| false |
386 |
1 |
|
T5 |
12 |
|
T22 |
9 |
|
T69 |
11 |
| true |
522 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2344 |
1 |
|
T1 |
23 |
|
T5 |
6 |
|
T20 |
2 |
| others[1] |
2347 |
1 |
|
T1 |
23 |
|
T4 |
1 |
|
T5 |
5 |
| others[2] |
2367 |
1 |
|
T1 |
29 |
|
T5 |
11 |
|
T20 |
1 |
| others[3] |
3922 |
1 |
|
T1 |
30 |
|
T5 |
19 |
|
T20 |
1 |
| false |
1284 |
1 |
|
T1 |
14 |
|
T5 |
6 |
|
T20 |
1 |
| true |
1498 |
1 |
|
T5 |
54 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9544 |
1 |
|
T1 |
119 |
|
T5 |
8 |
|
T20 |
1 |
| others[1] |
261 |
1 |
|
T4 |
1 |
|
T5 |
8 |
|
T36 |
1 |
| others[2] |
262 |
1 |
|
T5 |
13 |
|
T8 |
1 |
|
T51 |
1 |
| others[3] |
464 |
1 |
|
T5 |
18 |
|
T20 |
1 |
|
T8 |
1 |
| false |
156 |
1 |
|
T5 |
6 |
|
T228 |
1 |
|
T28 |
1 |
| true |
3075 |
1 |
|
T5 |
48 |
|
T20 |
3 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9752 |
1 |
|
T1 |
119 |
|
T5 |
9 |
|
T20 |
2 |
| others[1] |
479 |
1 |
|
T5 |
12 |
|
T24 |
1 |
|
T22 |
10 |
| others[2] |
455 |
1 |
|
T5 |
9 |
|
T20 |
1 |
|
T8 |
1 |
| others[3] |
757 |
1 |
|
T5 |
13 |
|
T20 |
2 |
|
T8 |
1 |
| false |
249 |
1 |
|
T5 |
3 |
|
T7 |
1 |
|
T22 |
4 |
| true |
2070 |
1 |
|
T4 |
1 |
|
T5 |
55 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9561 |
1 |
|
T1 |
119 |
|
T5 |
6 |
|
T6 |
40 |
| others[1] |
243 |
1 |
|
T5 |
14 |
|
T62 |
1 |
|
T107 |
1 |
| others[2] |
264 |
1 |
|
T5 |
7 |
|
T20 |
1 |
|
T8 |
1 |
| others[3] |
427 |
1 |
|
T5 |
21 |
|
T20 |
1 |
|
T24 |
1 |
| false |
147 |
1 |
|
T5 |
3 |
|
T7 |
1 |
|
T58 |
1 |
| true |
3120 |
1 |
|
T4 |
1 |
|
T5 |
50 |
|
T20 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9544 |
1 |
|
T1 |
119 |
|
T5 |
15 |
|
T20 |
3 |
| others[1] |
256 |
1 |
|
T5 |
13 |
|
T58 |
1 |
|
T62 |
2 |
| others[2] |
222 |
1 |
|
T5 |
8 |
|
T62 |
1 |
|
T121 |
1 |
| others[3] |
398 |
1 |
|
T5 |
13 |
|
T20 |
1 |
|
T8 |
1 |
| false |
133 |
1 |
|
T5 |
2 |
|
T131 |
1 |
|
T228 |
1 |
| true |
3209 |
1 |
|
T4 |
1 |
|
T5 |
50 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10062 |
1 |
|
T1 |
119 |
|
T5 |
14 |
|
T6 |
40 |
| others[1] |
756 |
1 |
|
T5 |
13 |
|
T22 |
13 |
|
T16 |
1 |
| others[2] |
761 |
1 |
|
T5 |
20 |
|
T20 |
1 |
|
T8 |
1 |
| others[3] |
1301 |
1 |
|
T5 |
43 |
|
T20 |
1 |
|
T22 |
23 |
| false |
377 |
1 |
|
T5 |
11 |
|
T8 |
1 |
|
T22 |
5 |
| true |
505 |
1 |
|
T4 |
1 |
|
T20 |
3 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10060 |
1 |
|
T1 |
119 |
|
T5 |
24 |
|
T20 |
1 |
| others[1] |
717 |
1 |
|
T5 |
22 |
|
T22 |
22 |
|
T52 |
1 |
| others[2] |
825 |
1 |
|
T5 |
24 |
|
T20 |
1 |
|
T22 |
11 |
| others[3] |
1217 |
1 |
|
T5 |
26 |
|
T20 |
2 |
|
T22 |
23 |
| false |
422 |
1 |
|
T5 |
5 |
|
T8 |
1 |
|
T9 |
1 |
| true |
521 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2368 |
1 |
|
T1 |
27 |
|
T5 |
11 |
|
T6 |
7 |
| others[1] |
2367 |
1 |
|
T1 |
28 |
|
T5 |
11 |
|
T20 |
1 |
| others[2] |
2350 |
1 |
|
T1 |
18 |
|
T5 |
10 |
|
T20 |
1 |
| others[3] |
3937 |
1 |
|
T1 |
37 |
|
T5 |
19 |
|
T20 |
2 |
| false |
1250 |
1 |
|
T1 |
9 |
|
T5 |
5 |
|
T20 |
1 |
| true |
1490 |
1 |
|
T4 |
1 |
|
T5 |
45 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9549 |
1 |
|
T1 |
119 |
|
T5 |
10 |
|
T20 |
1 |
| others[1] |
256 |
1 |
|
T5 |
10 |
|
T20 |
1 |
|
T8 |
1 |
| others[2] |
258 |
1 |
|
T5 |
10 |
|
T58 |
1 |
|
T25 |
1 |
| others[3] |
455 |
1 |
|
T5 |
16 |
|
T20 |
1 |
|
T51 |
1 |
| false |
138 |
1 |
|
T4 |
1 |
|
T5 |
6 |
|
T8 |
1 |
| true |
3106 |
1 |
|
T5 |
49 |
|
T20 |
2 |
|
T7 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |