Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9761 |
1 |
|
T1 |
119 |
|
T5 |
11 |
|
T20 |
2 |
| others[1] |
417 |
1 |
|
T5 |
9 |
|
T9 |
1 |
|
T22 |
6 |
| others[2] |
465 |
1 |
|
T5 |
14 |
|
T20 |
1 |
|
T7 |
1 |
| others[3] |
757 |
1 |
|
T5 |
16 |
|
T20 |
2 |
|
T22 |
16 |
| false |
207 |
1 |
|
T5 |
3 |
|
T22 |
1 |
|
T15 |
1 |
| true |
2155 |
1 |
|
T4 |
1 |
|
T5 |
48 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9558 |
1 |
|
T1 |
119 |
|
T5 |
13 |
|
T6 |
40 |
| others[1] |
256 |
1 |
|
T5 |
14 |
|
T7 |
1 |
|
T210 |
1 |
| others[2] |
244 |
1 |
|
T5 |
10 |
|
T58 |
1 |
|
T62 |
3 |
| others[3] |
424 |
1 |
|
T5 |
15 |
|
T20 |
1 |
|
T8 |
1 |
| false |
136 |
1 |
|
T5 |
8 |
|
T20 |
1 |
|
T58 |
1 |
| true |
3144 |
1 |
|
T4 |
1 |
|
T5 |
41 |
|
T20 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9554 |
1 |
|
T1 |
119 |
|
T5 |
13 |
|
T20 |
2 |
| others[1] |
228 |
1 |
|
T4 |
1 |
|
T5 |
9 |
|
T20 |
2 |
| others[2] |
221 |
1 |
|
T5 |
9 |
|
T30 |
1 |
|
T63 |
1 |
| others[3] |
404 |
1 |
|
T5 |
13 |
|
T9 |
1 |
|
T25 |
1 |
| false |
131 |
1 |
|
T5 |
8 |
|
T58 |
1 |
|
T170 |
1 |
| true |
3224 |
1 |
|
T5 |
49 |
|
T20 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10063 |
1 |
|
T1 |
119 |
|
T5 |
27 |
|
T20 |
1 |
| others[1] |
760 |
1 |
|
T5 |
19 |
|
T20 |
1 |
|
T9 |
1 |
| others[2] |
787 |
1 |
|
T5 |
21 |
|
T20 |
1 |
|
T22 |
13 |
| others[3] |
1228 |
1 |
|
T5 |
23 |
|
T20 |
1 |
|
T8 |
1 |
| false |
413 |
1 |
|
T5 |
11 |
|
T20 |
1 |
|
T22 |
8 |
| true |
511 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10063 |
1 |
|
T1 |
119 |
|
T5 |
14 |
|
T6 |
40 |
| others[1] |
751 |
1 |
|
T5 |
22 |
|
T20 |
1 |
|
T22 |
12 |
| others[2] |
730 |
1 |
|
T5 |
21 |
|
T20 |
2 |
|
T22 |
17 |
| others[3] |
1317 |
1 |
|
T5 |
33 |
|
T22 |
21 |
|
T69 |
26 |
| false |
370 |
1 |
|
T5 |
11 |
|
T8 |
1 |
|
T9 |
1 |
| true |
531 |
1 |
|
T4 |
1 |
|
T20 |
2 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2397 |
1 |
|
T1 |
25 |
|
T4 |
1 |
|
T5 |
14 |
| others[1] |
2470 |
1 |
|
T1 |
22 |
|
T5 |
12 |
|
T20 |
1 |
| others[2] |
2314 |
1 |
|
T1 |
30 |
|
T5 |
8 |
|
T20 |
3 |
| others[3] |
3912 |
1 |
|
T1 |
30 |
|
T5 |
19 |
|
T6 |
16 |
| false |
1198 |
1 |
|
T1 |
12 |
|
T5 |
5 |
|
T6 |
2 |
| true |
1471 |
1 |
|
T5 |
43 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9534 |
1 |
|
T1 |
119 |
|
T5 |
6 |
|
T6 |
40 |
| others[1] |
286 |
1 |
|
T5 |
9 |
|
T58 |
1 |
|
T131 |
1 |
| others[2] |
297 |
1 |
|
T5 |
13 |
|
T20 |
1 |
|
T58 |
2 |
| others[3] |
427 |
1 |
|
T4 |
1 |
|
T5 |
24 |
|
T20 |
2 |
| false |
113 |
1 |
|
T5 |
4 |
|
T105 |
1 |
|
T49 |
1 |
| true |
3105 |
1 |
|
T5 |
45 |
|
T20 |
2 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9754 |
1 |
|
T1 |
119 |
|
T5 |
9 |
|
T6 |
40 |
| others[1] |
422 |
1 |
|
T5 |
9 |
|
T20 |
1 |
|
T8 |
1 |
| others[2] |
449 |
1 |
|
T5 |
10 |
|
T8 |
1 |
|
T22 |
8 |
| others[3] |
778 |
1 |
|
T5 |
17 |
|
T20 |
3 |
|
T9 |
1 |
| false |
213 |
1 |
|
T4 |
1 |
|
T5 |
2 |
|
T20 |
1 |
| true |
2146 |
1 |
|
T5 |
54 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9541 |
1 |
|
T1 |
119 |
|
T5 |
10 |
|
T6 |
40 |
| others[1] |
256 |
1 |
|
T4 |
1 |
|
T5 |
7 |
|
T20 |
1 |
| others[2] |
241 |
1 |
|
T5 |
10 |
|
T58 |
1 |
|
T62 |
1 |
| others[3] |
432 |
1 |
|
T5 |
14 |
|
T20 |
1 |
|
T51 |
1 |
| false |
136 |
1 |
|
T5 |
6 |
|
T20 |
1 |
|
T49 |
1 |
| true |
3156 |
1 |
|
T5 |
54 |
|
T20 |
2 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9527 |
1 |
|
T1 |
119 |
|
T5 |
7 |
|
T6 |
40 |
| others[1] |
239 |
1 |
|
T5 |
11 |
|
T20 |
1 |
|
T105 |
1 |
| others[2] |
238 |
1 |
|
T5 |
8 |
|
T8 |
1 |
|
T62 |
1 |
| others[3] |
418 |
1 |
|
T5 |
19 |
|
T20 |
1 |
|
T8 |
1 |
| false |
117 |
1 |
|
T5 |
8 |
|
T20 |
1 |
|
T9 |
1 |
| true |
3223 |
1 |
|
T4 |
1 |
|
T5 |
48 |
|
T20 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10026 |
1 |
|
T1 |
119 |
|
T5 |
17 |
|
T6 |
40 |
| others[1] |
800 |
1 |
|
T5 |
24 |
|
T20 |
1 |
|
T22 |
9 |
| others[2] |
798 |
1 |
|
T5 |
19 |
|
T8 |
1 |
|
T22 |
19 |
| others[3] |
1260 |
1 |
|
T5 |
33 |
|
T22 |
24 |
|
T69 |
23 |
| false |
369 |
1 |
|
T5 |
8 |
|
T22 |
4 |
|
T69 |
11 |
| true |
509 |
1 |
|
T4 |
1 |
|
T20 |
4 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10082 |
1 |
|
T1 |
119 |
|
T5 |
17 |
|
T6 |
40 |
| others[1] |
768 |
1 |
|
T5 |
15 |
|
T20 |
1 |
|
T22 |
19 |
| others[2] |
754 |
1 |
|
T5 |
23 |
|
T22 |
10 |
|
T69 |
16 |
| others[3] |
1257 |
1 |
|
T5 |
36 |
|
T22 |
21 |
|
T51 |
1 |
| false |
383 |
1 |
|
T5 |
10 |
|
T9 |
1 |
|
T22 |
8 |
| true |
518 |
1 |
|
T4 |
1 |
|
T20 |
4 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2344 |
1 |
|
T1 |
33 |
|
T5 |
8 |
|
T20 |
2 |
| others[1] |
2396 |
1 |
|
T1 |
24 |
|
T5 |
11 |
|
T6 |
4 |
| others[2] |
2410 |
1 |
|
T1 |
16 |
|
T5 |
9 |
|
T20 |
1 |
| others[3] |
3907 |
1 |
|
T1 |
29 |
|
T5 |
18 |
|
T20 |
1 |
| false |
1210 |
1 |
|
T1 |
17 |
|
T5 |
5 |
|
T20 |
1 |
| true |
1495 |
1 |
|
T4 |
1 |
|
T5 |
50 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9566 |
1 |
|
T1 |
119 |
|
T5 |
9 |
|
T6 |
40 |
| others[1] |
269 |
1 |
|
T5 |
6 |
|
T20 |
1 |
|
T8 |
1 |
| others[2] |
268 |
1 |
|
T5 |
15 |
|
T20 |
1 |
|
T51 |
1 |
| others[3] |
443 |
1 |
|
T5 |
17 |
|
T20 |
1 |
|
T24 |
1 |
| false |
119 |
1 |
|
T5 |
6 |
|
T20 |
2 |
|
T105 |
1 |
| true |
3097 |
1 |
|
T4 |
1 |
|
T5 |
48 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9768 |
1 |
|
T1 |
119 |
|
T5 |
13 |
|
T20 |
1 |
| others[1] |
450 |
1 |
|
T5 |
10 |
|
T20 |
1 |
|
T7 |
1 |
| others[2] |
434 |
1 |
|
T5 |
12 |
|
T20 |
1 |
|
T24 |
1 |
| others[3] |
771 |
1 |
|
T5 |
17 |
|
T20 |
2 |
|
T9 |
1 |
| false |
224 |
1 |
|
T5 |
4 |
|
T8 |
1 |
|
T22 |
4 |
| true |
2115 |
1 |
|
T4 |
1 |
|
T5 |
45 |
|
T22 |
41 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9570 |
1 |
|
T1 |
119 |
|
T5 |
7 |
|
T6 |
40 |
| others[1] |
257 |
1 |
|
T5 |
12 |
|
T20 |
1 |
|
T29 |
1 |
| others[2] |
264 |
1 |
|
T5 |
9 |
|
T382 |
1 |
|
T109 |
1 |
| others[3] |
408 |
1 |
|
T4 |
1 |
|
T5 |
18 |
|
T8 |
1 |
| false |
113 |
1 |
|
T5 |
8 |
|
T20 |
1 |
|
T107 |
1 |
| true |
3150 |
1 |
|
T5 |
47 |
|
T20 |
3 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9562 |
1 |
|
T1 |
119 |
|
T5 |
10 |
|
T6 |
40 |
| others[1] |
250 |
1 |
|
T5 |
8 |
|
T20 |
1 |
|
T36 |
1 |
| others[2] |
249 |
1 |
|
T5 |
8 |
|
T58 |
1 |
|
T228 |
1 |
| others[3] |
425 |
1 |
|
T5 |
17 |
|
T20 |
1 |
|
T8 |
1 |
| false |
116 |
1 |
|
T5 |
7 |
|
T58 |
1 |
|
T107 |
1 |
| true |
3160 |
1 |
|
T4 |
1 |
|
T5 |
51 |
|
T20 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10025 |
1 |
|
T1 |
119 |
|
T5 |
24 |
|
T6 |
40 |
| others[1] |
774 |
1 |
|
T5 |
24 |
|
T22 |
17 |
|
T16 |
1 |
| others[2] |
757 |
1 |
|
T5 |
9 |
|
T8 |
1 |
|
T9 |
1 |
| others[3] |
1313 |
1 |
|
T5 |
36 |
|
T20 |
1 |
|
T22 |
19 |
| false |
392 |
1 |
|
T5 |
8 |
|
T20 |
1 |
|
T22 |
10 |
| true |
501 |
1 |
|
T4 |
1 |
|
T20 |
3 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10064 |
1 |
|
T1 |
119 |
|
T5 |
20 |
|
T20 |
2 |
| others[1] |
771 |
1 |
|
T5 |
19 |
|
T20 |
1 |
|
T22 |
14 |
| others[2] |
722 |
1 |
|
T5 |
22 |
|
T22 |
11 |
|
T15 |
1 |
| others[3] |
1304 |
1 |
|
T5 |
32 |
|
T22 |
23 |
|
T105 |
1 |
| false |
376 |
1 |
|
T5 |
8 |
|
T20 |
1 |
|
T22 |
9 |
| true |
525 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2384 |
1 |
|
T1 |
22 |
|
T5 |
9 |
|
T20 |
1 |
| others[1] |
2351 |
1 |
|
T1 |
16 |
|
T5 |
9 |
|
T6 |
8 |
| others[2] |
2357 |
1 |
|
T1 |
24 |
|
T5 |
10 |
|
T20 |
2 |
| others[3] |
3927 |
1 |
|
T1 |
46 |
|
T5 |
14 |
|
T20 |
2 |
| false |
1256 |
1 |
|
T1 |
11 |
|
T5 |
9 |
|
T6 |
4 |
| true |
1487 |
1 |
|
T4 |
1 |
|
T5 |
50 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9561 |
1 |
|
T1 |
119 |
|
T5 |
15 |
|
T6 |
40 |
| others[1] |
264 |
1 |
|
T5 |
8 |
|
T20 |
2 |
|
T51 |
1 |
| others[2] |
282 |
1 |
|
T5 |
7 |
|
T20 |
1 |
|
T58 |
1 |
| others[3] |
449 |
1 |
|
T4 |
1 |
|
T5 |
22 |
|
T9 |
1 |
| false |
122 |
1 |
|
T5 |
7 |
|
T20 |
1 |
|
T7 |
1 |
| true |
3084 |
1 |
|
T5 |
42 |
|
T20 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9744 |
1 |
|
T1 |
119 |
|
T5 |
9 |
|
T20 |
1 |
| others[1] |
448 |
1 |
|
T5 |
9 |
|
T8 |
1 |
|
T22 |
6 |
| others[2] |
432 |
1 |
|
T5 |
12 |
|
T20 |
1 |
|
T22 |
7 |
| others[3] |
737 |
1 |
|
T5 |
12 |
|
T20 |
3 |
|
T8 |
1 |
| false |
223 |
1 |
|
T5 |
6 |
|
T22 |
6 |
|
T105 |
1 |
| true |
2178 |
1 |
|
T4 |
1 |
|
T5 |
53 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9540 |
1 |
|
T1 |
119 |
|
T5 |
11 |
|
T6 |
40 |
| others[1] |
246 |
1 |
|
T5 |
10 |
|
T20 |
2 |
|
T52 |
1 |
| others[2] |
257 |
1 |
|
T5 |
8 |
|
T58 |
2 |
|
T248 |
1 |
| others[3] |
438 |
1 |
|
T5 |
20 |
|
T20 |
1 |
|
T24 |
1 |
| false |
115 |
1 |
|
T5 |
7 |
|
T58 |
1 |
|
T62 |
1 |
| true |
3166 |
1 |
|
T4 |
1 |
|
T5 |
45 |
|
T20 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9553 |
1 |
|
T1 |
119 |
|
T5 |
11 |
|
T6 |
40 |
| others[1] |
260 |
1 |
|
T5 |
9 |
|
T20 |
1 |
|
T8 |
2 |
| others[2] |
225 |
1 |
|
T5 |
12 |
|
T20 |
2 |
|
T25 |
1 |
| others[3] |
384 |
1 |
|
T5 |
15 |
|
T52 |
1 |
|
T58 |
3 |
| false |
156 |
1 |
|
T5 |
11 |
|
T20 |
1 |
|
T131 |
1 |
| true |
3184 |
1 |
|
T4 |
1 |
|
T5 |
43 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10072 |
1 |
|
T1 |
119 |
|
T5 |
20 |
|
T6 |
40 |
| others[1] |
771 |
1 |
|
T5 |
19 |
|
T20 |
1 |
|
T9 |
1 |
| others[2] |
803 |
1 |
|
T5 |
24 |
|
T8 |
1 |
|
T22 |
12 |
| others[3] |
1237 |
1 |
|
T5 |
29 |
|
T8 |
1 |
|
T22 |
21 |
| false |
379 |
1 |
|
T5 |
9 |
|
T20 |
1 |
|
T22 |
7 |
| true |
500 |
1 |
|
T4 |
1 |
|
T20 |
3 |
|
T7 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |