Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	225480	1		T1	720		T4	404		T5	100
auto[FlashEraseBank]	253634	1		T4	395		T5	918		T20	21

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	263391	1		T1	352		T4	799		T5	414
auto[FlashOpProgram]	196375	1		T1	184		T5	545		T20	23
auto[FlashOpErase]	15348	1		T1	184		T5	59		T20	6
auto[FlashOpInvalid]	4000	1		T112	200		T214	200		T215	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	263391	1		T1	352		T4	799		T5	414
op[FlashOpProgram]	196375	1		T1	184		T5	545		T20	23
op[FlashOpErase]	15348	1		T1	184		T5	59		T20	6
read_erase_read	733	1		T5	4		T20	2		T8	1
read_prog_read	1339	1		T5	5		T20	6		T8	4

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	339696	1		T4	466		T5	95		T20	35
auto[FlashPartInfo]	135247	1		T1	720		T4	325		T5	923
auto[FlashPartInfo1]	953	1		T4	2		T20	12		T8	3
auto[FlashPartInfo2]	3218	1		T4	6		T20	8		T8	5

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	201225	1		T4	466		T5	29		T20	17
auto[FlashPartData]	auto[FlashOpProgram]	130863	1		T5	30		T20	14		T8	7
auto[FlashPartData]	auto[FlashOpErase]	3712	1		T5	36		T20	4		T8	2
auto[FlashPartData]	auto[FlashOpInvalid]	3896	1		T112	194		T214	192		T215	198
auto[FlashPartInfo]	auto[FlashOpRead]	59495	1		T1	352		T4	325		T5	385
auto[FlashPartInfo]	auto[FlashOpProgram]	64068	1		T1	184		T5	515		T20	4
auto[FlashPartInfo]	auto[FlashOpErase]	11606	1		T1	184		T5	23		T20	2
auto[FlashPartInfo]	auto[FlashOpInvalid]	78	1		T112	6		T214	8		T215	2
auto[FlashPartInfo1]	auto[FlashOpRead]	769	1		T4	2		T20	12		T8	3
auto[FlashPartInfo1]	auto[FlashOpProgram]	168	1		T89	1		T92	1		T97	1
auto[FlashPartInfo1]	auto[FlashOpErase]	8	1		T89	1		T90	1		T92	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	8	1		T89	2		T92	2		T97	2
auto[FlashPartInfo2]	auto[FlashOpRead]	1902	1		T4	6		T20	3		T8	1
auto[FlashPartInfo2]	auto[FlashOpProgram]	1276	1		T20	5		T8	4		T24	26
auto[FlashPartInfo2]	auto[FlashOpErase]	22	1		T423	1		T120	1		T424	4
auto[FlashPartInfo2]	auto[FlashOpInvalid]	18	1		T423	2		T424	8		T92	2