Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.48	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	4	28	87.50

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	4	28	87.50	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29799	1		T1	372		T5	12		T20	4
auto[1]	16	1		T334	1		T335	1		T336	2
auto[2]	101	1		T26	2		T60	8		T337	18
auto[3]	593	1		T26	1		T28	86		T338	86

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7713	1		T1	93		T5	3		T20	1
evic_idx[1]	7645	1		T1	93		T5	3		T20	1
evic_idx[2]	7583	1		T1	93		T5	3		T20	1
evic_idx[3]	7568	1		T1	93		T5	3		T20	1

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	29427	1		T1	372		T6	104		T21	308
evic_op[2]	476	1		T26	3		T62	1		T32	4

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	4	28	87.50	4

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[0] , evic_idx[1] , evic_idx[2]]	[evic_op[1]]	[auto[1]]	--	--	3
[evic_idx[3]]	[evic_op[1]]	[auto[2]]	0	1	1

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7230	1		T1	93		T6	26		T21	77
evic_idx[0]	evic_op[1]	auto[2]	2	1		T339	2		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	214	1		T28	33		T338	37		T276	35
evic_idx[0]	evic_op[2]	auto[0]	81	1		T32	1		T100	4		T54	4
evic_idx[0]	evic_op[2]	auto[1]	4	1		T336	1		T168	1		T340	1
evic_idx[0]	evic_op[2]	auto[2]	18	1		T337	7		T341	1		T342	4
evic_idx[0]	evic_op[2]	auto[3]	12	1		T26	1		T343	1		T344	1
evic_idx[1]	evic_op[1]	auto[0]	7231	1		T1	93		T6	26		T21	77
evic_idx[1]	evic_op[1]	auto[2]	2	1		T339	2		-	-		-	-
evic_idx[1]	evic_op[1]	auto[3]	148	1		T28	25		T338	24		T276	25
evic_idx[1]	evic_op[2]	auto[0]	89	1		T32	1		T100	4		T54	4
evic_idx[1]	evic_op[2]	auto[1]	1	1		T340	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[2]	13	1		T337	3		T342	3		T345	7
evic_idx[1]	evic_op[2]	auto[3]	9	1		T199	1		T277	1		T209	1
evic_idx[2]	evic_op[1]	auto[0]	7211	1		T1	93		T6	26		T21	77
evic_idx[2]	evic_op[1]	auto[2]	1	1		T339	1		-	-		-	-
evic_idx[2]	evic_op[1]	auto[3]	97	1		T28	17		T338	15		T276	17
evic_idx[2]	evic_op[2]	auto[0]	88	1		T32	1		T100	4		T54	4
evic_idx[2]	evic_op[2]	auto[1]	3	1		T346	1		T347	1		T340	1
evic_idx[2]	evic_op[2]	auto[2]	19	1		T26	2		T337	5		T341	6
evic_idx[2]	evic_op[2]	auto[3]	13	1		T199	1		T38	1		T201	1
evic_idx[3]	evic_op[1]	auto[0]	7204	1		T1	93		T6	26		T21	77
evic_idx[3]	evic_op[1]	auto[1]	2	1		T348	2		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	85	1		T28	11		T338	10		T276	14
evic_idx[3]	evic_op[2]	auto[0]	83	1		T62	1		T32	1		T100	4
evic_idx[3]	evic_op[2]	auto[1]	6	1		T334	1		T335	1		T336	1
evic_idx[3]	evic_op[2]	auto[2]	22	1		T337	3		T341	4		T342	7
evic_idx[3]	evic_op[2]	auto[3]	15	1		T199	1		T39	1		T343	1