Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	37302	1		T324	8376		T325	2544		T326	1364
rd_lvl[2]	34561	1		T327	1734		T324	4392		T325	1996
rd_lvl[3]	23394	1		T327	1534		T325	970		T326	732
rd_lvl[4]	31287	1		T327	346		T328	2471		T325	1009
rd_lvl[5]	26794	1		T9	1378		T329	1390		T327	1100
rd_lvl[6]	16197	1		T9	1507		T329	776		T327	1406
rd_lvl[7]	11129	1		T9	1		T330	1127		T282	579
rd_lvl[8]	16574	1		T280	1864		T331	1254		T330	699
rd_lvl[9]	11570	1		T332	605		T280	467		T331	318
rd_lvl[10]	6543	1		T7	633		T332	381		T282	10
rd_lvl[11]	6403	1		T7	386		T280	3		T273	211
rd_lvl[12]	4652	1		T208	466		T333	576		T327	26
rd_lvl[13]	3650	1		T7	87		T208	435		T333	328
rd_lvl[14]	7035	1		T35	638		T281	525		T220	872
rd_lvl[15]	6442	1		T34	754		T35	357		T102	577