Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	352428	1		T1	1		T2	1		T3	1
all_pins[1]	352428	1		T1	1		T2	1		T3	1
all_pins[2]	352428	1		T1	1		T2	1		T3	1
all_pins[3]	352428	1		T1	1		T2	1		T3	1
all_pins[4]	352428	1		T1	1		T2	1		T3	1
all_pins[5]	352428	1		T1	1		T2	1		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1760480	1		T1	6		T2	6		T3	6
values[0x1]	354088	1		T7	2212		T9	4594		T25	1112
transitions[0x0=>0x1]	318918	1		T7	2212		T9	3847		T25	1112
transitions[0x1=>0x0]	318907	1		T7	2212		T9	3847		T25	1112

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	352281	1		T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	147	1		T256	2		T257	2		T258	4
all_pins[0]	transitions[0x0=>0x1]	88	1		T257	1		T258	1		T320	2
all_pins[0]	transitions[0x1=>0x0]	77	1		T257	2		T258	1		T320	1
all_pins[1]	values[0x0]	352292	1		T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	136	1		T256	2		T257	3		T258	4
all_pins[1]	transitions[0x0=>0x1]	112	1		T256	1		T257	2		T258	3
all_pins[1]	transitions[0x1=>0x0]	2049	1		T34	454		T35	86		T102	426
all_pins[2]	values[0x0]	350355	1		T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	2073	1		T34	454		T35	86		T102	426
all_pins[2]	transitions[0x0=>0x1]	51	1		T256	1		T257	2		T258	1
all_pins[2]	transitions[0x1=>0x0]	243751	1		T7	1106		T9	2886		T34	819
all_pins[3]	values[0x0]	106655	1		T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	245773	1		T7	1106		T9	2886		T34	1273
all_pins[3]	transitions[0x0=>0x1]	212765	1		T7	1106		T9	2139		T34	819
all_pins[3]	transitions[0x1=>0x0]	72875	1		T7	1106		T9	961		T25	1112
all_pins[4]	values[0x0]	246545	1		T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	105883	1		T7	1106		T9	1708		T25	1112
all_pins[4]	transitions[0x0=>0x1]	105866	1		T7	1106		T9	1708		T25	1112
all_pins[4]	transitions[0x1=>0x0]	59	1		T258	1		T320	2		T321	2
all_pins[5]	values[0x0]	352352	1		T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	76	1		T257	1		T258	2		T320	2
all_pins[5]	transitions[0x0=>0x1]	36	1		T257	1		T258	2		T320	1
all_pins[5]	transitions[0x1=>0x0]	96	1		T256	2		T257	2		T258	3