Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	278	1		T256	4		T257	7		T258	7
all_values[1]	278	1		T256	4		T257	7		T258	7
all_values[2]	278	1		T256	4		T257	7		T258	7
all_values[3]	278	1		T256	4		T257	7		T258	7
all_values[4]	278	1		T256	4		T257	7		T258	7
all_values[5]	278	1		T256	4		T257	7		T258	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	966	1		T256	14		T257	29		T258	18
auto[1]	702	1		T256	10		T257	13		T258	24

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	532	1		T256	10		T257	12		T258	12
auto[1]	1136	1		T256	14		T257	30		T258	30

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	980	1		T256	18		T257	23		T258	24
auto[1]	688	1		T256	6		T257	19		T258	18

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	96	1		T256	2		T257	3		T258	4
all_values[0]	auto[0]	auto[1]	auto[1]	66	1		T256	2		T258	2		T319	3
all_values[0]	auto[1]	auto[0]	auto[1]	65	1		T257	3		T258	1		T320	2
all_values[0]	auto[1]	auto[1]	auto[1]	51	1		T257	1		T320	1		T321	2
all_values[1]	auto[0]	auto[0]	auto[1]	101	1		T256	2		T257	2		T258	1
all_values[1]	auto[0]	auto[1]	auto[1]	70	1		T256	2		T257	1		T258	3
all_values[1]	auto[1]	auto[0]	auto[1]	59	1		T257	2		T258	3		T319	1
all_values[1]	auto[1]	auto[1]	auto[1]	48	1		T257	2		T320	2		T322	2
all_values[2]	auto[0]	auto[0]	auto[0]	80	1		T256	1		T257	3		T258	2
all_values[2]	auto[0]	auto[1]	auto[0]	77	1		T258	3		T320	3		T319	2
all_values[2]	auto[1]	auto[0]	auto[1]	75	1		T256	3		T257	3		T320	2
all_values[2]	auto[1]	auto[1]	auto[1]	46	1		T257	1		T258	2		T322	1
all_values[3]	auto[0]	auto[0]	auto[0]	110	1		T256	3		T257	3		T258	2
all_values[3]	auto[0]	auto[1]	auto[0]	54	1		T257	4		T258	1		T320	2
all_values[3]	auto[1]	auto[0]	auto[1]	83	1		T256	1		T320	2		T322	3
all_values[3]	auto[1]	auto[1]	auto[1]	31	1		T258	4		T320	1		T319	1
all_values[4]	auto[0]	auto[0]	auto[0]	53	1		T257	2		T320	1		T319	2
all_values[4]	auto[0]	auto[0]	auto[1]	37	1		T320	1		T322	2		T321	1
all_values[4]	auto[0]	auto[1]	auto[0]	48	1		T256	2		T320	1		T319	2
all_values[4]	auto[0]	auto[1]	auto[1]	22	1		T257	1		T258	1		T323	1
all_values[4]	auto[1]	auto[0]	auto[1]	71	1		T257	2		T258	2		T320	3
all_values[4]	auto[1]	auto[1]	auto[1]	47	1		T256	2		T257	2		T258	4
all_values[5]	auto[0]	auto[0]	auto[0]	58	1		T256	2		T258	3		T320	1
all_values[5]	auto[0]	auto[0]	auto[1]	24	1		T257	4		T319	1		T322	1
all_values[5]	auto[0]	auto[1]	auto[0]	52	1		T256	2		T258	1		T320	1
all_values[5]	auto[0]	auto[1]	auto[1]	32	1		T258	1		T320	2		T323	1
all_values[5]	auto[1]	auto[0]	auto[1]	54	1		T257	2		T320	3		T319	1
all_values[5]	auto[1]	auto[1]	auto[1]	58	1		T257	1		T258	2		T323	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal