| T1068 |
/workspace/coverage/default/24.flash_ctrl_intr_rd_slow_flash.2446058880 |
|
|
Mar 31 02:56:43 PM PDT 24 |
Mar 31 03:00:23 PM PDT 24 |
39519202600 ps |
| T1069 |
/workspace/coverage/default/19.flash_ctrl_intr_rd_slow_flash.3185284480 |
|
|
Mar 31 02:55:55 PM PDT 24 |
Mar 31 02:59:27 PM PDT 24 |
9540976200 ps |
| T1070 |
/workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.1881741221 |
|
|
Mar 31 02:57:16 PM PDT 24 |
Mar 31 02:57:47 PM PDT 24 |
79108900 ps |
| T1071 |
/workspace/coverage/default/23.flash_ctrl_alert_test.2050272474 |
|
|
Mar 31 02:56:37 PM PDT 24 |
Mar 31 02:56:50 PM PDT 24 |
102258900 ps |
| T1072 |
/workspace/coverage/default/25.flash_ctrl_otp_reset.2537478791 |
|
|
Mar 31 02:56:55 PM PDT 24 |
Mar 31 02:59:04 PM PDT 24 |
37696100 ps |
| T1073 |
/workspace/coverage/default/3.flash_ctrl_phy_arb_redun.1201941948 |
|
|
Mar 31 02:49:40 PM PDT 24 |
Mar 31 02:50:56 PM PDT 24 |
886254600 ps |
| T1074 |
/workspace/coverage/default/12.flash_ctrl_prog_reset.1131354951 |
|
|
Mar 31 02:53:37 PM PDT 24 |
Mar 31 02:54:25 PM PDT 24 |
2230755000 ps |
| T45 |
/workspace/coverage/default/3.flash_ctrl_sec_cm.2191824365 |
|
|
Mar 31 02:49:35 PM PDT 24 |
Mar 31 04:08:27 PM PDT 24 |
2068876900 ps |
| T1075 |
/workspace/coverage/default/39.flash_ctrl_sec_info_access.104727409 |
|
|
Mar 31 02:58:44 PM PDT 24 |
Mar 31 02:59:50 PM PDT 24 |
1290871100 ps |
| T1076 |
/workspace/coverage/default/4.flash_ctrl_ro_derr.1385748117 |
|
|
Mar 31 02:50:03 PM PDT 24 |
Mar 31 02:52:22 PM PDT 24 |
3829718600 ps |
| T1077 |
/workspace/coverage/default/9.flash_ctrl_disable.1568316115 |
|
|
Mar 31 02:52:33 PM PDT 24 |
Mar 31 02:52:55 PM PDT 24 |
11404100 ps |
| T1078 |
/workspace/coverage/default/76.flash_ctrl_connect.3655105282 |
|
|
Mar 31 03:00:02 PM PDT 24 |
Mar 31 03:00:15 PM PDT 24 |
37896800 ps |
| T1079 |
/workspace/coverage/default/26.flash_ctrl_alert_test.1426380005 |
|
|
Mar 31 02:57:05 PM PDT 24 |
Mar 31 02:57:19 PM PDT 24 |
50357900 ps |
| T1080 |
/workspace/coverage/default/0.flash_ctrl_rand_ops.2231169396 |
|
|
Mar 31 02:47:47 PM PDT 24 |
Mar 31 02:51:46 PM PDT 24 |
99926200 ps |
| T1081 |
/workspace/coverage/default/42.flash_ctrl_disable.2132912133 |
|
|
Mar 31 02:58:57 PM PDT 24 |
Mar 31 02:59:19 PM PDT 24 |
15851200 ps |
| T1082 |
/workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.569599176 |
|
|
Mar 31 02:58:23 PM PDT 24 |
Mar 31 03:01:38 PM PDT 24 |
16237445400 ps |
| T1083 |
/workspace/coverage/default/9.flash_ctrl_re_evict.3362623170 |
|
|
Mar 31 02:52:29 PM PDT 24 |
Mar 31 02:53:05 PM PDT 24 |
317140600 ps |
| T1084 |
/workspace/coverage/default/12.flash_ctrl_rw_evict_all_en.741981299 |
|
|
Mar 31 02:53:36 PM PDT 24 |
Mar 31 02:54:05 PM PDT 24 |
27370800 ps |
| T1085 |
/workspace/coverage/default/2.flash_ctrl_error_mp.3203773841 |
|
|
Mar 31 02:48:38 PM PDT 24 |
Mar 31 03:26:31 PM PDT 24 |
99245985300 ps |
| T1086 |
/workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.804562750 |
|
|
Mar 31 02:54:48 PM PDT 24 |
Mar 31 02:57:58 PM PDT 24 |
16015725500 ps |
| T1087 |
/workspace/coverage/default/73.flash_ctrl_connect.2880384410 |
|
|
Mar 31 02:59:55 PM PDT 24 |
Mar 31 03:00:10 PM PDT 24 |
13851900 ps |
| T1088 |
/workspace/coverage/default/7.flash_ctrl_disable.366701023 |
|
|
Mar 31 02:51:36 PM PDT 24 |
Mar 31 02:51:57 PM PDT 24 |
17751300 ps |
| T1089 |
/workspace/coverage/default/3.flash_ctrl_fs_sup.2218332348 |
|
|
Mar 31 02:49:39 PM PDT 24 |
Mar 31 02:50:14 PM PDT 24 |
1249413700 ps |
| T1090 |
/workspace/coverage/default/36.flash_ctrl_sec_info_access.132132597 |
|
|
Mar 31 02:58:24 PM PDT 24 |
Mar 31 02:59:30 PM PDT 24 |
1357665400 ps |
| T1091 |
/workspace/coverage/default/48.flash_ctrl_hw_sec_otp.4111005053 |
|
|
Mar 31 02:59:26 PM PDT 24 |
Mar 31 03:00:50 PM PDT 24 |
4437491800 ps |
| T57 |
/workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.2818199478 |
|
|
Mar 31 02:49:39 PM PDT 24 |
Mar 31 02:49:53 PM PDT 24 |
23719400 ps |
| T1092 |
/workspace/coverage/default/1.flash_ctrl_fetch_code.1400967979 |
|
|
Mar 31 02:48:05 PM PDT 24 |
Mar 31 02:48:27 PM PDT 24 |
116669900 ps |
| T1093 |
/workspace/coverage/default/26.flash_ctrl_rw_evict.2874258053 |
|
|
Mar 31 02:57:06 PM PDT 24 |
Mar 31 02:57:41 PM PDT 24 |
86855500 ps |
| T1094 |
/workspace/coverage/default/73.flash_ctrl_otp_reset.3609235016 |
|
|
Mar 31 02:59:53 PM PDT 24 |
Mar 31 03:02:03 PM PDT 24 |
134250000 ps |
| T1095 |
/workspace/coverage/default/44.flash_ctrl_hw_sec_otp.110543918 |
|
|
Mar 31 02:59:06 PM PDT 24 |
Mar 31 03:01:16 PM PDT 24 |
9600296400 ps |
| T1096 |
/workspace/coverage/default/8.flash_ctrl_mp_regions.3171150045 |
|
|
Mar 31 02:51:40 PM PDT 24 |
Mar 31 03:05:22 PM PDT 24 |
12137059600 ps |
| T1097 |
/workspace/coverage/default/14.flash_ctrl_intr_rd.2393943389 |
|
|
Mar 31 02:54:11 PM PDT 24 |
Mar 31 02:56:35 PM PDT 24 |
1916132200 ps |
| T1098 |
/workspace/coverage/default/0.flash_ctrl_mp_regions.1768707212 |
|
|
Mar 31 02:47:46 PM PDT 24 |
Mar 31 02:52:40 PM PDT 24 |
12076582400 ps |
| T1099 |
/workspace/coverage/default/45.flash_ctrl_alert_test.3321563245 |
|
|
Mar 31 02:59:15 PM PDT 24 |
Mar 31 02:59:29 PM PDT 24 |
32393500 ps |
| T1100 |
/workspace/coverage/default/1.flash_ctrl_intr_wr.1976469087 |
|
|
Mar 31 02:48:11 PM PDT 24 |
Mar 31 02:50:02 PM PDT 24 |
40549275300 ps |
| T1101 |
/workspace/coverage/default/7.flash_ctrl_ro.612818416 |
|
|
Mar 31 02:51:26 PM PDT 24 |
Mar 31 02:53:23 PM PDT 24 |
568043000 ps |
| T1102 |
/workspace/coverage/default/1.flash_ctrl_rw_evict.2470447145 |
|
|
Mar 31 02:48:17 PM PDT 24 |
Mar 31 02:48:49 PM PDT 24 |
83589200 ps |
| T1103 |
/workspace/coverage/default/44.flash_ctrl_smoke.3714295774 |
|
|
Mar 31 02:59:06 PM PDT 24 |
Mar 31 03:02:44 PM PDT 24 |
103250900 ps |
| T1104 |
/workspace/coverage/default/17.flash_ctrl_mp_regions.4084723622 |
|
|
Mar 31 02:55:05 PM PDT 24 |
Mar 31 03:09:42 PM PDT 24 |
46063989700 ps |
| T1105 |
/workspace/coverage/default/6.flash_ctrl_error_prog_win.699257767 |
|
|
Mar 31 02:50:55 PM PDT 24 |
Mar 31 03:05:06 PM PDT 24 |
5157220500 ps |
| T1106 |
/workspace/coverage/default/0.flash_ctrl_rw_serr.2848508270 |
|
|
Mar 31 02:47:55 PM PDT 24 |
Mar 31 02:57:05 PM PDT 24 |
8005079300 ps |
| T1107 |
/workspace/coverage/default/0.flash_ctrl_rd_intg.2196053930 |
|
|
Mar 31 02:48:01 PM PDT 24 |
Mar 31 02:48:33 PM PDT 24 |
115227100 ps |
| T1108 |
/workspace/coverage/default/46.flash_ctrl_sec_info_access.2048704014 |
|
|
Mar 31 02:59:19 PM PDT 24 |
Mar 31 03:00:33 PM PDT 24 |
2636955400 ps |
| T1109 |
/workspace/coverage/default/6.flash_ctrl_rw_derr.1846671525 |
|
|
Mar 31 02:51:01 PM PDT 24 |
Mar 31 03:00:06 PM PDT 24 |
3753153000 ps |
| T1110 |
/workspace/coverage/default/36.flash_ctrl_intr_rd.3164007332 |
|
|
Mar 31 02:58:23 PM PDT 24 |
Mar 31 03:02:01 PM PDT 24 |
5539202400 ps |
| T1111 |
/workspace/coverage/default/26.flash_ctrl_sec_info_access.2962641488 |
|
|
Mar 31 02:57:06 PM PDT 24 |
Mar 31 02:58:24 PM PDT 24 |
3588204100 ps |
| T1112 |
/workspace/coverage/default/18.flash_ctrl_invalid_op.544867195 |
|
|
Mar 31 02:55:23 PM PDT 24 |
Mar 31 02:56:51 PM PDT 24 |
1945162000 ps |
| T1113 |
/workspace/coverage/default/1.flash_ctrl_rw.1203642152 |
|
|
Mar 31 02:48:07 PM PDT 24 |
Mar 31 02:57:59 PM PDT 24 |
31024123000 ps |
| T1114 |
/workspace/coverage/default/29.flash_ctrl_rw_evict_all_en.97079943 |
|
|
Mar 31 02:57:26 PM PDT 24 |
Mar 31 02:57:57 PM PDT 24 |
126183200 ps |
| T1115 |
/workspace/coverage/default/18.flash_ctrl_re_evict.2475330198 |
|
|
Mar 31 02:55:36 PM PDT 24 |
Mar 31 02:56:09 PM PDT 24 |
144332600 ps |
| T1116 |
/workspace/coverage/default/8.flash_ctrl_rw_evict_all_en.4187224786 |
|
|
Mar 31 02:51:53 PM PDT 24 |
Mar 31 02:52:25 PM PDT 24 |
327964000 ps |
| T1117 |
/workspace/coverage/default/3.flash_ctrl_wo.2969882643 |
|
|
Mar 31 02:49:17 PM PDT 24 |
Mar 31 02:51:55 PM PDT 24 |
6694829600 ps |
| T1118 |
/workspace/coverage/default/0.flash_ctrl_error_mp.2570566638 |
|
|
Mar 31 02:47:46 PM PDT 24 |
Mar 31 03:23:04 PM PDT 24 |
1966960900 ps |
| T1119 |
/workspace/coverage/default/32.flash_ctrl_rw_evict_all_en.1341646235 |
|
|
Mar 31 02:57:51 PM PDT 24 |
Mar 31 02:58:23 PM PDT 24 |
43205600 ps |
| T1120 |
/workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.1360325269 |
|
|
Mar 31 02:53:14 PM PDT 24 |
Mar 31 02:53:46 PM PDT 24 |
39447900 ps |
| T1121 |
/workspace/coverage/default/31.flash_ctrl_alert_test.1567405122 |
|
|
Mar 31 02:57:44 PM PDT 24 |
Mar 31 02:57:57 PM PDT 24 |
53378600 ps |
| T1122 |
/workspace/coverage/default/35.flash_ctrl_rw_evict_all_en.3481453623 |
|
|
Mar 31 02:58:16 PM PDT 24 |
Mar 31 02:58:49 PM PDT 24 |
72054800 ps |
| T1123 |
/workspace/coverage/default/35.flash_ctrl_smoke.969225421 |
|
|
Mar 31 02:58:09 PM PDT 24 |
Mar 31 03:00:36 PM PDT 24 |
684909100 ps |
| T1124 |
/workspace/coverage/default/18.flash_ctrl_lcmgr_intg.716449580 |
|
|
Mar 31 02:55:38 PM PDT 24 |
Mar 31 02:55:51 PM PDT 24 |
49431500 ps |
| T256 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.1820556479 |
|
|
Mar 31 12:29:31 PM PDT 24 |
Mar 31 12:29:45 PM PDT 24 |
49115400 ps |
| T40 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1299039391 |
|
|
Mar 31 12:29:36 PM PDT 24 |
Mar 31 12:29:51 PM PDT 24 |
62997800 ps |
| T257 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.344718091 |
|
|
Mar 31 12:29:44 PM PDT 24 |
Mar 31 12:29:57 PM PDT 24 |
43708400 ps |
| T258 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.1378677219 |
|
|
Mar 31 12:29:08 PM PDT 24 |
Mar 31 12:29:22 PM PDT 24 |
29964500 ps |
| T41 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.396483253 |
|
|
Mar 31 12:29:16 PM PDT 24 |
Mar 31 12:29:31 PM PDT 24 |
110358300 ps |
| T320 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.2736478822 |
|
|
Mar 31 12:29:37 PM PDT 24 |
Mar 31 12:29:50 PM PDT 24 |
16705400 ps |
| T42 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.289937647 |
|
|
Mar 31 12:29:39 PM PDT 24 |
Mar 31 12:44:26 PM PDT 24 |
654399300 ps |
| T1125 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2620338243 |
|
|
Mar 31 12:29:35 PM PDT 24 |
Mar 31 12:29:49 PM PDT 24 |
32730300 ps |
| T193 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3457904125 |
|
|
Mar 31 12:29:43 PM PDT 24 |
Mar 31 12:30:08 PM PDT 24 |
203764200 ps |
| T243 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3335699736 |
|
|
Mar 31 12:28:58 PM PDT 24 |
Mar 31 12:29:18 PM PDT 24 |
61395000 ps |
| T194 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.784346425 |
|
|
Mar 31 12:29:23 PM PDT 24 |
Mar 31 12:29:42 PM PDT 24 |
274182500 ps |
| T319 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.481820454 |
|
|
Mar 31 12:29:43 PM PDT 24 |
Mar 31 12:29:56 PM PDT 24 |
54555600 ps |
| T1126 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.1331029699 |
|
|
Mar 31 12:29:05 PM PDT 24 |
Mar 31 12:29:23 PM PDT 24 |
16258200 ps |
| T1127 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.964160554 |
|
|
Mar 31 12:29:21 PM PDT 24 |
Mar 31 12:29:34 PM PDT 24 |
193467900 ps |
| T195 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.868594265 |
|
|
Mar 31 12:29:24 PM PDT 24 |
Mar 31 12:29:40 PM PDT 24 |
48562700 ps |
| T1128 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1131768385 |
|
|
Mar 31 12:29:40 PM PDT 24 |
Mar 31 12:29:56 PM PDT 24 |
23818300 ps |
| T229 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.165750690 |
|
|
Mar 31 12:29:16 PM PDT 24 |
Mar 31 12:29:34 PM PDT 24 |
24676400 ps |
| T196 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.3288459603 |
|
|
Mar 31 12:29:28 PM PDT 24 |
Mar 31 12:44:10 PM PDT 24 |
348620200 ps |
| T322 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3371736423 |
|
|
Mar 31 12:29:43 PM PDT 24 |
Mar 31 12:29:56 PM PDT 24 |
48997300 ps |
| T244 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3453876603 |
|
|
Mar 31 12:29:37 PM PDT 24 |
Mar 31 12:29:56 PM PDT 24 |
106812900 ps |
| T323 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.3242378428 |
|
|
Mar 31 12:29:38 PM PDT 24 |
Mar 31 12:29:52 PM PDT 24 |
47692100 ps |
| T1129 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.2676134865 |
|
|
Mar 31 12:29:39 PM PDT 24 |
Mar 31 12:29:54 PM PDT 24 |
19821400 ps |
| T245 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2961661007 |
|
|
Mar 31 12:29:40 PM PDT 24 |
Mar 31 12:29:56 PM PDT 24 |
71605000 ps |
| T1130 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2883558957 |
|
|
Mar 31 12:29:20 PM PDT 24 |
Mar 31 12:29:34 PM PDT 24 |
13500400 ps |
| T295 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.2956134648 |
|
|
Mar 31 12:29:11 PM PDT 24 |
Mar 31 12:29:41 PM PDT 24 |
144640800 ps |
| T1131 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.551939190 |
|
|
Mar 31 12:29:43 PM PDT 24 |
Mar 31 12:29:57 PM PDT 24 |
17224500 ps |
| T321 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.3008980057 |
|
|
Mar 31 12:29:29 PM PDT 24 |
Mar 31 12:29:43 PM PDT 24 |
30731300 ps |
| T1132 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.2425231306 |
|
|
Mar 31 12:29:46 PM PDT 24 |
Mar 31 12:30:00 PM PDT 24 |
18412200 ps |
| T1133 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.4071242920 |
|
|
Mar 31 12:29:27 PM PDT 24 |
Mar 31 12:29:42 PM PDT 24 |
11406400 ps |
| T296 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1436443928 |
|
|
Mar 31 12:29:02 PM PDT 24 |
Mar 31 12:29:19 PM PDT 24 |
124031800 ps |
| T1134 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.2200277455 |
|
|
Mar 31 12:29:02 PM PDT 24 |
Mar 31 12:29:15 PM PDT 24 |
16947900 ps |
| T1135 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.2398380840 |
|
|
Mar 31 12:29:43 PM PDT 24 |
Mar 31 12:30:02 PM PDT 24 |
61712700 ps |
| T197 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.1931779494 |
|
|
Mar 31 12:29:36 PM PDT 24 |
Mar 31 12:29:55 PM PDT 24 |
52490900 ps |
| T1136 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.4263345785 |
|
|
Mar 31 12:29:28 PM PDT 24 |
Mar 31 12:29:43 PM PDT 24 |
18794200 ps |
| T1137 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3851526608 |
|
|
Mar 31 12:29:26 PM PDT 24 |
Mar 31 12:29:39 PM PDT 24 |
33326700 ps |
| T1138 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.3472091862 |
|
|
Mar 31 12:29:32 PM PDT 24 |
Mar 31 12:29:46 PM PDT 24 |
52145600 ps |
| T1139 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.3683283916 |
|
|
Mar 31 12:29:34 PM PDT 24 |
Mar 31 12:29:53 PM PDT 24 |
384099300 ps |
| T1140 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.811408846 |
|
|
Mar 31 12:28:59 PM PDT 24 |
Mar 31 12:29:13 PM PDT 24 |
21199800 ps |
| T1141 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.3914879406 |
|
|
Mar 31 12:29:44 PM PDT 24 |
Mar 31 12:29:57 PM PDT 24 |
27939400 ps |
| T198 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.2916628254 |
|
|
Mar 31 12:29:30 PM PDT 24 |
Mar 31 12:29:46 PM PDT 24 |
124731000 ps |
| T363 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.2008780745 |
|
|
Mar 31 12:29:36 PM PDT 24 |
Mar 31 12:30:28 PM PDT 24 |
836078200 ps |
| T249 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.2190306641 |
|
|
Mar 31 12:29:26 PM PDT 24 |
Mar 31 12:35:52 PM PDT 24 |
424792700 ps |
| T1142 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.3445796409 |
|
|
Mar 31 12:29:30 PM PDT 24 |
Mar 31 12:29:47 PM PDT 24 |
233339500 ps |
| T297 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.3945721405 |
|
|
Mar 31 12:28:53 PM PDT 24 |
Mar 31 12:29:32 PM PDT 24 |
3212806500 ps |
| T298 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.2048370154 |
|
|
Mar 31 12:29:43 PM PDT 24 |
Mar 31 12:29:58 PM PDT 24 |
283126400 ps |
| T1143 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.1975249887 |
|
|
Mar 31 12:29:50 PM PDT 24 |
Mar 31 12:30:03 PM PDT 24 |
17828000 ps |
| T230 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2307869757 |
|
|
Mar 31 12:29:13 PM PDT 24 |
Mar 31 12:29:28 PM PDT 24 |
29880600 ps |
| T1144 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.589932846 |
|
|
Mar 31 12:29:43 PM PDT 24 |
Mar 31 12:29:56 PM PDT 24 |
17062900 ps |
| T1145 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2311274089 |
|
|
Mar 31 12:29:20 PM PDT 24 |
Mar 31 12:29:36 PM PDT 24 |
15038900 ps |
| T1146 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.2056342685 |
|
|
Mar 31 12:29:05 PM PDT 24 |
Mar 31 12:29:19 PM PDT 24 |
16541400 ps |
| T1147 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.2227267150 |
|
|
Mar 31 12:29:40 PM PDT 24 |
Mar 31 12:29:54 PM PDT 24 |
59330900 ps |
| T252 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1876129191 |
|
|
Mar 31 12:29:19 PM PDT 24 |
Mar 31 12:29:38 PM PDT 24 |
63537100 ps |
| T1148 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.1923835092 |
|
|
Mar 31 12:29:30 PM PDT 24 |
Mar 31 12:29:45 PM PDT 24 |
264855300 ps |
| T1149 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.353521475 |
|
|
Mar 31 12:29:17 PM PDT 24 |
Mar 31 12:30:06 PM PDT 24 |
2390806300 ps |
| T1150 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.4002260678 |
|
|
Mar 31 12:29:28 PM PDT 24 |
Mar 31 12:29:41 PM PDT 24 |
12644400 ps |
| T1151 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.975074877 |
|
|
Mar 31 12:29:24 PM PDT 24 |
Mar 31 12:29:39 PM PDT 24 |
20103200 ps |
| T1152 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.2651602811 |
|
|
Mar 31 12:29:02 PM PDT 24 |
Mar 31 12:30:19 PM PDT 24 |
2235371100 ps |
| T1153 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.4143245183 |
|
|
Mar 31 12:29:15 PM PDT 24 |
Mar 31 12:29:32 PM PDT 24 |
32544500 ps |
| T299 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3878559270 |
|
|
Mar 31 12:29:26 PM PDT 24 |
Mar 31 12:35:50 PM PDT 24 |
612952400 ps |
| T263 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.3521254554 |
|
|
Mar 31 12:29:29 PM PDT 24 |
Mar 31 12:37:07 PM PDT 24 |
514620200 ps |
| T271 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3526655789 |
|
|
Mar 31 12:29:13 PM PDT 24 |
Mar 31 12:29:31 PM PDT 24 |
93282200 ps |
| T253 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.1406375664 |
|
|
Mar 31 12:29:39 PM PDT 24 |
Mar 31 12:29:55 PM PDT 24 |
56145000 ps |
| T260 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.4052642422 |
|
|
Mar 31 12:29:19 PM PDT 24 |
Mar 31 12:29:35 PM PDT 24 |
34875900 ps |
| T1154 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1623480333 |
|
|
Mar 31 12:29:39 PM PDT 24 |
Mar 31 12:29:53 PM PDT 24 |
14477300 ps |
| T300 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3617280298 |
|
|
Mar 31 12:29:26 PM PDT 24 |
Mar 31 12:29:42 PM PDT 24 |
401306800 ps |
| T1155 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.904634127 |
|
|
Mar 31 12:29:22 PM PDT 24 |
Mar 31 12:30:07 PM PDT 24 |
87036100 ps |
| T1156 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.351034013 |
|
|
Mar 31 12:29:30 PM PDT 24 |
Mar 31 12:29:46 PM PDT 24 |
34670500 ps |
| T1157 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.1291268922 |
|
|
Mar 31 12:29:40 PM PDT 24 |
Mar 31 12:29:57 PM PDT 24 |
54084200 ps |
| T1158 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.4158221321 |
|
|
Mar 31 12:29:37 PM PDT 24 |
Mar 31 12:29:50 PM PDT 24 |
58048400 ps |
| T1159 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.239191925 |
|
|
Mar 31 12:29:32 PM PDT 24 |
Mar 31 12:29:46 PM PDT 24 |
40411000 ps |
| T1160 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.3045121492 |
|
|
Mar 31 12:28:58 PM PDT 24 |
Mar 31 12:29:14 PM PDT 24 |
10960200 ps |
| T267 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1237479775 |
|
|
Mar 31 12:29:37 PM PDT 24 |
Mar 31 12:44:26 PM PDT 24 |
1351311100 ps |
| T231 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3735495987 |
|
|
Mar 31 12:29:18 PM PDT 24 |
Mar 31 12:29:32 PM PDT 24 |
18242000 ps |
| T1161 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1641319767 |
|
|
Mar 31 12:29:00 PM PDT 24 |
Mar 31 12:29:46 PM PDT 24 |
79099800 ps |
| T1162 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.1618389596 |
|
|
Mar 31 12:29:46 PM PDT 24 |
Mar 31 12:30:00 PM PDT 24 |
56595700 ps |
| T1163 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3151458143 |
|
|
Mar 31 12:29:40 PM PDT 24 |
Mar 31 12:29:55 PM PDT 24 |
14887100 ps |
| T1164 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.2149496627 |
|
|
Mar 31 12:29:14 PM PDT 24 |
Mar 31 12:29:27 PM PDT 24 |
28217300 ps |
| T254 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.365816703 |
|
|
Mar 31 12:29:26 PM PDT 24 |
Mar 31 12:29:44 PM PDT 24 |
169671100 ps |
| T265 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1094962152 |
|
|
Mar 31 12:29:32 PM PDT 24 |
Mar 31 12:37:08 PM PDT 24 |
702101100 ps |
| T1165 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.531807116 |
|
|
Mar 31 12:29:43 PM PDT 24 |
Mar 31 12:29:59 PM PDT 24 |
18521500 ps |
| T1166 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.464243408 |
|
|
Mar 31 12:29:21 PM PDT 24 |
Mar 31 12:29:35 PM PDT 24 |
14413200 ps |
| T301 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.496287760 |
|
|
Mar 31 12:28:55 PM PDT 24 |
Mar 31 12:41:25 PM PDT 24 |
9677129900 ps |
| T1167 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2445943814 |
|
|
Mar 31 12:29:40 PM PDT 24 |
Mar 31 12:29:54 PM PDT 24 |
52564800 ps |
| T1168 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.21905184 |
|
|
Mar 31 12:29:42 PM PDT 24 |
Mar 31 12:29:55 PM PDT 24 |
52284800 ps |
| T1169 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.4026377032 |
|
|
Mar 31 12:29:39 PM PDT 24 |
Mar 31 12:29:52 PM PDT 24 |
90876600 ps |
| T1170 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.1824246611 |
|
|
Mar 31 12:29:20 PM PDT 24 |
Mar 31 12:29:34 PM PDT 24 |
14644200 ps |
| T1171 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.3726538936 |
|
|
Mar 31 12:29:40 PM PDT 24 |
Mar 31 12:30:00 PM PDT 24 |
450171900 ps |
| T262 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3064595131 |
|
|
Mar 31 12:29:03 PM PDT 24 |
Mar 31 12:43:57 PM PDT 24 |
1407216100 ps |
| T1172 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.1376892775 |
|
|
Mar 31 12:29:38 PM PDT 24 |
Mar 31 12:29:52 PM PDT 24 |
16498900 ps |
| T1173 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.2169510979 |
|
|
Mar 31 12:29:39 PM PDT 24 |
Mar 31 12:29:53 PM PDT 24 |
15839300 ps |
| T1174 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.2122410905 |
|
|
Mar 31 12:29:41 PM PDT 24 |
Mar 31 12:29:55 PM PDT 24 |
30427000 ps |
| T261 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.3279216567 |
|
|
Mar 31 12:29:27 PM PDT 24 |
Mar 31 12:35:46 PM PDT 24 |
1547994300 ps |
| T354 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.3182511461 |
|
|
Mar 31 12:29:31 PM PDT 24 |
Mar 31 12:44:07 PM PDT 24 |
731553800 ps |
| T1175 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.3735953005 |
|
|
Mar 31 12:29:34 PM PDT 24 |
Mar 31 12:29:47 PM PDT 24 |
29729700 ps |
| T1176 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.1461878724 |
|
|
Mar 31 12:29:15 PM PDT 24 |
Mar 31 12:29:29 PM PDT 24 |
51622700 ps |
| T1177 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.1382325720 |
|
|
Mar 31 12:29:11 PM PDT 24 |
Mar 31 12:29:27 PM PDT 24 |
28439500 ps |
| T255 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.865846703 |
|
|
Mar 31 12:29:33 PM PDT 24 |
Mar 31 12:29:53 PM PDT 24 |
246244400 ps |
| T232 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1621845575 |
|
|
Mar 31 12:28:57 PM PDT 24 |
Mar 31 12:29:10 PM PDT 24 |
66437600 ps |
| T1178 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2401339287 |
|
|
Mar 31 12:29:42 PM PDT 24 |
Mar 31 12:29:55 PM PDT 24 |
12531900 ps |
| T1179 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3675568179 |
|
|
Mar 31 12:29:26 PM PDT 24 |
Mar 31 12:29:44 PM PDT 24 |
975024200 ps |
| T1180 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.458195148 |
|
|
Mar 31 12:29:26 PM PDT 24 |
Mar 31 12:29:47 PM PDT 24 |
172440600 ps |
| T1181 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1058844160 |
|
|
Mar 31 12:29:21 PM PDT 24 |
Mar 31 12:29:56 PM PDT 24 |
1128600400 ps |
| T1182 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.4096988191 |
|
|
Mar 31 12:29:34 PM PDT 24 |
Mar 31 12:29:51 PM PDT 24 |
39821200 ps |
| T1183 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.3640307457 |
|
|
Mar 31 12:29:20 PM PDT 24 |
Mar 31 12:29:34 PM PDT 24 |
44525600 ps |
| T1184 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.2643830236 |
|
|
Mar 31 12:29:22 PM PDT 24 |
Mar 31 12:29:38 PM PDT 24 |
24651100 ps |
| T1185 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.46056573 |
|
|
Mar 31 12:29:19 PM PDT 24 |
Mar 31 12:29:35 PM PDT 24 |
18288900 ps |
| T1186 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.750635138 |
|
|
Mar 31 12:29:35 PM PDT 24 |
Mar 31 12:29:53 PM PDT 24 |
48753700 ps |
| T1187 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.2265493465 |
|
|
Mar 31 12:29:44 PM PDT 24 |
Mar 31 12:29:58 PM PDT 24 |
15442000 ps |
| T1188 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.99836327 |
|
|
Mar 31 12:29:16 PM PDT 24 |
Mar 31 12:29:57 PM PDT 24 |
3576512300 ps |
| T266 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.346885869 |
|
|
Mar 31 12:29:29 PM PDT 24 |
Mar 31 12:29:49 PM PDT 24 |
84461400 ps |
| T1189 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.1941148509 |
|
|
Mar 31 12:29:22 PM PDT 24 |
Mar 31 12:29:36 PM PDT 24 |
14866800 ps |
| T1190 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.36615437 |
|
|
Mar 31 12:29:26 PM PDT 24 |
Mar 31 12:29:39 PM PDT 24 |
95114700 ps |
| T361 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3079430416 |
|
|
Mar 31 12:29:34 PM PDT 24 |
Mar 31 12:41:56 PM PDT 24 |
3065900500 ps |
| T1191 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3783807199 |
|
|
Mar 31 12:29:10 PM PDT 24 |
Mar 31 12:29:28 PM PDT 24 |
41561000 ps |
| T1192 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3525514588 |
|
|
Mar 31 12:29:28 PM PDT 24 |
Mar 31 12:29:44 PM PDT 24 |
30777400 ps |
| T1193 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.2253209476 |
|
|
Mar 31 12:29:30 PM PDT 24 |
Mar 31 12:29:45 PM PDT 24 |
16691000 ps |
| T1194 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.2527122229 |
|
|
Mar 31 12:29:44 PM PDT 24 |
Mar 31 12:29:58 PM PDT 24 |
14884200 ps |
| T1195 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1349968030 |
|
|
Mar 31 12:29:16 PM PDT 24 |
Mar 31 12:29:33 PM PDT 24 |
34564100 ps |
| T1196 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.851799810 |
|
|
Mar 31 12:29:15 PM PDT 24 |
Mar 31 12:29:28 PM PDT 24 |
16884600 ps |
| T233 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.4201498915 |
|
|
Mar 31 12:28:53 PM PDT 24 |
Mar 31 12:29:08 PM PDT 24 |
16195600 ps |
| T1197 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.4255923358 |
|
|
Mar 31 12:29:05 PM PDT 24 |
Mar 31 12:29:18 PM PDT 24 |
50990800 ps |
| T1198 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.4097508098 |
|
|
Mar 31 12:29:20 PM PDT 24 |
Mar 31 12:29:57 PM PDT 24 |
25658000 ps |
| T1199 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.2248762686 |
|
|
Mar 31 12:29:26 PM PDT 24 |
Mar 31 12:29:44 PM PDT 24 |
133388800 ps |
| T1200 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.1356509652 |
|
|
Mar 31 12:28:51 PM PDT 24 |
Mar 31 12:29:04 PM PDT 24 |
27316000 ps |
| T1201 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.205111631 |
|
|
Mar 31 12:29:31 PM PDT 24 |
Mar 31 12:29:48 PM PDT 24 |
27714800 ps |
| T1202 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.4084502477 |
|
|
Mar 31 12:29:33 PM PDT 24 |
Mar 31 12:29:50 PM PDT 24 |
26233300 ps |
| T1203 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.80641580 |
|
|
Mar 31 12:29:30 PM PDT 24 |
Mar 31 12:29:43 PM PDT 24 |
13374500 ps |
| T1204 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.897530010 |
|
|
Mar 31 12:29:37 PM PDT 24 |
Mar 31 12:29:50 PM PDT 24 |
29335900 ps |
| T259 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.579511223 |
|
|
Mar 31 12:29:38 PM PDT 24 |
Mar 31 12:29:55 PM PDT 24 |
339088900 ps |
| T357 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.2868464699 |
|
|
Mar 31 12:29:18 PM PDT 24 |
Mar 31 12:36:55 PM PDT 24 |
189458000 ps |
| T1205 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1592254035 |
|
|
Mar 31 12:28:54 PM PDT 24 |
Mar 31 12:29:08 PM PDT 24 |
14171200 ps |
| T1206 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.1854523261 |
|
|
Mar 31 12:29:25 PM PDT 24 |
Mar 31 12:29:41 PM PDT 24 |
34681500 ps |
| T355 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.362598162 |
|
|
Mar 31 12:29:35 PM PDT 24 |
Mar 31 12:37:10 PM PDT 24 |
1698494600 ps |
| T1207 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2725169775 |
|
|
Mar 31 12:28:57 PM PDT 24 |
Mar 31 12:29:12 PM PDT 24 |
47660900 ps |
| T302 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.2109035182 |
|
|
Mar 31 12:29:25 PM PDT 24 |
Mar 31 12:30:00 PM PDT 24 |
217761600 ps |
| T1208 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.1795130792 |
|
|
Mar 31 12:29:34 PM PDT 24 |
Mar 31 12:29:49 PM PDT 24 |
22361400 ps |
| T268 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.4085990752 |
|
|
Mar 31 12:29:32 PM PDT 24 |
Mar 31 12:29:52 PM PDT 24 |
208516300 ps |
| T1209 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1544083275 |
|
|
Mar 31 12:29:24 PM PDT 24 |
Mar 31 12:29:41 PM PDT 24 |
158495900 ps |
| T1210 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.2865305312 |
|
|
Mar 31 12:29:42 PM PDT 24 |
Mar 31 12:30:01 PM PDT 24 |
68584100 ps |
| T358 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2491706994 |
|
|
Mar 31 12:28:59 PM PDT 24 |
Mar 31 12:41:24 PM PDT 24 |
4243470900 ps |
| T303 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1681059307 |
|
|
Mar 31 12:29:27 PM PDT 24 |
Mar 31 12:29:47 PM PDT 24 |
651185000 ps |
| T356 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.468272235 |
|
|
Mar 31 12:29:25 PM PDT 24 |
Mar 31 12:44:01 PM PDT 24 |
2210837000 ps |
| T304 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1622418863 |
|
|
Mar 31 12:29:21 PM PDT 24 |
Mar 31 12:29:37 PM PDT 24 |
118823200 ps |
| T1211 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3506566753 |
|
|
Mar 31 12:29:29 PM PDT 24 |
Mar 31 12:29:46 PM PDT 24 |
348216500 ps |
| T1212 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.127950336 |
|
|
Mar 31 12:29:05 PM PDT 24 |
Mar 31 12:29:22 PM PDT 24 |
77593900 ps |
| T1213 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.889637190 |
|
|
Mar 31 12:29:41 PM PDT 24 |
Mar 31 12:29:55 PM PDT 24 |
27112300 ps |
| T1214 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2807059596 |
|
|
Mar 31 12:29:27 PM PDT 24 |
Mar 31 12:29:41 PM PDT 24 |
63742700 ps |
| T1215 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.2607883445 |
|
|
Mar 31 12:29:18 PM PDT 24 |
Mar 31 12:29:36 PM PDT 24 |
118975300 ps |
| T1216 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.2340955193 |
|
|
Mar 31 12:29:33 PM PDT 24 |
Mar 31 12:29:47 PM PDT 24 |
24032500 ps |
| T1217 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.3448980024 |
|
|
Mar 31 12:29:28 PM PDT 24 |
Mar 31 12:29:44 PM PDT 24 |
82521400 ps |
| T234 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1825795635 |
|
|
Mar 31 12:29:15 PM PDT 24 |
Mar 31 12:29:29 PM PDT 24 |
32946600 ps |
| T1218 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.2560599361 |
|
|
Mar 31 12:29:39 PM PDT 24 |
Mar 31 12:29:53 PM PDT 24 |
14745400 ps |
| T1219 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.2054852904 |
|
|
Mar 31 12:29:15 PM PDT 24 |
Mar 31 12:29:28 PM PDT 24 |
24608200 ps |
| T1220 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.1941083261 |
|
|
Mar 31 12:29:23 PM PDT 24 |
Mar 31 12:29:57 PM PDT 24 |
331331600 ps |
| T269 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.316506705 |
|
|
Mar 31 12:29:36 PM PDT 24 |
Mar 31 12:29:53 PM PDT 24 |
109159800 ps |
| T353 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.4243685373 |
|
|
Mar 31 12:29:24 PM PDT 24 |
Mar 31 12:29:40 PM PDT 24 |
107461000 ps |
| T1221 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.1407916121 |
|
|
Mar 31 12:29:41 PM PDT 24 |
Mar 31 12:29:54 PM PDT 24 |
50343300 ps |
| T359 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.2104236063 |
|
|
Mar 31 12:29:29 PM PDT 24 |
Mar 31 12:44:13 PM PDT 24 |
1268281100 ps |
| T1222 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2089176763 |
|
|
Mar 31 12:29:16 PM PDT 24 |
Mar 31 12:29:51 PM PDT 24 |
30526000 ps |
| T1223 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.2014466424 |
|
|
Mar 31 12:29:43 PM PDT 24 |
Mar 31 12:29:57 PM PDT 24 |
52465100 ps |
| T1224 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.3474453999 |
|
|
Mar 31 12:29:27 PM PDT 24 |
Mar 31 12:29:46 PM PDT 24 |
45176300 ps |
| T1225 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.4116828828 |
|
|
Mar 31 12:29:30 PM PDT 24 |
Mar 31 12:29:44 PM PDT 24 |
29036500 ps |
| T1226 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3964562284 |
|
|
Mar 31 12:29:36 PM PDT 24 |
Mar 31 12:30:07 PM PDT 24 |
843354300 ps |
| T1227 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.667058111 |
|
|
Mar 31 12:29:27 PM PDT 24 |
Mar 31 12:29:43 PM PDT 24 |
46170000 ps |
| T1228 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.3181431477 |
|
|
Mar 31 12:29:25 PM PDT 24 |
Mar 31 12:29:39 PM PDT 24 |
12818000 ps |
| T1229 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.2994061633 |
|
|
Mar 31 12:29:43 PM PDT 24 |
Mar 31 12:29:57 PM PDT 24 |
83989800 ps |
| T1230 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3299931475 |
|
|
Mar 31 12:29:17 PM PDT 24 |
Mar 31 12:29:32 PM PDT 24 |
38258900 ps |
| T264 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3473187418 |
|
|
Mar 31 12:28:56 PM PDT 24 |
Mar 31 12:29:13 PM PDT 24 |
258399500 ps |
| T1231 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.3864327103 |
|
|
Mar 31 12:29:27 PM PDT 24 |
Mar 31 12:29:40 PM PDT 24 |
102101100 ps |
| T360 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.597500710 |
|
|
Mar 31 12:29:27 PM PDT 24 |
Mar 31 12:42:06 PM PDT 24 |
4114383600 ps |
| T1232 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1984140127 |
|
|
Mar 31 12:29:29 PM PDT 24 |
Mar 31 12:29:45 PM PDT 24 |
22008100 ps |
| T1233 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1419650482 |
|
|
Mar 31 12:29:32 PM PDT 24 |
Mar 31 12:29:49 PM PDT 24 |
219841200 ps |
| T270 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2606368423 |
|
|
Mar 31 12:29:33 PM PDT 24 |
Mar 31 12:29:52 PM PDT 24 |
90202900 ps |
| T1234 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.3813770628 |
|
|
Mar 31 12:28:54 PM PDT 24 |
Mar 31 12:29:11 PM PDT 24 |
397597800 ps |
| T1235 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.897942627 |
|
|
Mar 31 12:29:27 PM PDT 24 |
Mar 31 12:29:43 PM PDT 24 |
55086900 ps |
| T1236 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.1475690694 |
|
|
Mar 31 12:29:03 PM PDT 24 |
Mar 31 12:29:16 PM PDT 24 |
51577800 ps |
| T1237 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.4092953578 |
|
|
Mar 31 12:29:26 PM PDT 24 |
Mar 31 12:29:43 PM PDT 24 |
40397900 ps |
| T1238 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.397053026 |
|
|
Mar 31 12:29:44 PM PDT 24 |
Mar 31 12:29:57 PM PDT 24 |
51194100 ps |
| T1239 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.2828685293 |
|
|
Mar 31 12:29:29 PM PDT 24 |
Mar 31 12:29:43 PM PDT 24 |
84091300 ps |
| T1240 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.3509858180 |
|
|
Mar 31 12:29:06 PM PDT 24 |
Mar 31 12:29:20 PM PDT 24 |
57655800 ps |
| T362 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.1930840037 |
|
|
Mar 31 12:29:31 PM PDT 24 |
Mar 31 12:37:02 PM PDT 24 |
350201700 ps |
| T1241 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.1599415581 |
|
|
Mar 31 12:29:29 PM PDT 24 |
Mar 31 12:29:43 PM PDT 24 |
42407800 ps |
| T1242 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2616729765 |
|
|
Mar 31 12:29:18 PM PDT 24 |
Mar 31 12:30:20 PM PDT 24 |
5052191600 ps |
| T1243 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.3115260011 |
|
|
Mar 31 12:28:54 PM PDT 24 |
Mar 31 12:29:12 PM PDT 24 |
113511800 ps |
| T1244 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.2893848826 |
|
|
Mar 31 12:29:25 PM PDT 24 |
Mar 31 12:29:42 PM PDT 24 |
137876900 ps |
| T1245 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.2357238560 |
|
|
Mar 31 12:29:23 PM PDT 24 |
Mar 31 12:29:40 PM PDT 24 |
119690800 ps |
| T1246 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.3603091094 |
|
|
Mar 31 12:29:24 PM PDT 24 |
Mar 31 12:30:08 PM PDT 24 |
1519581000 ps |
| T1247 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.2110757786 |
|
|
Mar 31 12:29:28 PM PDT 24 |
Mar 31 12:29:45 PM PDT 24 |
129260400 ps |
| T1248 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.4089474831 |
|
|
Mar 31 12:29:30 PM PDT 24 |
Mar 31 12:29:44 PM PDT 24 |
45903300 ps |
| T1249 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3538742431 |
|
|
Mar 31 12:29:30 PM PDT 24 |
Mar 31 12:29:49 PM PDT 24 |
124803100 ps |
| T1250 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3920179544 |
|
|
Mar 31 12:29:05 PM PDT 24 |
Mar 31 12:29:20 PM PDT 24 |
30593300 ps |