Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	296376	1		T1	2		T2	1		T3	1
all_values[1]	296376	1		T1	2		T2	1		T3	1
all_values[2]	296376	1		T1	2		T2	1		T3	1
all_values[3]	296376	1		T1	2		T2	1		T3	1
all_values[4]	296376	1		T1	2		T2	1		T3	1
all_values[5]	296376	1		T1	2		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	599055	1		T1	12		T2	6		T3	6
auto[1]	1179201	1		T18	5284		T4	15664		T5	10168

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	870708	1		T1	7		T2	4		T3	4
auto[1]	907548	1		T1	5		T2	2		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	296221	1		T1	2		T2	1		T3	1
all_values[0]	auto[1]	auto[1]	155	1		T248	1		T249	7		T250	6
all_values[1]	auto[0]	auto[1]	296220	1		T1	2		T2	1		T3	1
all_values[1]	auto[1]	auto[1]	156	1		T248	2		T249	3		T250	3
all_values[2]	auto[0]	auto[0]	1596	1		T1	2		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	54	1		T248	1		T249	2		T299	2
all_values[2]	auto[1]	auto[0]	294670	1		T18	1321		T4	3916		T5	2542
all_values[2]	auto[1]	auto[1]	56	1		T248	1		T300	1		T299	1
all_values[3]	auto[0]	auto[0]	1606	1		T1	2		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	59	1		T249	3		T250	1		T300	2
all_values[3]	auto[1]	auto[0]	78168	1		T18	1321		T4	974		T5	1271
all_values[3]	auto[1]	auto[1]	216543	1		T4	2942		T5	1271		T30	1188
all_values[4]	auto[0]	auto[0]	1146	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	496	1		T1	1		T10	1		T15	1
all_values[4]	auto[1]	auto[0]	197344	1		T18	1		T4	2932		T5	1271
all_values[4]	auto[1]	auto[1]	97390	1		T18	1320		T4	984		T5	1271
all_values[5]	auto[0]	auto[0]	1516	1		T1	2		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	141	1		T6	1		T20	1		T34	1
all_values[5]	auto[1]	auto[0]	294662	1		T18	1321		T4	3916		T5	2542
all_values[5]	auto[1]	auto[1]	57	1		T248	2		T249	5		T250	1