Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
234 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
10 | 
 | 
T22 | 
14 | 
| others[1] | 
191 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
9 | 
 | 
T51 | 
1 | 
| others[2] | 
225 | 
1 | 
 | 
T24 | 
13 | 
 | 
T37 | 
1 | 
 | 
T22 | 
11 | 
| others[3] | 
357 | 
1 | 
 | 
T24 | 
9 | 
 | 
T6 | 
1 | 
 | 
T22 | 
21 | 
| false | 
110 | 
1 | 
 | 
T24 | 
8 | 
 | 
T22 | 
6 | 
 | 
T75 | 
2 | 
| true | 
12890 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
8332 | 
1 | 
 | 
T24 | 
22 | 
 | 
T113 | 
1 | 
 | 
T26 | 
12 | 
| others[1] | 
1219 | 
1 | 
 | 
T10 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
25 | 
| others[2] | 
1208 | 
1 | 
 | 
T18 | 
1 | 
 | 
T24 | 
20 | 
 | 
T26 | 
22 | 
| others[3] | 
2160 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
25 | 
 | 
T26 | 
31 | 
| false | 
655 | 
1 | 
 | 
T24 | 
9 | 
 | 
T26 | 
8 | 
 | 
T56 | 
12 | 
| true | 
433 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
8301 | 
1 | 
 | 
T15 | 
1 | 
 | 
T18 | 
1 | 
 | 
T24 | 
16 | 
| others[1] | 
1303 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
26 | 
 | 
T26 | 
22 | 
| others[2] | 
1240 | 
1 | 
 | 
T24 | 
22 | 
 | 
T26 | 
14 | 
 | 
T21 | 
3 | 
| others[3] | 
2081 | 
1 | 
 | 
T24 | 
28 | 
 | 
T26 | 
34 | 
 | 
T21 | 
6 | 
| false | 
666 | 
1 | 
 | 
T3 | 
1 | 
 | 
T24 | 
9 | 
 | 
T113 | 
1 | 
| true | 
416 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T14 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
104 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
6 | 
 | 
T37 | 
1 | 
| others[1] | 
99 | 
1 | 
 | 
T24 | 
5 | 
 | 
T37 | 
1 | 
 | 
T22 | 
6 | 
| others[2] | 
118 | 
1 | 
 | 
T24 | 
12 | 
 | 
T22 | 
5 | 
 | 
T75 | 
4 | 
| others[3] | 
169 | 
1 | 
 | 
T15 | 
1 | 
 | 
T55 | 
1 | 
 | 
T24 | 
7 | 
| false | 
49 | 
1 | 
 | 
T24 | 
2 | 
 | 
T22 | 
1 | 
 | 
T75 | 
2 | 
| true | 
13468 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
246 | 
1 | 
 | 
T24 | 
10 | 
 | 
T22 | 
6 | 
 | 
T75 | 
10 | 
| others[1] | 
233 | 
1 | 
 | 
T24 | 
10 | 
 | 
T33 | 
1 | 
 | 
T22 | 
14 | 
| others[2] | 
207 | 
1 | 
 | 
T24 | 
7 | 
 | 
T22 | 
7 | 
 | 
T75 | 
9 | 
| others[3] | 
391 | 
1 | 
 | 
T2 | 
1 | 
 | 
T4 | 
1 | 
 | 
T24 | 
22 | 
| false | 
128 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
6 | 
 | 
T22 | 
2 | 
| true | 
12802 | 
1 | 
 | 
T1 | 
1 | 
 | 
T3 | 
1 | 
 | 
T14 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
8088 | 
1 | 
 | 
T3 | 
1 | 
 | 
T15 | 
1 | 
 | 
T55 | 
1 | 
| others[1] | 
1113 | 
1 | 
 | 
T24 | 
17 | 
 | 
T26 | 
14 | 
 | 
T21 | 
2 | 
| others[2] | 
1049 | 
1 | 
 | 
T24 | 
20 | 
 | 
T26 | 
13 | 
 | 
T21 | 
3 | 
| others[3] | 
1838 | 
1 | 
 | 
T18 | 
1 | 
 | 
T24 | 
33 | 
 | 
T26 | 
17 | 
| false | 
552 | 
1 | 
 | 
T10 | 
1 | 
 | 
T15 | 
1 | 
 | 
T17 | 
1 | 
| true | 
1367 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T14 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
226 | 
1 | 
 | 
T24 | 
6 | 
 | 
T37 | 
1 | 
 | 
T22 | 
8 | 
| others[1] | 
244 | 
1 | 
 | 
T14 | 
1 | 
 | 
T24 | 
13 | 
 | 
T22 | 
9 | 
| others[2] | 
218 | 
1 | 
 | 
T24 | 
10 | 
 | 
T37 | 
1 | 
 | 
T22 | 
7 | 
| others[3] | 
365 | 
1 | 
 | 
T24 | 
16 | 
 | 
T28 | 
1 | 
 | 
T22 | 
11 | 
| false | 
118 | 
1 | 
 | 
T15 | 
1 | 
 | 
T55 | 
1 | 
 | 
T4 | 
1 | 
| true | 
12836 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
233 | 
1 | 
 | 
T24 | 
10 | 
 | 
T6 | 
1 | 
 | 
T51 | 
1 | 
| others[1] | 
235 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
13 | 
 | 
T22 | 
6 | 
| others[2] | 
208 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
6 | 
 | 
T22 | 
6 | 
| others[3] | 
352 | 
1 | 
 | 
T24 | 
12 | 
 | 
T22 | 
16 | 
 | 
T75 | 
18 | 
| false | 
110 | 
1 | 
 | 
T24 | 
2 | 
 | 
T22 | 
4 | 
 | 
T75 | 
3 | 
| true | 
12869 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
8278 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
19 | 
 | 
T26 | 
13 | 
| others[1] | 
1210 | 
1 | 
 | 
T14 | 
1 | 
 | 
T24 | 
14 | 
 | 
T26 | 
28 | 
| others[2] | 
1290 | 
1 | 
 | 
T24 | 
25 | 
 | 
T26 | 
21 | 
 | 
T21 | 
1 | 
| others[3] | 
2190 | 
1 | 
 | 
T3 | 
1 | 
 | 
T15 | 
1 | 
 | 
T18 | 
1 | 
| false | 
608 | 
1 | 
 | 
T24 | 
8 | 
 | 
T113 | 
1 | 
 | 
T26 | 
6 | 
| true | 
431 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T10 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1284 | 
1 | 
 | 
T24 | 
29 | 
 | 
T26 | 
14 | 
 | 
T56 | 
23 | 
| others[1] | 
1264 | 
1 | 
 | 
T15 | 
1 | 
 | 
T18 | 
1 | 
 | 
T24 | 
16 | 
| others[2] | 
1270 | 
1 | 
 | 
T24 | 
18 | 
 | 
T26 | 
20 | 
 | 
T21 | 
2 | 
| others[3] | 
2087 | 
1 | 
 | 
T24 | 
30 | 
 | 
T113 | 
1 | 
 | 
T26 | 
32 | 
| false | 
626 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
8 | 
 | 
T26 | 
7 | 
| true | 
424 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
97 | 
1 | 
 | 
T24 | 
2 | 
 | 
T22 | 
5 | 
 | 
T75 | 
5 | 
| others[1] | 
111 | 
1 | 
 | 
T24 | 
7 | 
 | 
T37 | 
1 | 
 | 
T22 | 
4 | 
| others[2] | 
96 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
2 | 
 | 
T22 | 
3 | 
| others[3] | 
182 | 
1 | 
 | 
T24 | 
6 | 
 | 
T37 | 
1 | 
 | 
T22 | 
4 | 
| false | 
60 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
3 | 
 | 
T22 | 
2 | 
| true | 
6409 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
238 | 
1 | 
 | 
T55 | 
1 | 
 | 
T4 | 
1 | 
 | 
T24 | 
10 | 
| others[1] | 
258 | 
1 | 
 | 
T24 | 
6 | 
 | 
T22 | 
11 | 
 | 
T75 | 
18 | 
| others[2] | 
240 | 
1 | 
 | 
T24 | 
11 | 
 | 
T30 | 
1 | 
 | 
T27 | 
1 | 
| others[3] | 
419 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
17 | 
 | 
T32 | 
1 | 
| false | 
115 | 
1 | 
 | 
T24 | 
5 | 
 | 
T37 | 
1 | 
 | 
T22 | 
2 | 
| true | 
5685 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1075 | 
1 | 
 | 
T24 | 
22 | 
 | 
T26 | 
8 | 
 | 
T21 | 
1 | 
| others[1] | 
1085 | 
1 | 
 | 
T18 | 
1 | 
 | 
T24 | 
18 | 
 | 
T26 | 
8 | 
| others[2] | 
1027 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
18 | 
 | 
T26 | 
3 | 
| others[3] | 
1823 | 
1 | 
 | 
T1 | 
1 | 
 | 
T3 | 
1 | 
 | 
T10 | 
1 | 
| false | 
556 | 
1 | 
 | 
T24 | 
12 | 
 | 
T26 | 
3 | 
 | 
T21 | 
2 | 
| true | 
1389 | 
1 | 
 | 
T2 | 
1 | 
 | 
T14 | 
1 | 
 | 
T55 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
248 | 
1 | 
 | 
T3 | 
1 | 
 | 
T24 | 
18 | 
 | 
T33 | 
1 | 
| others[1] | 
233 | 
1 | 
 | 
T4 | 
1 | 
 | 
T24 | 
8 | 
 | 
T22 | 
12 | 
| others[2] | 
245 | 
1 | 
 | 
T24 | 
10 | 
 | 
T5 | 
1 | 
 | 
T22 | 
13 | 
| others[3] | 
384 | 
1 | 
 | 
T55 | 
1 | 
 | 
T24 | 
11 | 
 | 
T37 | 
1 | 
| false | 
131 | 
1 | 
 | 
T24 | 
6 | 
 | 
T22 | 
5 | 
 | 
T75 | 
3 | 
| true | 
5714 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T14 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
215 | 
1 | 
 | 
T24 | 
10 | 
 | 
T37 | 
1 | 
 | 
T22 | 
9 | 
| others[1] | 
218 | 
1 | 
 | 
T24 | 
12 | 
 | 
T34 | 
1 | 
 | 
T22 | 
10 | 
| others[2] | 
211 | 
1 | 
 | 
T24 | 
8 | 
 | 
T22 | 
12 | 
 | 
T75 | 
16 | 
| others[3] | 
368 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
17 | 
 | 
T22 | 
20 | 
| false | 
103 | 
1 | 
 | 
T24 | 
4 | 
 | 
T22 | 
4 | 
 | 
T75 | 
2 | 
| true | 
5840 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1256 | 
1 | 
 | 
T14 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
24 | 
| others[1] | 
1257 | 
1 | 
 | 
T24 | 
20 | 
 | 
T26 | 
10 | 
 | 
T21 | 
2 | 
| others[2] | 
1251 | 
1 | 
 | 
T10 | 
1 | 
 | 
T18 | 
1 | 
 | 
T55 | 
1 | 
| others[3] | 
2141 | 
1 | 
 | 
T24 | 
34 | 
 | 
T26 | 
32 | 
 | 
T21 | 
2 | 
| false | 
618 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
3 | 
 | 
T26 | 
16 | 
| true | 
432 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1286 | 
1 | 
 | 
T24 | 
18 | 
 | 
T26 | 
26 | 
 | 
T21 | 
2 | 
| others[1] | 
1256 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
17 | 
 | 
T26 | 
22 | 
| others[2] | 
1283 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
29 | 
 | 
T113 | 
1 | 
| others[3] | 
2054 | 
1 | 
 | 
T18 | 
1 | 
 | 
T24 | 
24 | 
 | 
T26 | 
22 | 
| false | 
647 | 
1 | 
 | 
T24 | 
13 | 
 | 
T26 | 
8 | 
 | 
T21 | 
2 | 
| true | 
429 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
97 | 
1 | 
 | 
T24 | 
2 | 
 | 
T22 | 
1 | 
 | 
T75 | 
5 | 
| others[1] | 
102 | 
1 | 
 | 
T24 | 
3 | 
 | 
T22 | 
3 | 
 | 
T75 | 
2 | 
| others[2] | 
106 | 
1 | 
 | 
T24 | 
6 | 
 | 
T37 | 
1 | 
 | 
T22 | 
5 | 
| others[3] | 
190 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
9 | 
 | 
T22 | 
7 | 
| false | 
64 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
5 | 
 | 
T37 | 
1 | 
| true | 
6396 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
259 | 
1 | 
 | 
T55 | 
1 | 
 | 
T24 | 
11 | 
 | 
T5 | 
1 | 
| others[1] | 
233 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
10 | 
 | 
T22 | 
13 | 
| others[2] | 
272 | 
1 | 
 | 
T4 | 
1 | 
 | 
T24 | 
8 | 
 | 
T32 | 
1 | 
| others[3] | 
388 | 
1 | 
 | 
T2 | 
1 | 
 | 
T24 | 
12 | 
 | 
T6 | 
1 | 
| false | 
130 | 
1 | 
 | 
T24 | 
5 | 
 | 
T33 | 
1 | 
 | 
T22 | 
8 | 
| true | 
5673 | 
1 | 
 | 
T1 | 
1 | 
 | 
T3 | 
1 | 
 | 
T14 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1098 | 
1 | 
 | 
T24 | 
20 | 
 | 
T26 | 
13 | 
 | 
T56 | 
10 | 
| others[1] | 
1093 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
19 | 
 | 
T113 | 
1 | 
| others[2] | 
1034 | 
1 | 
 | 
T18 | 
1 | 
 | 
T24 | 
19 | 
 | 
T26 | 
8 | 
| others[3] | 
1768 | 
1 | 
 | 
T24 | 
38 | 
 | 
T26 | 
24 | 
 | 
T21 | 
4 | 
| false | 
543 | 
1 | 
 | 
T15 | 
1 | 
 | 
T17 | 
1 | 
 | 
T24 | 
5 | 
| true | 
1419 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
243 | 
1 | 
 | 
T3 | 
1 | 
 | 
T24 | 
11 | 
 | 
T22 | 
11 | 
| others[1] | 
223 | 
1 | 
 | 
T55 | 
1 | 
 | 
T24 | 
7 | 
 | 
T22 | 
7 | 
| others[2] | 
214 | 
1 | 
 | 
T24 | 
6 | 
 | 
T6 | 
1 | 
 | 
T22 | 
4 | 
| others[3] | 
366 | 
1 | 
 | 
T4 | 
1 | 
 | 
T24 | 
16 | 
 | 
T33 | 
1 | 
| false | 
128 | 
1 | 
 | 
T24 | 
5 | 
 | 
T34 | 
1 | 
 | 
T22 | 
3 | 
| true | 
5781 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T14 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
196 | 
1 | 
 | 
T24 | 
6 | 
 | 
T22 | 
11 | 
 | 
T75 | 
8 | 
| others[1] | 
206 | 
1 | 
 | 
T24 | 
12 | 
 | 
T37 | 
2 | 
 | 
T22 | 
10 | 
| others[2] | 
239 | 
1 | 
 | 
T24 | 
13 | 
 | 
T22 | 
18 | 
 | 
T75 | 
11 | 
| others[3] | 
365 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
14 | 
 | 
T34 | 
1 | 
| false | 
126 | 
1 | 
 | 
T24 | 
4 | 
 | 
T22 | 
5 | 
 | 
T75 | 
4 | 
| true | 
5823 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1218 | 
1 | 
 | 
T18 | 
1 | 
 | 
T24 | 
28 | 
 | 
T26 | 
18 | 
| others[1] | 
1306 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
18 | 
 | 
T113 | 
1 | 
| others[2] | 
1244 | 
1 | 
 | 
T14 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
18 | 
| others[3] | 
2106 | 
1 | 
 | 
T24 | 
25 | 
 | 
T26 | 
32 | 
 | 
T21 | 
1 | 
| false | 
643 | 
1 | 
 | 
T24 | 
12 | 
 | 
T26 | 
10 | 
 | 
T56 | 
5 | 
| true | 
438 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1246 | 
1 | 
 | 
T18 | 
1 | 
 | 
T24 | 
21 | 
 | 
T26 | 
26 | 
| others[1] | 
1284 | 
1 | 
 | 
T24 | 
18 | 
 | 
T113 | 
1 | 
 | 
T26 | 
18 | 
| others[2] | 
1257 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
15 | 
 | 
T26 | 
13 | 
| others[3] | 
2082 | 
1 | 
 | 
T3 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
39 | 
| false | 
657 | 
1 | 
 | 
T24 | 
8 | 
 | 
T26 | 
18 | 
 | 
T21 | 
1 | 
| true | 
429 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T14 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
91 | 
1 | 
 | 
T24 | 
7 | 
 | 
T37 | 
1 | 
 | 
T22 | 
3 | 
| others[1] | 
104 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
3 | 
 | 
T22 | 
3 | 
| others[2] | 
115 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
3 | 
 | 
T22 | 
3 | 
| others[3] | 
182 | 
1 | 
 | 
T24 | 
3 | 
 | 
T37 | 
1 | 
 | 
T22 | 
5 | 
| false | 
56 | 
1 | 
 | 
T24 | 
2 | 
 | 
T22 | 
3 | 
 | 
T75 | 
1 | 
| true | 
6407 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
243 | 
1 | 
 | 
T55 | 
1 | 
 | 
T4 | 
1 | 
 | 
T24 | 
10 | 
| others[1] | 
236 | 
1 | 
 | 
T14 | 
1 | 
 | 
T24 | 
7 | 
 | 
T30 | 
1 | 
| others[2] | 
234 | 
1 | 
 | 
T3 | 
1 | 
 | 
T24 | 
10 | 
 | 
T22 | 
12 | 
| others[3] | 
387 | 
1 | 
 | 
T2 | 
1 | 
 | 
T24 | 
15 | 
 | 
T33 | 
1 | 
| false | 
105 | 
1 | 
 | 
T24 | 
6 | 
 | 
T22 | 
4 | 
 | 
T75 | 
3 | 
| true | 
5750 | 
1 | 
 | 
T1 | 
1 | 
 | 
T10 | 
1 | 
 | 
T15 | 
2 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1065 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
18 | 
 | 
T113 | 
1 | 
| others[1] | 
1070 | 
1 | 
 | 
T18 | 
1 | 
 | 
T24 | 
24 | 
 | 
T26 | 
15 | 
| others[2] | 
1044 | 
1 | 
 | 
T24 | 
21 | 
 | 
T26 | 
8 | 
 | 
T21 | 
4 | 
| others[3] | 
1826 | 
1 | 
 | 
T3 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
34 | 
| false | 
581 | 
1 | 
 | 
T24 | 
4 | 
 | 
T26 | 
10 | 
 | 
T21 | 
1 | 
| true | 
1369 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T14 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
229 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
9 | 
 | 
T5 | 
1 | 
| others[1] | 
221 | 
1 | 
 | 
T14 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
13 | 
| others[2] | 
246 | 
1 | 
 | 
T24 | 
15 | 
 | 
T33 | 
1 | 
 | 
T51 | 
1 | 
| others[3] | 
381 | 
1 | 
 | 
T55 | 
1 | 
 | 
T24 | 
15 | 
 | 
T6 | 
1 | 
| false | 
136 | 
1 | 
 | 
T24 | 
7 | 
 | 
T22 | 
6 | 
 | 
T75 | 
5 | 
| true | 
5742 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
219 | 
1 | 
 | 
T24 | 
7 | 
 | 
T34 | 
1 | 
 | 
T22 | 
13 | 
| others[1] | 
209 | 
1 | 
 | 
T24 | 
11 | 
 | 
T6 | 
1 | 
 | 
T37 | 
1 | 
| others[2] | 
231 | 
1 | 
 | 
T15 | 
1 | 
 | 
T55 | 
1 | 
 | 
T24 | 
16 | 
| others[3] | 
362 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
14 | 
 | 
T22 | 
11 | 
| false | 
110 | 
1 | 
 | 
T24 | 
3 | 
 | 
T33 | 
1 | 
 | 
T28 | 
1 | 
| true | 
5824 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1289 | 
1 | 
 | 
T24 | 
15 | 
 | 
T26 | 
18 | 
 | 
T21 | 
2 | 
| others[1] | 
1213 | 
1 | 
 | 
T24 | 
26 | 
 | 
T26 | 
13 | 
 | 
T21 | 
1 | 
| others[2] | 
1275 | 
1 | 
 | 
T24 | 
23 | 
 | 
T26 | 
26 | 
 | 
T21 | 
1 | 
| others[3] | 
2119 | 
1 | 
 | 
T15 | 
2 | 
 | 
T24 | 
28 | 
 | 
T113 | 
1 | 
| false | 
610 | 
1 | 
 | 
T10 | 
1 | 
 | 
T18 | 
1 | 
 | 
T24 | 
9 | 
| true | 
449 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1228 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
17 | 
 | 
T113 | 
1 | 
| others[1] | 
1243 | 
1 | 
 | 
T24 | 
26 | 
 | 
T26 | 
17 | 
 | 
T56 | 
24 | 
| others[2] | 
1272 | 
1 | 
 | 
T24 | 
22 | 
 | 
T26 | 
14 | 
 | 
T21 | 
4 | 
| others[3] | 
2127 | 
1 | 
 | 
T15 | 
1 | 
 | 
T18 | 
1 | 
 | 
T24 | 
24 | 
| false | 
652 | 
1 | 
 | 
T24 | 
12 | 
 | 
T26 | 
12 | 
 | 
T21 | 
2 | 
| true | 
433 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 
 
 
| 0% | 
10% | 
20% | 
30% | 
40% | 
50% | 
60% | 
70% | 
80% | 
90% | 
100% |