Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Summary for Group Instance   mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
6 | 
0 | 
6 | 
100.00 | 
Variables for Group Instance  mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 
6 | 
0 | 
6 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
97 | 
1 | 
 | 
T24 | 
2 | 
 | 
T37 | 
1 | 
 | 
T22 | 
5 | 
| others[1] | 
93 | 
1 | 
 | 
T24 | 
5 | 
 | 
T22 | 
1 | 
 | 
T75 | 
2 | 
| others[2] | 
105 | 
1 | 
 | 
T15 | 
2 | 
 | 
T24 | 
5 | 
 | 
T22 | 
3 | 
| others[3] | 
171 | 
1 | 
 | 
T24 | 
7 | 
 | 
T37 | 
1 | 
 | 
T33 | 
1 | 
| false | 
48 | 
1 | 
 | 
T24 | 
3 | 
 | 
T119 | 
3 | 
 | 
T85 | 
3 | 
| true | 
6441 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
259 | 
1 | 
 | 
T15 | 
1 | 
 | 
T4 | 
1 | 
 | 
T24 | 
16 | 
| others[1] | 
221 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
8 | 
 | 
T22 | 
10 | 
| others[2] | 
227 | 
1 | 
 | 
T24 | 
7 | 
 | 
T37 | 
1 | 
 | 
T28 | 
1 | 
| others[3] | 
378 | 
1 | 
 | 
T24 | 
14 | 
 | 
T34 | 
1 | 
 | 
T22 | 
15 | 
| false | 
112 | 
1 | 
 | 
T24 | 
8 | 
 | 
T37 | 
1 | 
 | 
T22 | 
4 | 
| true | 
5758 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1063 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
19 | 
 | 
T113 | 
1 | 
| others[1] | 
1104 | 
1 | 
 | 
T24 | 
22 | 
 | 
T26 | 
10 | 
 | 
T21 | 
3 | 
| others[2] | 
1071 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
15 | 
 | 
T26 | 
7 | 
| others[3] | 
1746 | 
1 | 
 | 
T2 | 
1 | 
 | 
T18 | 
1 | 
 | 
T4 | 
1 | 
| false | 
581 | 
1 | 
 | 
T24 | 
12 | 
 | 
T26 | 
1 | 
 | 
T21 | 
1 | 
| true | 
1390 | 
1 | 
 | 
T1 | 
1 | 
 | 
T3 | 
1 | 
 | 
T14 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
240 | 
1 | 
 | 
T4 | 
1 | 
 | 
T24 | 
7 | 
 | 
T34 | 
1 | 
| others[1] | 
218 | 
1 | 
 | 
T24 | 
13 | 
 | 
T37 | 
1 | 
 | 
T22 | 
8 | 
| others[2] | 
246 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
8 | 
 | 
T51 | 
1 | 
| others[3] | 
402 | 
1 | 
 | 
T24 | 
12 | 
 | 
T37 | 
1 | 
 | 
T28 | 
1 | 
| false | 
105 | 
1 | 
 | 
T24 | 
4 | 
 | 
T22 | 
4 | 
 | 
T75 | 
4 | 
| true | 
5744 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
227 | 
1 | 
 | 
T55 | 
1 | 
 | 
T24 | 
10 | 
 | 
T33 | 
1 | 
| others[1] | 
227 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
17 | 
 | 
T34 | 
1 | 
| others[2] | 
224 | 
1 | 
 | 
T24 | 
6 | 
 | 
T22 | 
5 | 
 | 
T75 | 
13 | 
| others[3] | 
395 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
15 | 
 | 
T6 | 
1 | 
| false | 
132 | 
1 | 
 | 
T24 | 
2 | 
 | 
T37 | 
1 | 
 | 
T28 | 
1 | 
| true | 
5750 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1211 | 
1 | 
 | 
T55 | 
1 | 
 | 
T24 | 
22 | 
 | 
T26 | 
14 | 
| others[1] | 
1301 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
20 | 
 | 
T113 | 
1 | 
| others[2] | 
1221 | 
1 | 
 | 
T18 | 
1 | 
 | 
T24 | 
17 | 
 | 
T26 | 
19 | 
| others[3] | 
2131 | 
1 | 
 | 
T14 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
29 | 
| false | 
656 | 
1 | 
 | 
T24 | 
13 | 
 | 
T26 | 
9 | 
 | 
T21 | 
2 | 
| true | 
435 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1276 | 
1 | 
 | 
T24 | 
17 | 
 | 
T26 | 
15 | 
 | 
T21 | 
2 | 
| others[1] | 
1284 | 
1 | 
 | 
T14 | 
1 | 
 | 
T15 | 
1 | 
 | 
T18 | 
1 | 
| others[2] | 
1211 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
20 | 
 | 
T113 | 
1 | 
| others[3] | 
2102 | 
1 | 
 | 
T3 | 
1 | 
 | 
T24 | 
36 | 
 | 
T26 | 
37 | 
| false | 
653 | 
1 | 
 | 
T24 | 
12 | 
 | 
T26 | 
12 | 
 | 
T56 | 
6 | 
| true | 
429 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T10 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
105 | 
1 | 
 | 
T24 | 
8 | 
 | 
T22 | 
4 | 
 | 
T75 | 
5 | 
| others[1] | 
104 | 
1 | 
 | 
T24 | 
4 | 
 | 
T22 | 
2 | 
 | 
T75 | 
4 | 
| others[2] | 
121 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
6 | 
 | 
T37 | 
1 | 
| others[3] | 
175 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
9 | 
 | 
T22 | 
5 | 
| false | 
59 | 
1 | 
 | 
T37 | 
1 | 
 | 
T22 | 
1 | 
 | 
T75 | 
3 | 
| true | 
6391 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
219 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
10 | 
 | 
T30 | 
1 | 
| others[1] | 
243 | 
1 | 
 | 
T24 | 
12 | 
 | 
T6 | 
1 | 
 | 
T37 | 
1 | 
| others[2] | 
248 | 
1 | 
 | 
T24 | 
4 | 
 | 
T22 | 
20 | 
 | 
T75 | 
13 | 
| others[3] | 
417 | 
1 | 
 | 
T3 | 
1 | 
 | 
T24 | 
23 | 
 | 
T51 | 
1 | 
| false | 
111 | 
1 | 
 | 
T24 | 
4 | 
 | 
T22 | 
4 | 
 | 
T75 | 
8 | 
| true | 
5717 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T14 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1084 | 
1 | 
 | 
T17 | 
1 | 
 | 
T24 | 
19 | 
 | 
T26 | 
7 | 
| others[1] | 
1089 | 
1 | 
 | 
T2 | 
1 | 
 | 
T14 | 
1 | 
 | 
T24 | 
24 | 
| others[2] | 
1050 | 
1 | 
 | 
T55 | 
1 | 
 | 
T24 | 
13 | 
 | 
T26 | 
9 | 
| others[3] | 
1790 | 
1 | 
 | 
T15 | 
2 | 
 | 
T24 | 
34 | 
 | 
T26 | 
12 | 
| false | 
589 | 
1 | 
 | 
T18 | 
1 | 
 | 
T24 | 
11 | 
 | 
T113 | 
1 | 
| true | 
1353 | 
1 | 
 | 
T1 | 
1 | 
 | 
T3 | 
1 | 
 | 
T10 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
221 | 
1 | 
 | 
T24 | 
9 | 
 | 
T37 | 
1 | 
 | 
T28 | 
1 | 
| others[1] | 
223 | 
1 | 
 | 
T4 | 
1 | 
 | 
T24 | 
9 | 
 | 
T37 | 
1 | 
| others[2] | 
238 | 
1 | 
 | 
T24 | 
13 | 
 | 
T22 | 
9 | 
 | 
T75 | 
11 | 
| others[3] | 
378 | 
1 | 
 | 
T24 | 
11 | 
 | 
T30 | 
1 | 
 | 
T33 | 
1 | 
| false | 
118 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
4 | 
 | 
T22 | 
6 | 
| true | 
5777 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
241 | 
1 | 
 | 
T24 | 
15 | 
 | 
T6 | 
1 | 
 | 
T34 | 
1 | 
| others[1] | 
210 | 
1 | 
 | 
T24 | 
4 | 
 | 
T22 | 
6 | 
 | 
T75 | 
14 | 
| others[2] | 
216 | 
1 | 
 | 
T24 | 
11 | 
 | 
T37 | 
1 | 
 | 
T22 | 
13 | 
| others[3] | 
368 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
15 | 
 | 
T28 | 
1 | 
| false | 
119 | 
1 | 
 | 
T24 | 
11 | 
 | 
T22 | 
7 | 
 | 
T75 | 
3 | 
| true | 
5801 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1278 | 
1 | 
 | 
T24 | 
20 | 
 | 
T26 | 
14 | 
 | 
T21 | 
1 | 
| others[1] | 
1265 | 
1 | 
 | 
T14 | 
1 | 
 | 
T18 | 
1 | 
 | 
T24 | 
16 | 
| others[2] | 
1241 | 
1 | 
 | 
T24 | 
15 | 
 | 
T26 | 
10 | 
 | 
T56 | 
23 | 
| others[3] | 
2037 | 
1 | 
 | 
T15 | 
2 | 
 | 
T24 | 
38 | 
 | 
T26 | 
39 | 
| false | 
684 | 
1 | 
 | 
T24 | 
12 | 
 | 
T113 | 
1 | 
 | 
T26 | 
10 | 
| true | 
450 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1299 | 
1 | 
 | 
T24 | 
14 | 
 | 
T26 | 
13 | 
 | 
T21 | 
2 | 
| others[1] | 
1248 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
25 | 
 | 
T26 | 
20 | 
| others[2] | 
1261 | 
1 | 
 | 
T18 | 
1 | 
 | 
T24 | 
23 | 
 | 
T26 | 
22 | 
| others[3] | 
2081 | 
1 | 
 | 
T24 | 
31 | 
 | 
T26 | 
29 | 
 | 
T21 | 
2 | 
| false | 
646 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
8 | 
 | 
T113 | 
1 | 
| true | 
420 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
105 | 
1 | 
 | 
T24 | 
2 | 
 | 
T22 | 
6 | 
 | 
T75 | 
2 | 
| others[1] | 
109 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
2 | 
 | 
T75 | 
5 | 
| others[2] | 
94 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
3 | 
 | 
T22 | 
4 | 
| others[3] | 
143 | 
1 | 
 | 
T24 | 
8 | 
 | 
T37 | 
1 | 
 | 
T22 | 
5 | 
| false | 
51 | 
1 | 
 | 
T24 | 
2 | 
 | 
T37 | 
1 | 
 | 
T22 | 
4 | 
| true | 
6453 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
240 | 
1 | 
 | 
T3 | 
1 | 
 | 
T24 | 
8 | 
 | 
T37 | 
1 | 
| others[1] | 
244 | 
1 | 
 | 
T55 | 
1 | 
 | 
T24 | 
13 | 
 | 
T37 | 
1 | 
| others[2] | 
215 | 
1 | 
 | 
T14 | 
1 | 
 | 
T24 | 
7 | 
 | 
T22 | 
9 | 
| others[3] | 
401 | 
1 | 
 | 
T2 | 
1 | 
 | 
T24 | 
18 | 
 | 
T5 | 
1 | 
| false | 
127 | 
1 | 
 | 
T4 | 
1 | 
 | 
T24 | 
5 | 
 | 
T22 | 
6 | 
| true | 
5728 | 
1 | 
 | 
T1 | 
1 | 
 | 
T10 | 
1 | 
 | 
T15 | 
2 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1025 | 
1 | 
 | 
T24 | 
17 | 
 | 
T26 | 
14 | 
 | 
T5 | 
1 | 
| others[1] | 
1119 | 
1 | 
 | 
T2 | 
1 | 
 | 
T15 | 
1 | 
 | 
T55 | 
1 | 
| others[2] | 
1073 | 
1 | 
 | 
T3 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
20 | 
| others[3] | 
1761 | 
1 | 
 | 
T10 | 
1 | 
 | 
T17 | 
1 | 
 | 
T18 | 
1 | 
| false | 
578 | 
1 | 
 | 
T24 | 
9 | 
 | 
T26 | 
8 | 
 | 
T21 | 
2 | 
| true | 
1399 | 
1 | 
 | 
T1 | 
1 | 
 | 
T14 | 
1 | 
 | 
T4 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
214 | 
1 | 
 | 
T24 | 
10 | 
 | 
T37 | 
1 | 
 | 
T28 | 
1 | 
| others[1] | 
253 | 
1 | 
 | 
T15 | 
2 | 
 | 
T24 | 
13 | 
 | 
T22 | 
6 | 
| others[2] | 
260 | 
1 | 
 | 
T14 | 
1 | 
 | 
T4 | 
1 | 
 | 
T24 | 
12 | 
| others[3] | 
371 | 
1 | 
 | 
T24 | 
16 | 
 | 
T37 | 
1 | 
 | 
T22 | 
14 | 
| false | 
117 | 
1 | 
 | 
T24 | 
3 | 
 | 
T22 | 
2 | 
 | 
T75 | 
5 | 
| true | 
5740 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
205 | 
1 | 
 | 
T55 | 
1 | 
 | 
T24 | 
9 | 
 | 
T22 | 
6 | 
| others[1] | 
193 | 
1 | 
 | 
T24 | 
8 | 
 | 
T6 | 
1 | 
 | 
T22 | 
7 | 
| others[2] | 
219 | 
1 | 
 | 
T24 | 
7 | 
 | 
T37 | 
1 | 
 | 
T28 | 
1 | 
| others[3] | 
393 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
25 | 
 | 
T22 | 
16 | 
| false | 
120 | 
1 | 
 | 
T24 | 
6 | 
 | 
T22 | 
5 | 
 | 
T75 | 
5 | 
| true | 
5825 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1289 | 
1 | 
 | 
T3 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
18 | 
| others[1] | 
1226 | 
1 | 
 | 
T18 | 
1 | 
 | 
T24 | 
20 | 
 | 
T26 | 
21 | 
| others[2] | 
1220 | 
1 | 
 | 
T24 | 
19 | 
 | 
T26 | 
22 | 
 | 
T21 | 
1 | 
| others[3] | 
2074 | 
1 | 
 | 
T14 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
24 | 
| false | 
706 | 
1 | 
 | 
T24 | 
20 | 
 | 
T26 | 
10 | 
 | 
T56 | 
15 | 
| true | 
440 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T10 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1300 | 
1 | 
 | 
T24 | 
21 | 
 | 
T113 | 
1 | 
 | 
T26 | 
26 | 
| others[1] | 
1271 | 
1 | 
 | 
T24 | 
20 | 
 | 
T26 | 
20 | 
 | 
T21 | 
2 | 
| others[2] | 
1213 | 
1 | 
 | 
T15 | 
1 | 
 | 
T18 | 
1 | 
 | 
T24 | 
22 | 
| others[3] | 
2104 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
25 | 
 | 
T26 | 
27 | 
| false | 
641 | 
1 | 
 | 
T24 | 
13 | 
 | 
T26 | 
12 | 
 | 
T21 | 
1 | 
| true | 
426 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
95 | 
1 | 
 | 
T24 | 
4 | 
 | 
T22 | 
4 | 
 | 
T75 | 
5 | 
| others[1] | 
96 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
5 | 
 | 
T22 | 
6 | 
| others[2] | 
119 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
3 | 
 | 
T22 | 
4 | 
| others[3] | 
191 | 
1 | 
 | 
T24 | 
12 | 
 | 
T37 | 
1 | 
 | 
T22 | 
9 | 
| false | 
58 | 
1 | 
 | 
T24 | 
2 | 
 | 
T37 | 
1 | 
 | 
T22 | 
2 | 
| true | 
6396 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
228 | 
1 | 
 | 
T2 | 
1 | 
 | 
T4 | 
1 | 
 | 
T24 | 
8 | 
| others[1] | 
244 | 
1 | 
 | 
T3 | 
1 | 
 | 
T55 | 
1 | 
 | 
T24 | 
8 | 
| others[2] | 
223 | 
1 | 
 | 
T24 | 
6 | 
 | 
T32 | 
1 | 
 | 
T22 | 
15 | 
| others[3] | 
411 | 
1 | 
 | 
T24 | 
21 | 
 | 
T37 | 
1 | 
 | 
T22 | 
25 | 
| false | 
134 | 
1 | 
 | 
T24 | 
4 | 
 | 
T27 | 
1 | 
 | 
T22 | 
7 | 
| true | 
5715 | 
1 | 
 | 
T1 | 
1 | 
 | 
T14 | 
1 | 
 | 
T10 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1022 | 
1 | 
 | 
T18 | 
1 | 
 | 
T24 | 
18 | 
 | 
T113 | 
1 | 
| others[1] | 
1115 | 
1 | 
 | 
T24 | 
27 | 
 | 
T26 | 
11 | 
 | 
T21 | 
3 | 
| others[2] | 
1029 | 
1 | 
 | 
T24 | 
19 | 
 | 
T26 | 
6 | 
 | 
T21 | 
3 | 
| others[3] | 
1841 | 
1 | 
 | 
T15 | 
2 | 
 | 
T17 | 
1 | 
 | 
T55 | 
1 | 
| false | 
527 | 
1 | 
 | 
T3 | 
1 | 
 | 
T24 | 
9 | 
 | 
T26 | 
5 | 
| true | 
1421 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T14 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
238 | 
1 | 
 | 
T24 | 
8 | 
 | 
T37 | 
1 | 
 | 
T33 | 
1 | 
| others[1] | 
241 | 
1 | 
 | 
T14 | 
1 | 
 | 
T55 | 
1 | 
 | 
T24 | 
13 | 
| others[2] | 
232 | 
1 | 
 | 
T3 | 
1 | 
 | 
T24 | 
9 | 
 | 
T22 | 
14 | 
| others[3] | 
376 | 
1 | 
 | 
T24 | 
15 | 
 | 
T22 | 
12 | 
 | 
T75 | 
12 | 
| false | 
136 | 
1 | 
 | 
T24 | 
6 | 
 | 
T22 | 
6 | 
 | 
T75 | 
9 | 
| true | 
5732 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T10 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
213 | 
1 | 
 | 
T24 | 
11 | 
 | 
T37 | 
1 | 
 | 
T22 | 
11 | 
| others[1] | 
197 | 
1 | 
 | 
T24 | 
7 | 
 | 
T22 | 
12 | 
 | 
T75 | 
10 | 
| others[2] | 
229 | 
1 | 
 | 
T24 | 
13 | 
 | 
T37 | 
1 | 
 | 
T22 | 
10 | 
| others[3] | 
361 | 
1 | 
 | 
T24 | 
11 | 
 | 
T33 | 
1 | 
 | 
T22 | 
19 | 
| false | 
117 | 
1 | 
 | 
T24 | 
4 | 
 | 
T34 | 
1 | 
 | 
T22 | 
6 | 
| true | 
5838 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1211 | 
1 | 
 | 
T14 | 
1 | 
 | 
T24 | 
17 | 
 | 
T26 | 
18 | 
| others[1] | 
1251 | 
1 | 
 | 
T18 | 
1 | 
 | 
T24 | 
24 | 
 | 
T26 | 
19 | 
| others[2] | 
1251 | 
1 | 
 | 
T3 | 
1 | 
 | 
T24 | 
17 | 
 | 
T26 | 
26 | 
| others[3] | 
2153 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
35 | 
 | 
T113 | 
1 | 
| false | 
644 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
8 | 
 | 
T26 | 
5 | 
| true | 
445 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T10 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1245 | 
1 | 
 | 
T24 | 
15 | 
 | 
T26 | 
20 | 
 | 
T21 | 
5 | 
| others[1] | 
1247 | 
1 | 
 | 
T24 | 
15 | 
 | 
T26 | 
14 | 
 | 
T21 | 
2 | 
| others[2] | 
1262 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
21 | 
 | 
T26 | 
15 | 
| others[3] | 
2156 | 
1 | 
 | 
T15 | 
1 | 
 | 
T18 | 
1 | 
 | 
T24 | 
44 | 
| false | 
625 | 
1 | 
 | 
T24 | 
6 | 
 | 
T113 | 
1 | 
 | 
T26 | 
12 | 
| true | 
420 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
111 | 
1 | 
 | 
T24 | 
4 | 
 | 
T22 | 
4 | 
 | 
T75 | 
6 | 
| others[1] | 
100 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
1 | 
 | 
T22 | 
4 | 
| others[2] | 
113 | 
1 | 
 | 
T24 | 
6 | 
 | 
T37 | 
1 | 
 | 
T22 | 
4 | 
| others[3] | 
182 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
6 | 
 | 
T37 | 
1 | 
| false | 
49 | 
1 | 
 | 
T24 | 
3 | 
 | 
T22 | 
1 | 
 | 
T75 | 
1 | 
| true | 
6400 | 
1 | 
 | 
T1 | 
1 | 
 | 
T2 | 
1 | 
 | 
T3 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
231 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
9 | 
 | 
T37 | 
1 | 
| others[1] | 
249 | 
1 | 
 | 
T24 | 
7 | 
 | 
T22 | 
7 | 
 | 
T75 | 
6 | 
| others[2] | 
260 | 
1 | 
 | 
T24 | 
7 | 
 | 
T28 | 
1 | 
 | 
T22 | 
11 | 
| others[3] | 
367 | 
1 | 
 | 
T2 | 
1 | 
 | 
T24 | 
20 | 
 | 
T6 | 
1 | 
| false | 
139 | 
1 | 
 | 
T24 | 
8 | 
 | 
T51 | 
1 | 
 | 
T22 | 
7 | 
| true | 
5709 | 
1 | 
 | 
T1 | 
1 | 
 | 
T3 | 
1 | 
 | 
T14 | 
1 | 
 
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
6 | 
0 | 
6 | 
100.00 | 
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others[0] | 
1125 | 
1 | 
 | 
T4 | 
1 | 
 | 
T24 | 
19 | 
 | 
T26 | 
6 | 
| others[1] | 
1029 | 
1 | 
 | 
T1 | 
1 | 
 | 
T14 | 
1 | 
 | 
T15 | 
1 | 
| others[2] | 
1041 | 
1 | 
 | 
T15 | 
1 | 
 | 
T24 | 
23 | 
 | 
T26 | 
12 | 
| others[3] | 
1778 | 
1 | 
 | 
T2 | 
1 | 
 | 
T18 | 
1 | 
 | 
T24 | 
30 | 
| false | 
592 | 
1 | 
 | 
T24 | 
12 | 
 | 
T26 | 
6 | 
 | 
T21 | 
1 | 
| true | 
1390 | 
1 | 
 | 
T3 | 
1 | 
 | 
T10 | 
1 | 
 | 
T17 | 
1 | 
 
 
 
| 0% | 
10% | 
20% | 
30% | 
40% | 
50% | 
60% | 
70% | 
80% | 
90% | 
100% |