Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1253 |
1 |
|
T24 |
17 |
|
T113 |
1 |
|
T26 |
17 |
| others[1] |
1292 |
1 |
|
T24 |
16 |
|
T26 |
20 |
|
T21 |
3 |
| others[2] |
1261 |
1 |
|
T14 |
1 |
|
T24 |
19 |
|
T26 |
18 |
| others[3] |
2053 |
1 |
|
T3 |
1 |
|
T15 |
2 |
|
T24 |
40 |
| false |
673 |
1 |
|
T18 |
1 |
|
T24 |
9 |
|
T26 |
15 |
| true |
423 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
107 |
1 |
|
T24 |
2 |
|
T37 |
1 |
|
T22 |
1 |
| others[1] |
105 |
1 |
|
T24 |
2 |
|
T22 |
6 |
|
T75 |
5 |
| others[2] |
114 |
1 |
|
T15 |
1 |
|
T24 |
1 |
|
T22 |
3 |
| others[3] |
163 |
1 |
|
T15 |
1 |
|
T24 |
6 |
|
T37 |
1 |
| false |
41 |
1 |
|
T24 |
1 |
|
T22 |
2 |
|
T75 |
1 |
| true |
6425 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
254 |
1 |
|
T24 |
10 |
|
T22 |
14 |
|
T75 |
11 |
| others[1] |
223 |
1 |
|
T15 |
1 |
|
T24 |
8 |
|
T22 |
11 |
| others[2] |
239 |
1 |
|
T24 |
13 |
|
T30 |
1 |
|
T34 |
1 |
| others[3] |
398 |
1 |
|
T15 |
1 |
|
T55 |
1 |
|
T24 |
22 |
| false |
130 |
1 |
|
T24 |
6 |
|
T51 |
1 |
|
T22 |
8 |
| true |
5711 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1040 |
1 |
|
T24 |
19 |
|
T26 |
9 |
|
T21 |
3 |
| others[1] |
1069 |
1 |
|
T14 |
1 |
|
T15 |
1 |
|
T24 |
19 |
| others[2] |
1063 |
1 |
|
T2 |
1 |
|
T24 |
22 |
|
T26 |
10 |
| others[3] |
1813 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T18 |
1 |
| false |
584 |
1 |
|
T24 |
12 |
|
T26 |
5 |
|
T21 |
3 |
| true |
1386 |
1 |
|
T3 |
1 |
|
T10 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
199 |
1 |
|
T24 |
10 |
|
T34 |
1 |
|
T22 |
5 |
| others[1] |
223 |
1 |
|
T24 |
5 |
|
T30 |
1 |
|
T37 |
1 |
| others[2] |
208 |
1 |
|
T4 |
1 |
|
T24 |
10 |
|
T37 |
1 |
| others[3] |
406 |
1 |
|
T24 |
16 |
|
T32 |
1 |
|
T22 |
23 |
| false |
127 |
1 |
|
T24 |
6 |
|
T22 |
7 |
|
T75 |
4 |
| true |
5792 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T15 |
1 |
|
T24 |
9 |
|
T22 |
13 |
| others[1] |
209 |
1 |
|
T24 |
14 |
|
T28 |
1 |
|
T22 |
17 |
| others[2] |
219 |
1 |
|
T24 |
9 |
|
T22 |
6 |
|
T75 |
11 |
| others[3] |
389 |
1 |
|
T24 |
20 |
|
T37 |
1 |
|
T22 |
13 |
| false |
119 |
1 |
|
T15 |
1 |
|
T24 |
5 |
|
T22 |
3 |
| true |
5792 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1289 |
1 |
|
T15 |
1 |
|
T24 |
20 |
|
T26 |
22 |
| others[1] |
1272 |
1 |
|
T3 |
1 |
|
T24 |
24 |
|
T26 |
15 |
| others[2] |
1222 |
1 |
|
T24 |
15 |
|
T26 |
14 |
|
T21 |
4 |
| others[3] |
2105 |
1 |
|
T15 |
1 |
|
T18 |
1 |
|
T55 |
1 |
| false |
625 |
1 |
|
T24 |
7 |
|
T113 |
1 |
|
T26 |
10 |
| true |
442 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1267 |
1 |
|
T3 |
1 |
|
T24 |
16 |
|
T26 |
26 |
| others[1] |
1248 |
1 |
|
T15 |
1 |
|
T24 |
16 |
|
T113 |
1 |
| others[2] |
1307 |
1 |
|
T18 |
1 |
|
T24 |
25 |
|
T26 |
21 |
| others[3] |
2077 |
1 |
|
T15 |
1 |
|
T24 |
35 |
|
T26 |
25 |
| false |
637 |
1 |
|
T24 |
9 |
|
T26 |
7 |
|
T21 |
1 |
| true |
419 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
84 |
1 |
|
T24 |
4 |
|
T37 |
1 |
|
T75 |
6 |
| others[1] |
102 |
1 |
|
T24 |
4 |
|
T37 |
1 |
|
T22 |
1 |
| others[2] |
101 |
1 |
|
T15 |
2 |
|
T24 |
2 |
|
T22 |
4 |
| others[3] |
154 |
1 |
|
T24 |
6 |
|
T22 |
7 |
|
T75 |
7 |
| false |
55 |
1 |
|
T24 |
1 |
|
T22 |
4 |
|
T75 |
1 |
| true |
6459 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T24 |
10 |
|
T22 |
9 |
|
T75 |
3 |
| others[1] |
231 |
1 |
|
T24 |
15 |
|
T37 |
1 |
|
T22 |
13 |
| others[2] |
260 |
1 |
|
T24 |
15 |
|
T34 |
1 |
|
T22 |
12 |
| others[3] |
375 |
1 |
|
T2 |
1 |
|
T14 |
1 |
|
T24 |
17 |
| false |
150 |
1 |
|
T55 |
1 |
|
T24 |
2 |
|
T30 |
1 |
| true |
5714 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1059 |
1 |
|
T15 |
1 |
|
T24 |
21 |
|
T26 |
4 |
| others[1] |
1125 |
1 |
|
T1 |
1 |
|
T10 |
1 |
|
T17 |
1 |
| others[2] |
1047 |
1 |
|
T24 |
19 |
|
T26 |
11 |
|
T21 |
2 |
| others[3] |
1775 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T15 |
1 |
| false |
567 |
1 |
|
T24 |
10 |
|
T26 |
1 |
|
T21 |
2 |
| true |
1382 |
1 |
|
T14 |
1 |
|
T55 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T24 |
10 |
|
T32 |
1 |
|
T22 |
9 |
| others[1] |
217 |
1 |
|
T24 |
7 |
|
T6 |
1 |
|
T28 |
1 |
| others[2] |
208 |
1 |
|
T24 |
10 |
|
T51 |
1 |
|
T22 |
11 |
| others[3] |
397 |
1 |
|
T15 |
2 |
|
T24 |
24 |
|
T22 |
16 |
| false |
109 |
1 |
|
T3 |
1 |
|
T24 |
6 |
|
T33 |
1 |
| true |
5783 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
202 |
1 |
|
T24 |
8 |
|
T22 |
9 |
|
T75 |
15 |
| others[1] |
227 |
1 |
|
T24 |
12 |
|
T34 |
1 |
|
T22 |
9 |
| others[2] |
248 |
1 |
|
T24 |
12 |
|
T33 |
1 |
|
T22 |
9 |
| others[3] |
321 |
1 |
|
T24 |
14 |
|
T6 |
1 |
|
T22 |
18 |
| false |
117 |
1 |
|
T24 |
7 |
|
T37 |
1 |
|
T22 |
7 |
| true |
5840 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1227 |
1 |
|
T15 |
1 |
|
T24 |
17 |
|
T26 |
16 |
| others[1] |
1296 |
1 |
|
T3 |
1 |
|
T15 |
1 |
|
T24 |
23 |
| others[2] |
1277 |
1 |
|
T24 |
24 |
|
T26 |
20 |
|
T21 |
3 |
| others[3] |
2059 |
1 |
|
T18 |
1 |
|
T55 |
1 |
|
T24 |
28 |
| false |
643 |
1 |
|
T24 |
9 |
|
T26 |
17 |
|
T56 |
9 |
| true |
453 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1224 |
1 |
|
T15 |
2 |
|
T24 |
22 |
|
T26 |
24 |
| others[1] |
1247 |
1 |
|
T18 |
1 |
|
T24 |
12 |
|
T26 |
18 |
| others[2] |
1246 |
1 |
|
T24 |
16 |
|
T26 |
22 |
|
T21 |
3 |
| others[3] |
2185 |
1 |
|
T24 |
36 |
|
T113 |
1 |
|
T26 |
30 |
| false |
621 |
1 |
|
T24 |
15 |
|
T26 |
6 |
|
T21 |
2 |
| true |
432 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
89 |
1 |
|
T22 |
5 |
|
T75 |
3 |
|
T290 |
1 |
| others[1] |
112 |
1 |
|
T24 |
2 |
|
T22 |
3 |
|
T75 |
5 |
| others[2] |
105 |
1 |
|
T15 |
1 |
|
T24 |
3 |
|
T37 |
2 |
| others[3] |
165 |
1 |
|
T15 |
1 |
|
T24 |
11 |
|
T22 |
8 |
| false |
50 |
1 |
|
T24 |
1 |
|
T22 |
1 |
|
T75 |
1 |
| true |
6434 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
215 |
1 |
|
T24 |
4 |
|
T27 |
1 |
|
T32 |
1 |
| others[1] |
226 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T24 |
8 |
| others[2] |
244 |
1 |
|
T55 |
1 |
|
T24 |
14 |
|
T37 |
1 |
| others[3] |
411 |
1 |
|
T15 |
1 |
|
T24 |
15 |
|
T33 |
1 |
| false |
117 |
1 |
|
T24 |
6 |
|
T22 |
6 |
|
T75 |
4 |
| true |
5742 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1025 |
1 |
|
T14 |
1 |
|
T24 |
18 |
|
T26 |
13 |
| others[1] |
1046 |
1 |
|
T2 |
1 |
|
T24 |
14 |
|
T113 |
1 |
| others[2] |
1072 |
1 |
|
T24 |
16 |
|
T26 |
8 |
|
T21 |
2 |
| others[3] |
1779 |
1 |
|
T1 |
1 |
|
T15 |
2 |
|
T18 |
1 |
| false |
599 |
1 |
|
T24 |
17 |
|
T26 |
8 |
|
T21 |
2 |
| true |
1434 |
1 |
|
T3 |
1 |
|
T10 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T24 |
10 |
|
T22 |
10 |
|
T75 |
9 |
| others[1] |
236 |
1 |
|
T24 |
9 |
|
T34 |
1 |
|
T22 |
16 |
| others[2] |
217 |
1 |
|
T4 |
1 |
|
T24 |
10 |
|
T30 |
1 |
| others[3] |
378 |
1 |
|
T24 |
11 |
|
T22 |
19 |
|
T75 |
20 |
| false |
128 |
1 |
|
T24 |
4 |
|
T22 |
3 |
|
T75 |
4 |
| true |
5772 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
213 |
1 |
|
T24 |
11 |
|
T37 |
1 |
|
T51 |
1 |
| others[1] |
208 |
1 |
|
T24 |
9 |
|
T22 |
8 |
|
T75 |
11 |
| others[2] |
202 |
1 |
|
T24 |
5 |
|
T22 |
5 |
|
T75 |
7 |
| others[3] |
370 |
1 |
|
T55 |
1 |
|
T24 |
18 |
|
T37 |
1 |
| false |
131 |
1 |
|
T24 |
6 |
|
T22 |
7 |
|
T75 |
4 |
| true |
5831 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1281 |
1 |
|
T24 |
18 |
|
T26 |
22 |
|
T21 |
2 |
| others[1] |
1244 |
1 |
|
T24 |
16 |
|
T26 |
19 |
|
T21 |
3 |
| others[2] |
1242 |
1 |
|
T15 |
2 |
|
T24 |
19 |
|
T26 |
14 |
| others[3] |
2101 |
1 |
|
T10 |
1 |
|
T18 |
1 |
|
T24 |
37 |
| false |
647 |
1 |
|
T24 |
11 |
|
T113 |
1 |
|
T26 |
10 |
| true |
440 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1278 |
1 |
|
T24 |
21 |
|
T26 |
16 |
|
T21 |
2 |
| others[1] |
1274 |
1 |
|
T18 |
1 |
|
T24 |
17 |
|
T26 |
22 |
| others[2] |
1254 |
1 |
|
T15 |
2 |
|
T24 |
21 |
|
T26 |
20 |
| others[3] |
2097 |
1 |
|
T24 |
36 |
|
T113 |
1 |
|
T26 |
33 |
| false |
624 |
1 |
|
T24 |
6 |
|
T26 |
9 |
|
T21 |
1 |
| true |
428 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
109 |
1 |
|
T15 |
1 |
|
T24 |
5 |
|
T37 |
1 |
| others[1] |
99 |
1 |
|
T24 |
4 |
|
T22 |
6 |
|
T75 |
2 |
| others[2] |
111 |
1 |
|
T24 |
5 |
|
T22 |
6 |
|
T75 |
6 |
| others[3] |
187 |
1 |
|
T15 |
1 |
|
T24 |
7 |
|
T37 |
1 |
| false |
51 |
1 |
|
T24 |
3 |
|
T22 |
1 |
|
T75 |
3 |
| true |
6398 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
230 |
1 |
|
T15 |
1 |
|
T24 |
10 |
|
T37 |
1 |
| others[1] |
237 |
1 |
|
T24 |
12 |
|
T34 |
1 |
|
T22 |
5 |
| others[2] |
227 |
1 |
|
T24 |
6 |
|
T6 |
1 |
|
T30 |
1 |
| others[3] |
429 |
1 |
|
T2 |
1 |
|
T14 |
1 |
|
T15 |
1 |
| false |
116 |
1 |
|
T24 |
4 |
|
T22 |
2 |
|
T75 |
1 |
| true |
5716 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1111 |
1 |
|
T14 |
1 |
|
T55 |
1 |
|
T4 |
1 |
| others[1] |
1059 |
1 |
|
T18 |
1 |
|
T24 |
24 |
|
T26 |
7 |
| others[2] |
1023 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T15 |
1 |
| others[3] |
1784 |
1 |
|
T10 |
1 |
|
T15 |
1 |
|
T24 |
22 |
| false |
575 |
1 |
|
T24 |
11 |
|
T26 |
2 |
|
T21 |
1 |
| true |
1403 |
1 |
|
T1 |
1 |
|
T17 |
1 |
|
T26 |
47 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
213 |
1 |
|
T24 |
9 |
|
T22 |
10 |
|
T75 |
5 |
| others[1] |
244 |
1 |
|
T3 |
1 |
|
T24 |
12 |
|
T5 |
1 |
| others[2] |
251 |
1 |
|
T24 |
10 |
|
T22 |
10 |
|
T75 |
13 |
| others[3] |
387 |
1 |
|
T15 |
2 |
|
T24 |
16 |
|
T37 |
2 |
| false |
89 |
1 |
|
T24 |
5 |
|
T6 |
1 |
|
T22 |
2 |
| true |
5771 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
223 |
1 |
|
T55 |
1 |
|
T24 |
8 |
|
T22 |
9 |
| others[1] |
230 |
1 |
|
T24 |
9 |
|
T6 |
1 |
|
T22 |
14 |
| others[2] |
224 |
1 |
|
T24 |
10 |
|
T37 |
1 |
|
T51 |
1 |
| others[3] |
349 |
1 |
|
T24 |
20 |
|
T33 |
1 |
|
T28 |
1 |
| false |
137 |
1 |
|
T24 |
3 |
|
T37 |
1 |
|
T22 |
3 |
| true |
5792 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1278 |
1 |
|
T24 |
17 |
|
T26 |
19 |
|
T21 |
2 |
| others[1] |
1290 |
1 |
|
T24 |
21 |
|
T113 |
1 |
|
T26 |
20 |
| others[2] |
1208 |
1 |
|
T15 |
1 |
|
T24 |
16 |
|
T26 |
23 |
| others[3] |
2122 |
1 |
|
T15 |
1 |
|
T18 |
1 |
|
T24 |
38 |
| false |
628 |
1 |
|
T24 |
9 |
|
T26 |
6 |
|
T21 |
1 |
| true |
429 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
3 |
1 |
|
T77 |
1 |
|
T99 |
1 |
|
T369 |
1 |
| others[1] |
14 |
1 |
|
T148 |
1 |
|
T141 |
1 |
|
T150 |
1 |
| others[2] |
9 |
1 |
|
T97 |
1 |
|
T106 |
1 |
|
T145 |
1 |
| others[3] |
11 |
1 |
|
T78 |
1 |
|
T147 |
1 |
|
T151 |
1 |
| false |
4 |
1 |
|
T370 |
1 |
|
T371 |
1 |
|
T372 |
1 |
| true |
45 |
1 |
|
T88 |
1 |
|
T66 |
1 |
|
T134 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1 |
1 |
|
T373 |
1 |
|
- |
- |
|
- |
- |
| others[1] |
8 |
1 |
|
T374 |
1 |
|
T375 |
1 |
|
T376 |
1 |
| others[2] |
1 |
1 |
|
T377 |
1 |
|
- |
- |
|
- |
- |
| others[3] |
2 |
1 |
|
T378 |
1 |
|
T379 |
1 |
|
- |
- |
| false |
13 |
1 |
|
T31 |
1 |
|
T368 |
1 |
|
T358 |
1 |
| true |
24 |
1 |
|
T158 |
1 |
|
T159 |
1 |
|
T380 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1 |
1 |
|
T381 |
1 |
|
- |
- |
|
- |
- |
| others[1] |
6 |
1 |
|
T374 |
1 |
|
T382 |
1 |
|
T383 |
1 |
| others[2] |
4 |
1 |
|
T384 |
1 |
|
T375 |
1 |
|
T385 |
1 |
| others[3] |
8 |
1 |
|
T158 |
1 |
|
T358 |
1 |
|
T380 |
1 |
| false |
9 |
1 |
|
T159 |
1 |
|
T386 |
1 |
|
T387 |
1 |
| true |
21 |
1 |
|
T31 |
1 |
|
T368 |
1 |
|
T359 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |