Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10220 |
1 |
|
T3 |
1 |
|
T24 |
25 |
|
T26 |
100 |
| others[1] |
787 |
1 |
|
T24 |
18 |
|
T19 |
11 |
|
T110 |
1 |
| others[2] |
824 |
1 |
|
T24 |
21 |
|
T21 |
4 |
|
T57 |
1 |
| others[3] |
1356 |
1 |
|
T18 |
1 |
|
T24 |
27 |
|
T21 |
3 |
| false |
427 |
1 |
|
T24 |
10 |
|
T113 |
1 |
|
T21 |
2 |
| true |
503 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2417 |
1 |
|
T24 |
9 |
|
T26 |
18 |
|
T56 |
25 |
| others[1] |
2413 |
1 |
|
T15 |
1 |
|
T24 |
11 |
|
T26 |
13 |
| others[2] |
2435 |
1 |
|
T18 |
1 |
|
T55 |
1 |
|
T24 |
12 |
| others[3] |
3973 |
1 |
|
T24 |
13 |
|
T113 |
1 |
|
T26 |
39 |
| false |
1303 |
1 |
|
T15 |
1 |
|
T26 |
9 |
|
T56 |
6 |
| true |
1576 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9617 |
1 |
|
T24 |
5 |
|
T26 |
100 |
|
T30 |
1 |
| others[1] |
284 |
1 |
|
T24 |
13 |
|
T110 |
1 |
|
T22 |
14 |
| others[2] |
283 |
1 |
|
T24 |
12 |
|
T32 |
1 |
|
T22 |
14 |
| others[3] |
449 |
1 |
|
T3 |
1 |
|
T14 |
1 |
|
T24 |
22 |
| false |
127 |
1 |
|
T24 |
2 |
|
T22 |
6 |
|
T75 |
6 |
| true |
3357 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9891 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T24 |
16 |
| others[1] |
474 |
1 |
|
T2 |
1 |
|
T24 |
4 |
|
T21 |
1 |
| others[2] |
477 |
1 |
|
T14 |
1 |
|
T15 |
1 |
|
T24 |
9 |
| others[3] |
775 |
1 |
|
T15 |
1 |
|
T24 |
16 |
|
T5 |
1 |
| false |
235 |
1 |
|
T24 |
9 |
|
T21 |
1 |
|
T22 |
4 |
| true |
2265 |
1 |
|
T3 |
1 |
|
T10 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9628 |
1 |
|
T4 |
1 |
|
T24 |
7 |
|
T26 |
100 |
| others[1] |
250 |
1 |
|
T24 |
15 |
|
T33 |
1 |
|
T22 |
13 |
| others[2] |
275 |
1 |
|
T24 |
11 |
|
T113 |
1 |
|
T110 |
1 |
| others[3] |
433 |
1 |
|
T14 |
1 |
|
T24 |
14 |
|
T6 |
1 |
| false |
143 |
1 |
|
T18 |
1 |
|
T24 |
3 |
|
T37 |
1 |
| true |
3388 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9616 |
1 |
|
T15 |
1 |
|
T55 |
1 |
|
T24 |
11 |
| others[1] |
267 |
1 |
|
T24 |
11 |
|
T57 |
1 |
|
T33 |
1 |
| others[2] |
259 |
1 |
|
T24 |
11 |
|
T37 |
1 |
|
T110 |
1 |
| others[3] |
412 |
1 |
|
T18 |
1 |
|
T24 |
11 |
|
T6 |
1 |
| false |
111 |
1 |
|
T15 |
1 |
|
T24 |
8 |
|
T47 |
1 |
| true |
3452 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10198 |
1 |
|
T24 |
16 |
|
T26 |
100 |
|
T21 |
4 |
| others[1] |
837 |
1 |
|
T55 |
1 |
|
T24 |
15 |
|
T113 |
1 |
| others[2] |
821 |
1 |
|
T24 |
22 |
|
T21 |
1 |
|
T30 |
1 |
| others[3] |
1343 |
1 |
|
T15 |
1 |
|
T18 |
1 |
|
T24 |
38 |
| false |
424 |
1 |
|
T24 |
10 |
|
T21 |
1 |
|
T19 |
3 |
| true |
494 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10190 |
1 |
|
T24 |
18 |
|
T26 |
100 |
|
T21 |
2 |
| others[1] |
814 |
1 |
|
T15 |
1 |
|
T18 |
1 |
|
T24 |
24 |
| others[2] |
825 |
1 |
|
T24 |
14 |
|
T21 |
4 |
|
T19 |
6 |
| others[3] |
1329 |
1 |
|
T15 |
1 |
|
T24 |
36 |
|
T21 |
5 |
| false |
401 |
1 |
|
T24 |
9 |
|
T21 |
1 |
|
T30 |
1 |
| true |
534 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2462 |
1 |
|
T24 |
8 |
|
T26 |
20 |
|
T56 |
17 |
| others[1] |
2390 |
1 |
|
T15 |
1 |
|
T24 |
9 |
|
T113 |
1 |
| others[2] |
2408 |
1 |
|
T18 |
1 |
|
T24 |
13 |
|
T26 |
23 |
| others[3] |
3987 |
1 |
|
T15 |
1 |
|
T24 |
16 |
|
T26 |
31 |
| false |
1248 |
1 |
|
T24 |
7 |
|
T26 |
10 |
|
T56 |
6 |
| true |
1598 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9636 |
1 |
|
T3 |
1 |
|
T24 |
10 |
|
T26 |
100 |
| others[1] |
295 |
1 |
|
T24 |
9 |
|
T37 |
1 |
|
T189 |
1 |
| others[2] |
277 |
1 |
|
T2 |
1 |
|
T18 |
1 |
|
T24 |
13 |
| others[3] |
403 |
1 |
|
T24 |
19 |
|
T33 |
1 |
|
T22 |
12 |
| false |
128 |
1 |
|
T24 |
2 |
|
T32 |
1 |
|
T22 |
4 |
| true |
3354 |
1 |
|
T1 |
1 |
|
T14 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9819 |
1 |
|
T14 |
1 |
|
T24 |
11 |
|
T26 |
100 |
| others[1] |
455 |
1 |
|
T24 |
14 |
|
T57 |
1 |
|
T19 |
5 |
| others[2] |
479 |
1 |
|
T15 |
1 |
|
T24 |
7 |
|
T21 |
2 |
| others[3] |
845 |
1 |
|
T3 |
1 |
|
T10 |
1 |
|
T15 |
1 |
| false |
236 |
1 |
|
T24 |
7 |
|
T21 |
1 |
|
T19 |
1 |
| true |
2259 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9623 |
1 |
|
T15 |
1 |
|
T18 |
1 |
|
T24 |
9 |
| others[1] |
284 |
1 |
|
T24 |
13 |
|
T73 |
1 |
|
T22 |
8 |
| others[2] |
235 |
1 |
|
T4 |
1 |
|
T24 |
8 |
|
T113 |
1 |
| others[3] |
486 |
1 |
|
T3 |
1 |
|
T15 |
1 |
|
T24 |
14 |
| false |
139 |
1 |
|
T55 |
1 |
|
T24 |
8 |
|
T22 |
6 |
| true |
3326 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9630 |
1 |
|
T15 |
1 |
|
T24 |
11 |
|
T26 |
100 |
| others[1] |
245 |
1 |
|
T24 |
9 |
|
T113 |
1 |
|
T110 |
1 |
| others[2] |
248 |
1 |
|
T15 |
1 |
|
T55 |
1 |
|
T24 |
11 |
| others[3] |
445 |
1 |
|
T24 |
16 |
|
T37 |
1 |
|
T33 |
1 |
| false |
135 |
1 |
|
T18 |
1 |
|
T24 |
7 |
|
T57 |
1 |
| true |
3390 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10190 |
1 |
|
T24 |
18 |
|
T113 |
1 |
|
T26 |
100 |
| others[1] |
795 |
1 |
|
T24 |
16 |
|
T21 |
2 |
|
T19 |
9 |
| others[2] |
837 |
1 |
|
T18 |
1 |
|
T24 |
21 |
|
T21 |
5 |
| others[3] |
1345 |
1 |
|
T24 |
31 |
|
T21 |
5 |
|
T19 |
17 |
| false |
431 |
1 |
|
T24 |
15 |
|
T21 |
2 |
|
T19 |
8 |
| true |
495 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10147 |
1 |
|
T24 |
17 |
|
T26 |
100 |
|
T21 |
5 |
| others[1] |
833 |
1 |
|
T24 |
22 |
|
T113 |
1 |
|
T21 |
1 |
| others[2] |
813 |
1 |
|
T18 |
1 |
|
T24 |
17 |
|
T21 |
6 |
| others[3] |
1402 |
1 |
|
T24 |
35 |
|
T21 |
3 |
|
T57 |
1 |
| false |
389 |
1 |
|
T24 |
10 |
|
T22 |
7 |
|
T25 |
1 |
| true |
509 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2395 |
1 |
|
T24 |
10 |
|
T26 |
20 |
|
T56 |
27 |
| others[1] |
2416 |
1 |
|
T15 |
2 |
|
T18 |
1 |
|
T24 |
8 |
| others[2] |
2409 |
1 |
|
T24 |
7 |
|
T26 |
15 |
|
T56 |
16 |
| others[3] |
3991 |
1 |
|
T24 |
20 |
|
T113 |
1 |
|
T26 |
36 |
| false |
1311 |
1 |
|
T55 |
1 |
|
T24 |
7 |
|
T26 |
10 |
| true |
1571 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9623 |
1 |
|
T24 |
10 |
|
T26 |
100 |
|
T56 |
100 |
| others[1] |
272 |
1 |
|
T18 |
1 |
|
T24 |
12 |
|
T5 |
1 |
| others[2] |
288 |
1 |
|
T14 |
1 |
|
T24 |
9 |
|
T51 |
1 |
| others[3] |
437 |
1 |
|
T15 |
1 |
|
T24 |
19 |
|
T22 |
15 |
| false |
127 |
1 |
|
T24 |
5 |
|
T57 |
1 |
|
T22 |
5 |
| true |
3346 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9816 |
1 |
|
T14 |
1 |
|
T15 |
1 |
|
T55 |
1 |
| others[1] |
464 |
1 |
|
T24 |
10 |
|
T19 |
6 |
|
T37 |
1 |
| others[2] |
471 |
1 |
|
T10 |
1 |
|
T15 |
1 |
|
T17 |
1 |
| others[3] |
822 |
1 |
|
T3 |
1 |
|
T24 |
15 |
|
T21 |
5 |
| false |
230 |
1 |
|
T24 |
5 |
|
T19 |
1 |
|
T37 |
1 |
| true |
2290 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9613 |
1 |
|
T24 |
7 |
|
T26 |
100 |
|
T56 |
100 |
| others[1] |
266 |
1 |
|
T24 |
5 |
|
T22 |
11 |
|
T75 |
8 |
| others[2] |
247 |
1 |
|
T14 |
1 |
|
T55 |
1 |
|
T24 |
9 |
| others[3] |
436 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T24 |
15 |
| false |
130 |
1 |
|
T24 |
9 |
|
T189 |
1 |
|
T22 |
6 |
| true |
3401 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9620 |
1 |
|
T18 |
1 |
|
T24 |
10 |
|
T26 |
100 |
| others[1] |
245 |
1 |
|
T24 |
12 |
|
T37 |
1 |
|
T51 |
1 |
| others[2] |
267 |
1 |
|
T24 |
8 |
|
T164 |
1 |
|
T22 |
11 |
| others[3] |
403 |
1 |
|
T15 |
1 |
|
T55 |
1 |
|
T24 |
20 |
| false |
132 |
1 |
|
T24 |
6 |
|
T22 |
7 |
|
T75 |
2 |
| true |
3426 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10213 |
1 |
|
T24 |
16 |
|
T113 |
1 |
|
T26 |
100 |
| others[1] |
822 |
1 |
|
T24 |
22 |
|
T21 |
4 |
|
T19 |
9 |
| others[2] |
796 |
1 |
|
T24 |
25 |
|
T21 |
1 |
|
T19 |
8 |
| others[3] |
1314 |
1 |
|
T3 |
1 |
|
T18 |
1 |
|
T24 |
29 |
| false |
452 |
1 |
|
T24 |
9 |
|
T21 |
2 |
|
T19 |
9 |
| true |
496 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10184 |
1 |
|
T24 |
18 |
|
T26 |
100 |
|
T21 |
3 |
| others[1] |
774 |
1 |
|
T24 |
19 |
|
T21 |
3 |
|
T19 |
13 |
| others[2] |
824 |
1 |
|
T15 |
1 |
|
T18 |
1 |
|
T24 |
19 |
| others[3] |
1378 |
1 |
|
T24 |
34 |
|
T113 |
1 |
|
T21 |
3 |
| false |
410 |
1 |
|
T24 |
11 |
|
T21 |
2 |
|
T19 |
10 |
| true |
523 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2413 |
1 |
|
T24 |
7 |
|
T26 |
19 |
|
T56 |
21 |
| others[1] |
2442 |
1 |
|
T24 |
16 |
|
T26 |
20 |
|
T56 |
18 |
| others[2] |
2391 |
1 |
|
T15 |
1 |
|
T55 |
1 |
|
T24 |
10 |
| others[3] |
3959 |
1 |
|
T15 |
1 |
|
T24 |
13 |
|
T113 |
1 |
| false |
1299 |
1 |
|
T18 |
1 |
|
T24 |
7 |
|
T26 |
8 |
| true |
1589 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9634 |
1 |
|
T24 |
11 |
|
T26 |
100 |
|
T30 |
1 |
| others[1] |
303 |
1 |
|
T24 |
10 |
|
T6 |
1 |
|
T57 |
1 |
| others[2] |
269 |
1 |
|
T3 |
1 |
|
T24 |
8 |
|
T73 |
1 |
| others[3] |
466 |
1 |
|
T15 |
1 |
|
T24 |
15 |
|
T27 |
1 |
| false |
140 |
1 |
|
T24 |
5 |
|
T22 |
2 |
|
T75 |
3 |
| true |
3281 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9825 |
1 |
|
T24 |
10 |
|
T26 |
100 |
|
T21 |
1 |
| others[1] |
459 |
1 |
|
T17 |
1 |
|
T24 |
7 |
|
T21 |
2 |
| others[2] |
505 |
1 |
|
T55 |
1 |
|
T24 |
11 |
|
T21 |
2 |
| others[3] |
795 |
1 |
|
T15 |
1 |
|
T4 |
1 |
|
T24 |
13 |
| false |
264 |
1 |
|
T15 |
1 |
|
T24 |
4 |
|
T21 |
2 |
| true |
2245 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9609 |
1 |
|
T18 |
1 |
|
T24 |
9 |
|
T26 |
100 |
| others[1] |
246 |
1 |
|
T24 |
12 |
|
T5 |
1 |
|
T37 |
2 |
| others[2] |
233 |
1 |
|
T15 |
1 |
|
T24 |
5 |
|
T32 |
1 |
| others[3] |
444 |
1 |
|
T55 |
1 |
|
T24 |
13 |
|
T47 |
1 |
| false |
122 |
1 |
|
T24 |
10 |
|
T33 |
1 |
|
T110 |
1 |
| true |
3439 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9657 |
1 |
|
T24 |
10 |
|
T26 |
100 |
|
T6 |
1 |
| others[1] |
257 |
1 |
|
T15 |
1 |
|
T24 |
15 |
|
T22 |
13 |
| others[2] |
247 |
1 |
|
T24 |
14 |
|
T110 |
1 |
|
T22 |
9 |
| others[3] |
388 |
1 |
|
T55 |
1 |
|
T24 |
16 |
|
T22 |
12 |
| false |
117 |
1 |
|
T24 |
3 |
|
T57 |
1 |
|
T34 |
1 |
| true |
3427 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10190 |
1 |
|
T24 |
16 |
|
T26 |
100 |
|
T56 |
100 |
| others[1] |
807 |
1 |
|
T24 |
23 |
|
T21 |
1 |
|
T57 |
1 |
| others[2] |
808 |
1 |
|
T24 |
18 |
|
T113 |
1 |
|
T21 |
5 |
| others[3] |
1366 |
1 |
|
T15 |
1 |
|
T24 |
33 |
|
T21 |
7 |
| false |
411 |
1 |
|
T18 |
1 |
|
T24 |
11 |
|
T21 |
2 |
| true |
511 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10206 |
1 |
|
T24 |
15 |
|
T26 |
100 |
|
T21 |
6 |
| others[1] |
829 |
1 |
|
T18 |
1 |
|
T24 |
19 |
|
T21 |
1 |
| others[2] |
749 |
1 |
|
T15 |
1 |
|
T24 |
19 |
|
T21 |
3 |
| others[3] |
1346 |
1 |
|
T24 |
36 |
|
T113 |
1 |
|
T21 |
2 |
| false |
435 |
1 |
|
T24 |
12 |
|
T21 |
3 |
|
T19 |
6 |
| true |
528 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2369 |
1 |
|
T24 |
7 |
|
T26 |
20 |
|
T56 |
20 |
| others[1] |
2440 |
1 |
|
T15 |
1 |
|
T24 |
9 |
|
T26 |
20 |
| others[2] |
2460 |
1 |
|
T55 |
1 |
|
T24 |
10 |
|
T26 |
22 |
| others[3] |
4028 |
1 |
|
T15 |
1 |
|
T18 |
1 |
|
T24 |
20 |
| false |
1232 |
1 |
|
T24 |
3 |
|
T26 |
8 |
|
T56 |
7 |
| true |
1564 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9676 |
1 |
|
T24 |
13 |
|
T26 |
100 |
|
T6 |
1 |
| others[1] |
307 |
1 |
|
T24 |
6 |
|
T5 |
1 |
|
T57 |
1 |
| others[2] |
281 |
1 |
|
T24 |
7 |
|
T113 |
1 |
|
T33 |
1 |
| others[3] |
476 |
1 |
|
T2 |
1 |
|
T14 |
1 |
|
T15 |
1 |
| false |
159 |
1 |
|
T3 |
1 |
|
T24 |
10 |
|
T27 |
1 |
| true |
3194 |
1 |
|
T1 |
1 |
|
T10 |
1 |
|
T15 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |